THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 features applications D D D D D D D D D D D D D D D D D Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both Signal-to-Noise and Distortion Ratio: 68 dB at fI = 2 MHz Differential Nonlinearity Error: 1 LSB Integral Nonlinearity Error: 1.5 LSB Auto-Scan Mode for 2, 3, or 4 Inputs 3-V or 5-V Digital Interface Compatible Low Power: 216 mW Max at 5 V Power Down: 1 mW Max 5-V Analog Single Supply Operation Internal Voltage References . . . 50 PPM/C and 5% Accuracy Glueless DSP Interface Parallel C/DSP Interface Radar Applications Communications Control Applications High-Speed DSP Front-End Automotive Applications DA PACKAGE (TOP VIEW) description D0 D1 D2 D3 D4 D5 1 32 2 31 3 30 4 29 5 28 6 27 BVDD BGND D6 D7 D8 D9 D10/RA0 D11/RA1 CONV_CLK SYNC 7 26 8 25 9 24 10 23 11 22 AINP AINM BINP BINM REFIN REFOUT REFP REFM AGND AVDD CS0 CS1 WR (R/W) RD DVDD DGND 12 21 The THS1207 is a CMOS, low-power, 12-bit, 13 20 6 MSPS analog-to-digital converter (ADC). The 14 19 speed, resolution, bandwidth, and single-supply 15 18 operation are suited for applications in radar, 16 17 imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS1207 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential-inputs. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The THS1207C is characterized for operation from 0C to 70C, the THS1207I is characterized for operation from -40C to 85C. AVAILABLE OPTIONS PACKAGED DEVICE TA TSSOP (DA) 0C to 70C THS1207CDA -40C to 85C THS1207IDA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 functional block diagram AVDD DVDD 2.5 V 3.5 V REFP VREFP 1.225 V REF 1.5 V REFOUT REFM REFIN AINP S/H AINM S/H BINP S/H VREFM Single Ended and/or Differential MUX + - BVDD 12 Bit Pipeline ADC 12 Buffers BINM S/H CONV_CLK CS0 CS1 RD Logic and Control Control Register BGND WR (R/W) SYNC AGND 2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10/RA0 D11/RA1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 DGND THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AINP 32 I Analog input, single-ended or positive input of differential channel A AINM 31 I Analog input, single-ended or negative input of differential channel A BINP 30 I Analog input, single-ended or positive input of differential channel B BINM 29 I Analog input, single-ended or negative input of differential channel B AVDD AGND 23 I Analog supply voltage 24 I Analog ground BVDD BGND 7 I Digital supply voltage for buffer 8 I Digital ground for buffer CONV_CLK 15 I Digital input. This input is the conversion clock input. CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) DGND 17 I Digital ground. Ground reference for digital circuitry. DVDD 18 I Digital supply voltage D0 - D9 1-6, 9-12 I/O/Z Digital input, output; D0 = LSB D10/RA0 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is required for writing to the control register 0 and control register 1. See Table 8. D11/RA1 14 I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register. This is required for writing to control register 0 and control register 1. See Table 8. REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be connected to the reference output REFOUT. REFP 26 I Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. REFM 25 I Reference input, requires a bypass capacitor of 10 F to AGND in order to bypass the internal reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9. REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 A. The reference output requires a capacitor of 10 F to AGND for filtering and stability. RD 19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active low as a data read select from the processor. See timing section. SYNC 16 O Synchronization output. This signal indicates in a multichannel operation that data of channel A is brought to the digital output and can therefore be used for synchronization. WR (R/W) 20 I This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only input WR, which is active low and used as data write select from the processor. In this case, the RD input is used as a read input from the processor. See timing section. The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, DGND to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V BGND to BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V AGND to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.3 V to AVDD + 1.5 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 + AGND to AVDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to BVDD/DVDD + 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Operating free-air temperature range,TA: THS1207C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C THS1207I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions power supply Supply voltage MIN NOM MAX AVDD DVDD 4.75 5 5.25 4.75 5 5.25 BVDD 3 UNIT V 5.25 analog and reference inputs MIN Analog input voltage in single-ended configuration NOM MAX V 2.5 VREFP 4 3.5 AVDD-1.2 V VREFM 1 Common-mode input voltage VCM in differential configuration External reference voltage,VREFP (optional) External reference voltage, VREFM (optional) 1.4 Input voltage difference, REFP - REFM UNIT V 1.5 V 2 V digital inputs MIN NOM MAX High level input voltage High-level voltage, VIH Low level input voltage, Low-level voltage VIL BVDD = 3.3 V BVDD = 5.25 V Input CONV_CLK frequency DVDD = 4.75 V to 5.25 V 0.1 CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DVDD = 4.75 V to 5.25 V 80 83 5000 ns CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DVDD = 4.75 V to 5.25 V 80 83 5000 ns THS1207CDA Operating free-air free air temperature, temperature TA 4 THS1207IDA POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2 UNIT BVDD = 3.3 V BVDD = 5.25 V V 2.6 V 0.6 0.6 6 0 70 -40 85 V V MHz C THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal (unless otherwise noted) digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital inputs IIH IIL High-level input current DVDD = digital inputs -50 50 A Low-level input current Digital input = 0 V -50 50 A Ci Input capacitance 5 pF Digital outputs VOH VOL High-level output voltage Low-level output voltage IOH = -50 A IOL = 50 A BVDD = 3.3V, 3 3V 5V IOZ CO High-impedance-state output current CS1 = DGND, CS0 = DVDD CL Load capacitance at databus D0 - D11 BVDD-0.5 V -10 Output capacitance 0.4 V 10 A 5 pF 30 pF electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.3 V, fs = 6 MSPS, VREF = internal (unless otherwise noted) dc specifications PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 12 Bits Integral nonlinearity, INL Differential nonlinearity, DNL After calibration in single-ended mode Offset error After calibration in differential mode Gain error 1.5 LSB 1 LSB 20 LSB -20 20 LSB -20 20 LSB Input capacitance 15 Input leakage current VAIN = VREFM to VREFP pF 10 A V Accuracy, VREFP 3.3 3.5 3.7 Accuracy, VREFM 1.4 1.5 1.6 Temperature coefficient 50 Reference noise 2.475 V PPM/C V 100 Accuracy, REFOUT UNIT 2.5 2.525 V IDDA Analog supply current AVDD = DVDD =5 V, BVDD = 3.3 V 36 40 mA IDDD Digital supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 0.5 3 mA IDDB Buffer supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 1.5 4 mA Power dissipation AVDD = DVDD = 5 V, BVDD = 3.3 V 186 216 mW Power dissipation in power down with conversion clock inactive AVDD = DVDD = 5 V, BVDD = 3.3 V 0.25 mW POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 electrical characteristics over recommended operating conditions, VREF = internal, fs = 6 MSPS, fI = 2 MHz at -1dBFS (unless otherwise noted) ac specifications, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF PARAMETER SINAD Signal to noise ratio + distortion Signal-to-noise SNR Signal to noise ratio Signal-to-noise THD Total harmonic distortion ENOB Effective number of bits SFDR Spurious free dynamic range TEST CONDITIONS MIN TYP Differential mode 63 63 Single-ended mode 62 64 Differential mode 64 69 Single-ended mode 64 68 MAX dB dB Differential mode -70 -67 Single-ended mode -68 -64 Differential mode 10.17 10.5 Single-ended mode 10 10.3 Differential mode 67 71 Single-ended mode 65 69 UNIT dB Bits dB Analog Input Full-power bandwidth with a source impedance of 150 in differential configuration. 96 FS sinewave, sinewave -3 3 dB Full-power bandwidth with a source impedance of 150 in single-ended configuration. MHz 54 Small-signal bandwidth with a source impedance of 150 in differential configuration. Small-signal bandwidth with a source impedance of 150 in single-ended configuration. 96 sinewave -3 3 dB 100 mVpp sinewave, MHz 54 timing specifications, AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF PARAMETER TEST CONDITIONS MIN TYP MAX tpipe tsu(CONV_CLKL-READL) Latency Setup time, CONV_CLK low before CS valid 10 tCONV_CLK ns tsu(READH-CONV_CLKL) td(CONV_CLKL-SYNCL) Setup time, CS invalid to CONV_CLK low 20 ns Delay time, CONV_CLK low to SYNC low 10 ns td(CONV_CLKL-SYNCH) Delay time, CONV_CLK low to SYNC high 10 ns 6 5 UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 detailed description reference voltage The THS1207 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. analog inputs The THS1207 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed. converter The THS1207 uses a 12-bit pipelined multistaged architecture, which achieves a high sample rate with low power consumption. The THS1207 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples. conversion An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal. The conversion values are available at the output with a latency of 5 clock cycles. sampling rate The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations. Table 1. Maximum Conversion Rate NUMBER OF CHANNELS MAXIMUM CONVERSION RATE PER CHANNEL 1 single-ended channel 1 6 MSPS 2 single-ended channels 2 3 MSPS 3 single-ended channels 3 2 MSPS 4 single-ended channels 4 1.5 MSPS 1 differential channel 1 6 MSPS 2 differential channels 2 3 MSPS 1 single-ended and 1 differential channel 2 3 MSPS 2 single-ended and 1 differential channels 3 2 MSPS CHANNEL CONFIGURATION The maximum conversion rate in the continuous conversion mode per channel, fc, is given by: fc MSPS + #6channels POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 detailed description (continued) conversion During conversion the ADC operates with a free running external clock signal applied to the input CONV_CLK. With every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding read signal. The THS1207 offers up to four analog input to be selected. It is important to provide the channel information to the system, this means to know which channel is available to the databus. To maintain this channel integrity, the THS1207 an output signal SYNC, which is always active low if data of channel 1 is applied to the databus. Figure 1 shows the timing of the conversion when one analog input channel is selected. The maximum throughput rate is 6 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information is not required for one analog input. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 1 and in the read and SYNC timing table. A more detailed description of the timing is given in the section timing and signal description of the THS1207. Sample N Channel 1 Sample N+1 Channel 1 Sample N+2 Channel 1 Sample N+3 Channel 1 Sample N+4 Channel 1 Sample N+5 Channel 1 Sample N+6 Channel 1 Sample N+7 Channel 1 Sample N+8 Channel 1 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) CONV_CLK tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) READ Data N-4 Channel 1 Data N-3 Channel 1 Data N-2 Channel 1 Data N-1 Channel 1 Data N Channel 1 Data N+1 Channel 1 READ is the logical combination from CS0, CS1 and RD Figure 1. Conversion Timing in 1-Channel Operation 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Data N+2 Channel 1 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 conversion (continued) Figure 2 shows the conversion timing when 2 analog input channels are selected. The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is available to the databus. The signal SYNC is always active low if data of channel 1 is available to the databus. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 2 and in the read and SYNC timing table. A more detailed description of the timing is given in the section timing and signal description of the THS1207. Sample N Channel 1, 2 Sample N+1 Channel 1, 2 Sample N+2 Channel 1, 2 Sample N+3 Channel 1, 2 Sample N+4 Channel 1, 2 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) CONV_CLK tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) READ td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH) SYNC Data N-2 Channel 1 Data N-2 Channel 2 Data N-1 Channel 1 Data N-1 Channel 2 Data N Channel 1 Data N Channel 2 Data N+1 Channel 1 READ is the logical combination from CS0, CS1 and RD Figure 2. Conversion Timing in 2-Channel Operation Figure 3 shows the conversion timing when 3 analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is available to the databus. The signal SYNC is always active low if data of channel 1 is available to the databus. The data of channel 1 is followed by the data of channel 2 and data of channel 3 before channel 1 is again available to the data bus and SYNC is active low. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 3 and in the read and SYNC timing table. A more detailed description of the timing is given in the section timing and signal description of the THS1207. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 conversion (continued) Sample N Channel 1, 2, 3 Sample N+1 Channel 1, 2, 3 Sample N+2 Channel 1, 2, 3 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) CONV_CLK tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) READ td(CONV_CLKL-SYNCH) td(CONV_CLKL-SYNCL) SYNC Data N-2 Channel 3 Data N-1 Channel 1 Data N-1 Channel 2 Data N-1 Channel 3 Data N Channel 1 Data N Channel 2 Data N Channel 3 Figure 3. Conversion Timing in 3-Channel Operation Figure 4 shows the timing of the conversion mode where 4 analog input channels are selected. The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is available to the databus. The signal SYNC is always active low if data of channel 1 is available to the databus. The data of channel 1 is followed by the data of channel 2, data of channel 3 and data of channel 4 before channel 1 is again available to the data bus and SYNC is active low. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 4 and in the read and SYNC timing table. A more detailed description of the timing is given in the section timing and signal description of the THS1207. Sample N Channel 1, 2, 3, 4 Sample N+1 Channel 1, 2, 3, 4 AIN td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) CONV_CLK tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) READ tsu(CONV_CLKL-SYNCH) tsu(CONV_CLKL-SYNCL) SYNC Data N-1 Channel 1 Data N-1 Channel 2 Data N-1 Channel 3 Data N-1 Channel 4 Data N Channel 1 Data N Channel 2 READ is the logical combination from CS0, CS1 and RD Figure 4. Timing of Continuous Conversion Mode (4-channel operation) 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Data N Channel 3 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 digital output data format The digital output data format of the THS1207 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 2. Binary Output Format for Single-Ended Configuration SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP FFFh AIN = (VREFP + VREFM)/2 800h AIN = VREFM 000h Table 3. Twos Complement Output Format for Single-Ended Configuration SINGLE-ENDED, TWOS COMPLEMENT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP 7FFh AIN = (VREFP + VREFM)/2 000h AIN = VREFM 800h Table 4. Binary Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP - AINM VREF = VREFP - VREFM Vin = VREF Vin = 0 FFFh Vin = -VREF 000h 800h Table 5. Twos Complement Output Format for Differential Configuration DIFFERENTIAL, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE Vin = AINP - AINM VREF = VREFP - VREFM Vin = VREF Vin = 0 7FFh Vin = -VREF 800h 000h POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 ADC control register The THS1207 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 6. Table 6. Bit Definitions of Control Register CR0 and CR1 BIT BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF CR1 RBACK OFFSET BIN/2's R/W RESERVED RESERVED RESERVED RESERVED RESERVED RESET writing to control register 0 and control register 1 The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper data bits D10 and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 7 shows the addressing of each control register. Table 7. Control Register Addressing D0 - D9 D10/RA0 D11/RA1 Addressed Control Register Desired register value 0 0 Control Register 0 Desired register value 1 0 Control Register 1 Desired register value 0 1 Reserved for future Desired register value 1 1 Reserved for future Start Use Default Values? No Yes Write 0x401 to THS1207 (Set Reset Bit in CR1) Clear RESET By Writing 0x400 to CR1 Write 0x401 to THS1207 (Set Reset Bit in CR1) Clear RESET By Writing 0x400 to CR1 Write The User Configuration to CR0 Write The User Configuration to CR1 (Must Exclude RESET) Continue Figure 5. THS1207 Configuration Flow 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 ADC control registers control register 0 (see Table 8) - - BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF Table 8. Control Register 0 Bit Functions BITS RESET VALUE NAME 0 0 VREF 1 0 RESERVED 2 0 PD 3, 4 0,0 CHSEL0, CHSEL1 5,6 1,0 DIFF0, DIFF1 7 0 SCAN Autoscan enable Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 8. 8,9 0,0 TEST0, TEST1 Test input enable Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC in its bits. FUNCTION Vref select: Bit 0 = 0 The internal reference is used Bit 0 = 1 The external reference voltage is used for the ADC RESERVED Power down. Bit 2 = 0 The ADC is active Bit 2 = 1 Power down The reading and writing to and from the digital outputs is possible during power down. Channel select Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 8. Number of differential channels Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 8. Refer to Table 6 for selection of the three different test voltages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 analog input channel selection The analog input channels of the THS1207 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 9 shows the possible selections. Table 9. Analog Input Channel Configurations 14 BIT 7 SCAN BIT 6 DIFF1 BIT 5 DIFF0 BIT 4 CHSEL1 BIT 3 CHSEL0 0 0 0 0 0 Analog input AINP (single ended) 0 0 0 0 1 Analog input AINM (single ended) 0 0 0 1 0 Analog input BINP (single ended) 0 0 0 1 1 Analog input BINM (single ended) 0 0 1 0 0 Differential channel (AINP-AINM) 0 0 1 0 1 Differential channel (BINP-BINM) 1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, ... 1 0 0 1 0 Autoscan three single ended channels: AINP, AINM, BINP, AINP, ... 1 0 0 1 1 Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, ... 1 0 1 0 1 Autoscan one differential channel and one single ended channel AINP, (BINP-BINM), AINP, (BINP-BINM), ... 1 0 1 1 0 Autoscan one differential channel and two single ended channel AINP, AINM, (BINP-BINM), AINP, ... 1 1 0 0 1 Autoscan two differential channels (AINP-AINM), (BINP-BINM), (AINP-AINM), ... 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved 1 0 0 0 0 Reserved 1 0 1 0 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved DESCRIPTION OF THE SELECTED INPUTS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 analog input channel selection (continued) test mode The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 10. Table 10. Test Mode BIT 9 TEST1 BIT 8 TEST0 OUTPUT RESULT 0 0 Normal mode 0 1 1 0 VREFP ((VREFM)+(VREFP))/2 1 1 VREFM Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 analog input channel selection (continued) control register 1 (see Table 9) - - BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 - - RBACK OFFSET BIN/2s R/W RESERVED RESERVED RESERVED RESERVED RESERVED RESET Table 11. Control Register 1 Bit Functions BITS RESET VALUE NAME 0 0 RESET FUNCTION Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. To bring the device out of reset, a 0 has to be written into this bit. 1 0 RESERVED Always write 0 2, 3 0,0 RESERVED Always write 0 4 1 RESERVED Always write 0 5 1 RESERVED Always write 0 6 0 R/W R/W, RD/WR selection Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR becomes a write input. 7 0 BIN/2s Complement select If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 20 through Table 23. 8 0 OFFSET Offset cancellation mode Bit 8 = 0 normal conversion mode Bit 8 = 1 offset calibration mode If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error. 9 0 RBACK Debug mode Bit 9 = 0 normal conversion mode Bit 9 = 1 enable debug mode When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. To bring the device back into normal conversion mode, this bit has to be set back to 0 by writing again to control register 1. 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 timing and signal description of the THS1207 The reading from the THS1207 and writing to the THS1207 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select inputs can be used to interface easily to a processor. Reading from the THS1207 takes place by an internal RDint signal, which is generated from the logical combination of the external signals CS0, CS1 and RD (see Figure 6). This signal is then used to strobe out the words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RDint active while the write input (WR) is inactive. The first of those external signals switching to an inactive state deactivates RDint again. Writing to the THS1207 takes place by an internal WRint signal, which is generated from the logical combination of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input (RD) is inactive. The first of those external signals going to its inactive state deactivates WRint again. Read Enable CS0 CS1 RD Write Enable WR Control/Data Registers Data Bits Figure 6. Logical Combination of CS0, CS1, RD, and WR POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 timing and signal description of the THS1207 (continued) read timing (using R/W, CS0-controlled) Figure 7 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 7. t su(CS0H-CONV_CLKL) t su(CONV_CLKL-CS0L) CONV_CLK 10% 10% tw(CS) CS0 10% 90% 10% CS1 IIII IIII IIII R/W IIII IIII IIII th(R/W) tsu(R/W) 90% 90% RD t t a h 90% 90% D(O-11) Figure 7. Read Timing Diagram Using R/W (CS0-controlled) read timing parameter (CS0-controlled) PARAMETER MIN TYP MAX UNIT tsu(CONV_CLKL-CSOL) tsu(CSOH-CONV_CLKL) Setup time, CONV_CLK low before CS valid 10 ns Setup time, CS invalid to CONV_CLK low 20 ns tsu(R/W) ta Setup time, R/W high to last CS valid 0 Access time, last CS valid to data valid 0 10 ns th th(R/W) Hold time, first CS invalid to data invalid 0 5 ns tw(CS) Pulse duration, CS active 18 Hold time, first external CS invalid to R/W change POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ns 5 ns 10 ns THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 timing and signal description of the THS1207 (continued) write timing diagram (using R/W, CS0-controlled) Figure 8 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The writing to the THS1207 can be performed irrespective of the conversion clock signal CONV_CLK. tw(CS) 90% CS0 10% 10% CS1 R/W III III III tsu(R/W) th(R/W) 10% III III III 10% RD tsu th 90% 90% D(0-11) Figure 8. Write Timing Diagram Using R/W (CS0-controlled) write timing parameter (CS0-controlled) PARAMETER MIN TYP MAX UNIT tsu(R/W) tsu Setup time, R/W stable to last CS valid 0 ns Setup time, data valid to first CS invalid 5 ns th th(R/W) Hold time, first CS invalid to data invalid 2 ns 5 ns tw(CS) Pulse duration, CS active 10 ns Hold time, first CS invalid to R/W change POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 analog input configuration and reference voltage The THS1207 features four analog input channels. These can be configured for either single-ended or differential operation. Figure 9 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference voltages). The analog input voltage range is between VREFM to VREFP. This means that VREFM defines the minimum voltage, and VREFP defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V (see also section reference voltage). The resulting analog input voltage swing of 2 V can be expressed by: V REFM v AINP v VREFP (1) VREFP 12-Bit ADC AINP VREFM Figure 9. Single-Ended Input Stage A differential operation is desired in many applications due to a better signal-to-noise ration. Figure 10 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The differential operation mode provides in terms of performance benefits over single-ended mode and is therefore recommended for best performance. The THS1207 offers 2 differential analog inputs and in the single-ended mode 4 analog inputs. If the analog input architecture is differential, common mode noise and common mode voltages can be rejected. Additional details for both modes are given below. VREFP AINP + VADC 12-Bit ADC - AINM VREFM Figure 10. Differential Input Stage 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the input of the ADC is the difference between the input AINP and AINM. The voltage VADC can be calculated as follows: V + ABS(AINP-AINM) ADC (2) The advantage to single-ended operation is that the common-mode voltage V CM + AINM )2 AINP (3) can be rejected in the differential configuration, if the following condition for the analog input voltages is true: v AINM, AINP v AVDD 1 VvV v4 V CM AGND (4) (5) single-ended mode of operation The THS1207 can be configured for single-ended operation using dc or ac-coupling. In either case, the input of the THS1207 must be driven from an operational amplifier that does not degrade the ADC performance. Because the THS1207 operates from a single supply 5 V, it will be necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc and ac-coupling. dc-coupling An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS1207. The analog input voltage range of the THS1207 is between 1.5 V and 3.5 V. An operational amplifier can be used as shown in Figure 11. Figure 11 shows an example where the analog input signal in the range between -1 V up to 1 V. This signal is shifted by an operational amplifier to the analog input range of the THS1207 (1.5 V to 3.5 V). The operational amplifier is configured as an inverting amplifier with a gain of -1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS1207 by using a resistor divider. Therefore, the operational amplifier output voltage is centered at 2.5 V. The 10 mF tantalum capacitor is required for bypassing REFOUT. REFIN of the THS1207 must be connected directly to REFOUT in single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors. R1 3.5 V 2.5 V 1.5 V 5V 1V 0V R1 _ THS1207 RS AINP -1 V 1.25 V + C REFIN REFOUT + R2 10 F R2 Figure 11. Level-Shift for DC-Coupled Input POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 differential mode of operation For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode. Mini Circuits T4-1 49.9 THS1007 R AINP 200 C R AINM C 10 F + REFOUT Figure 12. Transformer Coupled Input TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) 70 SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 80 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 65 60 55 50 45 40 0 1 2 3 4 5 6 7 0 1 fs - Sampling Frequency - MHz Figure 13 22 2 3 4 Figure 14 POST OFFICE BOX 655303 5 fs - Sampling Frequency - MHz * DALLAS, TEXAS 75265 6 7 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (SINGLE-ENDED) SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (SINGLE-ENDED) 70 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 85 65 80 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 90 75 70 65 60 55 50 60 55 50 45 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 45 40 40 0 1 2 3 4 5 6 0 7 1 2 Figure 15 4 5 6 7 Figure 16 TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) 85 SINAD - Signal-to-Noise and Distortion - dB 80 80 THD - Total Harmonic Distortion - dB 3 fs - Sampling Frequency - MHz fs - Sampling Frequency - MHz 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 75 70 65 60 55 50 45 40 0 1 2 3 4 5 6 7 0 1 fs - Sampling Frequency - MHz 2 3 4 5 6 7 fs - Sampling Frequency - MHz Figure 17 Figure 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE vs SAMPLING FREQUENCY (DIFFERENTIAL) SPURIOUS FREE DYNAMIC RANGE vs SAMPLING FREQUENCY (DIFFERENTIAL) 80 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 95 90 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = -0.5 dB FS 75 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 100 85 80 75 70 65 60 55 50 70 65 60 55 50 45 45 40 40 0 1 2 3 4 5 6 0 7 1 2 Figure 19 SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 75 70 65 60 55 50 45 40 1.0 1.5 7 2.0 2.5 3.0 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 75 70 65 60 55 50 45 40 0 fi - Input Frequency - MHz 0.5 1.0 1.5 Figure 22 POST OFFICE BOX 655303 2.0 fi - Input Frequency - MHz Figure 21 24 6 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 0.5 5 SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) 85 0 4 Figure 20 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) 80 3 fs - Sampling Frequency - MHz fs - Sampling Frequency - MHz * DALLAS, TEXAS 75265 2.5 3.0 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE vs INPUT FREQUENCY (SINGLE-ENDED) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (SINGLE-ENDED) 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 95 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 75 90 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 100 85 80 75 70 65 60 55 50 70 65 60 55 50 45 45 40 40 0 0.5 1.0 1.5 2.0 2.5 fi - Input Frequency - MHz 0 3.0 0.5 1.0 2.0 2.5 3.0 Figure 24 Figure 23 SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) 90 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 80 SINAD - Signal-to-Noise and Distortion - dB THD - Total Harmonic Distortion - dB 1.5 fi - Input Frequency - MHz 70 60 50 40 30 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 70 60 50 40 30 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 fi - Input Frequency - MHz fi - Input Frequency - MHz Figure 26 Figure 25 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 TYPICAL CHARACTERISTICS SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY (DIFFERENTIAL) SIGNAL-TO-NOISE vs INPUT FREQUENCY (DIFFERENTIAL) 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 80 70 SNR - Signal-to-Noise - dB SFDR - Spurious Free Dynamic Range - dB 90 70 60 50 40 60 50 40 30 30 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 20 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 fi - Input Frequency - MHz 1.0 2.5 3.0 3.5 Figure 28 EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (DIFFERENTIAL) EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (SINGLE-ENDED) 12 12 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS ENOB - Effective Number of Bits - Bits ENOB - Effective Number of Bits - Bits 2.0 fi - Input Frequency - MHz Figure 27 11 10 9 8 7 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 11 10 9 8 7 6 6 0 1 2 3 4 5 6 7 fs - Sampling Frequency - MHz 0 1 2 3 4 Figure 30 POST OFFICE BOX 655303 5 fs - Sampling Frequency - MHz Figure 29 26 1.5 * DALLAS, TEXAS 75265 6 7 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (DIFFERENTIAL) EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY (SINGLE-ENDED) 12 ENOB - Effective Number of Bits - Bits AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 11 10 9 8 7 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 11 10 9 8 7 6 6 0 0.5 1.0 1.5 2.0 2.5 3.0 0 3.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 fi - Input Frequency - MHz fi - Input Frequency - MHz Figure 32 Figure 31 GAIN vs INPUT FREQUENCY (SINGLE-ENDED) 5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS 0 -5 G - Gain - dB ENOB - Effective Number of Bits - Bits 12 -10 -15 -20 -25 -30 0 10 20 30 40 50 60 70 80 90 100 110 120 fi - Input Frequency - MHz Figure 33 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS Magnitude - dB 0 -20 -40 -60 -80 -100 -120 -140 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 f - Frequency - Hz Figure 34 FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = -0.5 dB FS Magnitude - dB 0 -20 -40 -60 -80 -100 -120 -140 0 500000 1000000 1500000 2000000 2500000 f - Frequency - Hz Figure 35 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3000000 3500000 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 DNL - Differential Nonlinearity - LSB TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY vs ADC CODE 1.0 AVDD = 5 V DVDD = BVDD = 3 V fs = 8 MSPS 0.8 0.6 0.4 0.2 -0.0 -0.2 -0.4 -0.6 -0.8 -1 0 500 1000 1500 2000 2500 3000 3500 4000 3000 3500 4000 ADC Code Figure 36 INL - Integral Nonlinearity - LSB INTEGRAL NONLINEARITY vs ADC CODE 1.0 0.8 0.6 0.4 0.2 -0.0 -0.2 -0.4 AVDD = 5 V DVDD = BVDD = 3 V fs = 8 MSPS -0.6 -0.8 -1 0 500 1000 1500 2000 2500 ADC Code Figure 37 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than 1 LSB ensures no missing codes. zero offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. gain error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. effective number of bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N + (SINAD6.02* 1.76) it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 THS1207 12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER SLAS284 - AUGUST 2000 MECHANICAL DATA DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 38 PINS SHOWN 0,30 0,19 0,65 38 0,13 M 20 6,20 NOM 8,40 7,80 0,15 NOM Gage Plane 1 19 0,25 A 0- 8 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 28 30 32 38 A MAX 9,80 11,10 11,10 12,60 A MIN 9,60 10,90 10,90 12,40 DIM 4040066 / D 11/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated