THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
D
Signal-to-Noise and Distortion Ratio:
68 dB at fI = 2 MHz
D
Differential Nonlinearity Error: ±1 LSB
D
Integral Nonlinearity Error: ±1.5 LSB
D
Auto-Scan Mode for 2, 3, or 4 Inputs
D
3-V or 5-V Digital Interface Compatible
D
Low Power: 216 mW Max at 5 V
D
Power Down: 1 mW Max
D
5-V Analog Single Supply Operation
D
Internal Voltage References . . . 50 PPM/°C
and ±5% Accuracy
D
Glueless DSP Interface
D
Parallel µC/DSP Interface
applications
D
Radar Applications
D
Communications
D
Control Applications
D
High-Speed DSP Front-End
D
Automotive Applications
description
The THS1207 is a CMOS, low-power, 12-bit,
6 MSPS analog-to-digital converter (ADC). The
speed, resolution, bandwidth, and single-supply
operation are suited for applications in radar,
imaging, high-speed acquisition, and commu-
nications. A multistage pipelined architecture with
output error correction logic provides for no
missing codes over the full operating temperature range. Internal control registers are used to program the ADC
into the desired mode. The THS1207 consists of four analog inputs, which are sampled simultaneously. These
inputs can be selected individually and configured to single-ended or differential-inputs. Internal reference
voltages for the ADC (1.5 V and 3.5 V) are provided. An external reference can also be chosen to suit the dc
accuracy and temperature drift requirements of the application.
The THS1207C is characterized for operation from 0°C to 70°C, the THS1207I is characterized for operation
from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
TATSSOP
(DA)
0°C to 70°C THS1207CDA
–40°C to 85°C THS1207IDA
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
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9
10
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12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
D10/RA0
D11/RA1
CONV_CLK
SYNC
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
DA PACKAGE
(TOP VIEW)
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Logic and Control
12 Bit
Pipeline
ADC
S/H
S/H
S/H
S/H
Single
Ended
and/or
Differential
MUX
+
–
VREFM
1.5 V
3.5 V
1.225 V
REF
12
Buffers
2.5 V
Control
Register
AVDD DVDD
AGND DGND
REFOUT
BVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10/RA0
D11/RA1
BGND
REFP
REFM
AINP
AINM
BINP
BINM
CONV_CLK
CS0
CS1
RD
WR (R/W)
REFIN
VREFP
SYNC
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AINP 32 IAnalog input, single-ended or positive input of dif ferential channel A
AINM 31 IAnalog input, single-ended or negative input of differential channel A
BINP 30 IAnalog input, single-ended or positive input of differential channel B
BINM 29 IAnalog input, single-ended or negative input of differential channel B
AVDD 23 IAnalog supply voltage
AGND 24 IAnalog ground
BVDD 7 I Digital supply voltage for buffer
BGND 8 I Digital ground for buffer
CONV_CLK 15 IDigital input. This input is the conversion clock input.
CS0 22 IChip select input (active low)
CS1 21 IChip select input (active high)
DGND 17 IDigital ground. Ground reference for digital circuitry.
DVDD 18 IDigital supply voltage
D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB
D10/RA0 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control
register . This is required for writing to the control register 0 and control register 1. See T able 8.
D11/RA1 14 I/O/Z Digital input, output (D1 1 = MSB). The data line D1 1 is also used as an address line (RA1) for
the control register . This is required for writing to control register 0 and control register 1. See
Table 8.
REFIN 28 ICommon-mode reference input for the analog input channels. It is recommended that this pin
be connected to the reference output REFOUT.
REFP 26 IReference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal
reference voltage. An external reference voltage at this input can be applied. This option can
be programmed through control register 0. See Table 9.
REFM 25 IReference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal
reference voltage. An external reference voltage at this input can be applied. This option can
be programmed through control register 0. See Table 9.
REFOUT 27 OAnalog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The
reference output requires a capacitor of 10 µF to AGND for filtering and stability.
RD†19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a
digital input, active low as a data read select from the processor. See timing section.
SYNC 16 OSynchronization output. This signal indicates in a multichannel operation that data of channel
A is brought to the digital output and can therefore be used for synchronization.
WR (R/W)†20 I This input is programmable. It functions as a read-write input R/W and can also be configured
as a write-only input WR, which is active low and used as data write select from the processor.
In this case, the RD input is used as a read input from the processor. See timing section.
†The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, DGND to DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BGND to BVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AGND to AVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range,TA: THS1207C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THS1207I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
power supply
MIN NOM MAX UNIT
AVDD 4.75 5 5.25
Supply voltage DVDD 4.75 5 5.25 V
BVDD 3 5.25
analog and reference inputs
MIN NOM MAX UNIT
Analog input voltage in single-ended configuration VREFM VREFP V
Common-mode input voltage VCM in differential configuration 1 2.5 4 V
External reference voltage,VREFP (optional) 3.5 AVDD–1.2 V
External reference voltage, VREFM (optional) 1.4 1.5 V
Input voltage difference, REFP – REFM 2 V
digital inputs
MIN NOM MAX UNIT
High level in
p
ut voltage VIH
BVDD = 3.3 V 2 V
High
-
le
v
el
inp
u
t
v
oltage
,
V
IH BVDD = 5.25 V 2.6 V
Low level in
p
ut voltage VIL
BVDD = 3.3 V 0.6 V
Lo
w-
le
v
el
inp
u
t
v
oltage
,
V
IL BVDD = 5.25 V 0.6 V
Input CONV_CLK frequency DVDD = 4.75 V to 5.25 V 0.1 6 MHz
CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DVDD = 4.75 V to 5.25 V 80 83 5000 ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DVDD = 4.75 V to 5.25 V 80 83 5000 ns
O
p
erating free air tem
p
erature TA
THS1207CDA 0 70 °
C
Operating
free
-
air
temperat
u
re
,
T
ATHS1207IDA –40 85
°C
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V,
BVDD = 3.3 V, VREF = internal (unless otherwise noted)
digital specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital inputs
IIH High-level input current DVDD = digital inputs –50 50 µA
IIL Low-level input current Digital input = 0 V –50 50 µA
CiInput capacitance 5 pF
Digital outputs
VOH High-level output voltage IOH = –50 µA
BVDD = 3 3V 5V
BVDD–0.5 V
VOL Low-level output voltage IOL = 50 µA
BV
DD =
3
.
3V
,
5V
0.4 V
IOZ High-impedance-state output current CS1 = DGND, CS0 = DVDD –10 10 µA
COOutput capacitance 5 pF
CLLoad capacitance at databus D0 – D11 30 pF
electrical characteristics over recommended operating conditions, AVDD = DVDD = 5 V,
BVDD = 3.3 V, fs = 6 MSPS, VREF = internal (unless otherwise noted)
dc specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Integral nonlinearity , INL ±1.5 LSB
Differential nonlinearity, DNL ±1 LSB
Offset error
After calibration in single-ended mode 20 LSB
Offset
error
After calibration in differential mode –20 20 LSB
Gain error –20 20 LSB
Input capacitance 15 pF
Input leakage current VAIN = VREFM to VREFP ±10 µA
Accuracy, VREFP 3.3 3.5 3.7 V
Accuracy, VREFM 1.4 1.5 1.6 V
Temperature coefficient 50 PPM/°C
Reference noise 100 µV
Accuracy, REFOUT 2.475 2.5 2.525 V
IDDA Analog supply current AVDD = DVDD =5 V, BVDD = 3.3 V 36 40 mA
IDDD Digital supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 0.5 3 mA
IDDB Buffer supply voltage AVDD = DVDD = 5 V, BVDD = 3.3 V 1.5 4 mA
Power dissipation AVDD = DVDD = 5 V, BVDD = 3.3 V 186 216 mW
Power dissipation in power down with conver-
sion clock inactive AVDD = DVDD = 5 V, BVDD = 3.3 V 0.25 mW
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, VREF = internal, fs = 6 MSPS,
fI = 2 MHz at –1dBFS (unless otherwise noted)
ac specifications, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SINAD
Signal to noise ratio + distortion
Differential mode 63 63
dB
SINAD
Signal
-
to
-
noise
ratio
+
distortion
Single-ended mode 62 64
dB
SNR
Signal to noise ratio
Differential mode 64 69
dB
SNR
Signal
-
to
-
noise
ratio
Single-ended mode 64 68
dB
THD
Total harmonic distortion
Differential mode –70 –67
dB
THD
Total
harmonic
distortion
Single-ended mode –68 –64
dB
ENOB
Effective number of bits
Differential mode 10.17 10.5
Bits
ENOB
Effecti
v
e
n
u
mber
of
bits
Single-ended mode 10 10.3
Bits
SFDR
S
p
urious free dynamic range
Differential mode 67 71
dB
SFDR
Sp
u
rio
u
s
free
d
y
namic
range
Single-ended mode 65 69
dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
w
v
, –
54
MH
z
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
pp
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
w
v
, –
54
MH
z
timing specifications, AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpipe Latency 5 tCONV_CLK
tsu(CONV_CLKL-READL) Setup time, CONV_CLK low before CS valid 10 ns
tsu(READH-CONV_CLKL) Setup time, CS invalid to CONV_CLK low 20 ns
td(CONV_CLKL-SYNCL) Delay time, CONV_CLK low to SYNC low 10 ns
td(CONV_CLKL-SYNCH) Delay time, CONV_CLK low to SYNC high 10 ns
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
reference voltage
The THS1207 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V . An external reference can also be used through two reference input pins, REFP and
REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
analog inputs
The THS1207 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
converter
The THS1207 uses a 12-bit pipelined multistaged architecture, which achieves a high sample rate with low
power consumption. The THS1207 distributes the conversion over several smaller ADC sub-blocks, refining
the conversion with progressively higher accuracy as the device passes the results from stage to stage. This
distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.
A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input
sample while the second through the eighth stages operate on the seven preceding samples.
conversion
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal. The conversion values are available
at the output with a latency of 5 clock cycles.
sampling rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels.
Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate
CHANNEL CONFIGURATION NUMBER OF
CHANNELS MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel 16 MSPS
2 single-ended channels 23 MSPS
3 single-ended channels 32 MSPS
4 single-ended channels 41.5 MSPS
1 differential channel 16 MSPS
2 differential channels 23 MSPS
1 single-ended and 1 differential channel 23 MSPS
2 single-ended and 1 differential channels 32 MSPS
The maximum conversion rate in the continuous conversion mode per channel, is given by:
fc
+
6 MSPS
# channels
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
conversion
During conversion the ADC operates with a free running external clock signal applied to the input CONV_CLK.
With every falling edge of the CONV_CLK signal a new converted value is available to the databus with the
corresponding read signal. The THS1207 offers up to four analog input to be selected. It is important to provide
the channel information to the system, this means to know which channel is available to the databus. T o maintain
this channel integrity, the THS1207 an output signal SYNC, which is always active low if data of channel 1 is
applied to the databus.
Figure 1 shows the timing of the conversion when one analog input channel is selected. The maximum
throughput rate is 6 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since
this information is not required for one analog input. There is a certain timing relationship required for the read
signal with respect to the conversion clock. This can be seen in Figure 1 and in the read and SYNC timing table.
A more detailed description of the timing is given in the section timing and signal description of the THS1207.
Sample N
Channel 1 Sample N+2
Channel 1 Sample N+3
Channel 1
Sample N+1
Channel 1 Sample N+4
Channel 1 Sample N+5
Channel 1 Sample N+6
Channel 1 Sample N+7
Channel 1 Sample N+8
Channel 1
Data N–1
Channel 1 Data N
Channel 1 Data N+1
Channel 1 Data N+2
Channel 1
Data N–4
Channel 1 Data N–3
Channel 1 Data N–2
Channel 1
AIN
CONV_CLK
READ†
†READ is the logical combination from CS0, CS1 and RD
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
Figure 1. Conversion Timing in 1-Channel Operation
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
conversion (continued)
Figure 2 shows the conversion timing when 2 analog input channels are selected. The maximum throughput
rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is always active low if data of channel 1 is available
to the databus. There is a certain timing relationship required for the read signal with respect to the conversion
clock. This can be seen in Figure 2 and in the read and SYNC timing table. A more detailed description of the
timing is given in the section timing and signal description of the THS1207.
Sample N
Channel 1, 2 Sample N+1
Channel 1, 2 Sample N+2
Channel 1, 2 Sample N+3
Channel 1, 2 Sample N+4
Channel 1, 2
Data N–1
Channel 2 Data N
Channel 1 Data N
Channel 2 Data N+1
Channel 1
Data N–2
Channel 1 Data N–2
Channel 2 Data N–1
Channel 1
AIN
CONV_CLK
READ†
†READ is the logical combination from CS0, CS1 and RD
SYNC
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH)
Figure 2. Conversion Timing in 2-Channel Operation
Figure 3 shows the conversion timing when 3 analog input channels are selected. The maximum throughput
rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is always active low if data of channel 1 is available
to the databus. The data of channel 1 is followed by the data of channel 2 and data of channel 3 before channel
1 is again available to the data bus and SYNC is active low. There is a certain timing relationship required for
the read signal with respect to the conversion clock. This can be seen in Figure 3 and in the read and SYNC
timing table. A more detailed description of the timing is given in the section timing and signal description of the
THS1207.
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
conversion (continued)
Sample N
Channel 1, 2, 3 Sample N+1
Channel 1, 2, 3 Sample N+2
Channel 1, 2, 3
Data N–1
Channel 3 Data N
Channel 1 Data N
Channel 2 Data N
Channel 3
Data N–2
Channel 3 Data N–1
Channel 1 Data N–1
Channel 2
AIN
CONV_CLK
READ†
SYNC
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH)
Figure 3. Conversion Timing in 3-Channel Operation
Figure 4 shows the timing of the conversion mode where 4 analog input channels are selected. The maximum
throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the databus. The signal SYNC is always active low if data of channel
1 is available to the databus. The data of channel 1 is followed by the data of channel 2, data of channel 3 and
data of channel 4 before channel 1 is again available to the data bus and SYNC is active low . There is a certain
timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure
4 and in the read and SYNC timing table. A more detailed description of the timing is given in the section timing
and signal description of the THS1207.
Sample N
Channel 1, 2, 3, 4 Sample N+1
Channel 1, 2, 3, 4
Data N–1
Channel 4 Data N
Channel 1 Data N
Channel 2 Data N
Channel 3
Data N–1
Channel 1 Data N–1
Channel 2 Data N–1
Channel 3
AIN
CONV_CLK
READ†
†READ is the logical combination from CS0, CS1 and RD
SYNC
td(A) td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-SYNCH)
tsu(CONV_CLKL-SYNCL)
Figure 4. Timing of Continuous Conversion Mode (4-channel operation)
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital output data format
The digital output data format of the THS1207 can either be in binary format or in twos complement format. The
following tables list the digital outputs for the analog input voltages.
Table 2. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = VREFP FFFh
AIN = (VREFP + VREFM)/2 800h
AIN = VREFM 000h
Table 3. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = VREFP 7FFh
AIN = (VREFP + VREFM)/2 000h
AIN = VREFM 800h
Table 4. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF FFFh
Vin = 0 800h
Vin = –VREF 000h
Table 5. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP – AINM
VREF = VREFP – VREFM
Vin = VREF 7FFh
Vin = 0 000h
Vin = –VREF 800h
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC control register
The THS1207 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in Table 6.
Table 6. Bit Definitions of Control Register CR0 and CR1
BIT BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF
CR1 RBACK OFFSET BIN/2’s R/W RESERVED RESERVED RESERVED RESERVED RESERVED RESET
writing to control register 0 and control register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper data bits D10
and D1 1, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0
to D9 contain the desired control register value. Table 7 shows the addressing of each control register.
Table 7. Control Register Addressing
D0 – D9 D10/RA0 D1 1/RA1 Addressed Control Register
Desired register value 0 0 Control Register 0
Desired register value 1 0 Control Register 1
Desired register value 0 1 Reserved for future
Desired register value 1 1 Reserved for future
Start
Use Default
Values?
Yes
Write 0x401 to
THS1207
(Set Reset Bit in CR1)
No
Write 0x401 to
THS1207
(Set Reset Bit in CR1)
Clear RESET By
Writing 0x400 to CR1
Write The User
Configuration to CR0
Write The User
Configuration to CR1
(Must Exclude RESET)
Continue
Clear RESET By
Writing 0x400 to
CR1
Figure 5. THS1207 Configuration Flow
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
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ADC control registers
control register 0 (see Table 8)
– – BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
– – TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF
Table 8. Control Register 0 Bit Functions
BITS RESET
VALUE NAME FUNCTION
0 0 VREF V ref select:
Bit 0 = 0 → The internal reference is used
Bit 0 = 1 → The external reference voltage is used for the ADC
1 0 RESERVED RESERVED
2 0 PD Power down.
Bit 2 = 0 → The ADC is active
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down.
3, 4 0,0 CHSEL0,
CHSEL1 Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 8.
5,6 1,0 DIFF0, DIFF1 Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 8.
7 0 SCAN Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 8.
8,9 0,0 TEST0,
TEST1 Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC in its bits.
Refer to Table 6 for selection of the three different test voltages.
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
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analog input channel selection
The analog input channels of the THS1207 can be selected via bits 3 to 7 of control register 0. One single
channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the
selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more
than one input channel is selected. Table 9 shows the possible selections.
Table 9. Analog Input Channel Configurations
BIT 7
SCAN BIT 6
DIFF1 BIT 5
DIFF0 BIT 4
CHSEL1 BIT 3
CHSEL0 DESCRIPTION OF THE SELECTED INPUTS
0 0 0 0 0 Analog input AINP (single ended)
0 0 0 0 1 Analog input AINM (single ended)
0 0 0 1 0 Analog input BINP (single ended)
0 0 0 1 1 Analog input BINM (single ended)
0 0 1 0 0 Differential channel (AINP–AINM)
0 0 1 0 1 Differential channel (BINP–BINM)
1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, …
1 0 0 1 0 Autoscan three single ended channels: AINP, AINM, BINP, AINP, …
1 0 0 1 1 Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …
1 0 1 0 1 Autoscan one differential channel and one single ended channel AINP,
(BINP–BINM), AINP, (BINP–BINM), …
1 0 1 1 0 Autoscan one differential channel and two single ended channel AINP,
AINM, (BINP–BINM), AINP, …
1 1 0 0 1 Autoscan two differential channels (AINP–AINM), (BINP–BINM),
(AINP–AINM), …
0 0 1 1 0 Reserved
0 0 1 1 1 Reserved
1 0 0 0 0 Reserved
1 0 1 0 0 Reserved
1 0 1 1 1 Reserved
1 1 0 0 0 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 Reserved
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 Reserved
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
analog input channel selection (continued)
test mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 10.
Table 10. Test Mode
BIT 9
TEST1 BIT 8
TEST0 OUTPUT RESULT
0 0 Normal mode
0 1 VREFP
1 0 ((VREFM)+(VREFP))/2
1 1 VREFM
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
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analog input channel selection (continued)
control register 1 (see Table 9)
– – BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
– – RBACK OFFSET BIN/2s R/W RESERVED RESERVED RESERVED RESERVED RESERVED RESET
Table 11. Control Register 1 Bit Functions
BITS RESET
VALUE NAME FUNCTION
0 0 RESET Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset
values. To bring the device out of reset, a 0 has to be written into this bit.
1 0 RESERVED Always write 0
2, 3 0,0 RESERVED Always write 0
4 1 RESERVED Always write 0
5 1 RESERVED Always write 0
6 0 R/W R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set
to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write
with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input
WR becomes a write input.
7 0 BIN/2s Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to T able 20 through Table 23.
8 0 OFFSET Of fset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a con-
version. The conversion result is stored in an offset register and subtracted from all conversions in order
to reduce the offset error.
9 0 RBACK Debug mode
Bit 9 = 0 → normal conversion mode
Bit 9 = 1 → enable debug mode
When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control
register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of
control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. To bring the
device back into normal conversion mode, this bit has to be set back to 0 by writing again to control register 1.
THS1207
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timing and signal description of the THS1207
The reading from the THS1207 and writing to the THS1207 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS1207 takes place by an internal RDint signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 6). This signal is then used to strobe out the
words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes
RDint active while the write input (WR) is inactive. The first of those external signals switching to an inactive state
deactivates RDint again.
Writing to the THS1207 takes place by an internal WRint signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and
1. The last external signal (either CS0, CS1 or WR) to become valid switches WRint active while the read input
(RD) is inactive. The first of those external signals going to its inactive state deactivates WRint again.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 6. Logical Combination of CS0, CS1, RD, and WR
THS1207
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timing and signal description of the THS1207 (continued)
read timing (using R/W, CS0-controlled)
Figure 7 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data
should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 7.
tsu(CONV_CLKL–CS0L)
tsu(CS0H–CONV_CLKL)
tath
10% 10%
90%
90%
90% 90%
90%
10% 10%
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
CONV_CLK
CS0
CS1
R/W
RD
D(O–11)
tw(CS)
tsu(R/W)th(R/W)
Figure 7. Read Timing Diagram Using R/W (CS0-controlled)
read timing parameter (CS0-controlled)
PARAMETER MIN TYP MAX UNIT
tsu(CONV_CLKL-CSOL) Setup time, CONV_CLK low before CS valid 10 ns
tsu(CSOH-CONV_CLKL) Setup time, CS invalid to CONV_CLK low 20 ns
tsu(R/W)Setup time, R/W high to last CS valid 0 ns
taAccess time, last CS valid to data valid 0 10 ns
thHold time, first CS invalid to data invalid 0 5 ns
th(R/W)Hold time, first external CS invalid to R/W change 5 ns
tw(CS) Pulse duration, CS active 10 ns
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
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timing and signal description of the THS1207 (continued)
write timing diagram (using R/W, CS0-controlled)
Figure 8 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The writing to the THS1207
can be performed irrespective of the conversion clock signal CONV_CLK.
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÏÏÏ
ÏÏÏ
ÏÏÏ
90%
90% 90%
10%
tw(CS)
tsu(R/W)th(R/W)
CS0
CS1
R/W
RD
D(0–11)
10%
tsu th
10% 10%
Figure 8. Write Timing Diagram Using R/W (CS0-controlled)
write timing parameter (CS0-controlled)
PARAMETER MIN TYP MAX UNIT
tsu(R/W)Setup time, R/W stable to last CS valid 0 ns
tsu Setup time, data valid to first CS invalid 5 ns
thHold time, first CS invalid to data invalid 2 ns
th(R/W)Hold time, first CS invalid to R/W change 5 ns
tw(CS) Pulse duration, CS active 10 ns
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
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analog input configuration and reference voltage
The THS1207 features four analog input channels. These can be configured for either single-ended or
differential operation. Figure 9 shows a simplified model, where a single-ended configuration for channel AINP
is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference
voltages). The analog input voltage range is between VREFM to VREFP. This means that VREFM defines the
minimum voltage, and VREFP defines the maximum voltage, which can be applied to the ADC. The internal
reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V (see also section
reference voltage). The resulting analog input voltage swing of 2 V can be expressed by:
VREFM
v
AINP
v
VREFP
12-Bit
ADC
VREFP
VREFM
AINP
Figure 9. Single-Ended Input Stage
A differential operation is desired in many applications due to a better signal-to-noise ration. Figure 10 shows
a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The
differential operation mode provides in terms of performance benefits over single-ended mode and is therefore
recommended for best performance. The THS1207 offers 2 dif ferential analog inputs and in the single-ended
mode 4 analog inputs. If the analog input architecture is differential, common mode noise and common mode
voltages can be rejected. Additional details for both modes are given below.
12-Bit
ADC
VREFP
VREFM
AINP
ΣVADC
AINM
+
–
Figure 10. Differential Input Stage
(1)
THS1207
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In comparison to the single-ended configuration it can be seen that the voltage, VADC, which is applied at the
input of the ADC is the difference between the input AINP and AINM. The voltage VADC can be calculated as
follows:
VADC
+
ABS(AINP–AINM)
The advantage to single-ended operation is that the common-mode voltage
VCM
+
AINM
)
AINP
2
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND
v
AINM, AINP
v
AVDD
1V
v
VCM
v
4V
single-ended mode of operation
The THS1207 can be configured for single-ended operation using dc or ac-coupling. In either case, the input
of the THS1207 must be driven from an operational amplifier that does not degrade the ADC performance.
Because the THS1207 operates from a single supply 5 V , it will be necessary to level-shift ground-based bipolar
signals to comply with its input requirements. This can be achieved with dc and ac-coupling.
dc-coupling
An operational amplifier can be configured to shift the signal level according to the analog input voltage range
of the THS1207. The analog input voltage range of the THS1207 is between 1.5 V and 3.5 V. An operational
amplifier can be used as shown in Figure 11.
Figure 11 shows an example where the analog input signal in the range between –1 V up to 1 V. This signal is
shifted by an operational amplifier to the analog input range of the THS1207 (1.5 V to 3.5 V). The operational
amplifier is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the
noninverting input is derived from the 2.5-V output reference REFOUT of the THS1207 by using a resistor
divider. Therefore, the operational amplifier output voltage is centered at 2.5 V. The 10 mF tantalum capacitor
is required for bypassing REFOUT. REFIN of the THS1207 must be connected directly to REFOUT in
single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.
_
+
5 V
R1
R1RS
3.5 V
2.5 V
1.5 V THS1207
AINP
REFOUT
R2
R2
1.25 V
1 V
0 V
–1 V REFIN
+
C
10 µF
Figure 11. Level-Shift for DC-Coupled Input
(2)
(3)
(4)
(5)
THS1207
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SLAS284 – AUGUST 2000
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differential mode of operation
For the differential mode of operation, a conversion from single-ended to dif ferential is required. A conversion
to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best
performance is achieved in differential mode.
THS1007
AINP
AINM
REFOUT
C
C
R
R
200 Ω
49.9 Ω
Mini Circuits
T4–1
+
10 µF
Figure 12. Transformer Coupled Input
TYPICAL CHARACTERISTICS
Figure 13
40
45
50
55
60
65
70
75
80
01234567
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 14
40
45
50
55
60
65
70
01234567
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs – Sampling Frequency – MHz
SINAD – Signal-to-Noise and Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
40
45
50
55
60
65
70
75
80
85
90
01234567
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs – Sampling Frequency – MHz
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 16
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs – Sampling Frequency – MHz
SNR – Signal-to-Noise – dB
40
45
50
55
60
65
70
01234567
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 17
40
45
50
55
60
65
70
75
80
85
01234567
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 18
40
45
50
55
60
65
70
75
80
01234567
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs – Sampling Frequency – MHz
SINAD – Signal-to-Noise and Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
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TYPICAL CHARACTERISTICS
Figure 19
40
45
50
55
60
65
70
75
80
85
90
95
100
01234567
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs – Sampling Frequency – MHz
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 20
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs – Sampling Frequency – MHz
SNR – Signal-to-Noise – dB
40
45
50
55
60
65
70
75
80
01234567
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = –0.5 dB FS
Figure 21
40
45
50
55
60
65
70
75
80
85
0 0.5 1.0 1.5 2.0 2.5 3.0
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 22
40
45
50
55
60
65
70
75
80
0 0.5 1.0 1.5 2.0 2.5 3.0
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
SINAD – Signal-to-Noise and Distortion – dB
fi – Input Frequency – MHz
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 23
40
45
50
55
60
65
70
75
80
85
90
95
100
0 0.5 1.0 1.5 2.0 2.5 3.0
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
Figure 24
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (SINGLE-ENDED)
SNR – Signal-to-Noise – dB
40
45
50
55
60
65
70
75
80
0 0.5 1.0 1.5 2.0 2.5 3.0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
Figure 25
20
30
40
50
60
70
80
90
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
THD – Total Harmonic Distortion – dB
Figure 26
20
30
40
50
60
70
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
SINAD – Signal-to-Noise and Distortion – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
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TYPICAL CHARACTERISTICS
Figure 27
20
30
40
50
60
70
80
90
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
SFDR – Spurious Free Dynamic Range – dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
20
30
40
50
60
70
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Figure 28
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
SNR – Signal-to-Noise – dB
Figure 29
6
7
8
9
10
11
12
01234567
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz Figure 30
6
7
8
9
10
11
12
01234567
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fs – Sampling Frequency – MHz
THS1207
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TYPICAL CHARACTERISTICS
Figure 31
6
7
8
9
10
11
12
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz Figure 32
6
7
8
9
10
11
12
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
ENOB – Effective Number of Bits – Bits
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
Fi
g
ure 33
–30
–25
–20
–15
–10
–5
0
5
0 102030405060708090100110120
G – Gain – dB
GAIN
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
fi – Input Frequency – MHz
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 34
–140
–120
–100
–80
–60
–40
–20
0
20
0 500000 1000000 1500000 2000000 2500000 3000000 3500000
Magnitude – dB
f – Frequency – Hz
FAST FOURIER TRANSFORM (4096 POINTS)
(SINGLE-ENDED)
vs
FREQUENCY
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
–140
–120
–100
–80
–60
–40
–20
0
20
0 500000 1000000 1500000 2000000 2500000 3000000 3500000
Figure 35
Magnitude – dB
f – Frequency – Hz
FAST FOURIER TRANSFORM (4096 POINTS)
(DIFFERENTIAL)
vs
FREQUENCY
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 6 MHz, AIN = –0.5 dB FS
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
–1
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
1.0
0 500 1000 1500 2000 2500 3000 3500 4000
DNL – Differential Nonlinearity – LSB
ADC Code
DIFFERENTIAL NONLINEARITY
vs
ADC CODE
AVDD = 5 V
DVDD = BVDD = 3 V
fs = 8 MSPS
Figure 37
–1
–0.8
–0.6
–0.4
–0.2
–0.0
0.2
0.4
0.6
0.8
1.0
0 500 1000 1500 2000 2500 3000 3500 4000
INL – Integral Nonlinearity – LSB
ADC Code
INTEGRAL NONLINEARITY
vs
ADC CODE
AVDD = 5 V
DVDD = BVDD = 3 V
fs = 8 MSPS
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N
+
(SINAD
*
1.76)
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal
and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
THS1207
12-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS284 – AUGUST 2000
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
4040066/D 11/98
0,25
0,75
0,50
0,15 NOM
Gage Plane
6,20
NOM 8,40
7,80
32
11,10
11,10
30
Seating Plane
10,9010,90
20
0,19
19
A
0,30
38
1
PINS **
A MAX
A MIN
DIM
1,20 MAX
9,60
9,80
28
M
0,13
0°–8°
0,10
0,65
38
12,60
12,40
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
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