PDM31516 32K x 16 CMOS Static SRAM Features Description The PDM31516 is a high-performance CMOS static RAM organized as 32,768 x 16 bits. This product is produced using Paradigm's proprietary CMOS technology which offers the designer the highest speed parts. The PDM31516 features low power dissipation using chip enable (CE) and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. High-speed access times - Com'l: 12, 15, 17 and 20 ns - Ind: 15, 17 and 20 ns Low power operation (typical) - PDM31516SA Active: 200 mW Standby: 50 mW High-density 32K x 16 architecture 3.3V (0.3V) power supply Fully static operation TTL-compatible inputs and outputs Outbut buffer controls: OE Data byte controls: LB, UB Packages: 44-pin Plastic TSOP - T 44-pin Plastic SOJ (400 mil) - SO The PDM31516 operates from a single +3.3V power supply and all the inputs and outputs are fully TTLcompatible. The PDM31516 is available in a 400-mil 44-pin plastic SOJ and a 44-pin plastic TSOP package. 1 2 3 4 5 6 7 Functional Block Diagram 8 9 10 11 12 Rev. 1.0 - 7/24/96 7-17 PDM31516 Pin Configuration 44-Pin SOJ 44-Pin TSOP Pin Description Name Description A14-A0 Address Inputs I/O15-I/O0 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input LB, UB Data Byte Control Inputs NC No Connect VCC Power (+3.3V) VSS Ground Operating Mode Mode CE OE WE LB UB I/O7-I/O0 I/O15-I/O8 Power Read L L H L L Output Output ICC H L High Impedance Output ICC L H Output High Impedance ICC L L Input Input ICC H L High Impedance Input ICC L H Input High Impedance ICC Write Output Disable Standby L X L L H H X X High Impedance High Impedance ICC L X X H H High Impedance High Impedance ICC H X X X X High Impedance High Impedance ISB NOTE:1.H = VIH, L = VIL, X = DON'T CARE 7-18 Rev. 1.0 - 7/24/96 PDM31516 Absolute Maximum Ratings Symbol Rating Com'l. Ind. Unit VTERM Terminal Voltage with Respect to VSS -0.5 to +4.6 -0.5 to +4.6 V TBIAS Temperature Under Bias -55 to +125 -55 to +135 C TSTG Storage Temperature -55 to +125 -65 to +150 C PD Power Dissipation 1.5 1.5 W IOUT DC Output Current 50 50 mA 1 2 NOTE:1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 4 Recommended DC Operating Conditions Symbol Description Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V VSS Supply Voltage 0 0 0 V Industrial Ambient Temperature -40 25 85 C Commercial Ambient Temperature 0 25 70 C 5 6 7 8 DC Electrical Characteristics (VCC = 3.3V 0.3V) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = Vss to VCC Com'l/ Ind. -5 5 A ILO Output Leakage Current VCC= Max., CE = VIH, VOUT = Vss to VCC Com'l/ Ind. -5 5 A VIL Input Low Voltage -0.3(1) 0.8 V VIH Input High Voltage 2.2 Vcc + 0.3 V VOL Output Low Voltage IOL = 8 mA, VCC = Min. -- 0.4 V VOH Output High Voltage IOH = -4 mA, VCC = Min. 2.4 -- V 9 10 11 NOTE:1.Undershoots to -3.0V for 10 ns are allowed once per cycle. 12 Rev. 1.0 - 7/24/96 7-19 PDM31516 Power Supply Characteristics -12 Symbol Parameter ICC Operating Current CE = VIL Com'l. 150 -15 -17 -20 Com'l Ind. Com'l Ind. Com'l Ind. 140 150 130 140 120 130 Unit mA f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH 40 35 35 35 35 30 30 mA 10 10 15 10 15 10 15 mA f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE VHC f=0 VCC = Max., VIN VCC - 0.2V or 0.2V NOTES: All values are maximum guaranteed values. VLC 0.2V, VHC VCC - 0.2V Capacitance(1) (TA = +25C, f = 1.0 MHz) Symbol Parameter CIN CI/O NOTE: Conditions Max. Unit Input Capacitance VIN = VSS 6 pF Output Capacitance VI/O = VSS 8 pF 1. This parameter is determined by device characterization, but is not production tested. AC Test Conditions Input pulse levels Input rise and fall times 2.5 ns Input timing reference levels 1.5V Output reference levels 1.5V Output load Figure 1. Output Load 7-20 VSS to 3.0V See Figures 1 and 2 Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE) Rev. 1.0 - 7/24/96 PDM31516 Read Cycle Timing Diagram(1) 1 2 3 4 5 6 AC Electrical Characteristics Description -12 READ Cycle -15 -17 -20 Symbol Min Max Min Max Min Max Min Max Unit READ cycle time tRC 12 -- 15 -- 17 -- 20 -- ns Address access time tAA -- 12 -- 15 -- 17 -- 20 ns Chip enable access time tACE -- 12 -- 15 -- 17 -- 20 ns Byte access time tBA -- 7 -- 8 -- 9 -- 9 ns Output hold from address change tOH 3 -- 3 -- 3 -- 3 -- ns Byte disable to output in low-Z tLZBE 0 -- 0 -- 0 -- 0 -- ns Byte enable to output in high-Z tHZBE -- 8 -- 9 -- 9 -- 7 ns Chip enable to output in low-Z(1) tLZCE 3 -- 3 -- 3 -- 3 -- ns Chip disable to output high-Z(1,2) tHZCE -- 7 -- 8 -- 9 -- 9 ns Output enable access time tAOE -- 7 -- 8 -- 9 -- 9 ns Output enable to output in low-Z tLZOE 1 -- 1 -- 1 -- 1 -- ns Output disable to output in high-Z(2) tHZOE -- 7 -- 8 -- 9 -- 9 ns NOTES: 1. 2. Rev. 1.0 - 7/24/96 7 8 9 10 11 At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. tHZCE, tHZOE, and tHZWE are specified with CL = 5 pF as in Figure 2. Transition is measured 200 mV from steady state voltage. 12 7-21 PDM31516 Write Cycle 1 Timing Diagram(5) (WE Controlled) Write Cycle 2 Timing Diagram(5) (CE Controlled) 7-22 Rev. 1.0 - 7/24/96 PDM31516 Write Cycle 3 Timing Diagram(5) (UB, LB Controlled) 1 2 3 4 5 6 AC Electrical Characteristics Description -12 WRITE Cycle Sym -15 -17 -20 WRITE cycle time tWC 12 -- 15 -- 17 -- 20 -- ns Chip enable to end of write tCW 10 -- 11 -- 11 -- 12 -- ns Address valid to end of write tAW 10 -- 11 -- 11 -- 12 -- ns Byte pulse width tBW 10 -- 12 -- 12 -- 13 -- ns Address setup time tAS 0 -- 0 -- 0 -- 0 -- ns Address hold from end of write tAH 0 -- 0 -- 0 -- 0 -- ns Write pulse width tWP 8 -- 9 -- 9 -- 10 -- ns Data setup time tDS 7 -- 8 -- 9 -- 9 -- ns Data hold time tDH 0 -- 0 -- 0 -- 0 -- ns Byte disable to output in low Z(4,5) tLZBE 1 -- 1 -- 1 -- 1 -- ns Byte enable to output in high Z(4,5) tHZBE -- 7 -- 8 -- 8 -- 9 ns Output disable to output in low Z(4,5) tLZOE 0 -- 0 -- 0 -- 0 -- ns Output enable to output in high Z(4,5) tHZOE -- 7 -- 8 -- 8 -- 9 ns Write disable to output in low Z(4,5) tLZWE 1 -- 1 -- 1 -- 1 -- ns Z(4,5) tHZWE -- 7 -- 8 -- 8 -- 9 ns Write enable to output in high 7 Min. Max. Min. Max. Min. Max. Min. Max. Unit 8 9 10 11 12 Rev. 1.0 - 7/24/96 7-23 PDM31516 NOTES: 1. The operating temperature (TA) is guaranteed with transverse air flow exceeding 400 linear feet per minute. 2. WE is HIGH for read cycles. 3. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high impedance state. 4. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high impedance state. 5. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period. 6. The following parameters are measured using the load shown in Figures 1 and 2. (A) tCOE, tOEE, tBE, tOEW .....Output Enable Time (B) tCOD, tODO, tBD, tODW ....Output Disable Time Ordering Information 7-24 Rev. 1.0 - 7/24/96