OKI Semiconductor MSC23136C/CL-xxBS10/DS10 1,048,576-Word x 36-Bit DRAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The OKI MSC23136C/CL-xxBS510/DS10 is a fully decoded 1,048,576-word x 36-bit CMOS Dynamic Random Access Memory Module composed of eight 4-Mb DRAMs (1M x 4) in SO] packages and two 2-Mb DRAMs (1M x 2) in SOJ packages mounted with ten decoupling capacitors on a 72-pin glass epoxy single-inline package. This module is generally used for memory expansion in parity applications such as workstations. The low-power version (CL) offers reduced power consumption for mobile computing applications like laptops and palmtops. FEATURES * 1-Meg x 36-bit organization * 72-Pin Socket Insertable Module MS$C23136C/CL-xxBS10 : Gold tab MSC23136C/CL-xxDS10: Solder tab * Single 5 V supply +10% tolerance * Access times : 60, 70, 80 ns *Input : TTL compatible * Output : TTL compatible, 3-state * Refresh : 1024 cycles/16 ms (128 ms : L-version) * CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability * Multi-bit test mode capability * Fast Page Mode capability PRODUCT FAMILY Family Access Time (Max.) Cycle Time Power Dissipation trac | taa tcac (Min.} [Operating (Max.}| Standby (Max.) MSC23136C/CL-60BS10/DS10 | 6Ons | 30ns | 151s 110 ns 5280 mW 55 mW/ MSC23136C/CL-70BS10/DS10 | 7Ons | 35ns | 20ns 130 ns _ 4730 mw 9.9 mW (L-version) MSC23136C/CL-B0BS10/DS10 | 80ns | 40ns | 20ns 150 ns 4180 mW 153MSC23136C/CL-xxBS10/DS10 OKA Semiconductor PIN CONFIGURATION MSC23136C/CL-xxBS10/DS10 4 107.95 20.2 9.28 May. 3.38 0.2 101.19 Typ. 2 Oo 1 im) 703 oOo oo oil $3.18 ; 5 TYP.) typt 1) 4 a 10.16 antl 1 72) 3.7 Min, 2.03 Typ. R157 t 95.25 *1 The common size difference of the board width 12.5 mm of its height is specified as 0.2. The value above 12.5 mm is specified as +0.5. Pin No. |Pin Name| | Pin No. (Pin Name! | Pin No. |Pin Name] | Pin No. |Pin Name} | Pin No. |Pin Name 1 Vss 16 Ad 31 AB 46 NG 61 DaQ14 2 Dad 17 AS 32 AS 47 WE 62 DQ33 3 DQ18 18 AG 33 NC 48 NC 63 0015 4 pai 19 NC 34 RAS2 49 pag 64 DQa34 Da19 20 pa4 35 DQ26 50 0027 65 DQ16 6 DQ2 21 DQ22 36 Das 51 pa10 66 NC 7 baz0 22 DQ5 37 DQt7 52 0028 67 PDI 8 DQ3 23 023 38 DQ35 3 0a1 68 PO2 9 DQ21 24 DO6 39 Vss 54 D0Q29 69 PD3 10 Vee 25 DO24 40 ASO 55 Dai2 70 PDA 11 NC 26 DQ? 41 CAS2 56 Da30 71 NG 12 AO 27 one25 42 CASS 57 DQ13 72 Vss 13 Al 28 A7 43 CAST 58 DQ31 14 A2 29 NC 44 ASQ 59 Veo 15 Ag 30 Voc 45 NC 60 DQ32 Presence Detect Pins 67 POI Vss Vss Vss 68 PD2 Vss Vss Vss 69 PD3 NC Vss NC 70 PD4 NC NC Vss 154OKI Semiconductor BLOCK DIAGRAM AQ - A9 WE ao-ag DQ F- Da0 Ao-ag 00 DQ FAST RAS og poe RAS2 RAS 0g (ozo CASO CAS a CAS? CAS a WE DQ DQ3 WE Da 60021 OE |. OE Veo Vg, iL Vee Vsg IS @| Ao-ag DG f 004 Ap-ag DO |-- 0022 RAS DO -- DOs HAS BO + 0023 DQ DO6 00 + D024 a pa + 007 os 00 | pas UE OE Veco Vg IL Veo Vsg @ AO-A9 DQ + DO8 AQ-A9 DQ +- DG26 RAS = DO } DQ17 RAS 00 + 0035 CAS CASI CAS2 CAS2 WE TE WE tL Veo Vss 7 Veco Vss Ib fue 8, wo oe as bad - 0d11 ne 6o | Dd29 WE DQ + 0412 We Da } DdO30 OE GE Voc Vss Ib Vec Vss Ib LJ AQ-A9 bo + Dats AQ- AS 00 -- 0O31 L__| wag Da | Dda14 RAE DO } 0032 one BEB am LL ies BP We OE WE Vec Vss Ib "| Veo Vss ID Veco # a a> cid Vs + + MSC231436C/CL-xxBS10/DS10 155MSC23136C/CL-xxBS10/DS10 OKI Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symboi Rating Unit Voltage on Any Pin Relative to Vss Vin. Vout -1.0 to 7.0 Vv Voltage Vcc Supply Relative to Vss Vec -1.0t07.0 V Short Circuit Output Current los 50 mA Power Dissipation Pp 10 Ww Operating Temperature Topr Oto 70 C Storage Temperature Tstg 40 to 125 C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (Ta =0C to 70C) Parameter Symbol Min. Typ. Max. Unit Vee 4.5 5.0 5.5 Vv Power Supply Voltage Ves 0 0 0 V input High Voltage Vin 24 ~ 6.5 V input Low Voltage Vit -1.0 _ 0.8 Vv CapacitanceCapacitance (Ta = 25C, f= 1 MH2) Parameter Symbot Typ. Max. Unit input Capacitance {AQ - A9) Cint 70 pF Input Capacitance (WE) Cinz 80 pF Input Capacitance (RASO, RAS2) Cina 43 pF Input Capacitance (CASO - CA53) Cina _ 24 pF /0 Capacitance (DQ0 - 0035) Coa _ 13 oF Note: Capacitance measured with Boonton Meter. 156OKI Semiconductor MSC23136C/CL-xxBS10/DS10 Dc Characteristics (cc = 5 V 210%, Ta = 0C to 70C) MSC23136C/CL|MSC23136C/CL|MSC23136C/CL Parameter Symbot Condition -60BS10/DS10 | -70BS10/DS10} -808S10/DS10| Unit |Note Min. } Max.| Min. | Max.) Min. | Max. OVSViS6.5V; Input Leakage Current Ii | Allother pins not | -100 ) 100 | -100 | 100 | -100| 1400 | pA under test = OV Output Leakage Current | Ig | Dour sable -10 | 10 | -10 | 10 | -10] 10 | pa OVEVoe55V Output High Voltage Von | loo = -5.0 mA 2.4 Vee 2.4 | Vee 24 ) Veco} V Output Low Voltage Vor | lop =4.2 mA 0 0.4 0 0.4 0 0.4 Vv Average Power . Supply Current lcor | RAS: CAS cycling. |_| ogo | | aso | | 760 | mal 1.2 , tre = Min. (Operating) Power Supply RAS, CAS =Vin _ 20 _ 20 _ 20 | mA} 1 Current (Standby) lcco | RAS, GAS _ 10 _ 10 _ 10 | mA; 1 2Vec-0.2V _ 1.8 _ 18 _ 1.8 | mA; 1,5 Average Power RAS cycling, Supply Current leca | CAS = Vin, | 960 | | 860 | | 760 | mA; 1,2 (RAS-only Refresh) tac = Min. Average Power RAS cycling, Supply Current Ioce | CAS betore RAS, | 960 | | 860 | 760 | mA] 1,2 (CAS before RAS Refresh) tre = Min. Average Power RAS = Vit, Supply Current lcc7 | CAS cycling, | 760} | 670 | | 580 |] mA/ 1,3 (Fast Page Mode) tec = Min. Average Power tac = 125 us, 12 Suppty Current lec1o | CAS before _ 3 3 _ 3 | mA 4 5 (Battery Backup) RAS cycling Notes: 1. Specified values are obtained with the output open. - ae wn L-version. Address can be changed once or less while RAS=Vj,. Address can be changed once or less while CAS=Vjq1. Veco -0.2V Vip $65 V,-10V SV S02 V. 157MSC23136C/CL-xxBS10/DS10 OKI Semiconductor AC Characteristics (1/2) (Voc = 5 V 210%, Ta = OC ta 70C) Note 1,2,3,9,10 MSC23136C/CL| MSC 23136C/CL|MSC23136C/CL Parameter Symbol) -60BS10/DS10| -70BS10/DS10 | -808S10/DS10| Unit} Note Min. | Max. | Min. | Max. | Min. | Max. Random Read or Write Cycle Time tac | 110 _ 130 _ 150 _ ns | Fast Page Mode Cycle Time tec 40 45 50 _ ns Access Time from RAS trac | 60 _ 70 _ 80 ns 145.6 Access Time from CAS. teac | 15 20 20 | as | 4,5 Access Time from Column Address ta | 30 _ 35 _ 40 ns | 4,6 Access Time from CAS Precharge tcpa | 35 _ 40 _ 45 ng 4 Output Low Impedance Time fram CAS teL2 0 0 _ 0 |ns| 4 Output Butter Turn-oft Delay Time torr 0 15 0 20 0 20 j ns| 7 Transition Time tr 3 50 3 50 3 50 ns 3 Refresh Period trer _ 16 _ 16 _ 16 ms Refresh Period (L-version) ther | 128 | 128 | 128 | ms RAS Precharge Time tap | 40 50 60 | ns RAS Pulse Width tras | 60 10K 70 10K 80 10K | as RAS Pulse Width (Fast Page Mode) trase | 60 | 100K | 70 | 100K | 80 | 100K | as RAS Hold Time tase | 15 _ 20 20 | ns CAS Precharge Time tep 10 = 10 10 ~ ns CAS Pulse Width teas | 15 10K | 20 10K | 20 | 10K | ns CAS Hold Time tesH 60 _ 70 _ 80 _ ns GAS to RAS Precharge Time tere | 5 _ 5 _ 5 | ns RAS to CAS Delay Time taco | 20 45 20 50 20 60 ns 5 RAS to Column Address Detay Time trap | 15 30 15 35 15 40 ns 6 Row Address Set-up Time tasr 0 ~_ 0 _ 0 _ ns Row Address Hold Time tray 10 _ 10 _ 10 _ ns Column Address Set-up Time tasc 0 _ 0 0 ns Column Address Hold Time teany | 15 18 16 _ ns Column Address Hold Time from RAS tar 50 _ 55 60 ns Column Address to RAS Lead Time tra | 30 _ 35 _~ 40 | ons 158OE I Semiconductor AC Characteristics (2/2) MSC23136C/CL-xxBS10/DS10 Veco =5 V 210%, Ta=OC to 70C) Note 1,2,3,9,10 MSC23136C/CLIMSC23136C/CL MSC23136C/CL Parameter Symbol; -60BS10/DS10 | -708$10/DS$10 | -60BS10/DS10 | Unit | Note Min. | Max.| Min. | Max.) Min. | Max. Read Command Set-up Time tracs 0 _ 0 _ 0 _ rs | Read Command Hold Time taco 0 _ 0 _ 0 _ ns 8 Read Command Hold Time referenced to RAS | tary 0 _ 0 _ 0 _ ns 8 Write Command Set-up Time twes _ 0 _ 0 ins Write Command Hold Time tweu 10 _ 10 _ 10 _ ns Write Command Hold Time from RAS twen | 45 _ 50 60 - | ons Write Command Pulse Width twp 10 _ 10 _ 10 ns Write Command to RAS Lead Time taw. | 15 20 _ 20 | ns Write Command to CAS Lead Time tow. | 15 _ 20 = 20 | ns Data-in Set-up Time tos 0 _ 0 _ q _ ns Data-in Hold Time tou 15 15 _ 15 | ns Data-in Hold Time from RAS tona | 50 | 55 60 |} _s CAS Active Delay Time from RAS Precharge| tapc 5 _ 5 5 | ns RAS to CAS Set-up Time (CAS before RAS} tesa 5 5 5 {ns RAS to CAS Hold Time (CAS before RAS} | toun | 10 | 10 10 | | #s CAS Precharge Time (Refresh Counter Test)| topt 30 _ 35 _ 40 _ ns WE to RAS Precharge Time (CAS before RAS)! twap | 10 10 _ 10 | ns WE Hold Time from RAS (CAS before RAS) tway ; 10 ]}] 10 10 | | os RAS to WE Set-up Time {Test Mode) twrs | 10 10 10 | os RAS to WE Hold Time (Test Mode) twrH | 10 10 10 | ns 159MSC23136C/CL-xxBS10/DS10 OKI Semiconductor Notes: 160 1. 10. A start-up delay of 200 pts is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. _ When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. AC mesurement assume ty = 5 ns. Ving (Min.} and Vj, (Max.) are reference levels for measuring input timing signals. Transition times are measured between Vip and Vj_. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. Operation within the tpcp (Max.) limit ensures that trac (Max.) can be met. trpcp (Max.) is specified as a reference point only. If tpcpis greater than the specified tpcp (Max.) limit, access time is controlled by tcac. Operation within the trap (Max.) limit ensures that trac (Max.) can be met. trap (Max.) is specified as a reference point only. Iftpapis greater than the specified trap (Max.) limit, access time is controlled by taa. torr (Max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels. trcH OF trrH must be satisfied for a read cycle. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This made is latched and remains in effect until the exit cycle is generated. In a test mode CAO is not used and each DQ pin now accesses 2 bit locations. Ina read cycle, if the 2 data bits are equal, the DQ pin will indicate a high level. If the 2 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. Ina test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. See ADDENDUM E for AC Timing Waveforms