CAT5241WI-10 - Catalyst Semiconductor, Inc.

DESCRIPTION

The CAT5241 is four Digitally Programmable

Potentiometers (DPPs™) integrated with control logic

and 16 bytes of NVRAM memory. Each DPP consists of

a series of 63 resistive elements connected between two

externally accessible end points. The tap points between

each resistive element are connected to the wiper outputs

with CMOS switches. A separate 6-bit control register

(WCR) independently controls the wiper tap switches for

each DPP. Associated with each wiper control register

are four 6-bit non-volatile memory data registers (DR)

used for storing up to four wiper settings. Writing to the

wiper control register or any of the non-volatile data

CAT5241

Quad Digitally Programmable Potentiometers (DPP™)

with 64 Taps and 2-wire Interface

FEATURES

■ Four linear-taper digitally programmable

potentiometers

■64 resistor taps per potentiometer

■End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ

■Potentiometer control and memory access via

2-wire interface (I2C like)

■Low wiper resistance, typically 80ΩΩ

ΩΩ

Ω

■Nonvolatile memory storage for up to four wiper

settings for each potentiometer

■Automatic recall of saved wiper settings at

power up

■2.5 to 6.0 volt operation

■Standby current less than 1µA

■1,000,000 nonvolatile WRITE cycles

■100 year nonvolatile memory data retention

■20-lead SOIC and TSSOP packages

■Industrial temperature range

PIN CONFIGURATION FUNCTIONAL DIAGRAM

Characteristics subject to change without notice Document No. 2011, Rev. J

registers is via a 2-wire serial bus (I2C-like). On power-

up, the contents of the first data register (DR0) for each

of the four potentiometers is automatically loaded into its

respective wiper control register (WCR).

The CAT5241 can be used as a potentiometer or as a

two terminal, variable resistor. It is intended for circuit

level or system level adjustments in a wide variety of

applications.

H1 H2 H3

R RR

L0 L1 L2 L3

R RR

WIPER

CONTROL

REGISTERS

NONVOLATILE

DATA

REGISTERS

2-WIRE BUS

INTERFACE

CONTROL

LOGIC

SCL

SDA

CAT

5241

RW0

RL0

RH0

RW1

RL1

RH1

SDA

GND

VCC

RW3

RL3

RH3

SCL

RW2

RL2

RH2

SOIC Package (J, W)

TSSOP Package (U, Y)

CAT5241

Document No. 2011, Rev. J

PIN DESCRIPTION

(SOIC) Name Function

W0 Wiper Terminal for Potentiometer 0

L0 Low Reference Terminal for Potentiometer 0

H0 High Reference Terminal for Potentiometer 0

4 A0 Device Address, LSB

5 A2 Device Address

W1 Wiper Terminal for Potentiometer 1

L1 Low Reference Terminal for Potentiometer 1

H1 High Reference Terminal for Potentiometer 1

9 SDA Serial Data Input/Output

10 GND Ground

11 RH2 High Reference Terminal for Potentiometer 2

12 RL2 Low Reference Terminal for Potentiometer 2

13 RW2 Wiper Terminal for Potentiometer 2

14 SCL Bus Serial Clock

15 A3 Device Address

16 A1 Device Address

17 RH3 High Reference Terminal for Potentiometer 3

18 RL3 Low Reference Terminal for Potentiometer 3

19 RW3 Wiper Terminal for Potentiometer 3

20 VCC Supply Voltage

PIN DESCRIPTIONS

SCL: Serial Clock

The CAT5241 serial clock input pin is used to clock

all data transfers into or out of the device.

SDA: Serial Data

The CAT5241 bidirectional serial data pin is used

to transfer data into and out of the device. The

SDA pin is an open drain output and can be wire-

or'd with the other open drain or open collector

outputs.

A0, A1, A2, A3: Device Address Inputs

These inputs set the device address when ad-

dressing multiple devices. A total of sixteen

devices can be addressed on a single bus. A

match in the slave address must be made with the

address input in order to initiate communication

with the CAT5241.

RH, RL:Resistor End Points

The four sets of RH and RL pins are equivalent to

the terminal connections on a mechanical potenti-

ometer.

RW:Wiper

The four RW pins are equivalent to the wiper

terminal of a mechanical potentiometer.

DEVICE OPERATION

The CAT5241 is four resistor arrays integrated with 2-

wire serial interface logic, four 6-bit wiper control registers

and sixteen 6-bit, non-volatile memory data registers.

Each resistor array contains 63 separate resistive

elements connected in series. The physical ends of

each array are equivalent to the fixed terminals of a

mechanical potentiometer (RH and RL). RH and RL are

symmetrical and may be interchanged. The tap positions

between and at the ends of the series resistors are

connected to the output wiper terminals (RW) by a

CMOS transistor switch. Only one tap point for each

potentiometer is connected to its wiper terminal at a time

and is determined by the value of the wiper control

registers or the non-volatile memory data registers via

the 2-wire bus. Additional instructions allow data to be

transferred between the wiper control registers and

each respective potentiometer's non-volatile data

registers. Also, the device can be instructed to operate

in an "increment/decrement" mode.

CAT5241

Document No. 2011, Rev. J

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ..................-55°C to +125°C

Storage Temperature........................-65°C to +150°C

Voltage on any Pin with

Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V

VCC with Respect to Ground ................ -2.0V to +7.0V

Package Power Dissipation

Capability (TA = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs)............ 300°C

Wiper Current.................................................. +12mA

Notes:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.

Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any

other conditions outside of those listed in the operational sections

of this specification is not implied. Exposure to any absolute

maximum rating for extended periods may affect device perfor-

mance and reliability.

Notes:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(4) LSB = RTOT / 63 or (RH - RL) / 63, single pot

(5) n = 0, 1, 2, ..., 63

Recommended Operating Conditions:

VCC = +2.5V to +6.0V

Temperature Min Max

Industrial -40°C85°C

POTENTIOMETER CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Test Conditions Min Typ Max Units

RPOT Potentiometer Resistance (-00)100 kΩ

RPOT Potentiometer Resistance (-50)50 kΩ

RPOT Potentiometer Resistance (-10)10 kΩ

RPOT Potentiometer Resistance (-25)2.5 kΩ

Potentiometer Resistance +20 %

Tolerance

RPOT Matching 1 %

Power Rating 25°C, each pot 50 mW

IWWiper Current +6 mA

RWWiper Resistance IW = +3mA @ VCC =3V 300 Ω

RWWiper Resistance IW = +3mA @ VCC = 5V 80 150 Ω

VTERM Voltage on any RH or RL Pin VSS = 0V GND VCC V

VNNoise (1) TBD nV/ Hz

Resolution 1.6 %

Absolute Linearity (2) Rw(n)(actual)-R(n)(expected)(5) +1 LSB (4)

Relative Linearity (3) Rw(n+1)-[Rw(n)+LSB](5) +0.2 LSB (4)

TCRPOT Temperature Coefficient of RPOT (1) +300 ppm/°C

TCRATIO Ratiometric Temp. Coefficient (1) 20 ppm/°C

CH/CL/CWPotentiometer Capacitances (1) 10/10/25 pF

fc Frequency Response RPOT = 50kΩ(1) 0.4 MHz

CAT5241

Document No. 2011, Rev. J

Symbol Parameter Min Typ Max Units

fSCL Clock Frequency 400 kHz

TI(1) Noise Suppression Time Constant at SCL, SDA Inputs 50 ns

tAA SLC Low to SDA Data Out and ACK Out 0.9 µs

tBUF(1) Time the Bus Must be Free Before a New 1.2 µs

Transmission Can Start

tHD:STA Start Condition Hold Time 0.6 µs

tLOW Clock Low Period 1.2 µs

tHIGH Clock High Period 0.6 µs

tSU:STA Start Condition SetupTime (For a Repeated Start Condition) 0.6 µs

tHD:DAT Data in Hold Time 0 ns

tSU:DAT Data in Setup Time 100 ns

tR(1) SDA and SCL Rise Time 0.3 µs

tF(1) SDA and SCL Fall Time 300 ns

tSU:STO Stop Condition Setup Time 0.6 µs

tDH Data Out Hold Time 50 ns

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

CAPACITANCE

TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Conditions Min Typ Max Units

CI/O(1) Input/Output Capacitance (SDA) VI/O = 0V 8 pF

CIN(1) Input Capacitance (A0, A1, A2, A3, SCL) VIN = 0V 6 pF

POWER UP TIMING (1)

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Min Typ Max Units

tPUR Power-up to Read Operation 1 ms

tPUW Power-up to Write Operation 1 ms

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Test Conditions Min Typ Max Units

ICC Power Supply Current fSCL = 400kHz 1 mA

ISB Standby Current (VCC = 5.0V) VIN = GND or VCC; SDA Open 1 µA

ILI Input Leakage Current VIN = GND to VCC 10 µA

ILO Output Leakage Current VOUT = GND to VCC 10 µA

VIL Input Low Voltage -1 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 1.0 V

VOL1 Output Low Voltage (VCC = 3.0V) IOL = 3 mA 0.4 V

A.C. CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

CAT5241

Document No. 2011, Rev. J

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tFtLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

Figure 1. Bus Timing

tWR

STOP

CONDITION START

CONDITION ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

Figure 2. Write Cycle Timing

START BIT

SDA

STOP BIT

SCL

Figure 3. Start/Stop Timing

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Min Typ Max Units

tWR Write Cycle Time 5 ms

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,

the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter Reference Test Method Min Typ Max Units

NEND(1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

TDR(1) Data Retention MIL-STD-883, Test Method 1008 100 Years

VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA

CAT5241

Document No. 2011, Rev. J

SERIAL BUS PROTOCOL

The following defines the features of the 2-wire bus

protocol:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high will

be interpreted as a START or STOP condition.

The device controlling the transfer is a master,

typically a processor or controller, and the device

being controlled is the slave. The master will always

initiate data transfers and provide the clock for both

transmit and receive operations. Therefore, the

CAT5241 will be considered a slave device in all

applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT5241 monitors the

SDA and SCL lines and will not respond until this

condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address of

the particular slave device it is requesting. The four most

significant bits of the 8-bit slave address are fixed as

0101 for the CAT5241 (see Figure 5). The next four

significant bits (A3, A2, A1, A0) are the device address

bits and define which device the Master is accessing. Up

to sixteen devices may be individually addressed by the

system. Typically, +5V and ground are hard-wired to

these pins to establish the device's address.

After the Master sends a START condition and the slave

address byte, the CAT5241 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address.

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The

Acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data.

The CAT5241 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation,

it responds with an acknowledge after receiving each

8-bit byte.

When the CAT5241 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for

an acknowledge. Once it receives this acknowledge, the

CAT5241 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

ACKNOWLEDGE

START

SCL FROM

MASTER 89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 4. Acknowledge Timing

5020 FHD F06

CAT5241

Document No. 2011, Rev. J

WRITE OPERATIONS

In the Write mode, the Master device sends the START

condition and the slave address information to the Slave

device. After the Slave generates an acknowledge, the

Master sends the instruction byte that defines the

requested operation of CAT5241. The instruction byte

consist of a four-bit opcode followed by two register

selection bits and two pot selection bits. After receiving

another acknowledge from the Slave, the Master device

transmits the data to be written into the selected register.

The CAT5241 acknowledges once more and the Master

generates the STOP condition, at which time if a non-

volatile data register is being selected, the device begins

an internal programming cycle to non-volatile memory.

While this internal cycle is in progress, the device will not

respond to any request from the Master device.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host's write operation,

the CAT5241 initiates the internal write cycle. ACK

polling can be initiated immediately. This involves issuing

the start condition followed by the slave address. If the

CAT5241 is still busy with the write operation, no ACK

will be returned. If the CAT5241 has completed the write

operation, an ACK will be returned and the host can then

proceed with the next instruction operation.

Figure 6. Write Timing

Figure 5. Slave Address Bits

0 1 0 1 A3 A2 A1 A0

CAT5241

* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

DR WCR DATA

BUS A CTIVITY :

MASTER

SDA LINE

SLAVE/DPP

ADDRESS

INSTRUCTION

BYTE

Fixed Variable op code

Data Register

Address

Pot/WCR

Address

CAT5241

Document No. 2011, Rev. J

INSTRUCTION AND REGISTER

DESCRIPTION

SLAVE ADDRESS BYTE

The first byte sent to the CAT5241 from the master/

processor is called the Slave/DPP Address Byte. The

most significant four bits of the slave address are a

device type identifier. These bits for the CAT5241 are

fixed at 0101[B] (refer to Table 1).

The next four bits, A3 - A0, are the internal slave address

and must match the physical device address which is

defined by the state of the A3 - A0 input pins for the

CAT5241 to successfully continue the command

sequence. Only the device which slave address matches

the incoming device address sent by the master executes

the instruction. The A3 - A0 inputs can be actively driven

by CMOS input signals or tied to VCC or VSS.

INSTRUCTION BYTE

The next byte sent to the CAT5241 contains the instruction

and register pointer information. The four most significant

bits used provide the instruction opcode I [3:0]. The P1

and P0 bits point to one of four Wiper Control Registers.

The least two significant bits, R1 and R0, point to one of

the four data registers of each associated potentiometer.

The format is shown in Table 2.

Table 1. Identification Byte Format

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Device Type

Identifier Slave Address

Table 2. Instruction Byte Format

I3 I2 I1 I0 R1 R0

P1 P0

(MSB) (LSB)

Instruction Data Register

WCR/Pot Selection

Opcode Selection

Data Register Selected R1 R0

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

Data Register Selection

CAT5241

Document No. 2011, Rev. J

Table 3. Instruction Set

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5241 contains four 6-bit Wiper Control Registers,

one for each potentiometer. The Wiper Control Register

output is decoded to select one of 64 switches along its

resistor array. The contents of the WCR can be altered

in four ways: it may be written by the host via Write Wiper

Control Register instruction; it may be written by

transferring the contents of one of four associated Data

Registers via the XFR Data Register instruction, it can be

modified one step at a time by the Increment/decrement

instruction (see Instruction section for more details).

Finally, it is loaded with the content of its data register

zero (DR0) upon power-up.

The Wiper Control Register is a volatile register that

loses its contents when the CAT5241 is powered-down.

Although the register is automatically loaded with the

value in DR0 upon power-up, this may be different from

the value present at power-down.

Data Registers (DR)

Each potentiometer has four 6-bit non-volatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Control

is a non-volatile operation and will take a maximum of

5ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can be

used as standard memory locations for system

parameters or user preference data.

INSTRUCTIONS

Four of the nine instructions are three bytes in length.

These instructions are:

—Read Wiper Control Register - read the current

wiper position of the selected potentiometer in the WCR

—Write Wiper Control Register - change current

wiper position in the WCR of the selected potentiometer

—Read Data Register - read the contents of the

selected Data Register

—Write Data Register - write a new value to the

selected Data Register

The basic sequence of the three byte instructions is

illustrated in Figure 8. These three-byte instructions

Note: 1/0 = data is one or zero

Instruction

Instruction Set

OperationI3 I2 I1 I0 R1 R0

Read Wiper Control

Write Wiper Control Register 1010 0 0 Write new value to the Wiper Control

Read Data Register 1011 1/01/0Read the contents of the Data Register

pointed to by P1-P0 and R1-R0

Write Data Register 1100 1/01/0Write new value to the Data Register

pointed to by P1-P0 and R1-R0

XFR Data Register to Wiper

Control Register 1101 1/01/0Transfer the contents of the Data Register

pointed to by P1-P0 and R1-R0 to its

associated Wiper Control Register

XFR Wiper Control Register

to Data Register 1110 1/01/0Transfer the contents of the Wiper Control

Global XFR Data Registers

to Wiper Control Registers 0001 1/01/0Transfer the contents of the Data Registers

pointed to by R1-R0 of all four pots to their

respective Wiper Control Registers

Global XFR Wiper Control

Registers to Data Register 1000 1/01/0Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1-R0 of all four pots

Increment/Decrement Wiper

Control Register 0010 0 0 Enable Increment/decrement of the Control

Latch pointed to by P1-P0

WCR1/

1/0 1/0

WCR0/

CAT5241

Document No. 2011, Rev. J

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper.

The response of the wiper to this action will be delayed

by tWRL. A transfer from the WCR (current wiper position),

to a Data Register is a write to non-volatile memory and

takes a minimum of tWR to complete. The transfer can

occur between one of the four potentiometers and one

of its associated registers; or the transfer can occur

between all potentiometers and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 7. These instructions

transfer data between the host/processor and the

CAT5241; either between the host and one of the data

registers or directly between the host and the Wiper

Control Register. These instructions are:

—XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

—XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated

Data Register.

—Global XFR Data Register to Wiper

Control Register

This transfers the contents of all specified Data

Registers to the associated Wiper Control

Registers.

—Global XFR Wiper Counter Register to

Data Register

This transfers the contents of all Wiper Control

Registers to the specified associated Data

Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5

and 9). The Increment/Decrement command is different

from the other commands. Once the command is issued

and the CAT5241 has responded with an acknowledge,

the master can clock the selected wiper up and/or down

in one segment steps; thereby providing a fine tuning

capability to the host. For each SCL clock pulse (tHIGH)

while SDA is HIGH, the selected wiper will move one

resistor segment towards the RH terminal. Similarly, for

each SCL clock pulse while SDA is LOW, the selected

wiper will move one resistor segment towards the RL

terminal.

See Instructions format for more detail.

Figure 7. Two-Byte Instruction Sequence

Figure 8. Three-Byte Instruction Sequence

Figure 9. Increment/Decrement Instruction Sequence

0101

A2 A0 A

I2 I1 I0 R1 R0 A

SDA

ID3 ID2 ID1 ID0

Device ID Internal Instruction

Opcode

Address Register

Address

P1 P0

Pot/WCR

Address

A3 I3

I3 I2 I1 I0

ID3 ID2 ID1ID0

Device ID Internal Instruction

Opcode

Address Data

Address

0101

A2 A1 A0 A

Pot/WCR

Address

P1 P0 A

SDA

I3 I2 I1 I0 R1 R0

ID3 ID2

ID1

ID0

Device ID Internal Instruction

Opcode

Address Data

Address

WCR[7:0]

Data Register D[7:0]

0101

A2 A1 A0 A

KPot/WCR

Address

P1 P0 A

SDA

D7 D6 D5 D4 D3 D2 D1 D0

CAT5241

Document No. 2011, Rev. J

Figure 10. Increment/Decrement Timing Limits

INSTRUCTION FORMAT

Read Wiper Control Register (WCR)

Write Wiper Control Register (WCR)

Read Data Register (DR)

Write Data Register (DR)

SCL

SDA

INC/DEC

Command

Issued

Voltage Out

WRID

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A3A2A1A0 1 0 0 1 P1 P0 0 0 7 6 5 4 3 2 1 0

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A3 A2 A1 A0 1 0 1 1 P1 P0 R1 R0 7 6 5 4 3 2 1 0

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A3 A2 A1 A0 1 1 0 0 P1 P0 R1 R0 7 6 5 4 3 2 1 0

DEVICE ADDRESSES INSTRUCTION DATA

0 1 0 1 A3A2A1A0 1 0 1 0 P1 P0 0 0 7 6 5 4 3 2 1 0

CAT5241

Document No. 2011, Rev. J

DEVICE ADDRESS INSTRUCTION

0 1 0 1 A3 A2 A1 A0 1 1 1 0 P1 P0 R1R0

DEVICE ADDRESS INSTRUCTION

0 1 0 1 A3A2A1A0 10 00 00R1R0

Global Transfer Wiper Control Register (WCR) to Data Register (DR)

INSTRUCTION FORMAT (continued)

Transfer Wiper Control Register (WCR) to Data Register (DR)

Transfer Data Register (DR) to Wiper Control Register (WCR)

Increment (I)/Decrement (D) Wiper Control Register (WCR)

Notes:

(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.

Global Transfer Data Register (DR) to Wiper Control Register (WCR)

DEVICE ADDRESS INSTRUCTION

0 1 0 1 A3 A2 A1 A0 0 0 0 1 0 0 R1R0

DEVICE ADDRESS INSTRUCTION

0 1 0 1 A3 A2 A1 A0 1 1 1 0 P1 P0 R1R0

DEVICE ADDRESS INSTRUCTION DATA

0 1 0 1 A3 A2 A1 A0 0 0 1 0 P1P0 0 0 I/D I/D I/D I/D

• • •

CAT5241

Document No. 2011, Rev. J

Notes:

(1) The device used in the above example is a CAT5241JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel)

ORDERING INFORMATION

-10

-25: 2.5kohm

-10: 10kohm

-50: 50kohm

-00: 100kohm

5241

U: TSSOP

W: SOIC (Lead free, Halogen free)

Y: TSSOP (Lead free, Halogen free)

CAT5241

Document No. 2011, Rev. J

20-LEAD 300 MIL WIDE SOIC (J, W)

0.2914 (7.40)

0.2992 (7.60) 0.394 (10.00)

0.419 (10.65)

0.0926 (2.35)

0.1043 (2.65)

0.0040 (0.10)

0.0118 (0.30)

0.050 (1.27) BSC 0.013 (0.33)

0.020 (0.51)

0—8

0.0091 (0.23)

0.0125 (0.32)

0.010 (0.25)

0.029 (0.75) X 45

0.016 (0.40)

0.050 (1.27)

0.5985 (15.20)

0.6141 (15.60)

PACKAGING INFORMATION

CAT5241

Document No. 2011, Rev. J

20-LEAD 300 MIL WIDE TSSOP (U, Y)

1.0

A1 A2

θ2

0.20

R1 R

θ1

GAUGE PLANE

θ3L

DETAIL A

SECTION A-A

0.076MM

SEATING PLANE

DETAIL A

SYMBOL

θ1

θ2

θ3

REF

DIMENSION IN MM DIMENSION IN INCH

MIN MIN

NOM NOM

MAX MAX

1.20

0.15

1.05

0.75

6.60

6.50

4.50

0.30

0.25

0.20

0.16

0.05

0.80

0.50

6.40

6.30

4.30

0.09

0.19

0.09

0.90

0.60

6.50

6.40

4.40

0.22

.002

.031

.020

.252

.248

.169

.004

.007

.004

.035

.024

.256

.252

.173

.009

.043

.006

.041

.030

.260

.256

.177

.012

.010

.008

.006

1.0 REF

0.65 BSC .039 REF

.026 BSC

0808

12 REF

12 REF 12 REF

12 REF

JEDEC M0-153 VARIATION AC

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catalyst-semiconductor.com

Publication #: 2011

Revison: J

Issue date: 4/5/04

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™ DPPs ™ AE2 ™

I2C is a trademark of Philips Corporation

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

REVISION HISTORY

Date Rev. Reason

9/30/2003 G Deleted WP from Functional Diagram, pg. 1

3/3/2004 H Added TSSOP package in all areas

3/29/2004 I Eliminated data sheet designation

Eliminated Commercial temp range in all areas

Updated Absolute Max Ratings and Potentiometer

Characteristics notes

4/5/2004 J Corrected Potentiometer Resistance [Changed

(-2.5) to (-25)] in table