Features * Fast Read Access Time - 120 ns * Automatic Page Write Operation Internal Address and Data Latches for 128-Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 128-Byte Page Write Operation Low Power Dissipation 80 mA Active Current 300 pA CMOS Standby Current * Hardware and Software Data Protection DATA Poiling for End of Write Detection High Reliability CMOS Technology Endurance: 104 or 10 Cycles Data Retention: 10 Years Single 5V + 10% Supply * CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout Description The AT28C010 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmels advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 300 pA. (continued) Pin Configuration 32 LOC Pin Name | Function AO - A16 Addresses CE Chip Enable A14 DA13 OE Output Enable Daa FAQ WE Write Enable Hay oE O00 - VO7 | Data Inputs/Outputs Ber DCE NC No Connect bvo7 CERDIP, FLATPACK 44LC0C Top View Top View VY neq} a2 vec gegeeesueod PGA A162 31 0 WE . Ais3 30 FNC 8 $s % A13 Top View nade 29 A14 7] AB 4 3 1 7 26 Avs 280 A13 Ad neds o7H as Hatt AG | A7 | A14| WE | A13 asq7 26D ae HNc 5 | 2 | 26| 24 | 25 aca 25Hait ONG As | A12| VCC] Ao | AB Aas 2 poe DNC 7 6 | 29} 22 | 23 A210 23Pato DONG A3 | A4 | AtS| OE | A11 Aidit 220 CE DoE @ | a{ 30] 20 | 21 AOC 12 21 Phos AIO Ai | A2|A16/ CE} Ato voo 413 20 11 VO6 HCE 11] 10! 14] 16 | 49 voi 14 19 VOS vo2e Fj 15 18 vO4 = wos a GND C] 16 17 vos vo1| voz! vol vos | vos ay 1-Megabit (128K x 8) Paged Parallel EEPROMs AT28C010 Military Rev. 0010C10/98 3-127AIMEL The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writ- ing of up to 128-bytes simultaneously. During a write cycle, the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other opera- tions. Following the initiation of a write cycle, the device will automatically write the latched data using an internal con- trol timer. The end of a write cycle can be detected by Block Diagram DATA POLLING of 1/07. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmels 28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protec- tion mechanism is available to guard against inadvertent writes. The device also includes an extra 128-bytes of EEPROM for device identification or tracking. vcc + DATA INPUTS/OUTPUTS. GND > VOO - O07 teatetty 0E - WE _| OE, CE AND WE DATA LATCH LOGIC INPUT/OUTPUT cE BUFFERS I Y DECODER | Y-GATING ADDRESS __ | | INPUTS >| CELL MATRIX X DECODER IDENTIFICATION Absolute Maximum Ratings* Temperature Under Bias............ceceeeceen -55C to+125C | NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam- Storage Temperature 0... eee esnneees -65C to +150C age to the device. This is a stress rating only and functional operation of the device at these or any All Input Voltages other conditions beyond those indicated in the (including NC Pins) operational sections of this specification is not with Respect to Ground... eeeseseneer ree -0.6V to +6.25V implied. Exposure to absolute maximum rating conditions for extended periods may affect device All Output Voltages reliability. with Respect to Ground ..... cece -0.6V to Veg + 0.6V Voltage on OE and AQ with Respect to Ground oo... eee reeteee ree -0.6V to +13.5V 3-128 AT28C0O10 Mil mnmmmmmesneneeesmens A 1 2SC0 10 Nil Device Operation READ: The AT28C010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual- line control gives designers flexibility in preventing bus con- tention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a pro- gramming operation has been initiated and for the duration of two, a read operation will effectively be a polling opera- tion. PAGE WRITE: The page write operation of the AT28C010 allows 1 to 128-bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 addi- tional bytes. Each successive byte must be written within 150 Us (tai) of the previous byte. If the taro limit is exceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write opera- tion, A7 - A16 must be the same. The AO to AG inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing wili be written; unnec- essary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on 1/07. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling the AT28C010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in 1/O6 toggling between one and zero. Once the write has completed, /06 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- AIMEL tem power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C010 in the following ways: (a) Voc sense - if Voc is below 3.8V (typical) the write function is inhibited; (b) Voc power-on delay - once Voc has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controtled data protection feature has been implemented on the AT28C010. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after two the entire AT28C010 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28C010. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable com- mand sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of two, read operations will effectively be poll- ing operations. DEVICE IDENTIFICATION: An extra 128-bytes of EEPROM memory are available to the user for device iden- tification. By raising A9 to 12V + 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see Soft- ware Chip Erase application note for details. 3-129AIMEL DC and AC Operating Range AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25 Operating Mil. -55G - 125C -55C - 125C -55C - 125C -55C - 125C Temperature (Case) Voc Power Supply 5V 410% 5V + 10% 5V + 10% 5V + 10% Operating Modes Mode CE OE WE vo Read Vin Vit Vin Dour Write 2) Vi Vin Vie Dw Standby/Write Inhibit Vin x X High Z Write Inhibit xX x Vin Write Inhibit X Vic x Output Disable xX Vin x High Z Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms DC Characteristics Symbol Parameter Condition Min Max Units lu Input Load Current Vin = OV to Veg + 1V 10 pA lo Output Leakage Current Vyo = OV to Veg 10 pA Isp4 Veg Standby Current CMOS | CE = Veg - 0.3V to Veg + 1V 300 WA Isp2 Voc Standby Current TTL CE = 2.0V to Vog + 1V 3 mA lec Vec Active Current f = 5 MHZ; Ioyp = OMA 80 mA Vit Input Low Voltage 0.8 Vv Vin Input High Voltage 2.0 Vv Voi Output Low Voltage lo, = 2.4 mA 0.45 v Vout Output High Voltage loy = -400 PA 2.4 v Vous Output High Voltage CMOS | Igy =-100 WA; Veo = 4.5V 4,2 Vv 3-130 AT28C010 Mil seeees AT 28 C010 Mil AC Read Characteristics AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25 Symbol Parameter Min Max Min Max Min Max Min Max Units lace Address to Output Delay 120 150 200 250 ns tog CE to Output Delay 120 150 200 250 ns tog ? OE to Output Delay 0 50 55 0 55 0 55 ns toe 2? CE or GE to Output Float 50 55 55 55 ns ton Output Hold from OF, CE or 0 0 0 ns Address, whichever occurred first AC Read Waveforms) ADDRESS <[{_ ADDRESS VALID K CE 1tCcE > {OE > 1DF _ | l taco >} tOH > I OUTPUT HIGH 2 OUTPUT VALID >> Notes: 1. CE may be delayed up to tacg ~ tog after the address transition without impact on tacc. 2. OE may be delayed up to tog - tog after the falling edge of CE without impact on tog or by tace - tog after an address change without impact in tacc- 3. tpg is specified from OE or CE wichever occurs first (CL = 5 pF). 4, This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level 3.0V AC AC DRIVING MEASUREMENT LEVELS LEVEL 0.0V Pin Capacitance f= 1 MHz, T = 25C") Output Test Load 5.0V OUTPUT PIN Symbol Typ Max Units Conditions Ci 4 10 pF Vin = OV Cour 8 12 pF Vour = OV Note: 1. This parameter is 100% characterized and is not 100% tested. ATMEL 3-131AIMEL AC Write Characteristics Symbol Parameter Min Max Units twe Write Cycle Time 10 ms tas Address Set-up Time 0 ns tay Address Hold Time 50 ns tos Data Set-up Time 50 ns tou Data Hold Time 0 ns twe Write Pulse Width 100 ns tec Byte Load Cycle Time 150 ps tweu Write Pulse Width High 50 ns AC Write Waveforms WE Controlled OE =~ ee tOES tOEH ADDRESS < tas | |. tAH CE tCH aN tcs | WE KOON tWPH twP---- tDS --| |-_1DH DATA IN CE Controlled OE = ADDRESS x tAS | [-tAH WE ~~ tCH YN tcs | CE ee NN t~ tWPH twP tDS~ }tDH DATA IN 3-132 AT28C010 Mil s_eeeeeens A 1 2SC()10 [Vil Page Mode Characteristics Symbol Parameter Min Max Units tas: toes Address, OE Set-up Time 0 ns tan Address Hold Time 50 ns tes Chip Select Set-up Time 0 ns ton Chip Select Hold Time 0 ns twe Write Pulse Width (WE or CE) 100 ns tos Data Set-up Time 50 ns tou toen Data, OE Hold Time 0 ns Page Mode Write Waveforms )) J fo OE f VS VIN S VI NS OS tWPH ZA ; x _ 1 f- / { DATA Xvaup paTa | K xX , <x, BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 126 BYTE 127 |.twe _ Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE). 2. O must be high only when WE and CE are both low. Chip Erase Waveforms ts = 5 msec (min.) tw = ty = 10 msec (min.) Vy = 12.0V + 0.5V AMIEL saAIMEL Software Data ' Software Data Protection Enable Algorithm Protection Disable Algorithm! LOAD DATA AA LOAD DATA AA To TO ADDRESS 5555 ADDRESS 6555 7 Y LOAD DATA 55 LOAD DATA 55 To TO ADDRESS 2AAA ADDRESS 2AAA 1 Y LOAD DATA 80 LOAD DATA AO To To ADDRESS 5555 ADDRESS 5555 | waITES ENABLED Y LOAD DATA AA LOAD DATA XX TO TO ADDRESS 5555 ANY ADDRESS v v LOAD DATA 55 To LOAD LAST BYTE ADDRESS 2AAA TO t LAST ADDRESS | ENTER DATA PROTECT STATE LOAD ron 20 Notes: 1. Data Format: 1/07 - I/O0 (Hex); ADDRESS 5555 | exit DATA Address Format: A14 - AO (Hex). Y PROTECT STATE) 2. Write Protect state will be activated at end of write LOAD DATA XX even if no other data is loaded. To . ; ; ANY ADDRESS 3. Write Protect state will be deactivated at end of write y period even if no other data if loaded. LOAD LAST BYTE 4. 1 to 128 bytes of data are loaded. To LAST ADDRESS Software Protected Program Cycle Waveform!)2)) t OE eT US VS VS VISIONS tWwP tWPH {BLC we awn ea j~ tAS tAH AQ-AG XBYTE ADDRESS x - 5555 2AAA 5555 , A7 -A16 \X PAGE ADDRESS tDS tDH (- DATA x AA 55 AO x x x , BYTE 0 BYTE 126 BYTE 127 e two 4 Notes: 1. AO -A14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. 3-134 AT28C010 Milees A 1 28CO1 0 Mil Data Polling Characterstics') | . Symbol Parameter Min Typ Max Units tow Data Hold Time 10 ns toen OE Hold Time 10 ns toe OE to Output Delay ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Data Polling Waveforms WE y" cE L\S\S VS \ OE \ SS \ tDH 4 t0E -HIGHZ tw vO7 Z AO - A16 An An An An SX An) f{f Toggle Bit Characteristics" Symbol Parameter Min Typ Max Units ton Data Hold Time 10 ns toen GE Hold Time 10 ns toe OE to Output Delay @ ns toenp OE High Pulse 150 ns twr Write Recovery Time 0 ns Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. Toggle Bit Waveforms") Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any addres location may be used but the address should not vary. ANTIEL 2199AIMEL AT28C010 Ordering Information" tace loc (mA) (ns) Active Standby Ordering Code Package Operation Range 120 80 0.3 AT28C010(E)-12DM/883 32D6 Military/883C AT28C010(E)-12EM/883 32L Class B, Fully Compliant AT28C010-12FM/883 32F (-55C to 125C) AT28C010(E)-12LM/883 44L AT28C010(E)-12UM/883 30U 150 80 0.3 AT28C010(E)-15DM/883 3206 Military/883C AT28C010(E)-15EM/883 32L Class B, Fully Compliant AT28C010-15FM/883 32F {-55C to 125C) AT28C010(E)-15LM/883 44L AT28C010(E)-15UM/883 30U 200 80 0.3 AT28C010(E)-20DM/883 32D6 Military/883C AT28C010(E)-20EM/883 32L Class B, Fully Compliant AT28C010-20FM/883 32F (-55C to 125C) AT28C010(E)-20LM/883 44. AT28C010(E)-20UM/883 30U 250 80 0.3 AT28C010(E)-25DM/883 32D6 Military/883C AT28C010(E)-25EM/883 32L Class B, Fully Compliant AT28C010-25FM/883 32F (-55C to 125C) AT28C010(E)-25LM/883 44L AT28C010(E)-25UM/883 30U Note: 1. See Valid Part Number table below. Package Type 32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) 32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 30U 30-Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles 3-136 AT28C010 Mil mummmmneeneneeees AT 28C0 10 Mil 5962-38267 Ordering Information tace loc (MA) (ns) Active Standby Ordering Code Package Operation Range 120 80 0.3 5962-38267 07 MXX 32D6 Mititary/883C 962-38267 07 MZX 32F Class B, Fully Compliant 5962-38267 07 MYX 44L (-55C to 125C) 5962-38267 07 MTX 30U 150 80 0.3 5962-38267 05 MXX 32D6 Military/883C 5962-38267 05 MUX 32L Class B, Fully Compliant 5962-38267 05 MZX 32F (-55C to 125C) 5962-38267 05 MYX 44L 5962-38267 05 MTX 30U 200 80 0.3 5962-38267 03 MXX 32D6 Military/883C 5962-38267 03 MUX 32 Class B, Fully Compliant 5962-38267 03 MZX 32F (-55C to 125C) 5962-38267 03 MYX 44L 5962-38267 03 MTX 30U 250 80 0.3 5962-38267 01 MXX 32D6 Military/883C 5962-38267 01 MUX 32L Class B, Fully Compliant 5962-38267 01 MZX 32F (-55C to 125C) 5962-38267 01 MYX 44. 5962-38267 01 MTX 30U Note: 1. See Valid Part Number table below. Package Type 32D6 32-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) 32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L 32-Pad, Non-Windowed, Ceramic Leadiess Chip Carrier (LCC) 44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 30U 30-Pin, Ceramic Pin Grid Array (PGA) Ww Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles ATMEL 7Almet Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C010 12 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 12 DM/883, EM/883, LM/883, UM/883 AT28C010 15 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 15 DM/883, EM/883, LM/883, UM/883 AT28C010 20 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 20 DM/883, EM/883, LM/883, UM/883 AT28C010 25 DM/883, EM/883, FM/883, LM/883, UM/883 AT28C010E 25 DM/883, EM/883, LM/883, UM/883 AT28C010 - Ww Die Products | Reference Section: Parallel EEPROM Die Products 3-138 AT28C010 Mil mumps