CAT93C57LI-1.8 - ON Semiconductor L.L.C.

CAT93C46/56/57/66/86

1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM

FEATURES

■High speed operation:

– 93C46/56/57/66: 1MHz

– 93C86: 3MHz

■Low power CMOS technology

■1.8 to 6.0 volt operation

■Selectable x8 or x16 memory organization

■Self-timed write cycle with auto-clear

■Hardware and software write protection

■Power-up inadvertant write protection

■1,000,000 Program/erase cycles

■100 year data retention

■Commercial, industrial and automotive

temperature ranges

■Sequential read (except CAT93C46)

■ Program enable (PE) pin (CAT93C86 only)

■ “Green” package option available

PIN CONFIGURATION

DIP Package (P, L) SOIC Package (J,W)

CMOS EEPROM floating gate technology. The devices

are designed to endure 1,000,000 program/erase cycles

and have a data retention of 100 years. The devices are

available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-

pad TDFN packages.

DESCRIPTION

The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit

Serial EEPROM memory devices which are configured

as either registers of 16 bits (ORG pin at VCC) or 8 bits

(ORG pin at GND). Each register can be written (or read)

serially by using the DI (or DO) pin. The CAT93C46/56/

57/66/86 are manufactured using Catalyst’s advanced

SOIC Package (S,V)

PIN FUNCTIONS

Pin Name Function

CS Chip Select

SK Clock Input

DI Serial Data Input

DO Serial Data Output

VCC +1.8 to 6.0V Power Supply

GND Ground

ORG Memory Organization

NC No Connection

PE* Program Enable

Note: When the ORG pin is connected to VCC,

the x16 organization is selected. When it is

connected to ground, the x8 pin is selected. If

the ORG pin is left unconnected, then an internal

pullup device will select the x16 organization.

SOIC Package (K,X)

Characteristics subject to change without notice.

TSSOP Package (U,Y)

*Only For 93C86 ** TSSOP (U/Y) package only available for 93C46/56/57/66

Doc. No. 1023, Rev. J

VCC

NC (PE*)

ORG

GND

VCC

ORG

GND

VCC

ORG

GND

VCC

ORG

GND

NC (PE*) NC (PE*) NC (PE*)

VCC

ADDRESS

DECODER

MEMORY ARRA Y

ORGANIZATION

DATA

MODE DECODE

LOGIC

CLOCK

GENERATOR

OUTPUT

BUFFER

ORG

GND

PE*

BLOCK DIAGRAM TDFN Package (RD4, ZD4)

Bottom View

VCC

ORG

GND

CAT93C46

CAT93C56

CAT93C66

VCC

ORG

GND

93C46/56/57/66/86

Doc. No. 1023, Rev. J

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Units

ICC1 Power Supply Current fSK = 1MHz 3 mA

(Operating Write) VCC = 5.0V

ICC2 Power Supply Current fSK = 1MHz 500 µA

(Operating Read) VCC = 5.0V

ISB1 Power Supply Current CS = 0V 10 µA

(Standby) (x8 Mode) ORG=GND

ISB2(5) Power Supply Current CS=0V 0 µA

(Standby) (x16Mode) ORG=Float or VCC

ILI Input Leakage Current VIN = 0V to VCC 1µA

ILO Output Leakage Current VOUT = 0V to VCC,1µA

(Including ORG pin) CS = 0V

VIL1 Input Low Voltage 4.5V ≤ VCC < 5.5V -0.1 0.8 V

VIH1 Input High Voltage 4.5V ≤ VCC < 5.5V 2 VCC + 1 V

VIL2 Input Low Voltage 1.8V ≤ VCC < 4.5V 0 VCC x 0.2 V

VIH2 Input High Voltage 4.8V ≤ VCC < 4.5V VCC x 0.7 VCC+1 V

VOL1 Output Low Voltage 4.5V ≤ VCC < 5.5V 0.4 V

IOL = 2.1mA

VOH1 Output High Voltage 4.5V ≤ VCC < 5.5V 2.4 V

IOH = -400µA

VOL2 Output Low Voltage 1.8V ≤ VCC < 4.5V 0.2 V

IOL = 1mA

VOH2 Output High Voltage 1.8V ≤ VCC < 4.5V VCC - 0.2 V

IOH = -100µA

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ..................-55°C to +125°C

Storage Temperature........................-65°C to +150°C

Voltage on any Pin with

Respect to Ground(1) ............. -2.0V to +V CC +2.0V

VCC with Respect to Ground ................ -2.0V to +7.0V

Package Power Dissipation

Capability (TA = 25°C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current(2) ........................ 100 mA

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Typ Max Units

NEND(3) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

TDR(3) Data Retention MIL-STD-883, Test Method 1008 100 Years

VZAP(3) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

ILTH(3)(4) Latch-Up JEDEC Standard 17 100 mA

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

(5) Standby Current (ISB2)=0µA (<900nA) for 93C46/56/57/66, (ISB2)=2µA for 93C86.

93C46/56/57/66/86

Doc. No. 1023, Rev. J

PIN CAPACITANCE

Symbol Test Conditions Min Typ Max Units

COUT(3) Output Capacitance (DO) VOUT=0V 5 pF

CIN(3) Input Capacitance (CS, SK, DI, ORG) VIN=0V 5 pF

Note:

(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE

and ERASE commands.

(2) Applicable only to 93C86

(3) This parameter is tested initially and after a design or process change that affects the parameter.

INSTRUCTION SET

Instruction Device Start Opcode Address Data Comments PE(2)

Type Bit x8 x16 x8 x16

READ 93C46 1 10 A6-A0 A5-A0 Read Address AN–A0

93C56(1) 1 10 A8-A0 A7-A0

93C66 1 10 A8-A0 A7-A0

93C57 1 10 A7-A0 A6-A0

93C86 1 10 A10-A0 A9-A0 X

ERASE 93C46 1 11 A6-A0 A5-A0 Clear Address AN–A0

93C56(1) 1 11 A8-A0 A7-A0

93C66 1 11 A8-A0 A7-A0

93C57 1 11 A7-A0 A6-A0

93C86 1 11 A10-A0 A9-A0 I

WRITE 93C46 1 01 A6-A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0

93C56(1) 1 01 A8-A0 A7-A0 D7-D0 D15-D0

93C66 1 01 A8-A0 A7-A0 D7-D0 D15-D0

93C57 1 01 A7-A0 A6-A0 D7-D0 D15-D0

93C86 1 01 A10-A0 A9-A0 D7-D0 D15-D0 I

EWEN 93C46 1 00

11XXXXX 11XXXX

Write Enable

93C56 1 00

11XXXXXXX 11XXXXXX

93C66 1 00

11XXXXXXX 11XXXXXX

93C57 1 00

11XXXXXX 11XXXXX

93C86 1 00

11XXXXXXXXX 11XXXXXXXX

EWDS 93C46 1 00

00XXXXX 00XXXX

Write Disable

93C56 1 00

00XXXXXXX 00XXXXXX

93C66 1 00

00XXXXXXX 00XXXXXX

93C57 1 00

00XXXXXX 00XXXXX

93C86 1 00

00XXXXXXXXX 00XXXXXXXX

ERAL 93C46 1 00

10XXXXX 10XXXX

Clear All Addresses

93C56 1 00

10XXXXXXX 10XXXXXX

93C66 1 00

10XXXXXXX 10XXXXXX

93C57 1 00

10XXXXXX 10XXXXX

93C86 1 00

10XXXXXXXXX 10XXXXXXXX

WRAL 93C46 1 00

01XXXXX 01XXXX

D7-D0 D15-D0 Write All Addresses

93C56 1 00

01XXXXXXX 01XXXXXX

D7-D0 D15-D0

93C66 1 00

01XXXXXXX 01XXXXXX

D7-D0 D15-D0

93C57 1 00

01XXXXXX 01XXXXX

D7-D0 D15-D0

93C86 1 00

01XXXXXXXXX 01XXXXXXXX

D7-D0 D15-D0 I

93C46/56/57/66/86

Doc. No. 1023, Rev. J

Limits

VCC =V

CC =V

CC =

Test 1.8V-6V 2.5V-6V 4.5V-5.5V

SYMBOL PARAMETER Conditions Min Max Min Max Min Max Units

tCSS CS Setup Time 200 100 50 ns

tCSH CS Hold Time 0 0 0 ns

tDIS DI Setup Time 200 100 50 ns

tDIH DI Hold Time 200 100 50 ns

tPD1 Output Delay to 1 1 0.5 0.15 µs

tPD0 Output Delay to 0 1 0.5 0.15 µs

tHZ(1) Output Delay to High-Z 400 200 100 ns

tEW Program/Erase Pulse Width 5 5 5 ms

tCSMIN Minimum CS Low Time 1 0.5 0.15 µs

tSKHI Minimum SK High Time 1 0.5 0.15 µs

tSKLOW Minimum SK Low Time 1 0.5 0.15 µs

tSV Output Delay to Status Valid 1 0.5 0.1 µs

SKMAX Maximum Clock Frequency DC 500 DC 1000 DC 3000 kHz

A.C. CHARACTERISTICS (93C46/56/57/66)

Limits

VCC =V

CC =V

CC =

1.8V-6V 2.5V-6V 4.5V-5.5V

Test

SYMBOL PARAMETER Conditions Min Max Min Max Min Max Units

tCSS CS Setup Time 200 100 50 ns

tCSH CS Hold Time 0 0 0 ns

tDIS DI Setup Time 400 200 100 ns

tDIH DI Hold Time 400 200 100 ns

tPD1 Output Delay to 1 1 0.5 0.25 µs

tPD0 Output Delay to 0 1 0.5 0.25 µs

tHZ(1) Output Delay to High-Z 400 200 100 ns

tEW Program/Erase Pulse Width 10 10 10 ms

tCSMIN Minimum CS Low Time 1 0.5 0.25 µs

tSKHI Minimum SK High Time 1 0.5 0.25 µs

tSKLOW Minimum SK Low Time 1 0.5 0.25 µs

tSV Output Delay to Status Valid 1 0.5 0.25 µs

SKMAX Maximum Clock Frequency DC 250 DC 500 DC 1000 kHz

A.C. CHARACTERISTICS (93C86)

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

CL = 100pF

(3)

CL = 100pF

(3)

93C46/56/57/66/86

Doc. No. 1023, Rev. J

A.C. TEST CONDITIONS

Input Rise and Fall Times ≤ 50ns

Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V

Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V

Input Pulse Voltages 0.2VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V

Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V

POWER-UP TIMING (1)(2)

SYMBOL PARAMETER Max Units

tPUR Power-up to Read Operation 1 ms

tPUW Power-up to Write Operation 1 ms

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

(3) The input levels and timing reference points are shown in “AC Test Conditions” table.

93C46/56/57/66/86

Doc. No. 1023, Rev. J

DEVICE OPERATION

The CAT93C46/56(57)66/86 is a 1024/2048/4096/

16,384-bit nonvolatile memory intended for use with

industry standard microprocessors. The CAT93C46/56/

57/66/86 can be organized as either registers of 16 bits

or 8 bits. When organized as X16, seven 9-bit instruc-

tions for 93C46; seven 10-bit instructions for 93C57;

seven 11-bit instructions for 93C56 and 93C66; seven

13-bit instructions for 93C86; control the reading, writing

and erase operations of the device. When organized as

X8, seven 10-bit instructions for 93C46; seven 11-bit

instructions for 93C57; seven 12-bit instructions for

93C56 and 93C66: seven 14-bit instructions for 93C86;

control the reading, writing and erase operations of the

device. The CAT93C46/56/57/66/86 operates on a single

power supply and will generate on chip, the high voltage

required during any write operation.

Instructions, addresses, and write data are clocked into

the DI pin on the rising edge of the clock (SK). The DO

pin is normally in a high impedance state except when

reading data from the device, or when checking the

ready/busy status after a write operation.

The ready/busy status can be determined after the start

of a write operation by selecting the device (CS high) and

polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that

the device is ready for the next instruction. If necessary,

the DO pin may be placed back into a high impedance

state during chip select by shifting a dummy “1” into the

DI pin. The DO pin will enter the high impedance state on

the falling edge of the clock (SK). Placing the DO pin into

the high impedance state is recommended in applica-

tions where the DI pin and the DO pin are to be tied

together to form a common DI/O pin.

Figure 1. Sychronous Data Timing

93C46/56/57/66/86 F03

Figure 2a. Read Instruction Timing (93C46)

93C46/56/57/66/86 F04

tDIS tPD0,tPD1 tCSMIN

tCSS

tDIS tDIH

tSKHI tCSH

VALID VALID

D A TA V ALID

tSKLOW

tCSMIN

STANDBY

tHZ HIGH-ZHIGH-Z

11 0

ANAN—1A0

DNDN—1D1D0

tPD0

93C46/56/57/66/86

Doc. No. 1023, Rev. J

The format for all instructions sent to the device is a

logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/

/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)

(an additional bit when organized X8) and for write

operations a 16-bit data field (8-bit for X8 organizations).

Note: This note is applicable only to 93C86. The Write,

Erase, Write all and Erase all instructions require PE=1.

If PE is left floating, 93C86 is in Program Enabled mode.

For Write Enable and Write Disable instruction PE=don’t

care.

Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the CAT93C46/

56/57/66/86 will come out of the high impedance state

and, after sending an initial dummy zero bit, will begin

shifting out the data addressed (MSB first). The output

data bits will toggle on the rising edge of the SK clock and

are stable after the specified time delay (tPD0 or tPD1).

For the CAT93C56/57/66/86, after the initial data word

has been shifted out and CS remains asserted with the

SK clock continuing to toggle, the device will automatically

increment to the next address and shift out the next data

word in a sequential READ mode. As long as CS is

continuously asserted and SK continues to toggle, the

device will keep incrementing to the next address

automatically until it reaches to the end of the address

space, then loops back to address 0. In the sequential

READ mode, only the initial data word is preceeded by

a dummy zero bit. All subsequent data words will follow

without a dummy zero bit.

Write

After receiving a WRITE command, address and the

data, the CS (Chip Select) pin must be deselected for a

minimum of tCSMIN. The falling edge of CS will start the

self clocking clear and data store cycle of the memory

location specified in the instruction. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93C46/56/57/66/86 can be determined by selecting

the device and polling the DO pin. Since this device

features Auto-Clear before write, it is NOT necessary to

erase a memory location before it is written into.

Figure 3. Write Instruction Timing

93C46/56/57/66/86 F05

Figure 2b. Read Instruction Timing (93C56/57/66/86)

DO HIGH-Z

11 0

ANAN–1A0

Dummy 0 D15 . . . D0

D7 . . . D0

111111111111111

Address + 1

D15 . . . D0

D7 . . . D0

Address + 2

D15 . . . D0

D7 . . . D0

Address + n

D15 . . .

D7 . . .

Don't Care

tCSMIN

STANDBY

HIGH-Z

101

ANAN-1 A0DND0

BUSY

READY

STATUS

VERIFY

tSV tHZ

tEW

93C46/56/57/66/86

Doc. No. 1023, Rev. J

Erase

Upon receiving an ERASE command and address, the

CS (Chip Select) pin must be deasserted for a minimum

of tCSMIN. The falling edge of CS will start the self clocking

clear cycle of the selected memory location. The clocking

of the SK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of

the CAT93C46/56/57/66/86 can be determined by

selecting the device and polling the DO pin. Once

cleared, the content of a cleared location returns to a

logical “1” state.

Erase/Write Enable and Disable

The CAT93C46/56/57/66/86 powers up in the write

disable state. Any writing after power-up or after an

EWDS (write disable) instruction must first be preceded

by the EWEN (write enable) instruction. Once the write

instruction is enabled, it will remain enabled until power

to the device is removed, or the EWDS instruction is

sent. The EWDS instruction can be used to disable all

CAT93C46/56/57/66/86 write and clear instructions,

and will prevent any accidental writing or clearing of the

device. Data can be read normally from the device

regardless of the write enable/disable status.

Erase All

Upon receiving an ERAL command, the CS (Chip Select)

pin must be deselected for a minimum of tCSMIN. The

falling edge of CS will start the self clocking clear cycle

of all memory locations in the device. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93C46/56/57/66/86 can be determined by selecting

the device and polling the DO pin. Once cleared, the

contents of all memory bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN. The falling edge of CS will start the self clocking

data write to all memory locations in the device. The

clocking of the SK pin is not necessary after the device

has entered the self clocking mode. (Note 1.) The ready/

busy status of the CAT93C46/56/57/66/86 can be

determined by selecting the device and polling the DO

pin. It is not necessary for all memory locations to be

cleared before the WRAL command is executed.

93C46/56/57/66/86 F06

Figure 4. Erase Instruction Timing

STANDBY

HIGH-Z

ANAN-1

BUSY READY

ST ATUS VERIFY

tSV tHZ

tEW

tCS

93C46/56/57/66/86

Doc. No. 1023, Rev. J

Figure 7. WRAL Instruction Timing

93C46/56/57/66/86 F09

Figure 5. EWEN/EWDS Instruction Timing

93C46/56/57/66/86 F07

Figure 6. ERAL Instruction Timing

93C46/56/57/66/86 F08

STANDBY

* ENABLE=11

DISABLE=00

STANDBY

tCS

HIGH-Z

10 1

BUSY READY

ST ATUS VERIFY

tSV tHZ

tEW

ST ATUS VERIFY

STANDBY

HIGH-Z

10 1

BUSY READY

tSV tHZ

tEW

tCSMIN

DND0

93C46/56/57/66/86

Doc. No. 1023, Rev. J

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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catalyst-semiconductor.com

Publication #: 1023

Revison: J

Issue date: 6/23/03

Type: Final

ORDERING INFORMATION

Notes:

(1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,

Tape & Reel)

(2) TSSOP (U/Y) package only available for 93C46/56/57/66

Package

P = PDIP

S = SOIC (JEDEC)

J = SOIC (JEDEC)

K = SOIC (EIAJ)

U = TSSOP*

RD4 = TDFN (3x3mm)

ZD4 = TDFN (3x3mm, Lead free, Halogen free)

L = PDIP (Lead free, Halogen free)

V = SOIC, JEDEC (Lead free, Halogen free)

W = SOIC, JEDEC (Lead free, Halogen free)

X = SOIC, EIAJ (Lead free, Halogen free)

Y = TSSOP (Lead free, Halogen free)*

Prefix Device # Suffix

93C46 SITE13

Product

Number

93C46: 1K

93C56: 2K

93C57: 2K

93C66: 4K

93C86: 16K

Tape & Reel

TE13: 2000/Reel

-1.8

CAT

Temperature Range

Blank = Commercial (0° - 70°C)

I = Industrial (-40° - 85°C)

A = Automotive (-40° - 105°C)

Operating V oltage

Blank (Vcc=2.5 to 6.0V)

1.8 (Vcc=1.8 to 6.0V)

Optional

Company ID

E = Extended (-40°C to + 125°C)

*CAT93C46/56/57/66 only