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March 2010

FDS6930B Rev. A1

FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET

FDS6930B

Dual N-Channel Logic Level PowerTrench® MOSFET

Features

■5.5 A, 30 V. RDS(ON) = 38 m

Ω @ VGS = 10 V

RDS(ON) = 50 m

Ω @ VGS = 4.5 V

■Fast switching speed

■Low gate charge

■High performance trench technology for extremely

low RDS(ON)

■High power and current handling capability

General Description

These N-Channel Logic Level MOSFETs are produced using

Fairchild Semiconductor’s advanced PowerTrench process that

has been especially tailored to minimize the on-state resistance

and yet maintain superior switching performance.

These devices are well suited for low voltage and battery pow-

ered applications where low in-line power loss and fast switch-

ing are required.

Absolute Maximum Ratings TA= 25°C unless otherwise noted

Package Marking and Ordering Information

Symbol Parameter Ratings Units

VDSS Drain-Source Voltage 30 V

VGSS Gate-Source Voltage

± 20 V

IDDrain Current – Continuous (Note 1a) 5.5 A

– Pulsed 20

PDPower Dissipation for Dual Operation (Note 1) 2 W

Power Dissipation for Single Operation (Note 1a) 1.6

(Note 1b) 1

(Note 1c) 0.9

TJ, TSTG Operating and Storage Junction Temperature Range –55 to 150

°C

Thermal Characteristics

θJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78

°C/W

θJC Thermal Resistance, Junction-to-Case (Note 1) 40

°C/W

Device Marking Device Reel Size Tape width Quantity

FDS6930B FDS6930B 13" 12mm 2500 units

D2 D2

S1G1 S2 G2

Pin 1

SO-8

2www.fairchildsemi.com

FDS6930B Rev. A1

FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET

Electrical Characteristics TA = 25°C unless otherwise noted

Notes:

1. R

θJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is deﬁned as the solder mounting surface of the drain pins.

θJC is guaranteed by design while R

θCA is determined by the user's board design.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300

µs, Duty Cycle < 2.0%

3. Trr parameter will not be subjected to 100% production testing.

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250

µA30 V

∆BVDSS

∆TJ

Breakdown Voltage Temperature

Coefﬁcient

ID = 250

µA, Referenced to 25

°C 26 mV/

°C

IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V

VDS = 24 V, VGS = 0 V, TJ= 55

°C

µA

IGSS Gate–Source Leakage VGS =

±20 V, VDS = 0 V

±100 nA

On Characteristics (Note 2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250

µA 1 1.9 3 V

∆VGS(th)

∆TJ

Gate Threshold Voltage

Temperature Coefﬁcient

ID = 250

µA, Referenced to 25

°C –4.6 mV/

°C

RDS(on) Static Drain–Source

On–Resistance

VGS = 10 V, ID = 5.5 A

VGS = 4.5 V, ID = 4.8 A

VGS = 10 V, ID = 5.5 A, TJ= 125

°C

Ω

ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V 20 A

gFS Forward Transconductance VDS = 5 V, ID = 5.5 A 19 S

Dynamic Characteristics

Ciss Input Capacitance VDS = 15 V, V GS = 0 V,

f = 1.0 MHz

310 412 pF

Coss Output Capacitance 90 120 pF

Crss Reverse Transfer Capacitance 40 60 pF

RGGate Resistance VGS = 15 mV, f = 1.0 MHz 1.9

Ω

Switching Characteristics (Note 2)

td(on) Turn–On Delay Time VDD = 15 V, ID = 1 A,

VGS = 10 V, RGEN = 6

Ω

612 ns

trTurn–On Rise Time 612 ns

td(off) Turn–Off Delay Time 16 28 ns

tfTurn–Off Fall Time 24 ns

QgTotal Gate Charge VDS = 15 V, ID = 5.5 A,

VGS = 5 V

2.7 3.8 nC

Qgs Gate–Source Charge 1.0 nC

Qgd Gate–Drain Charge 0.7 nC

Drain–Source Diode Characteristics and Maximum Ratings

ISMaximum Continuous Drain–Source Diode Forward Current 1.3 A

VSD Drain–Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) 0.8 1.2 V

trr Diode Reverse Recovery Time (note3) IF = 5.5 A, diF/dt = 100 A/µs 16 32 nS

Qrr Diode Reverse Recovery Charge 6 nC

a) 78°C/W when mounted

on a 0.5 in2pad of 2 oz

copper

b) 125°C/W when

mounted on a 0.02 in2

pad of 2 oz copper

c) 135°C/W when

mounted on a

minimum pad.

3www.fairchildsemi.com

FDS6930B Rev. A1

FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET

Typical Characteristics

0 0.5 1 1.5 2

, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

= 10V

4.5V 3.5V

4.0V

3.0V

6.0V

0.8

1.2

1.4

1.6

1.8

048121620

, DRAIN CURRENT (A)

RDS(ON), NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

= 3.5V

4.5V

6.0V

10.0V

4.0V

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

0.6

0.8

1.2

1.4

1.6

-50 -25 0 25 50 75 100 125 150

, JUNCTION TEMPERATURE (

DS(ON)

, NORMALIZED

DRAIN-SOURCE ON-RESISTANCE

= 5.5A

= 10.0V

0.02

0.04

0.06

0.08

0.1

0.12

246810

, GATE TO SOURCE VOLTAGE (V)

DS(ON)

, ON-RESISTANCE (OHM)

= 2.75A

= 125°C

= 25°C

Figure 3. On-Resistance Variation with

Temperature.

Figure 4. On-Resistance Variation with

Gate-to-Source Voltage.

12345

VGS, GATE TO SOURCE VOLTAGE (V)

, DRAIN CURRENT (A)

TA = 125°C

25°C

-55°C

VDS = 5V

0.0001

0.001

0.01

0.1

100

0 0.2 0.4 0.6 0.8 1 1.2

, BODY DIODE FORWARD VOLTAGE (V)

, REVERSE DRAIN CURRENT (A)

= 0V

= 125°C

25°C

-55°C

Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature.

4www.fairchildsemi.com

FDS6930B Rev. A1

FDS6930B Dual N-Channel Logic Level PowerTrench® MOSFET

Typical Characteristics

0123456

, GATE CHARGE (nC)

VGS, GATE-SOURCE VOLTAGE (V)

= 5.5A

= 5V 15V

10V

100

200

300

400

500

0 5 10 15 20

, DRAIN TO SOURCE VOLTAGE (V)

CAPACITANCE (pF)

iss

oss

rss

f = 1 MHz

= 0 V

Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.

0.01

0.1

100

0.01 0.1 1 10 100

VDS, DRAIN-SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

10s

100ms

100µs

RDS(ON) LIMIT

VGS = 10.0V

SINGLE PULSE

RθJA = 135°C/W

TA = 25°C

10ms

1ms

0.001 0.01 0.1 1 10 100

, TIME (sec)

P(pk), PEAK TRANSIENT POWER (W)

SINGLE PULSE

θJA

= 135°C/W

= 25°C

Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum

Power Dissipation.

0.001

0.01

0.1

0.0001 0.001 0.01 0.1 1 10 100 1000

, TIME (sec)

r(t), NORMALIZED EFFECTIVE TRANSIENT

THERMAL RESISTANCE

θJA

(t) = r(t) * R

θJA

= 135°C/W

- T

= P * R

θJA

(t)

Duty Cycle, D = t

/ t

P(pk)

SINGLE PULSE

0.01

0.02

0.05

0.1

0.2

D = 0.5

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.

Transient thermal response will change depending on the circuit board design.

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Rev. I48

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