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FEATURES
DESCRIPTION/ORDERING
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
•Member of the Texas Instruments Widebus™Family
•Operates From 1.65 V to 3.6 V•Inputs Accept Voltages to 5.5 V•Max t
pd
of 4 ns at 3.3 V•Typical V
OLP
(Output Ground Bounce) <0.8 Vat V
CC
= 3.3 V, T
A
= 25 °C•Typical V
OHV
(Output V
OH
Undershoot) >2 V atV
CC
= 3.3 V, T
A
= 25 °C•Supports Mixed-Mode Signal Operation on AllPorts (5-V Input/Output Voltage With3.3-V V
CC
)•I
off
Supports Partial-Power-Down ModeOperation
•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Latch-Up Performance Exceeds 250 mA PerJESD 17•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)
INFORMATION
This 16-bit (dual-octal) noninverting bus transceiveris designed for 1.65-V to 3.6-V V
CC
operation.
The SN74LVCH16245A is designed for asynchronous communication between data buses. The logic levels ofthe direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-portoutputs or place both output ports into the high-impedance mode. The device transmits data from the A bus tothe B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs areactivated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW levelapplied to prevent excess I
CC
and I
CCZ
.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldownresistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and isnot disabled by OE or DIR.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translatorsin a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
K
abc
GRD OR ZRD PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
SN74LVCH16245A
16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
FBGA – GRD SN74LVCH16245AGRDR
Tape and reel LDH245AFBGA – ZRD (Pb-free) SN74LVCH16245AZRDR
Tube SN74LVCH16245ADLSSOP – DL SN74LVCH16245ADLR LVCH16245ATape and reel
74LVCH16245ADLRG4–40 °C to 85 °C SN74LVCH16245ADGGRTSSOP – DGG Tape and reel LVCH16245A74LVCH16245ADGGRG4
SN74LVCH16245ADGVRTVSOP – DGV Tape and reel LDH245A74LVCH16245ADGVRE4VFBGA – GQL SN74LVCH16245AGQLR
Tape and reel LDH245AVFBGA – ZQL (Pb-free) SN74LVCH16245AZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
TERMINAL ASSIGNMENTS
(1)
(56-Ball GQL/ZQL Package)
1 2 3 4 5 6
A1DIR NC NC NC NC 1 OE
B1B2 1B1 GND GND 1A1 1A2
C1B4 1B3 V
CC
V
CC
1A3 1A4
D1B6 1B5 GND GND 1A5 1A6
E1B8 1B7 1A7 1A8
F2B1 2B2 2A2 2A1
G2B3 2B4 GND GND 2A4 2A3
H2B5 2B6 V
CC
V
CC
2A6 2A5
J2B7 2B8 GND GND 2A8 2A7
K2DIR NC NC NC NC 2 OE
abc (1) NC – No internal connection
TERMINAL ASSIGNMENTS
(1)
(54-Ball GRD/ZRD Package)
1 2 3 4 5 6
A1B1 NC 1DIR 1 OE NC 1A1
B1B3 1B2 NC NC 1A2 1A3
C1B5 1B4 V
CC
V
CC
1A4 1A5
D1B7 1B6 GND GND 1A6 1A7
E2B1 1B8 GND GND 1A8 2A1
F2B3 2B2 GND GND 2A2 2A3
G2B5 2B4 V
CC
V
CC
2A4 2A5
H2B7 2B6 NC NC 2A6 2A7
J2B8 NC 2DIR 2 OE NC 2A8
(1) NC – No internal connection
2
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To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
Absolute Maximum Ratings
(1)
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
FUNCTION TABLE
(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS OUTPUT CIRCUITS
OPERATIONOE DIR A PORT B PORT
L L Enabled Hi-Z B data to A busL H Hi-Z Enabled A data to B busH X Hi-Z Hi-Z Isolation
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high or low state
(2) (3)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 70DGV package 58θ
JA
Package thermal impedance
(4)
DL package 63 °C/WGQL/ZQL package 42GRD/ZRD package 36T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
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Recommended Operating Conditions
(1)
SN74LVCH16245A
16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
MIN MAX UNIT
Operating 1.65 3.6V
CC
Supply voltage VData retention only 1.5V
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 5.5 VHigh or low state 0 V
CCV
O
Output voltage V3-state 0 5.5V
CC
= 1.65 V –4V
CC
= 2.3 V –8I
OH
High-level output current mAV
CC
= 2.7 V –12V
CC
= 3 V –24V
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current mAV
CC
= 2.7 V 12V
CC
= 3 V 24∆t/ ∆v Input transition rise or fall rate 5 ns/VT
A
Operating free-air temperature –40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
Switching Characteristics
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= –100 µA 1.65 V to 3.6 V V
CC
– 0.2I
OH
= –4 mA 1.65 V 1.2I
OH
= –8 mA 2.3 V 1.7V
OH
V2.7 V 2.2I
OH
= –12 mA
3 V 2.4I
OH
= –24 mA 3 V 2.2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45V
OL
I
OL
= 8 mA 2.3 V 0.7 VI
OL
= 12 mA 2.7 V 0.4I
OL
= 24 mA 3 V 0.55I
I
Control inputs V
I
= 0 to 5.5 V 3.6 V ±5µAV
I
= 0.58 V 151.65 VV
I
= 1.07 V –15V
I
= 0.7 V 452.3 VI
I(hold)
A or B port V
I
= 1.7 V –45 µAV
I
= 0.8 V 753 VV
I
= 2 V –75V
I
= 0 to 3.6 V
(2)
3.6 V ±500I
off
V
I
or V
O
= 5.5 V 0 ±10 µAI
OZ
(3)
V
O
= 0 V or (V
CC
to 5.5 V) 2.3 V to 3.6 V ±5µAV
I
= V
CC
or GND 20I
CC
I
O
= 0 3.6 V µA3.6 V ≤V
I
≤5.5 V
(4)
20∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 2.7 V to 3.6 V 500 µAC
i
Control inputs V
I
= V
CC
or GND 3.3 V 5 pFC
io
A or B port V
O
= V
CC
or GND 3.3 V 7.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.(2) This is the bus-hold maximum dynamic current required to switch the input from one state to another.(3) For the total leakage current in an I/O port, consult the I
I(hold)
specification for the input voltage condition 0 V < V
I
< V
CC
, and the I
OZspecification for the input voltage conditions V
I
= 0 V or V
I
= V
CC
to 5.5 V. The bus-hold current, at input voltage greater than V
CC
, isnegligible.
(4) This applies in the disabled state only.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 VFROM TO
±0.15 V ±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A or B B or A 1.5 7.1 1 4.5 1 4.7 1 4 nst
en
OE A or B 1.5 8.9 1 5.6 1.5 6.7 1.5 5.5 nst
dis
OE A or B 1.5 11.9 1 6.8 1.5 7.1 1.5 6.6 nst
sk(o)
1 ns
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Operating Characteristics
SN74LVCH16245A
16-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VTESTPARAMETER UNITCONDITIONS
TYP TYP TYP
Outputs enabled 36 36 40Power dissipation capacitanceC
pd
f = 10 MHz pFper transceiver
Outputs disabled 3 3 4
6
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PARAMETER MEASUREMENT INFORMATION
VM
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
tsu th
SN74LVCH16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES495B – OCTOBER 2003 – REVISED AUGUST 2006
Figure 1. Load Circuit and Voltage Waveforms
7Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74LVCH16245ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVCH16245ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVCH16245ADGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74LVCH16245ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCH16245ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCH16245ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCH16245ADL ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCH16245ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCH16245ADLR ACTIVE SSOP DL 48 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVCH16245AGQLR LIFEBUY BGA
MICROSTAR
JUNIOR
GQL 56 1000 TBD SNPB Level-1-240C-UNLIM
SN74LVCH16245AGRDR LIFEBUY BGA
MICROSTAR
JUNIOR
GRD 54 1000 TBD SNPB Level-1-240C-UNLIM
SN74LVCH16245AZQLR ACTIVE BGA
MICROSTAR
JUNIOR
ZQL 56 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
SN74LVCH16245AZRDR ACTIVE BGA
MICROSTAR
JUNIOR
ZRD 54 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2012
Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVCH16245ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74LVCH16245ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
SN74LVCH16245ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
SN74LVCH16245AGQLR BGA MI
CROSTA
R JUNI
OR
GQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1
SN74LVCH16245AGRDR BGA MI
CROSTA
R JUNI
OR
GRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
SN74LVCH16245AZQLR BGA MI
CROSTA
R JUNI
OR
ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1
SN74LVCH16245AZRDR BGA MI
CROSTA
R JUNI
OR
ZRD 54 1000 330.0 16.4 5.8 8.3 1.55 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVCH16245ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74LVCH16245ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0
SN74LVCH16245ADLR SSOP DL 48 1000 367.0 367.0 55.0
SN74LVCH16245AGQLR BGA MICROSTAR
JUNIOR GQL 56 1000 333.2 345.9 28.6
SN74LVCH16245AGRDR BGA MICROSTAR
JUNIOR GRD 54 1000 333.2 345.9 28.6
SN74LVCH16245AZQLR BGA MICROSTAR
JUNIOR ZQL 56 1000 333.2 345.9 28.6
SN74LVCH16245AZRDR BGA MICROSTAR
JUNIOR ZRD 54 1000 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
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