. Preliminary IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Features * 32K x 36 or 64K x 18 Organizations * Common I/O * 0.5 Micron CMOS Technology * Asynchronous Output Enable and Power Down Inputs * Synchronous Flow-Thru Mode Of Operation with Self-Timed Late Write * Dual Differential Input and Output Clocks. * Single +3.3V Power Supply and Ground * Boundary Scan using limited set of JTAG 1149.1 functions * Byte Write Capability & Global Write Enable * GTL/HSTL Input and Output levels * 7 X 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order. * Registered Addresses, Write Enables, Sync Select and Data Ins. * Programmable Impedance Output Drivers Description The IBM043610QLA and IBM04180QLA 1Mb SRAMS are Synchronous Flow-Thru Mode, high performance CMOS Static Random Access Memories that are versatile, wide I/O, and achieves 5 nsec cycle times. Dual differential K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the K Clock, all Addresses, Write-Enables, Sync Select and Data Ins are registered internally. Differential clocks C and C are used to control the Output Data hold time by allowing output data to change after the rising edge of the C clock. An internal Write buffer allows write data to follow one cycle after addresses and controls. The chip is operated with a single +3.3V power supply and is compatible with GTL/HSTL I/O interfaces. 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary X36 BGA Bump Layout (Top View) 1 2 3 4 5 6 7 A VDDQ SA8 SA7 NC SA4 SA3 VDDQ B NC NC NC NC NC NC NC C NC SA9 SA6 VDD SA5 SA2 NC D DQ23 DQ18 VSS ZQ VSS DQ17 E DQ19 DQ24 VSS SS VSS DQ11 DQ16 F VDDQ DQ20 VSS G VSS DQ15 VDDQ DQ14 DQ12 G DQ21 DQ25 SBWc C SBWb DQ10 H DQ26 DQ22 VSS C VSS DQ13 DQ9 J VDDQ VDD VREF VDD VREF VDD VDDQ K DQ27 DQ31 VSS K VSS DQ4 DQ8 L DQ32 DQ28 SBWd K SBWa DQ7 DQ3 M VDDQ DQ33 VSS SW VSS DQ2 VDDQ N DQ34 DQ29 VSS SA1 VSS DQ6 DQ1 P DQ30 DQ35 VSS SA0 VSS DQ0 DQ5 R NC SA14 M1* SA13 TDI T NC NC U VDDQ TMS VDD M2* SA10 NC SA12 SA11 NC ZZ TCK TDO NC VDDQ Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VDD. X18 BGA Bump Layout (Top View) 1 2 3 4 5 6 7 A VDDQ SA8 SA7 NC SA4 SA3 VDDQ B NC NC NC NC NC NC NC C NC SA9 SA6 VDD SA5 SA2 NC D DQ9 NC VSS ZQ VSS DQ8 NC E NC DQ10 VSS SS VSS NC DQ7 F VDDQ NC VSS G VSS DQ6 VDDQ DQ5 G NC DQ11 SBWb C VSS NC H DQ12 NC VSS C VSS DQ4 NC J VDDQ VDD VREF VDD VREF VDD VDDQ K NC DQ13 VSS K VSS NC DQ3 L DQ14 NC VSS K SBWa DQ2 NC M VDDQ DQ15 VSS SW VSS NC VDDQ N DQ16 NC VSS SA1 VSS DQ1 NC P NC DQ17 VSS SA0 VSS NC DQ0 R NC M2 SA11 NC SA12 SA10 ZZ NC VDDQ T NC U VDDQ SA15 M1 SA13 SA14 TMS TDI VDD NC TCK TDO Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VDD . (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Pin Description SA0-SA15 Address Input G Asynchronous Output Enable DQ0-DQ35 Data I/O SS Synchronous Select K, K Differential Input Register Clocks M1, M2 Clock Mode Inputs- Selects Single or Dual Clock Operation. C,C Differential Output Data Hold Control Clocks VREF(2) GTL/HSTL Input Reference Voltage SW Write Enable, Global VDD Power Supply (+3.3V) SBWa Write Enable, Byte a (DQ0-DQ8) VSS Ground SBWb Write Enable, Byte b (DQ9-DQ17) VDDQ SBWc Write Enable, Byte c (DQ18-DQ26) ZZ Asynchronous Sleep Mode SBWd Write Enable, Byte d (DQ27-DQ35) ZQ Output Driver Impedance Control TMS,TDI,TCK IEEE 1149.1 Test Inputs (LVTTL levels) NC No Connect TDO IEEE 1149.1 Test Output (LVTTL level) Output Power Supply Block Diagram Reg Lat SW SW Register SW Register SBW Register SBW Register 32Kx36 or Row Dec SS ZZ WR Add RD Add Reg 2:1 MUX SA0-SA15 K 64Kx18 Array Column Decode Read/Write Amp SBW Match Lat 2:1 MUX SS Register SS Register Write Buffer Set Res Set Res C Data Out Latch Lat Lat G DQ0-DQ35 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary SRAM FEATURES Late Write Late Write function allows for write data to be registered one cycle after addresses and controls. This feature will alleviate SRAM data bus contention going from a Read to Write cycle by eliminating one dead cycle. Late Write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. In the case a read cycle occurs after a write cycle, the address and write data information are stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be updated with address and data in the holding registers. Read cycle addresses are monitored to determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a byte by byte basis. When one byte is written during a write cycle, read data from the last written address will have new byte data from the write buffer and remaining bytes from the SRAM array. Dual Clock Operation In Dual Clock Operation, the K Clocks are used to register all synchronous inputs and start the SRAM operation. The C Clocks are used to control the output data timings. During Write (SW=L) or Deselect (SS=H) operations, the rising edge of C Clock triggers the time to HI-Z. During Read operations the location of the rising edge of the C Clock will determine the output data valid placement by allowing SRAM output data to flow through after the rising edge. When the rising edge of the C Clock occurs early in a Read cycle (e.g. tKHCH = Min.), data from the SRAM will become available at a tKHQV time, as it would in a Flow-Through Read implementation (see Dual Clock Diagram #1 below). As the C Clock rising edge moves away from tKHCH = Min., towards a tCHKH = Min., of the next K Clock rising edge, the output data may become "gated" by the C Clock (see Dual Clock Diagram #2 below). The SRAM access time will then become referenced to the C Clock (i.e. tCHQV). This feature allows SRAM users to fully control the output data hold time over voltage, temperature and process variations, and provide minimum output data latency. Dual Clock Diagram #1: Output data becomes available as a result of internal data lines flowing through the output latch unrestrained by the C clock. Dual Clock Diagram #2: Internal data lines await at the output latch for the rising edge of C clock.The C clock enables the output latch and allowsoutput data to become available. K K Data Lines* Data Lines* QB QA QB QA tCHKH=min C C tKHCH=min DQ QA DQ QA QB tKHQV QB tCHQV *Data Lines refer to internal data lines connecting to Data Output Latch See Block Diagram on page 3. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Mode Control Mode control pins: M1 and M2 are used to select four different JEDEC standard read protocols. This SRAM supports both the Single Clock, Flow-Through (M1 = VSS, M2 = VSS) and Dual Clock Flow-Through protocols (M1 = VDD, M2 = VDD). This data sheet only describes Dual Clock Flow-Through functionality. Mode control inputs must be set with power up and must not change during SRAM operation. Power Down Mode Power Down Mode or "Sleep" Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep mode, the outputs will go to a HI-Z state and the SRAM will draw standby current. SRAM data will be preserved and a recovery time (tZZR) is required before the SRAM resumes to normal operation. Programmable Impedance/Power Up Requirements An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 7.5% is between 175 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a time towards the optimum level. The output driver has 16 discrete binary weighted steps. The impedance update of the output driver occurs when the SRAM is in HI-Z. Write and Deselect operations will synchronously switch the SRAM into and out of HI-Z, therefore, triggering an update. The user may choose to invoke asynchronous G updates by providing a G setup and hold about the K Clock to guarantee the proper update. There are no power up requirements for the SRAM; however, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 clock cycles followed by a LO-Z to HI-Z transition. Ordering Information Part Number Organization Speed Leads IBM041810QLA - 5 64K x 18 7.0ns Access / 5 ns Cycle 7 X 17 BGA IBM041810QLA - 6 64K x 18 7.5ns Access / 6ns Cycle 7 X 17 BGA IBM041810QLA - 7 64K x 18 8.0ns Access / 7ns Cycle 7 X 17 BGA IBM043610QLA - 5 32K x 36 7.0ns Access / 5 ns Cycle 7 X 17 BGA IBM043610QLA - 6 32K x 36 7.5ns Access / 6ns Cycle 7 X 17 BGA IBM043610QLA - 7 32K x 36 8.0ns Access / 7ns Cycle 7 X 17 BGA 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Clock Truth Table K, C CLK ZZ SS SW SBWA SBWB SBWC SBWD DQ (n) DQ (n+1) Mode LH L L H X X X X Dout 0-35 X Read Cycle All Bytes LH L L L L H H H HIZ Din 0-8 Write Cycle 1st Byte LH L L L H L H H HIZ Din 9-17 Write Cycle 2nd Byte LH L L L H H L H HIZ Din 18-26 Write Cycle 3rd Byte LH L L L H H H L HIZ Din 27-35 Write Cycle 4th Byte LH L L L L L L L HIZ Din 0-35 Write Cycle All Bytes LH L L L H H H H HIZ HIZ Abort Write Cycle LH L H X X X X X HIZ X Deselect Cycle X H X X X X X X HIZ HIZ Sleep Mode Output Enable Truth Table Operation G DQ Read L Dout 0-35 Read H HIZ Sleep (ZZ=H) X HIZ Write (SW=L) X HIZ Deselect (SS=H) X HIZ Absolute Maximum Ratings Item Symbol Rating Units Notes Power Supply Voltage VDD -0.5 to 4.6 V 1 Input Voltage VIN -0.5 to VDD+0.5 V 1 VOUT -0.5 to VDD+0.5 V 1 TA 0 to +70 C 1 Storage Temperature TSTG -55 to +125 C 1 Short Circuit Output Current IOUT 25 mA 1 Output Voltage Operating Temperature 1.Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Recommended DC Operating Conditions (TA=0 to 70C) Parameter Symbol Min. Typ. Max. Units Notes Supply Voltage VDD 3.15 3.3 3.60 V 1 Output Driver Supply Voltage VDDQ 1.14 1.4 1.6 V 1 Input High Voltage VIH VREF +0.1 -- VDDQ + 0.3 V 1,2 Input Low Voltage VIL -0.3 -- VREF -0.1 V 1,3 VREF 0.55 0.70 0.90 V 1 Clocks Signal Voltage VIN - CLK -0.3 -- VDDQ + 0.3 V 1,4 Differential Clocks Signal Voltage VDIF - CLK 0.1 -- VDDQ + 0.6 V 1,5 Clocks Common Mode Voltage VCM - CLK 0.55 -- 0.90 V 1 IOUT -- 5 8 mA Input Reference Voltage Output Current 1.All voltages referenced to VSS. All VDD, VDDQ and VSS pins must be connected. 2.VIH(Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDD + 1.5 V (pulse width 4.0ns) 3.VIL(Min)DC = - 0.3 V, VIL(Min)AC= -1.5 V (pulse width 4.0ns) 4.VIN-CLK specifies the maximum allowable DC excursions of each differential clock (K, K, C, C) 5.VDIF-CLK specifies the minimum Clock differential voltage required for switching. Capacitance (TA=0 to +70C, VDD=3.3 -5% + 10% V, f=1MHz) Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) Symbol Test Condition Max Units CIN VIN = 0V 3 pF COUT VOUT = 0V 4 pF DC Electrical Characteristics (TA= 0 to +70C, VDD=3.3 5% V) Parameter Symbol Min. Max. Units Notes Average Power Supply Operating Current- X36 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) IDD5 IDD6 IDD7 -- -- 675 580 510 mA 1 Average Power Supply Operating Current - X18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) IDD5 IDD6 IDD7 -- -- 500 450 400 mA 1 Power Supply Standby Current (ZZ= VIH, All other inputs = VIH or VIL, IOUT = 0) ISB -- 10 mA 1 Input Leakage Current, any input (VIN = Vss or VDD) ILI -- +1 A Output Leakage Current (VOUT = Vss or VDD, DQ in HIZ ILO -- +1 A Output "High" Level Voltage (IOH=-6mA @ VDDQ / 2 + 0.3) VOH VDDQ / 2 + 0.3 VDDQ V 2 Output "Low" Level Voltage (IOL=+6mA @ VDDQ / 2 -0.3) VOL Vss VDDQ / 2 -0.3 V 2 1. IOUT = Chip Output Current 2. Minimum Impedance Output Driver 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Programmable Impedance Output Driver DC Electrical Characteristics Parameter ) (TA= 0 to +70C, VDD=3.3 - 5% + 10% V Symbol Min. Max. Units Notes Output "High" Level Voltage VOH VDDQ / 2 VDDQ V 1 Output "Low" Level Voltage VOL Vss VDDQ / 2 V 2 1. IOH = (VDDQ / 2) / (RQ / 5) 7.5% @ VOH = VDDQ / 2 For: 150 RQ 350 2. IOL = (VDDQ / 2) / (RQ / 5) 7.5% @ VOL = VDDQ / 2 For: 150 RQ 350 AC Test Conditions (TA=0 to +70C, VDD=3.3 - 5% + 10% V) Parameter Symbol Conditions Units Input High Level VIH 1.4 V Input Low Level VIL VSS V Input Reference Voltage VREF 0.7 V Differential Clocks Voltage VDIF-CLK 0.7 V Clocks Common Mode Voltage VCM-CLK 0.7 V Input Rise Time TR 0.5 ns Input Fall Time TF 0.5 ns 0.7 V Differential Cross Point V I/O Signals Reference Level (except K, C Clocks) Clocks Reference Level Output Load Conditions Notes 1 1.See AC Test Loading figure on page 8 AC Test Loading 50 16.7 50 0.7V 5pF 16.7 DQ 50 16.7 50 0.7V 5pF 0.7V (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary AC Characteristics (TA=0 to +70C, VDD=3.3 - 5% + 10% V) -5 Parameter -6 -7 Symbol Units Min. Max. Min. Max. Min. Max. Notes K Clock Cycle Time tKHKH 5.0 -- 6.0 -- 7.0 -- ns K Clock High Pulse Width tKHKL 1.5 -- 1.5 -- 1.5 -- ns K Clock Low Pulse Width tKLKH 1.5 -- 1.5 -- 1.5 -- ns C Clock Cycle Time tCHCH tKHKH -- tKHKH -- tKHKH -- ns C Clock High Pulse Width tCHCL 1.5 -- 1.5 -- 1.5 -- ns C Clock Low Pulse Width tCLCH 1.5 -- 1.5 -- 1.5 -- ns K to C Clock Delay tKHCH 1.5 -- 1.5 -- 1.5 -- ns C to K Clock Delay tCHKH 1.0 -- 1.0 -- 1.0 -- ns K Clock to Output Valid tKHQV -- 7.0 -- 7.5 -- 8.0 ns 1 Data Out Hold Time from K Clock tKHQX 2.5 -- 3.0 -- 3.5 -- ns 1,2,4 K Clock High to Output Active tKHQX4 2.5 -- 3.0 -- 3.5 -- ns 1,2,4 C Clock to Output Valid tCHQV -- 3.0 -- 3.5 -- 3.5 ns 1,5 Data Out Hold Time from C clock tCHQX 0.5 -- 0.5 -- 0.5 -- ns 1,2,5 C Clock High to Output High Z tCHQZ -- 2.5 -- 3.0 -- 3.5 ns 1,2 C Clock High to Output Active tCHQX2 0.5 -- 0.5 -- 0.5 -- ns 1,2,5 Address Setup Time tAVKH 0.5 -- 0.5 -- 0.5 -- ns Address Hold Time tKHAX 1.0 -- 1.0 -- 1.0 -- ns Synchronous Select Setup Time tSVKH 0.5 -- 0.5 -- 0.5 -- ns Synchronous Select Hold Time tKHSX 1.0 -- 1.0 -- 1.0 -- ns Write Enables Setup Time tWVKH 0.5 -- 0.5 -- 0.5 -- ns Write Enables Hold Time tKHWX 1.0 -- 1.0 -- 1.0 -- ns Data In Setup Time tDVKH 0.5 -- 0.5 -- 0.5 -- ns Data In Hold Time tKHDX 1.0 -- 1.0 -- 1.0 -- ns Output Enable to Output Valid tGLQV -- 2.5 -- 3.0 -- 3.5 ns 1 Output Enable to Low Z tGLQX 0.5 -- 0.5 -- 0.5 -- ns 1,2 Output Enable to High Z tGHQZ -- 2.5 -- 3.0 -- 3.5 ns 1,2 Output Enable Set-up Time tGHKH 0.5 -- 0.5 -- 0.5 -- ns 1,3 Output Enable Hold TIme tKHGX 1.5 -- 1.5 -- 1.5 -- ns 1,3 Sleep Mode Recovery TIme tZZR 5 -- 6 -- 7 -- ns Sleep Mode Enable TIme tZZE -- 5 -- 6 -- 7 ns 1.See AC Test Loading figure on page 8 2.Transitions are measured tbd mV from steady state voltage. 3.Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver updates during High Z. 4.tKHQX and tKHQX4 are used in instances where tKHCH = Min. and, therefore, the C Clock may not gate the output data. 5.tCHQV, tCHQX and tCHQX2 are used in instances where the output data is gated by the C Clock. 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Timing Diagram (Read and Deselect Cycles) tKLKH tKHKL tKHKH K tAVKH A1 SA A2 A3 A3 A4 tKHSX tKHAX SS tWVKH tSVKH SW tGLQV tKHWX G tKHQV tGHQZ Q3 Q2 DQ tGLQX tKHQX4 tCHQZ tCHQX2 tKHQV C tCHCL tKHCH tCHKH (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 20 tKHQX tCLCH tCHCH Q4 tCHQV tCHQX tCHQZ 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Timing Diagram (Read Followed by Write) tKLKH tKHKL tKHKH K tAVKH A1 SA A2 A4 tKHAX tSVKH SS A2 A3 tKHSX tKHWX SW tWVKH tKHWX SBW tWVKH G tKHQV tGHQZ tKHQV tKHDX DQ Q1 tKHCH tCHQZ D4 Q2 Q3 D2 tDVKH tDVKH tCHQV tKHDX C tCHCL tCLCH tCHCH Notes: 1. D2 is the input data written in memory location A2. 2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Timing Diagram (Sleep Mode) tKHKH K ZZ tZZR tZZE DQ (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary IEEE 1149.1 Tap And Boundary Scan The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE std. 1149.1, the SRAMs contain a TAP controller, Instruction register, Boundary Scan register, Bypass register and ID register. The TAP controller has a standard 16-state state machine that resets internally upon power-up, therefore, TRST signal is not required. Signal List * * * * TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Caution: TCK, TMS, TDI inputs must be biased down, even if JTAG is not used. JTAG Recommended DC Operating Conditions (TA=0 to 70C) Parameter Symbol Min. Typ. Max. Units Notes JTAG Input High Voltage VIH1 2.2 -- VDD+0.3 V 1 JTAG Input Low Voltage VIL1 -0.3 -- 0.8 V 1 JTAG Output High Level VOH1 2.4 -- -- V 1,2 JTAG Output Low Level VOL1 -- -- 0.4 V 1,3 1. 2. 3. All JTAG Inputs/Outputs are LVTTL Compatible only. IOH1 = -8mA at 2.4V. IOL1 = +8mA at 0.4V. JTAG AC Test Conditions (TA=0 to +70C, VDD=3.3 -5% + 10% V) Parameter Symbol Conditions Units Input Pulse High Level VIH1 3.0 V Input Pulse Low Level VIL1 0.0 V Input Rise Time TR1 2.0 ns Input Fall Time TF1 2.0 ns 1.5 V Input and Output Timing Reference Level Notes 1 1. See AC Test Loading figure on page 8 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary JTAG AC Characteristics (TA=0 to +70C, VDD=3.3 -5% + 10% V) Parameter Symbol Min. Max. Units TCK Cycle Time tTHTH 20 -- ns TCK High Pulse Width tTHTL 7 -- ns TCK Low Pulse Width tTLTH 7 -- ns TMS Setup tMVTH 4 -- ns TMS Hold tTHMX 4 -- ns TDI Setup tDVTH 4 -- ns TDI Hold tTHDX 4 -- ns TCK Low to Valid Data tTLOV -- 7 ns Notes 1 1. See AC Test Loading figure on page 8 JTAG Timing Diagram tTHTL tTLTH tTHTH TCK tTHMX TMS tTHDX tMVTH TDI tDVTH TDO tTLOV (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Scan Register Definition Register Name Bit Size X18 Bit Size X36 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan * 51 70 * The Boundary Scan chain consists of the following bits: * 36 or 18 bits for Data Inputs Depending on X18 or X36 Configuration * 15 bits for SA0 - SA14 for X36, 16 bits for SA0 - SA15 for X18 * 4 bits for SBWa - SBWd in X36, 2 bits for SBWa and SBWb in X18 * 11 bits for K, K, C, C, ZQ, SS, G, SW, ZZ, M1 and M2 * 4 bits for Place Holders * K, K, C, C clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling. ID Register Definition Field Bit Number and Description Part Revision Number (31:28) Device Density and Configuration (27:18) Vendor Definition (17:12) Manufacture JEDEC Code (11:1) Start Bit (0) 64K X18 0000 001 000 0011 000000 000 101 001 00 1 32K X36 0000 000 110 0100 000000 000 101 001 00 1 Instruction Set Code Instruction Notes 000 SAMPLE-Z 1,5 001 IDCODE 2 010 SAMPLE-Z 1,5 011 BYPASS 3 100 SAMPLE 4,5 101 BYPASS 3 110 BYPASS 3 111 BYPASS 3 1. Places DQs in HIZ in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in HIZ. 5. SRAM must not be in Sleep mode (ZZ = H) when SAMPLE-Z or SAMPLE instructions are invoked. List of IEEE 1149.1 standard violations: * * * * 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Boundary Scan Order (X36) (PH =Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 25 DQ15 6F 49 DQ22 2H 2 SA0 4P 26 DQ16 7E 50 DQ26 1H 3 SA12 4T 27 DQ11 6E 51 SBWc 3G 4 SA10 6R 28 DQ12 7D 52 ZQ 4D 5 SA11 5T 29 DQ17 6D 53 SS 4E 6 ZZ 7T 30 SA3 6A 54 C 4G 7 DQ0 6P 31 SA2 6C 55 C 4H 8 DQ5 7P 32 SA5 5C 56 SW 4M 9 DQ6 6N 33 SA4 5A 57 SBWd 3L 10 DQ1 7N 34 PH* 6B 58 DQ27 1K 11 DQ2 6M 35 PH* 5B 59 DQ31 2K 12 DQ7 6L 36 PH* 3B 60 DQ32 1L 13 DQ3 7L 37 PH* 2B 61 DQ28 2L 14 DQ4 6K 38 SA7 3A 62 DQ33 2M 15 DQ8 7K 39 SA6 3C 63 DQ34 1N 16 SBWa 5L 40 SA9 2C 64 DQ29 2N 17 K 4L 41 SA8 2A 65 DQ30 1P 18 K 4K 42 DQ18 2D 66 DQ35 2P 19 G 4F 43 DQ23 1D 67 SA13 3T 20 SBWb 5G 44 DQ24 2E 68 SA14 2R 21 DQ9 7H 45 DQ19 1E 69 SA1 4N 22 DQ13 6H 46 DQ20 2F 70 M1 3R 23 DQ14 7G 47 DQ25 2G 24 DQ10 6G 48 DQ21 1G 1. * Input of PH register connected to VSS 2. ** Input of PH register connected to VDD (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 20 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Boundary Scan Order (X18) (PH =Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 27 PH* 2B 2 SA10 6T 28 SA7 3A 3 SA0 4P 29 SA6 3C 30 SA9 2C . 4 SA11 6R 5 SA12 5T 31 SA8 2A 6 ZZ 7T 32 DQ9 1D 7 DQ0 7P 33 DQ10 2E 8 DQ1 6N 34 DQ11 2G 9 DQ2 6L 35 DQ12 1H 10 DQ3 7K 36 SBWb 3G 11 SBWa 5L 37 ZQ 4D 12 K 4L 38 SS 4E 13 K 4K 39 C 4G 14 G 4F 40 C 4H 15 DQ4 6H 41 SW 4M 16 DQ5 7G 42 DQ13 2K 17 DQ6 6F 43 DQ14 1L 18 DQ7 7E 44 DQ15 2M 19 DQ8 6D 45 DQ16 1N 20 SA3 6A 46 DQ17 2P 21 SA2 6C 47 SA14 3T 22 SA5 5C 48 SA15 2R 23 SA4 5A 49 SA1 4N 24 PH* 6B 50 SA13 2T 25 PH* 5B 51 M1 3R 26 PH* 3B 1. * Input of PH register connected to VSS 2. ** Input of PH register connected to VDD 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 0 1 1 Select IR 1 Capture IR Capture DR 0 0 Shift DR 0 Shift IR 0 1 1 1 1 Exit1 IR Exit1 DR 0 0 0 0 Pause DR Pause IR 1 1 Exit2 DR Exit2 IR 0 1 1 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 20 1 Update DR 0 0 Update IR 1 0 03H9038 SA14-4657-02 Revised 09/95 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary 7 x 17 BGA Dimensions 20.32 0.84 REF (119X) 0.75 0.15 Solder Ball 0.030" 0.006 7 6 3.19 REF 5 4 3 2 1 U T R P N M L K 7.62 1.27 J H G F E D C B A 12.00 0.25 14.00 22.00 Indicates A1 Location 20 0.25 1 0.25 Feature is for Lead Pin IDENTIFICATION Overmold 0.66 0.05 1.0 0.1 0.600 0.10 Typ 2.26 0.15 Note: All dimensions in Millimeters 03H9038 SA14-4657-02 Revised 09/95 (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 20 IBM043610QLA IBM041810QLA 32K X 36 & 64K X 18 SRAM Preliminary Revision Log Rev Contents of Modification 6/94 Initial Release of the 32K x 36 & 64K x 18 (5/6/7) BGA FLOW THRU Application Spec. 1/95 Addition of SRAM Features section. Changed parameter/signal names for JEDEC compatibility. 2/95 Add package dimensions and identify SA and DQ pins. 4/95 Correct ZQ in X36 pinout. 5/95 Release to Fax Server. 7/95 WWW Release. 9/95 Change tCHQV specs. (c)IBM Corporation, 1995. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 20 03H9038 SA14-4657-02 Revised 09/95 International Business Machines Corp.1996 Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com