BCM8212 PRODUCT Brief TRANSCEIVER WITH INTERNAL LOOP TIMING AND PHASE DETECTOR B C M 8 2 1 2 S U M M A R Y F E AT U R E S * 2.488-Gbps SONET/SDH transceiver with O F B E N E F I T S Low power consumption eliminates external heat * sinks, fans for system airflow, and expensive high dual differential serial I/O * Fully integrated CDR, MUX, DEMUX, and CMU with 16-bit, 155.52-MHz LVPECL interface * On-chip, PLL-based clock generator * Internal phase detector and charge pump for cleanup PLL * Line and system loopback modes * Loss-of-signal output (LOSB) and input (LOSIB) * TX and RX lock detect * Elastic buffering with FIFO overflow alarm * Selectable 77.76/155.52-MHz reference clock * Selectable RX clock and RX data squelch on LOS * Selectable loop timing mode * Dual 2.5V/3.3V supplies * Power dissipation: 1.2W typical * Selectable divide-by-32 or divide-by-16 receiver/ current power supplies. * Supports SONET dual-fiber ring architecture. High integration reduces design cycle and time to * market. * Provides increased port density per board and system. * Features low jitter: 3 mUIRMS typical. CMOS-based device uses the most effective silicon * economy of scale. Exceeds SONET jitter requirements, which allows the * use of low-cost optics. * Target applications: * OC-48/STM-16 transmission equipment * SONET/SDH optical modules * ADD/DROP multiplexers * Digital cross-connects * ATM switch backbone * SONET/SDH test equipment * Terabit and edge routers transmitter low-speed parallel output clock * Standard CMOS fabrication process * 23 x 23 mm, 208-pin BGA package Application Block Diagram 16 ORX 2.488 Gbps ORX OTX 155.52 Mbps 16 Network Interface Processor OTX BCM8212 155.52 Mbps 16 BCM8212 Network Interface Processor 16 B C M 8 2 1 2 O V E R V I E W Block Diagram PHDCKP PHDCKN A Phase Detector Charge Pump PD OUT PD LKDT FIFO Control RESETB CLK16IP OVFB Write Pointer CLK16IN TCK320 DI15 CKSEL 16:1 Parallelto-Serial Input Register DI0 16 x 5 FIFO Divide-by-2 Read Pointer B Output Retime TXDP TXDN M U X M TXCKP TXCKN RTSYNC M A B M U X REFCKP TCK16OP Divide-by-16 2.488 GHz PLL REFCKN REF 155EN DOSQ RCK16SQ TCK16ON TXLKDT F LVPECL REF IOVREF RDINP0 SELRD1 A LOSIB E VCN_CDR VCP_CDR J REFCKENB LPBKFB TSEL LPBKSB K CDR Divide-by-16 F Divide-by-2 L Loopback Logic L K DO15 F J RCK1SEL DO0 Output Register RDINP1 RDINN1 1:16 Serialto-Parallel M U X RDINN0 M U X M U X RCK16OP0 RCK16ON0 RCK16OP1 RCK16ON1 RXLKDT Loss Detect The BCM8212 SONET/SDH transceiver is a fully integrated serialization/deserialization SONET OC-48 (2.488 Gbps) interface device with an integrated Clock Multiplication Unit (CMU) and an integrated Clock and Data Recovery (CDR) circuit. On-chip clock synthesis is performed by the highfrequency and low-jitter, phase-locked loop on the BCM8212 transceiver chip, allowing the use of a slower 77.76/155.52-MHz external transmit clock reference. LOSB with the bit error rate requirements of the Telcordia GR-253CORE, ANSI, and ITU-T standards. The BCM8212 is packaged in a 23 x 23 x 1.53 mm, 208-pin BGA. The BCM8212 operates in a 2.5/3.3V configuration. The core and CML I/Os operate at 2.5V. The LVPECL I/Os operate at 3.3V. Dual RX and TX 2.488 Gbps interfaces support dual-fiber ring architectures. Clock recovery is performed on the device by synchronizing its on-chip VCO directly to the incoming data stream. The low-jitter, LVPECL interface guarantees compliance Broadcom(R), the pulse logo(R) and Connecting EverythingTM are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners. BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013 (c) 2002 by BROADCOM CORPORATION. All rights reserved. 8212-PB04-R-3.1.02 Phone: 949-450-8700 FAX: 949-450-8710 Email: info@broadcom.com Web: www.broadcom.com