ADVANCE INFORMATION Am29LV128M 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation -- 3 volt read, erase, and program operations Enhanced VersatileI/O control -- Device generates and tolerates all control and I/O voltages as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V Manufactured on 0.23 m MirrorBit process technology SecSi (Secured Silicon) Sector region -- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked at the factory or by the customer Flexible sector architecture -- Two hundred fifty-six 32 Kword (64 Kbyte) sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125C PERFORMANCE CHARACTERISTICS High performance -- 90 ns access time -- 25 ns page read times -- 0.4 s typical sector erase time -- 5.9 s typical write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word updates -- 4-word/8-byte page read buffer -- 16-word/32-byte write buffer Low power consumption (typical values at 3.0 V, 5 MHz) -- 30 mA typical active read current -- 50 mA typical erase/program current -- 1 A typical standby mode current Package options -- 56-pin TSOP -- 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word or byte programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Sector Group Protection: hardware-level method of preventing write operations within a sector group -- Temporary Sector Unprotect: VID-level method of changing code in locked sectors -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device -- Ready/Busy# output (RY/BY#) detects program or erase cycle completion This Data Sheet states AMD's current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 25270 Rev: A Amendment/+1 Issue Date: March 20, 2002 Refer to AMD's Website (www.amd.com) for the latest information. A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION The Am29LV128M is a 128 Mbit, 3.0 volt single power supply flash memory devices organized as 8,388,608 words or 16,777,216 bytes. The device has a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Ordering Information sections. The device is offered in a 56-pin TSOP or Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/OTM (VIO) control allows the host system to set the voltage levels that the device generates 2 and tolerates at all control and data I/Os to the same voltage level that is asserted on the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environment as required. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power c ons umption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSi (Secured Silicon) Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP#/ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. Am29LV128M A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE Part Number Am29LV128M VCC = 3.0-3.6 V Speed Option 90R (VIO = 3.0-3.6 V) VCC = 2.7-3.6 V 101 (VIO = 2.7-3.6 V) 112 (VIO = 1.65-3.6 V) 120 (VIO = 1.65-3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time (tPACC) 25 30 40 40 Max. OE# Access Time (ns) 25 30 40 40 BLOCK DIAGRAM DQ0-DQ15 (A-1) RY/BY# VCC Sector Switches VSS VIO Erase Voltage Generator Input/Output Buffers RESET# WE# WP#/ACC BYTE# State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# V CC Detector Address Latch STB Timer A22-A0 Am29LV128M STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 3 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAMS 4 NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Pin Standard TSOP 56-Pin Reverse TSOP Am29LV128M 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC NC A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 NC VIO 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAMS Fortified BGA Top View, Balls Facing Down A8 B8 C8 D8 E8 F8 G8 H8 NC A22 NC VIO VSS NC NC NC A7 B7 C7 D7 E7 F7 G7 H7 A13 A12 A14 A15 A16 A6 B6 C6 D6 E6 F6 G6 H6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A5 B5 C5 D5 E5 F5 G5 H5 WE# RESET# A21 A19 DQ5 DQ12 VCC DQ4 A4 B4 C4 D4 E4 F4 G4 H4 A18 A20 DQ2 DQ10 DQ11 DQ3 RY/BY# WP#/ACC BYTE# DQ15/A-1 VSS A3 B3 C3 D3 E3 F3 G3 H3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A2 B2 C2 D2 E2 F2 G2 H2 A3 A4 A2 A1 A0 CE# OE# VSS A1 B1 C1 D1 E1 F1 G1 H1 NC NC NC NC NC NC NC VIO Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not yet been determined. Contact AMD for further information. Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, SSOP, PLCC, PDIP). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Am29LV128M 5 A D V A N C E I N F O R M A T I O N PIN DESCRIPTION A22-A0 LOGIC SYMBOL = 23 Address inputs 23 DQ14-DQ0 = 15 Data inputs/outputs A22-A0 DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# CE# = Chip Enable input OE# OE# = Output Enable input WE# WE# = Write Enable input WP#/ACC WP#/ACC = Hardware Write Protect input; Acceleration input RESET# RESET# = Hardware Reset Pin input BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VIO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally 6 VIO BYTE# Am29LV128M 16 or 8 DQ15-DQ0 (A-1) RY/BY# A D V A N C E I N F O R M A T I O N ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV128M H 90R PC I TEMPERATURE RANGE I = Industrial (-40C to +85C) PACKAGE TYPE E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PC = 64-Ball Fortified Ball Grid Array (FBGA), 13 x 11 mm, 1.0 mm pitch (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = VIL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV128MH/L 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO Control 3.0 Volt-only Read, Program, and Erase Speed( ns) V IO Range V CC Range Am29LV128MH90R, Am29LV128ML90R 90 3.0-3.6 V 3.0-3.6 V Am29LV128MH101, Am29LV128ML101 100 2.7-3.6 V 110 1.65-3.6 V 120 1.65-3.6 V Valid Combinations for TSOP Package Am29LV128MH112, Am29LV128ML112 Am29LV128MH120, Am29LV128ML120 EI, FI Valid Combinations for Fortified BGA Package Order Number Package Marking Am29LV128MH90R, Am29LV128ML90R 2.7-3.6 V Am29LV128MH101, Am29LV128ML101 Am29LV128MH112, Am29LV128ML112 Am29LV128MH120, Am29LV128ML120 L128MH90R, L128ML90R PCI L128MH01V, L128ML01V L128MH11V, L128ML11V Speed V IO Range (ns) 90 3.0- 3.6 V 100 2.7- 3.6 V 110 1.65- 3.6 V 120 1.65- 3.6 V I L128MH12V, L128ML12V V CC Range 3.0- 3.6 V 2.7- 3.6 V Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV128M 7 A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS TS056/TSR056--56-Pin Standard/Reverse Thin Small Outline Package (TSOP) PACKAGE TS/TSR 56 JEDEC MO-142 (B) EC SYMBOL MIN. NOM. MAX. 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) A --- --- 1.20 2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). A1 0.05 --- 0.15 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. A2 0.95 1.00 1.05 4 b1 0.17 0.20 0.23 b c1 0.17 0.10 0.22 --- 0.27 0.16 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm. 7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. c 0.10 --- 0.21 D 19.90 20.00 20.20 D1 18.30 18.40 18.50 E 13.90 14.00 14.10 0.50 BASIC e L 0.50 0.60 0.70 O 0 3 5 R 0.08 --- 0.20 N 8 NOTES: 56 3160\38.10A Am29LV128M A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS LAA064--64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package Am29LV128M 9 A D V A N C E I N F O R M A T I O N REVISION SUMMARY Revision A (October 3, 2001) Ordering Information Initial release as abbreviated Advance Information data sheet. Corrected device density in device number/description. Physical Dimensions Revision A+1 (March 20, 2002) Added drawing that shows both TS056 and TSR056 specifications. Disitinctive Characteristics Clarified description of Enhanced VersatileIO control. Trademarks Copyright (c) 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 10 Am29LV128M