ADVANCE INFORMATION
This Data Sheet st ates AMD’s curr ent tech nical spec ifications reg arding the Product s describ ed herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 25270 Rev: AAmendment/+1
Issue Date: March 20, 2002
Refer to AMD
’
sWebs
i
te (www.amd.com) for the latest
i
nformat
i
on.
Am29LV128M
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit 3.0 Volt-only
Uniform Sector Flash Memory w i th Versa tileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■Single power supply operation
—3 volt read, erase, and program operations
■Enhanced Versat ileI/O control
—Device generates and tolerates all control and I/O
voltages as determined by the voltage on the VIO pi n;
operates fr om 1.65 to 3.6 V
■Manufactured on 0.23 µm MirrorBit process
technology
■SecSi (Secured Silicon) Sector region
—128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte rando m
Electronic S erial Number, accessible through a
command seque nce
—May be programmed and locked at the factory or by
the customer
■Flexible sector architecture
—Two hundred fifty-six 32 Kword (64 Kbyte) sectors
■Compatibility with JEDEC standards
—Prov ides pinout and software compatibility for
single-pow er suppl y flash, and superior inadvertent
write protection
■Minimum 100,000 erase cycle guarantee per sector
■20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■High performance
—90 ns access time
—25 ns page read t imes
—0.4 s typic al sector erase time
—5.9 µs typical write buffer word programming time:
16-word/32-byte w rite buffer reduces overall
programming time for multiple-wor d updates
—4-word/8-byte page read buffer
—16-word/32-byte write buffer
■Low power consumption (typical values at 3.0 V, 5
MHz)
—30 mA typical active read current
—50 mA typical erase/program current
—1 µA typical standby mode current
■Package options
—56-pin TSOP
—64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■Software features
—Program Suspend & Resume: read other sector s
before progra mming operation is completed
—Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
—Data# polling & toggle bits provide status
—Unlock Bypass Program command reduces ove rall
multiple-word or byte programming time
—CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■Hardware features
—Sector Group Protection: hardware-level method of
preventing write oper ations within a sector group
—Temporary Sector Unprotect: VID-level method of
changing code in locked sectors
—WP#/ACC input accel erates programming time
(when high vol tage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
—Hardware reset input (RESET#) resets device
—Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
2 Am29LV128M
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29LV 128M is a 128 Mbit, 3.0 v olt single power
supply flas h memory devices or ganized as 8,388,60 8
words or 16,777,216 bytes. The device has a 16-bit
wide data bus that can also function as an 8-bit wide
data bus by us ing the BYTE# input. The devic e c an be
prog ramme d eithe r in the host sy stem or in stan dard
EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (VCC) and an I/O voltage range (VIO), as
specif ied in the Product Selector Gui de and the Order-
ing Information sections. The dev ice is offered i n a
56-p in T SOP or Fortif ied BGA pac kage . Eac h de vic e
has se parat e chip en able (CE#) , w rite en able (W E#)
and output enable (OE#) controls.
Each device req uires only a single 3.0 volt po wer
supply for bo th read and wr ite functions. In addition to
a VCC input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times
through in creas ed curren t. This fea ture i s intended to
facilitate factory thro ughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
th e JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cyc les also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the d ata conte nts o f othe r sectors . The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (to ggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand seque nce o verhe ad by requi ring on ly two writ e
cycles to program data instead of four.
The VersatileI/O™ (VIO) control allows the ho st sys-
tem to set the voltage levels that the device generates
and tolerates at a ll control and data I/Os to the same
voltage level that is asserted on the VIO pin. This al-
lows the device to operate in a 1.8 V or 3 V system en-
vironment as required.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both progr am and er ase
operations in any combination of sectors of memory.
This can be achieve d in-syst em or via programming
equipment.
The Erase Susp end/Erase Resume feature allows
the host system to pause an erase operation in a
give n sec tor to r ead or progr am an y other sec tor and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given s ector
to read any other sector and then complete the pro-
gram operation.
The hardw are RESET# pin terminates any operation
in progress and res ets the device, aft er whic h it is then
ready for a new operation. Th e RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the dev ic e, enabling the host system to
read boot-up firmware fr om the Flash memory device.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on C E# an d R ESET#, or w hen ad dress es h ave b een
stable for a specified period of time.
The SecSi (Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
perm anently protec ted. Onc e th is sector is pro tected,
no further changes within the sector can occur.
The Writ e Pr ote ct (WP# /ACC) feature protec ts the
first or last sector by ass erting a logic low on the W P#
pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highe st levels of qua lity, re liability and co st effe c-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
Am29LV128M 3
ADVANCE INFORMATION
PRODUCT SELECTOR GUIDE
BLOCK DIAGRAM
Part Number Am29LV128M
Speed
Option
VCC = 3.0–3.6 V 90R
(VIO = 3.0–3.6 V)
VCC = 2.7–3.6 V 101
(VIO = 2.7–3.6 V) 112
(VIO = 1.65–3.6 V) 120
(VIO = 1.65–3.6 V)
Max. Access Time (ns) 90 100 110 120
Max. CE# Access Time (ns) 90 100 110 120
Max. Page access time (tPACC)25304040
Max. OE# Access Time (ns) 25 30 40 40
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
VIO
WE#
WP#/ACC
BYTE#
CE#
OE#
STB
STB
DQ0–DQ15 ( A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A22–A0
4 Am29LV128M
ADVANCE INFORMATION
CONNECTION DIAGRAMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
NC
NC
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
23
24
25
26
27
28
A4
A3
A2
A1
NC
NC
34
33
32
31
30
29
OE#
VSS
CE#
A0
NC
VIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
NC
NC
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0 23
24
25
26
27
28
A4
A3
A2
A1
NC
NC
34
33
32
31
30
29
OE#
VSS
CE#
A0
NC
VIO
56-Pin Standard TSOP
56-Pin Reverse TSOP
Am29LV128M 5
ADVANCE INFORMATION
CONNECTION DIAGRAMS
Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not
yet been determined. Contact AMD for further information.
Special Package Handling Instructions
Special handling is required f or Flash Memory produc ts
in molded packages (TSOP, BGA, SSOP, PLCC,
PDIP). The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
A2 C2 D2 E2 F2 G2 H2
A3 C3 D3 E3 F3 G3 H3
A4 C4 D4 E4 F4 G4 H4
A5 C5 D5 E5 F5 G5 H5
A6 C6 D6 E6 F6 G6 H6
A7 C7 D7 E7 F7 G7 H7
DQ15/A-1 VSSBYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSSCE#A0A1A2A4A3
A1 C1 D1 E1 F1 G1 H1
NC NC
VIO
NCNCNCNCNC
A8 C8
B2
B3
B4
B5
B6
B7
B1
B8 D8 E8 F8 G8 H8
NC NC
NCVSS
VIO
NCA22NC
Fortified BGA
Top View, Balls Facing Down
6 Am29LV128M
ADVANCE INFORMATION
PIN DESCRIPTION
A22–A0 = 23 Address inputs
DQ14–DQ0 = 15 Data inputs/outputs
DQ15/A-1 = DQ15 (Data input/output, word mode),
A-1 (LSB Address input, byte mode)
CE# = Chip Enable input
OE# = Output Enable input
WE# = Write Enable input
WP#/ACC = Hardware W rite Protec t input ;
Acceler ation input
RESET# = Hardware Reset Pin input
BYTE# = Selects 8-bit or 16-bit mode
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for
speed optio ns and voltage
supply tolerances)
VIO = Output Buffer power
VSS = Device Ground
NC = Pin Not Connected Internally
LOGIC SYMBOL
23 16 or 8
DQ15–DQ0
(A-1)
A22–A0
CE#
OE#
WE#
RESET#
RY/BY#
WP#/ACC
VIO
BYTE#
Am29LV128M 7
ADVANCE INFORMATION
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The or der number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
V al id Comb inati ons li st conf igu ration s plan ned to b e supp orted in vol -
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
le as ed combinations.
Am29LV128M H 90R PC I
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)
F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)
PC = 64-Ball Fortified Ball Grid Array (FBGA),
13 x 11 mm, 1.0 mm pitch (LAA064)
SPEED OPT ION
See Product Selector Guide and Valid Combinations
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = VIL)
H = Uniform sector device, highest address sector protected
L = Uniform sector device, lowest address sector protected
DEVIC E NUM BER/DES CRIPTION
Am29LV128MH/L
128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO Control
3.0 Volt-only Read, Program , and Erase
Valid C o m b in a tion s for
TSOP Package Speed(
ns) VIO
Range VCC
Range
Am29LV128MH90R,
Am29LV128ML90R
EI,
FI
90 3.0–3.6 V 3.0–3.6 V
Am29LV128MH101,
Am29LV128ML101 100 2.7–3.6 V
2.7–3.6 V
Am29LV128MH112,
Am29LV128ML112 110 1.65–3.6 V
Am29LV128MH120,
Am29LV128ML120 120 1.65–3.6 V
Valid C o m b in a tion s for
Fortified BGA Package Speed
(ns) VIO
Range VCC
Range
Order Number Package Marking
Am29LV128MH90R,
Am29LV128ML90R
PCI
L128MH90R,
L128ML90R
I
90 3.0–
3.6 V 3.0–
3.6 V
Am29LV128MH101,
Am29LV128ML101 L128MH01V,
L128ML01V 100 2.7–
3.6 V
2.7–
3.6 V
Am29LV128MH112,
Am29LV128ML112 L128MH11V,
L128ML11V 110 1.65–
3.6 V
Am29LV128MH120,
Am29LV128ML120 L128MH12V,
L128ML12V 120 1.65–
3.6 V
8 Am29LV128M
ADVANCE INFORMATION
PHYSICAL DIMENSIONS
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)
NOTES:
1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)
2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTUSION IS 0.15 mm PER SIDE.
6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b
DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN
PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.
7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10 mm AND 0.25 mm FROM THE LEAD TIP.
8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE
SEATING PLANE.
9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3160\38.10A
MO-142 (B) EC
TS/TSR 56
NOM.
---
---
1.00
1.20
0.15
1.05
MAX.
---
MIN.
0.95 0.20 0.230.17 0.22 0.270.17 --- 0.160.10 --- 0.210.10 20.00 20.2019.90
14.00 14.1013.90
0.60 0.700.50 3˚ 5˚0˚ --- 0.200.08 56
18.40 18.5018.30
0.05
0.50 BASIC
E
R
b1
JEDEC
PACKAGE
SYMBOL
A
A2
A1
D1
D
c1
c
b
e
L
N
O
Am29LV128M 9
ADVANCE INFORMATION
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package
10 Am29LV128M
ADVANCE INFORMATION
REVISION SUMMARY
Revision A (October 3, 2001)
Initial release as abbreviated Advance Information
data sheet.
Revision A+1 (March 20, 2002)
Disitinctive Characteristics
Clarified description of Enhanced VersatileIO control.
Ordering Information
Corrected device dens ity in device number/des crip-
tion.
Physical Dimensions
Added drawing that shows both TS056 and TSR056
specifications.
Trademarks
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
