1
DSC-2661/13
2002 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice.
SEPTEMBER 2002
CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9
8,192 x 9, 16,384 x 9
32,768 x 9 and 65,536 x 9
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
••
••
•First-In/First-Out Dual-Port memory
••
••
•2,048 x 9 organization (IDT7203)
••
••
•4,096 x 9 organization (IDT7204)
••
••
•8,192 x 9 organization (IDT7205)
••
••
•16,384 x 9 organization (IDT7206)
••
••
•32,768 x 9 organization (IDT7207)
••
••
•65,636 x 9 organization (IDT7208)
••
••
•High-speed: 12ns access time
••
••
•Low power consumption
— Active: 660mW (max.)
— Power-down: 44mW (max.)
••
••
•Asynchronous and simultaneous read and write
••
••
•Fully expandable in both word depth and width
••
••
•Pin and functionally compatible with IDT720X family
••
••
•Status Flags: Empty, Half-Full, Full
••
••
•Retransmit capability
••
••
•High-performance CMOS technology
••
••
•Military product compliant to MIL-STD-883, Class B
••
••
•Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567
(IDT7203), and 5962-89568 (IDT7204) are listed on this function
DESCRIPTION:
The IDT7203/7204/7205/7206/7207/7208 are dual-port memory buffers
with internal pointers that load and empty data on a first-in/first-out basis. The
device uses Full and Empty flags to prevent data overflow and underflow and
expansion logic to allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of the Write (W) and
Read (R) pins.
The device's 9-bit width provides a bit for a control or parity at the user’s
option. It also features a Retransmit (RT) capability that allows the read pointer
to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is
available in the single device and width expansion modes.
These FIFOs are fabricated using IDT’s high-speed CMOS technology.
They are designed for applications requiring asynchronous and simultaneous
read/writes in multiprocessing, rate buffering and other applications.
Military grade product is manufactured in compliance with the latest revision
of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
•
Industrial temperature range (–40
°
C to +85
°
C) is available
(plastic packages only)
W WRITE
CONTROL
READ
CONTROL
R
FLAG
LOGIC
EXPANSION
LOGIC
XI
WRITE
POINTER
RAM ARRAY
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
32,768 x 9
65,536 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA OUTPUTS
EF
FF
XO/HF
RS
FL/RT
0
(D -D8
)
0
(Q -Q 8
)
2661 drw01
2
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
PIN CONFIGURATIONS
Symbol Rating Com'l & Ind'l Military Unit
VTERM Terminal –0.5 to +7.0 –0.5 to +7.0 V
Voltage with
Respect to GND
TSTG Storage –55 to + 125 –65 to +155 °C
Temperature
IOUT DC Output –50 to +50 –50 to +50 mA
+Current
Reference Order Device
Package Type Identifier Code Availability
PLASTIC DIP P28-1 P All devices
PLASTIC THIN DIP P28-2 TP All except IDT7207/7208
CERDIP D28-1 D All except IDT7208
THIN CERDIP D28-3 TD Only for IDT7203/7204/7205
SOIC SO28-3 SO Only for IDT7204
Reference Order Device
Package Type Identifier Code Availability
PLCC J32-1 J All devices
LCC(1) L32-1 L All except IDT7208
TOP VIEW TOP VIEW
NOTE:
1. This package is only available in the military temperature range.
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
For RT/RS/XI input, VIH = 2.6V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
5
6
7
8
9
10
11
12
13
FF
XI
GND
1
2
3
4
14
28
27
26
25
24
23
22
21
EF
XO/HF
Vcc
FL/RT
RS
20
19
18
17
16
15
W
D
4
Q
7
R
2661 drw02a
D
5
D
7
D
6
Q
6
Q
5
Q
4
Q
8
Q
3
Q
2
Q
1
Q
0
D
8
D
3
D
2
D
1
D
0
5
6
7
8
9
10
11
12
13
FF
XI
Q
0
29
28
27
26
25
24
23
22
21
EF
XO/HF
D
6
NC
FL/RT
RS
14
15
16
17
18
19
20
4
3
2
1
32
31
30
INDEX
NC
W
NC
Vcc
GND
NC
R
2661 drw02b
D
7
D
4
D
5
D
8
D
3
D
2
D
1
D
0
Q
1
Q
2
Q
7
Q
6
Q
4
Q
5
Q
8
Q
3
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
Commercial/Industrial/Military
GND Supply Voltage 0 0 0 V
VIH(1) Input High Voltage 2.0 — — V
Commercial/Industrial
VIH(1) Input High Voltage Military 2.2 — — V
VIL(2) Input Low Voltage — — 0.8 V
Commercial/Industrial/Military
TAOperating Temperature Commercial 0 — 70 °C
TAOperating Temperature Industrial –40 — 85 °C
TAOperating Temperature Military –55 — 125 °C
3
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
IDT7203(1) IDT7203
IDT7204(1) IDT7204
Commercial and Industrial Military(3)
tA = 12, 15, 20, 25, 35, 50 ns tA = 20, 30, 40 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
ILI(6) Input Leakage Current (Any Input) – 1 — 1 – 1 — 1 µA
ILO(7) Output Leakage Current –10 — 10 –10 — 10 µA
VOH Output Logic “1” Voltage IOH = –2mA 2. 4 — — 2. 4 — — V
VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V
ICC1(8,9,10) Active Power Supply Current — — 1 20 — — 150 mA
ICC2(8,10,11) Standby Current (R=W=RS=FL/RT=VIH) ——12— —25mA
ICC3(8,10,12) Power Down Current — — 2 — — 4 mA
AC TEST CONDITIONS
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grades are available
as a standard device.
2. Industrial temperature range product for 25ns speed grade only is available as a standard
device. All other speed grades are available by special order.
3. Military temperature range product for the 40ns is only available for 7203.
4. Commercial temperature range product for the 12ns not available.
5. Commercial temperature range product for the 12ns, 15ns and 50ns not available.
IDT7205(2) IDT7205
IDT7206(2,4) IDT7206
IDT7207(2,4) IDT7207
IDT7208(2,5)
Commercial and Industrial Military
tA = 12, 15, 20, 25, 35, 50 ns tA = 20, 30 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
ILI(6) Input Leakage Current (Any Input) – 1 — 1 – 1 — 1 µA
ILO(7) Output Leakage Current –10 — 10 –10 — 10 µA
VOH Output Logic “1” Voltage IOH = –2mA 2. 4 — — 2.4 — — V
VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V
ICC1(8,9,10) Active Power Supply Current — — 1 20 — — 150 mA
ICC2(8,10,11) Standby Current (RS=FL/RT=VIH)——12——25mA
ICC3(8,10,12) Power Down Current — — 8 — — 12 mA
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
1.1KΩ
30pF*
680Ω
5V
D.U.T.
or equivalent circuit
2661 drw03
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, T A = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
6. Measurements with 0.4 ≤ VIN ≤ VCC.
7. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
8. Tested with outputs open (IOUT = 0).
9. R and W toggle at 20 MHz and data inputs switch at 10 MHz.
10. ICC measurements are made with outputs open.
11. All Inputs = VCC - 0.2V or GND + 0.2V, except R and W, which toggle at 20MHz.
12. All Inputs = VCC - 0.2V or GND + 0.2V, except R and W = VCC -0.2V.
CAPACITANCE(1) (TA = +25°C, f = 1.0 MHz)
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
Symbol Parameter Condition Max. Unit
CIN(1) Input Capacitance VIN = 0V 10 pF
COUT(1,2) Output Capacitance VOUT = 0V 10 pF
Figure 1. Output Load
*Includes jig and scope capacitances.
4
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Commercial Com'l & Ind'l Com'l & Military Commercial Com'l & Ind'l
IDT7203L12 IDT7203L15(2) IDT7203L20 IDT7208L20 IDT7203L25(2)
IDT7204L12 IDT7204L15(2) IDT7204L20 IDT7204L25(2)
IDT7205L12 IDT7205L15 IDT7205L20 IDT7205L25(3)
IDT7206L15 IDT7206L20 IDT7206L25(3)
IDT7207L15 IDT7207L20 IDT7207L25(3)
IDT7208L25(3)
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fSShift Frequency — 50 — 40 — 33.3 — 33.3 — 28.5 MHz
tRC Read Cycle Time 2 0 — 25 — 3 0 — 3 0 — 3 5 — ns
tAAccess Time — 12 — 15 — 2 0 — 2 0 — 2 5 ns
tRR Read Recovery Time 8 — 10 — 1 0 — 10 — 10 — ns
tRPW Read Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns
tRLZ Read LOW to Data Bus LOW(5) 3—5 —5—5—5—ns
tWLZ Write HIGH to Data Bus Low-Z(5,6) 3—5 —5—5—5—ns
tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — 5 — n s
tRHZ Read HIGH to Data Bus High-Z(5) — 12 — 15 — 15 — 15 — 18 ns
tWC Write Cycle Time 2 0 — 2 5 — 3 0 — 3 0 — 3 5 — ns
tWPW Write Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns
tWR Write Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tDS Data Set-up Time 9 — 11 — 12 — 12 — 15 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — ns
tRSC Reset Cycle Time 2 0 — 2 5 — 3 0 — 3 0 — 3 5 — ns
tRS Reset Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns
tRSS Reset Set-up Time(5) 12 — 15 — 20 — 20 — 25 — ns
tRTR Reset Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tRTC Retransmit Cycle Time 20 — 25 — 30 — 30 — 35 — ns
tRT Retransmit Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns
tRTS Retransmit Set-up Time(5) 12 — 15 — 20 — 20 — 25 — ns
tRTR Retransmit Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tEFL Reset to EF LOW — 12 — 25 — 30 — 30 — 35 ns
tHFH, tFFH Reset to HF and FF HIGH — 17 — 25 — 30 — 30 — 35 n s
tRTF Retransmit LOW to Flags Valid — 20 — 25 — 30 — 30 — 35 ns
tREF Read LOW to EF LOW — 12 — 15 — 20 — 20 — 25 ns
tRFF Read HIGH to FF HIGH — 14 — 15 — 20 — 20 — 25 ns
tRPE Read Pulse Width after EF HIGH 1 2 — 1 5 — 2 0 — 2 0 — 25 — ns
tWEF Write HIGH to EF HIGH — 12 — 15 — 20 — 20 — 25 ns
tWFF Write LOW to FF LOW — 14 — 15 — 20 — 20 — 25 ns
tWHF Write LOW to HF Flag LOW — 1 7 — 2 5 — 3 0 — 3 0 — 3 5 n s
tRHF Read HIGH to HF Flag HIGH — 17 — 25 — 30 — 30 — 35 ns
tWPF Write Pulse Width after FF HIGH 1 2 — 1 5 — 2 0 — 2 0 — 2 5 — ns
tXOL Read/Write LOW to XO LOW — 12 — 15 — 20 — 20 — 25 ns
tXOH Read/Write HIGH to XO HIGH — 12 — 15 — 20 — 20 — 25 ns
tXI XI Pulse Width(4) 12 — 15 — 20 — 20 — 25 — ns
tXIR XI Recovery Time 8 — 10 — 10 — 10 — 10 — ns
tXIS XI Set-up Time 8 — 10 — 10 — 10 — 10 — ns
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, T A = –55°C to +125°C)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.
3. Industrial temperature range product for 25ns speed grade only is available as a standard device. All other speed grades are available by special order.
4. Pulse widths less than minimum are not allowed.
5. Values guaranteed by design, not currently tested.
6. Only applies to read data flow-through mode.
5
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
AC ELECTRICAL CHARACTERISTICS(1) (CONTINUED)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, T A = –55°C to +125°C)
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
Military Commercial Military Commercial
IDT7203L30 IDT7203L35 IDT7203L40 IDT7203L50
IDT7204L30 IDT7204L35 IDT7204L50
IDT7205L30 IDT7205L35 IDT7205L50
IDT7206L30 IDT7206L35 IDT7206L50
IDT7207L30 IDT7207L35 IDT7207L50
IDT7208L35
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Unit
fSShift Frequency — 25 — 22.22 — 20 — 15 MHz
tRC Read Cycle Time 40 — 45 — 50 — 65 — n s
tAAccess Time — 3 0 — 35 — 4 0 — 50 ns
tRR Read Recovery Time 1 0 — 1 0 — 10 — 15 — ns
tRPW Read Pulse Width(2) 30 — 35 — 40 — 50 — ns
tRLZ Read LOW to Data Bus LOW(3) 5— 5—5—10—ns
tWLZ Write HIGH to Data Bus Low-Z(3,4) 5 — 10 — 10 — 15 — ns
tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — ns
tRHZ Read HIGH to Data Bus High-Z(3) —20 —20—25—30ns
tWC Write Cycle Time 4 0 — 4 5 — 5 0 — 6 5 — ns
tWPW Write Pulse Width(2) 30 — 35 — 40 — 50 — ns
tWR Write Recovery Time 10 — 10 — 10 — 15 — ns
tDS Data Set-up Time 18 — 18 — 20 — 30 — ns
tDH Data Hold Time 0 — 0 — 0 — 5 — ns
tRSC Reset Cycle Time 4 0 — 4 5 — 5 0 — 6 5 — ns
tRS Reset Pulse Width(2) 30 — 35 — 40 — 50 — ns
tRSS Reset Set-up Time(3) 30 — 35 — 40 — 50 — ns
tRTR Reset Recovery Time 1 0 — 10 — 10 — 15 — ns
tRTC Retransmit Cycle Time 40 — 45 — 50 — 65 — ns
tRT Retransmit Pulse Width(2) 30 — 35 — 40 — 50 — ns
tRTS Retransmit Set-up Time(3) 30 — 35 — 40 — 50 — ns
tRTR Retransmit Recovery Time 10 — 10 — 10 — 15 — ns
tEFL Reset to EF LOW —40 —45—50—65ns
tHFH, tFFH Reset to HF and FF HIGH — 40 — 45 — 50 — 65 ns
tRTF Retransmit LOW to Flags Valid — 40 — 45 — 50 — 65 ns
tREF Read LOW to EF LOW —30 —30—35—45ns
tRFF Read HIGH to FF HIGH — 30 — 30 — 35 — 45 ns
tRPE Read Pulse Width after EF HIGH 30 — 3 5 — 4 0 — 5 0 — n s
tWEF Write HIGH to EF HIGH — 30 — 30 — 35 — 45 ns
tWFF Write LOW to FF LOW —30 —30—35—45ns
tWHF Write LOW to HF Flag LOW — 4 0 — 4 5 — 5 0 — 6 5 n s
tRHF Read HIGH to HF Flag HIGH — 40 — 45 — 50 — 65 ns
tWPF Write Pulse Width after FF HIGH 30 — 3 5 — 4 0 — 5 0 — ns
tXOL Read/Write LOW to XO LOW —30 —35—40—50ns
tXOH Read/Write HIGH to XO HIGH — 30 — 35 — 40 — 50 ns
tXI XI Pulse Width(2) 30 — 35 — 40 — 50 — ns
tXIR XI Recovery Time 10 — 10 — 10 — 10 — n s
tXIS XI Set-up Time 10 — 15 — 15 — 15 — ns
6
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
loaded (see Operating Modes). The Single Device Mode is initiated by grounding
the Expansion In (XI).
The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data
when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit
operation will set the internal read pointer to the first location and will not affect the
write pointer. The status of the Flags will change depending on the relative locations
of the read and write pointers. Read Enable (R) and Write Enable (W) must be
in the HIGH state during retransmit. This feature is useful when less than 2,048/
4,096/8,192/16,384/32,768/65,536 writes are performed between resets. The
retransmit feature is not compatible with the Depth Expansion Mode.
EXPANSION IN ( XI ) — This input is a dual-purpose pin. Expansion In (XI)
is grounded to indicate an operation in the single device mode. Expansion In (XI)
is connected to Expansion Out (XO) of the previous device in the Depth Expansion
or Daisy-Chain Mode.
OUTPUTS:
FULL FLAG ( FF ) — The Full Flag (FF) will go LOW, inhibiting further write
operations, when the device is full. If the read pointer is not moved after Reset (RS),
the Full Flag (FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536
writes.
EMPTY FLAG ( EF ) — The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer, indicating that
the device is empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF ) — This is a dual-purpose
output. In the single device mode, when Expansion In (XI) is grounded, this output
acts as an indication of a half-full memory.
After half of the memory is filled, and at the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an XO pulse when the Write
pointer reaches the last location of memory, and an additional XO pulse when the
Read pointer reaches the last location of memory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data.
These outputs are in a high-impedance condition whenever Read (R) is in a HIGH
state.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
CONTROLS:
RESET ( RS ) — Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and write pointers are set
to the first location. A reset is required after power-up before a write operation can
take place. Both the Read Enable (R) and Write Enable (W) inputs must
be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before
the rising edge of RS) and should not change until tRSR after the rising
edge of RS.
WRITE ENABLE ( W ) — A write cycle is initiated on the falling edge of this
input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-
to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM
array sequentially and independently of any on-going read operation.
After half of the memory is filled, and at the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference
between the write pointer and read pointer is less-than or equal to one-half of the
total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge
of the last write signal, which inhibits further write operations. Upon the completion
of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a
new valid write to begin. When the FIFO is full, the internal write pointer is blocked
from W, so external changes in W will not affect the FIFO when it is full.
READ ENABLE ( R ) — A read cycle is initiated on the falling edge of the Read
Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on
a First-In/First-Out basis, independent of any ongoing write operations. After Read
Enable (R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-
impedance condition until the next Read operation. When all the data has been
read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read
cycle but inhibiting further read operations, with the data outputs remaining in a high-
impedance state. Once a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the
FIFO is empty, the internal read pointer is blocked from R so external changes will
not affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT ( FL/RT ) — This is a dual-purpose input. In
the Depth Expansion Mode, this pin is grounded to indicate that it is the first device
7
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Figure 4. Full Flag Timing From Last Write to First Read
NOTE:
1. W and R = VIH around the rising edge of RS.
Figure 2. Reset
Figure 3. Asynchronous Write and Read Operation
W
RS
R
EF
HF, FF
tRSC
tRS
tRSS
tRSS
tRSR
tEFL
tHFH, tFFH
2661 drw04
R
W
D0-D8
tRC
tA
tWR
tDS
DATA
tDH
tWPW
tWC
VALID
tRHZ
tDV
tA
tRR
tRPW
IN VALID
DATA OUT VALIDDATA OUT
DATA IN VALID
2661 drw05
Q0-Q8
tRLZ
R
W
FF
tRFF
tWFF
FIRST READ
IGNORED
WRITE
LAST WRITE
2661 drw06
8
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Figure 5. Empty Flag Timing From Last Read to First Write
NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse.
W
R
EF
t
WEF
t
REF
FIRST WRITE
IGNORED
READ
LAST READ
DATA
OUT
VALID
t
A
2661 drw07
t
RTC
t
RT
t
RTS
RT
W,R
HF, EF, FF
t
RTR
FLAG VALID
2661 drw08
t
RTF
EF
W
R
t
RPE
2661 drw09
t
WEF
FF
R
W
t
WPF
2661 drw10
t
RFF
Figure 6. Retransmit
9
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Figure 9. Half-Full Flag Timing
Figure 10. Expansion Out
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by
each system (i.e. FF is monitored on the device where W is used; EF is monitored
on the device where R is used). For additional information on the IDT7203/7204/
7205/7206/7207, refer to Tech Note 8: Operating FIFOs on Full and Empty
Boundary Conditions and Tech Note 6: Designing with FIFOs.
Single Device Mode
A single IDT7203/7204/7205/7206/7207/7208 may be used when the
application requirements are for 2,048/4,096/8,192/16,384/32,768/65,536 words
or less. These FIFOs are in a Single Device Configuration when the Expansion
In (XI) control input is grounded (see Figure 12).
Depth Expansion
These FIFOs can easily be adapted to applications when the require-
ments are for greater than 2,048/4,096/8,192/16,384/32,768/65,536 words.
Figure 14 demonstrates Depth Expansion using three IDT7203/7204/7205/
7206/7207/7208s. Any depth can be attained by adding additional IDT7203/
7204/7205/7206/7207/7208s. These devices operate in the Depth Expansion
mode when the following conditions are met:
1. The first device must be designated by grounding the First Load (FL) control
input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion
In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (FF) and Empty
Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all
must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in
the Depth Expansion Mode.
For additional information on the IDT7203/7204/7205/7206/7207, refer to
Tech Note 9: Cascading FIFOs or FIFO Modules.
W
R
HF
HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS
t
RHF
t
WHF
2661 drw11
W
R
XO
WRITE TO
LAST PHYSICAL
LOCATION
t
XOL
t
XOH
READ FROM
LAST PHYSICAL
LOCATION
2661 drw12
t
XOH
t
XOL
W
R
XI
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
tXI tXIR
2661 drw13
tXIS
tXIS
10
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
IDT
7203
7204
7205
7206
7207
7208
XI XI
9
18
9
WRITE (W)
FULL FLAG (FF)
RESET (RS)
9918
HFHF
DATA (D)
IN
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
DATA (Q)
OUT
IDT
7203
7204
7205
7206
7207
7208
2661 drw15
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the corresponding input
control signals of multiple devices. Status flags (EF, FF and HF) can be detected
from any one device. Figure 13 demonstrates an 18-bit word width by using
two IDT7203/7204/7205/7206/7207/7208s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206/7207/7208s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7203/7204/7205/7206/7207/7208s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read flow-through and
write flow-through mode. For the read flow-through mode (Figure 17), the
FIFO permits a reading of a single word after writing one word of data into an
empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing of
a single word of data immediately after reading one word of data from a full FIFO.
The R line causes the FF to be deasserted but the W line being LOW causes
it to be asserted again in anticipation of a new data word. On the rising edge of
W, the new word is loaded in the FIFO. The W line must be toggled when FF
is not asserted to write new data in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode
WRITE (W)
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
9
READ (R)
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
(HF)
IDT
7203
7204
7205
7206
7207
7208
(HALF-FULL FLAG)
2661 drw14
Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode
11
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
TRUTH TABLES
TABLE 1 – RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
NOTE:
1. Pointer will Increment if flag is HIGH.
TABLE 2 – RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
NOTES:
1. XI is connected to XO of previous device. See Figure 14.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
Figure 14. Block Diagram of 6,144 x 9, 12,288 x 9, 24,576 x 9, 49,152 x 9, 98,304 x 9, 196,608 x 9 FIFO Memory (Depth Expansion)
D
W
IDT
7203
7204
7205
7206
7207
7208
FF EF
FL
XO
RS
FULL EMPTY
V
CC
R
9
9
99
XI
9Q
FF EF
FL
XO
XI
FF EF
FL
XO
XI
IDT
7203
7204
7205
7206
7207
7208
IDT
7203
7204
7205
7206
7207
7208
2661 drw16
Inputs Internal Status Outputs
Mode RS FL/RT XI Read Pointer Write Pointer EF FF HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment(1) Increment(1) XXX
Inputs Internal Status Outputs
Mode RS FL/RT XI Read Pointer Write Pointer EF FF
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset All Other Devices 0 1 (1 ) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
12
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13..
Figure 16. Bidirectional FIFO Operation
IDT
7201A
R
B
EF
B
HF
B
W
A
FF
A
W
B
FF
B
SYSTEM A SYSTEM B
Q
B 0-8
D
B 0-8
Q
A 0-8
R
A
HF
A
EF
A
IDT
7203
7204
7205
7206
7207
7208
D
A 0-8
IDT
7203
7204
7205
7206
7207
7208
2661 drw18
R, W, RS
D0-DN
D0-D8
D9-DN
D9-D17
D18-DN
D(N-8)-DN
D(N-8)-DN
Q(N-8)-QN
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
DEPTH
EXPANSION
BLOCK
2661 drw17
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
DEPTH
EXPANSION
BLOCK
IDT7203
IDT7204
IDT7205
IDT7206
IDT7207
IDT7208
DEPTH
EXPANSION
BLOCK
Q(N-8)-QN
Q9-Q17
Q9-Q17
Q0-Q8
Q0-Q8
Figure 15. Compound FIFO Expansion
13
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
Figure 17. Read Data Flow-Through Mode
W
DATA
R
tRPE
IN
EF
DATA OUT
tWLZ tWEF tREF
DATA OUT VALID
2661 drw19
tA
Figure 18. Write Data Flow-Through Mode
R
DATA
IN
W
FF
DATA
OUT
t
DH
t
WFF
DATA
IN
VALID
DATA
OUT
VALID
2661 drw20
t
RFF
t
A
t
WPF
t
DS
14
CORPORATE HEADQUARTERS for SALES: for TECH SUPPORT:
2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753
Santa Clara, CA 95054 fax: 408-492-8674 e-mail: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device for IDT7203/7204, and 25ns speed grade only is available as a
standard device for IDT7205/7206/7207/7208. All other speed grades are available by special order.
2. The LCC is only available in the military temperature range.
3. The IDT7208 is only available in commercial speed grades of 20, 25 and 35 ns.
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
I
(1)
B
Industrial (−40° to +85°C)
Military (−55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
TP
D
TD
J
L
(2)
SO
Plastic DIP P28-1
Plastic Thin DIP P28-2 (all except 7207/7208)
CERDIP D28-1 (all except 7208)
Thin CERDIP D28-3 (only for 7203/7204/7205)
Plastic Leaded Chip Carrier PLCC J32-1
Leadless Chip Carrier LCC L32-1 (all except 7208)
Small Outline IC SOIC SO28-3 (only 7204)
12
15
20
(3)
25
(3)
30
35
(3)
40
50
Commercial 7203/04/05 Only
Commercial and (Industrial only 7203/04)
Commercial and Military
Commercial and Industrial
Military Only
Commercial Only
Military 7203 Only
Commercial Only
XXXX
Device Type
7203
7204
7205
7206
7207
7208
(3)
IDT
L Low Power
Access Time (t
A
)
Speed in
Nanoseconds
2661 drw21
2,048 x9 FIFO
4,096 x 9 FIFO
8,192 x 9 FIFO
16,384 x 9 FIFO
32,768 x 9 FIFO
65,536 x 9 FIFO
DATA SHEET HISTORY
05/10/2001 pgs. 2, 3, 4, 5, 11 and 14.
05/30/2001 pg. 2.
