1 Septem ber 26, 2002
UL62H256B
F32768 x 8 bit static CMOS RAM
F35 and 55 ns Access Time
FCommon data inputs and
data outputs
FThree-state outputs
FTyp. operating supply current
35 ns: 45 mA
55 ns: 30 mA
FStandby current < 30 µA at 125 °C
FPower supply voltage 2.5 V
FOperati ng temperature range
-40 °C to 85 °C
-40 °C to 125 °C
FCECC 90000 Quality Standard
FESD protection > 2000 V
(MIL STD 883C M3015.7)
FLatch-up immuni ty >100 m A
FPackage: SOP 28 (300/330 mi l)
The UL62H256B is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read - Standby
- Writ e - Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simul taneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word will be available at the
outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new i nformation
is available. The d ata outputs have
no preferred state. T he R ead cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
Data retention is guaranteed down
to 1.5 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Low Voltage Automotive Fast 32K x 8 SRAM
Pin Configuration
Top View
Signal Name Signal Descripti on
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Out
EChip Enable
GOutpu t Enable
WWrite Enable
VCC Power Supply Voltage
VSS Ground
Pin Description
1
A14 VCC28
2A12 W
27
4A6 A825
5A5 A924
3A7 A1326
6A4 A1123
7A3 G
22
8A2 A1021
12DQ1 DQ517
9A1 E
20
10
A0 DQ719
11DQ0 DQ618
13DQ2 DQ416
14VSS DQ315
SOP
Features Description
2 Septem ber 26, 200 2
UL62H256B
Operati ng Mod e E W G DQ0 - DQ7
Standby/not selected H * * High-Z
Internal Read L H H High-Z
R ead L H L Data Outputs Low-Z
Write L L * Da ta In p uts Hig h-Z
Truth Tab l e
Block Diagram
Maxim um Ratings aSymbol Min. Max. Unit
Power Supply Voltage VCC -0.3 4 V
Input Voltage VI-0.3 VCC + 0.3 bV
Outpu t Voltage VO-0.3 VCC + 0.3 bV
Power Dissipation PD-1W
Operating Temperature K-Type
A-Type Ta-40
-40 85
125 °C
Stor age Temperature Tstg -65 150 °C
Outpu t Short-Circuit Current
at VCC = 2.5 V and VO = 0 V c | I OS |100mA
Characteristics
a Stresses greater than those listed under Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, a nd f unct iona l ope ra tion of the dev ice at con ditio n ab ove th ose indi cate d in th e o perat ion al s ecti ons of t his sp ecif icati on is not impl ied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b Maximum vol tage is 4 V
c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
All voltages are referenced to VSS = 0 V (ground).
All character istics are valid in the power supply voltage range and i n the operating temperature range specified.
Dynamic measurements are ba sed on a rise and fall ti me of 5 ns, measured between 10 % and 90 % of VI,as well as
input levels of VIL = 0 V and VIH = 2.2 V. The timing reference level of all input and output signals is 1.1 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC VSS W GE
Row Address
Inputs
Column Address
Inputs
Address
Change
Detector
Column Decoder Row Decoder
Se ns e Amp lifie r /
Write Control Logic
Clock
Generator
Co mmo n Data I/O
Memory Cell
Array
512 Rows x
64 x 8 Columns
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
*H or L
3 Septem ber 26, 2002
UL62H256B
Recommended
Operating Conditions Symbol Conditions Min. Max. Unit
Power Supply Voltage VCC 2.3 2.7 V
Input Low V ol tage d VIL -0.2 0.4 V
Input High Voltage VIH 2.0 VCC + 0.2 V
Electrical Characteristic s Symbol Co nd itions Min. Max. Unit
Suppl y Current - Operating Mode
Suppl y Current - Standby Mode
(CMOS level)
Suppl y Current - Standby Mode
(TT L lev e l)
ICC(OP)
ICC(SB)
ICC(SB)1
VCC
VIL
VIH
tcW
tcW
tcW
VCC
VE
Ta
Ta
Ta
VCC
VE
Ta
Ta
= 2.7 V
= 0.6 V
= 2.0 V
= 35 ns
= 55 ns
= 70 ns
= 2.7 V
= VCC - 0. 2 V
70 °C
85 °C
125 °C
= 2.7 V
= 2.2 V
85 °C
125 °C
90
70
60
3
6
30
10
20
mA
mA
mA
µA
µA
µA
mA
mA
Outpu t High Voltage
Outpu t Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 2.3 V
=-0.5 mA
= 2.3 V
= 0.5 mA
2.0
0.4
V
V
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 2.7 V
= 2.7 V
= 2.7 V
= 0 V -2
A
µA
Outpu t High Current
Outpu t Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 2.3 V
= 2.0 V
= 2.3 V
= 0.4 V 0.5
-0.5 mA
mA
Outpu t Leakage Current
High at Three-State Outputs
Low at Three-St ate Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 2.7 V
= 2.7 V
= 2.7 V
=0 V -2
A
µA
d -2 V at Pulse Width 30 ns
4 Septem ber 26, 200 2
UL62H256B
Switching Characteristics
Read Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Read Cycle Time tRC tcR 35 55 ns
Address Access Tim e to Data Va lid tAA ta(A) 35 55 ns
Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns
G LOW to Data Valid tOE ta(G) 15 25 ns
E HIGH to Output in High-Z tHZCE tdis(E) 12 15 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
E LOW to Output in Low-Z tLZCE ten(E) 33ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
Output Hold Time from Address Change tOH tv(A) 33ns
E LOW to Power-Up Time tPU 00ns
E HIGH to Power-Down Time tPD 35 55 ns
Switching Characteristics
Write Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Write Cycle Time tWC tcW 35 55 ns
Write Pulse Width tWP tw(W) 20 35 ns
Write Setup Time tWP tsu(W) 20 35 ns
Address Setup Ti me tAS tsu(A) 00ns
Address Valid to End of Write tAW tsu(A-WH) 25 40 ns
Chip Enable Setup T i me tCW tsu(E) 25 40 ns
Pulse Width Chip Enable to End of Wri te tCW tw(E) 25 40 ns
Data Setup Time tDS tsu(D) 15 25 ns
Data Hold Time tDH th(D) 00ns
Address Hold from End of Write tAH th(A) 00ns
W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
W HIGH to Output in Low-Z tLZWE ten(W) 00ns
G LOW to Outp u t in Low- Z tLZOE ten(G) 00ns
5 Septem ber 26, 2002
UL62H256B
Data Retenti on Mo de
E - control led
Data Retention
2.3 V
tsu(DR) trec
VCC
E
VCC(DR) 1.5 V
0 V
2.0 V
2. 0 V
VCC(DR) - 0.2 V VE(DR) VCC(DR) + 0.3 V
Data Retention
Characteristics Symbol Conditions Min. Typ. Max. Unit
Alt. IEC
Data Retention Sup ply Voltage VCC(DR) 1.5 V
Data Retention Supply Current ICC(DR) VCC(DR) = 2 V
VE = VCC(DR) - 0.2 V
Ta 70 °C
Ta 85 °C
Ta 125 °C
3
5
20
µA
µA
µA
Data Retention Setup Time tCDR tsu(DR) See Data Retention
Waveforms (above) 0ns
Operating Recovery T i m e tRtrec tcR ns
Test Con f iguration for Functional Check
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VIH
VIL
VSS
VCC
2.5 V
3332
3077
VO
Input level according to the
relevant test measurement
Simultaneous measure-
ment of all 8 output pin s
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
W
G
e In measurement of tdis(E),tdis(W), ten(E), ten(W), t en(G) the capacitance is 5 pF.
30 pF e
6 Septem ber 26, 200 2
UL62H256B
Capacitance Conditions Symbol Min. Max. Unit
Input Capacit ance VCC
VI
f
Ta
= 2.5 V
= VSS
= 1 MHz
= 25 °C
CI7pF
Output Capacitance Co7pF
IC Code Numbers
UL62H256B SA35
Type
Package
S = SOP28 300 mil
S1 = SOP 28 330 mil
Operating Temperature Range
K = -40 to 85 °C
A = -40 to 125 °C
Access Time
35 = 35 ns
55 = 55 ns
The date of manufacture is given by the last 4 digits of the third line of the mark, the first 2 digit s indicating the year,
and the last 2 digits the calendar w eek.
Assembl y location and trace code are shown in line 4.
All pins not under test must be connected with ground by capacitors.
7 Septem ber 26, 2002
UL62H256B
tPU
tdis(G)
tdis(E)
tcR
Previous Data Valid Output Data Valid
Ad dres s Va li d
Addres s Valid
tsu(A)
High-Z
ten(E)
ten(G)
ta(G)
ta(E)
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
Read Cycle 2: G-, E-cont rolled (during Read Cycle: W = VIH)
ta(A)
tcR
tv(A)
Ai
DQi
Output
Ai
G
DQi
Output tPD
ICC(OP)
ICC(SB) 50 % 50 %
Output Data Valid
E
8 Septem ber 26, 200 2
UL62H256B
Write Cycle1: W-controlled
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A)
tsu(D)
tdis(W) ten(W)
Address Valid
Inpu t D ata Vali d
High-Z
tsu(A-WH)
Write Cycle 2: E-controlled
In p ut Data Valid
tsu(A)
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tw(E) th(A)
tsu(W)
tsu(D)
tdis(W)
t
en(E)
High-Z
Addres s Valid
tdis(G)
L- to H - lev e l undefined H- to L-level
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to c hange design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstra ße 28 D-01109 Dresden P. O. B. 80 01 34 D-01101 Dresden Ge rmany
Phone: +49 351 8822 306Fax: +49 351 8822 337 Email: memory@zmd.de http://www.zmd.de
September 26, 2002
UL62H256B
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the bod y, or other applica tio ns intended to support or s ustain life, or for an y other appl ication in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Compone nts used in life-support devices or systems must be expressly authorized by ZMD for such purpos e.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The inform ation in thi s doc um ent des cr ibes the t ype of com ponent and shall not be cons id ered as as sured c ha rac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe up on th e patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to ma ke change s in the products or specifications, or both,
presented in this publication at any time and without notice.