LTC2641/LTC2642
1
26412fd
For more information www.linear.com/LTC2641
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
16-/14-/12-Bit VOUT DACs in
3mm × 3mm DFN
The LTC
®
2641/LTC2642 are families of 16-, 14- and 12-bit
unbuffered voltage output DACs. These DACs operate from
a single 2.7V to 5.5V supply and are guaranteed mono-
tonic over temperature. The LTC2641A-16/LTC2642A-16
provide 16-bit performance (±1LSB INL and ±1LSB DNL)
over temperature. Unbuffered DAC outputs result in low
supply current of 120µA and a low offset error of ±1LSB.
Both the LTC2641 and LTC2642 feature a reference input
range of 2V to VDD. VOUT swings from 0V to VREF
. For
bipolar operation, the LTC2642 includes matched scaling
resistors for use with an external precision op amp (such
as the LT1678), generating a ±VREF output swing at RFB.
The LTC2641/LTC2642 use a simple SPI/MICROWIRE
compatible 3-wire serial interface which can be operated
at clock rates up to 50MHz and can interface directly
with optocouplers for applications requiring isolation. A
power-on reset circuit clears the LTC2641’s DAC output
to zero scale and the LTC2642’s DAC output to midscale
when power is initially applied. A logic low on the CLR pin
asynchronously clears the DAC to zero scale (LTC2641)
or midscale (LTC2642). These DACs are all specified over
the commercial and industrial ranges.
n Tiny 3mm × 3mm 8-Pin DFN Package
n Maximum 16-Bit INL Error: ±1LSB over Temperature
n Low 120µA Supply Current
n Guaranteed Monotonic over Temperature
n Low 0.5nV•sec Glitch Impulse
n 2.7V to 5.5V Single Supply Operation
n Fast 1µs Settling Time to 16 Bits
n Unbuffered Voltage Output Directly Drives 60k Loads
n 50MHz SPI/QSPI/MICROWIRE
Compatible
Serial Interface
n Power-On Reset Clears DAC Output to Zero Scale
(LTC2641) or Midscale (LTC2642)
n Schmitt-Trigger Inputs for Direct Optocoupler
Interface
n Asynchronous CLR Pin
n 8-Lead MSOP and 3mm × 3mm DFN Packages
(LTC2641)
n 10-Lead MSOP and 3mm × 3mm DFN Packages
(LTC2642)
n High Resolution Offset and Gain Adjustment
n Process Control and Industrial Automation
n Automatic Test Equipment
n Data Acquisition Systems
Bipolar 16-Bit DAC
LTC2642-16 Integral Nonlinearity
–
+
16-BIT DATA LATCH
CONTROL
LOGIC
16-BIT DAC
1/2 LT1678
INV
RFB
VDD
V
REF
2V TO VDD
BIPOLAR VOUT
–VREF TO VREF
0.1µF
5pF
REF
2.7V TO 5.5V
VOUT
GND 26412 TA01a
16-BIT SHIFT REGISTER
1µF0.1µF
LTC2642
POWER-ON
RESET
CS
SCLK
DIN
CLR
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
26412 TA01b
–0.6
0.6
0.8
0.2
49152 65535
VDD = 5V
VREF = 2.5V
±2.5V RANGE
INL 25°C
INL 90°C
INL –45°C
L, LT, LTC , LT M, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
LTC2641/LTC2642
2
26412fd
For more information www.linear.com/LTC2641
ABSOLUTE MAXIMUM RATINGS
VDD to GND .................................................. –0.3V to 6V
CS, SCLK, DIN,
CLR to GND ......................... –0.3V to (VDD + 0.3V) or 6V
REF, VOUT, INV to GND ........–0.3V to (VDD + 0.3V) or 6V
RFB to INV ....................................................... –6V to 6V
RFB to GND ..................................................... –6V to 6V
GND to GND (S8 Package) OBSOLETE .... –0.3V to 0.3V
(Note 1)
PIN CONFIGURATION
Operating Temperature Range
LTC2641C/LTC2642C ............................... 0°C to 70°C
LTC2641I/LTC2642I .............................–40°C to 85°C
Maximum Junction Temperature (Note 2) ............ 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
LTC2641 LTC2641 LTC2641
TOP VIEW
9
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
1REF
CS
SCLK
DIN
GND
VDD
VOUT
CLR
TJMAX = 125°C (NOTE 2), θJA = 43°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
REF
CS
SCLK
DIN
8
7
6
5
GND
VDD
VOUT
CLR
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C (NOTE 2), θJA = 120°C/W
1
2
3
4
8
7
6
5
TOP VIEW
VDD
GND
DIN
SCLK
VOUT
GND
REF
CS
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 110°C/W
OBSOLETE PACKAGE
LTC2642 LTC2642
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1GND
VDD
RFB
INV
VOUT
REF
CS
SCLK
DIN
CLR
TJMAX = 125°C (NOTE 2), θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
REF
CS
SCLK
DIN
CLR
10
9
8
7
6
GND
VDD
RFB
INV
VOUT
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C (NOTE 2), θJA = 120°C/W
LTC2641/LTC2642
3
26412fd
For more information www.linear.com/LTC2641
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2641ACDD-16#PBF LTC2641ACDD-16#TRPBF LCZP 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2641CDD-16#PBF LTC2641CDD-16#TRPBF LCZP 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2641CDD-14#PBF LTC2641CDD-14#TRPBF LCZN 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2641CDD-12#PBF LTC2641CDD-12#TRPBF LCZM 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2641AIDD-16#PBF LTC2641AIDD-16#TRPBF LCZP 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2641IDD-16#PBF LTC2641IDD-16#TRPBF LCZP 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2641IDD-14#PBF LTC2641IDD-14#TRPBF LCZN 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2641IDD-12#PBF LTC2641IDD-12#TRPBF LCZM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2641ACMS8-16#PBF LTC2641ACMS8-16#TRPBF LTCZS 8-Lead Plastic MSOP 0°C to 70°C
LTC2641CMS8-16#PBF LTC2641CMS8-16#TRPBF LTCZS 8-Lead Plastic MSOP 0°C to 70°C
LTC2641CMS8-14#PBF LTC2641CMS8-14#TRPBF LTCZR 8-Lead Plastic MSOP 0°C to 70°C
LTC2641CMS8-12#PBF LTC2641CMS8-12#TRPBF LTCZQ 8-Lead Plastic MSOP 0°C to 70°C
LTC2641AIMS8-16#PBF LTC2641AIMS8-16#TRPBF LTCZS 8-Lead Plastic MSOP –40°C to 85°C
LTC2641IMS8-16#PBF LTC2641IMS8-16#TRPBF LTCZS 8-Lead Plastic MSOP –40°C to 85°C
LTC2641IMS8-14#PBF LTC2641IMS8-14#TRPBF LTCZR 8-Lead Plastic MSOP –40°C to 85°C
LTC2641IMS8-12#PBF LTC2641IMS8-12#TRPBF LTCZQ 8-Lead Plastic MSOP –40°C to 85°C
LTC2642ACDD-16#PBF LTC2642ACDD-16#TRPBF LCZW 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2642CDD-16#PBF LTC2642CDD-16#TRPBF LCZW 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2642CDD-14#PBF LTC2642CDD-14#TRPBF LCZV 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2642CDD-12#PBF LTC2642CDD-12#TRPBF LCZT 10-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC2642AIDD-16#PBF LTC2642AIDD-16#TRPBF LCZW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2642IDD-16#PBF LTC2642IDD-16#TRPBF LCZW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2642IDD-14#PBF LTC2642IDD-14#TRPBF LCZV 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2642IDD-12#PBF LTC2642IDD-12#TRPBF LCZT 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC2642ACMS-16#PBF LTC2642ACMS-16#TRPBF LTCZZ 10-Lead Plastic MSOP 0°C to 70°C
LTC2642CMS-16#PBF LTC2642CMS-16#TRPBF LTCZZ 10-Lead Plastic MSOP 0°C to 70°C
LTC2642CMS-14#PBF LTC2642CMS-14#TRPBF LTCZY 10-Lead Plastic MSOP 0°C to 70°C
LTC2642CMS-12#PBF LTC2642CMS-12#TRPBF LTCZX 10-Lead Plastic MSOP 0°C to 70°C
LTC2642AIMS-16#PBF LTC2642AIMS-16#TRPBF LTCZZ 10-Lead Plastic MSOP –40°C to 85°C
LTC2642IMS-16#PBF LTC2642IMS-16#TRPBF LTCZZ 10-Lead Plastic MSOP –40°C to 85°C
LTC2642IMS-14#PBF LTC2642IMS-14#TRPBF LTCZY 10-Lead Plastic MSOP –40°C to 85°C
LTC2642IMS-12#PBF LTC2642IMS-12#TRPBF LTCZX 10-Lead Plastic MSOP –40°C to 85°C
OBSOLETE
LTC2641CS8-16#PBF LTC2641CS8-16#TRPBF 264116 8-Lead Plastic SO 0°C to 70°C
LTC2641IS8-16#PBF LTC2641IS8-16#TRPBF 264116 8-Lead Plastic SO –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2641/LTC2642
4
26412fd
For more information www.linear.com/LTC2641
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Input
VREF Reference Input Range l2.0 VDD V
RREF Reference Input Resistance (Note 5) Unipolar Mode (LTC2641)
Bipolar Mode (LTC2642)
l
l
11
8.5
14.8
11.4
kΩ
kΩ
Dynamic Performance—VOUT
SR Voltage Output Slew Rate Measured from 10% to 90% 15 V/µs
Output Settling Time To ±0.5LSB of FS 1 µs
DAC Glitch Impulse Major Carry Transition 0.5 nV•s
Digital Feedthrough Code = 0000hex; NCS = VDD;
SCLK, DIN 0V to VDD Levels
0.2 nV•s
Output Voltage Noise Density 10 nV/√Hz
Dynamic Performance—Reference Input
BW Reference –3dB Bandwidth Code = FFFFhex 1.3 MHz
Reference Feedthrough Code = 0000hex, VREF = 1VP-P at 100kHz 1 mVP-P
SNR Signal-to-Noise Ratio 92 dB
CIN(REF) Reference Input Capacitance Code = 0000hex
Code = FFFFhex
75
120
pF
pF
Digital Inputs
VIH Digital Input High Voltage VCC = 3.6V to 5.5V
VCC = 2.7V to 3.6V
l
l
2.4
2.0
V
V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS
LTC2641-12
LTC2642-12
LTC2641-14
LTC2642-14
LTC2641-16
LTC2642-16
LTC2641A-16
LTC2642A-16
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Static Performance
N Resolution l12 14 16 16 Bits
Monotonicity l12 14 16 16 Bits
DNL Differential Nonlinearity (Note 3) l±0.5 ±0.5 ±1 ±0.5 ±1 ±0.5 ±1 LSB
INL Integral Nonlinearity (Note 3) l±0.5 ±0.5 ±1 ±0.5 ±2 ±0.5 ±1 LSB
ZSE Zero Code Offset Error Code = 0 l1 2 2 2 LSB
ZSTC Zero Code Tempco ±0.05 ±0.05 ±0.05 ±0.05 ppm/°C
GE Gain Error l±0.5 ±2 ±1 ±4 ±2 ±5 ±2 ±5 LSB
GETC Gain Error Tempco ±0.1 ±0.1 ±0.1 ±0.1 ppm/°C
ROUT DAC Output Resistance (Note 4) 6.2 6.2 6.2 6.2 kΩ
Bipolar Resistor Matching (LTC2642) RFB/RINV 1 1 1 1
Ratio Error (Note 7) l±0.1 ±0.03 ±0.015 ±0.015 %
BZE Bipolar Zero Offset Error (LTC2642) l±0.5 ±2 ±0.5 ±4 ±2 ±5 ±2 ±5 LSB
BZSTC Bipolar Zero Tempco (LTC2642) ±0.1 ±0.1 ±0.1 ±0.1 ppm/°C
PSR Power Supply Rejection ΔVDD = ±10% l±0.5 ±0.5 ±1 ±1 LSB
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
LTC2641/LTC2642
5
26412fd
For more information www.linear.com/LTC2641
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: LTC2641-16/LTC2642-16 ±1LSB = ±0.0015% = ±15.3ppm of full
scale. LTC2641-14/LTC2642-14 ±1LSB = ±0.006% = ±61ppm of full scale.
LTC2641-12/LTC2642-12 ±1LSB = ±0.024% = ±244ppm of full scale.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
l
l
0.8
0.6
V
V
IIN Digital Input Current VIN = GND to VDD l±1 µA
CIN Digital Input Capacitance (Note 6) l3 10 pF
VHHysteresis Voltage 0.15 V
Power Supply
VDD Supply Voltage l2.7 5.5 V
IDD Supply Current, VDD Digital Inputs = 0V or VDD l120 200 µA
PDPower Dissipation Digital Inputs = 0V or VDD, VDD = 5V
Digital Inputs = 0V or VDD, VDD = 3V
0.60
0.36
mW
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t1DIN Valid to SCLK Setup Time l10 ns
t2DIN Valid to SCLK Hold Time l0 ns
t3SCLK Pulse Width High l9 ns
t4SCLK Pulse Width Low l9 ns
t5CS Pulse High Width l10 ns
t6LSB SCLK High to CS High l8 ns
t7CS Low to SCLK High l8 ns
t8CS High to SCLK Positive Edge l8 ns
t9CLR Pulse Width Low l15 ns
fSCLK SCLK Frequency 50% Duty Cycle l50 MHz
VDD High to CS Low (Power-Up Delay) 30 µs
Note 4: ROUT tolerance is typically ±20%.
Note 5: Reference input resistance is code dependent. Minimum is at
871Chex (34,588) in unipolar mode and at 671Chex (26, 396) in bipolar
mode.
Note 6: Guaranteed by design and not production tested.
Note 7: Guaranteed by gain error and offset error testing, not production
tested.
LTC2641/LTC2642
6
26412fd
For more information www.linear.com/LTC2641
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
Integral Nonlinearity (INL)
vs Supply (VDD)INL vs VREF
Differential Nonlinearity (DNL)
Differential Nonlinearity (DNL)
vs Supply (VDD)DNL vs VREF
INL vs Temperature DNL vs Temperature Bipolar Zero Error vs Temperature
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
26412 G01
–0.6
0.6
0.8
0.2
49152 65535
LTC2642-16
VREF = 2.5V
VDD = 5V
VDD (V)
2
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
34
26412 G02
–0.6
0.6
0.8
0.2
56
VREF = 2.5V
+INL
–INL
VREF (V)
2
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
34
26412 G03
–0.6
0.6
0.8
0.2
56
VDD = 5.5V
+INL
–INL
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
26412 G04
–0.6
0.6
0.8
0.2
49152 65535
LTC2642-16
VREF = 2.5V
VDD = 5V
VDD (V)
2
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
34
26412 G05
–0.6
0.6
0.8
0.2
56
VREF = 2.5V
+DNL
–DNL
VREF (V)
2
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
34
26412 G06
–0.6
0.6
0.8
0.2
56
VDD = 5.5V
+DNL
–DNL
TEMPERATURE (°C)
–40
INL (LSB)
0.2
0.6
60
26412 G07
–0.2
–0.6
0
0.4
0.8
1.0
–0.4
–0.8
–1.0 –15 10 35 85
VREF = 2.5V
VDD = 5V
+INL
–INL
TEMPERATURE (°C)
–40
DNL (LSB)
0.2
0.6
60
26412 G08
–0.2
–0.6
0
0.4
0.8
1.0
–0.4
–0.8
–1.0 –15 10 35 85
VREF = 2.5V
VDD = 5V
+DNL
–DNL
TEMPERATURE (°C)
–40
BZE (LSB)
1
3
60
26412 G09
–1
–3
0
2
4
5
–2
–4
–5 –15 10 35 85
VREF = 2.5V
VDD = 5V
LTC2641/LTC2642
7
26412fd
For more information www.linear.com/LTC2641
TYPICAL PERFORMANCE CHARACTERISTICS
Bipolar Gain Error vs Temperature
Unbuffered Zero Scale Error vs
Temperature (LTC2641-16)
Unbuffered Full-Scale Error vs
Temperature (LTC2641-16)
14-Bit Integral Nonlinearity (INL)
(LTC2642-14) IREF vs Code (Unipolar LTC2641)
14-Bit Differential Nonlinearity
(DNL) (LTC2642-14)
12-Bit Integral Nonlinearity (INL)
(LTC2642-12)
12-Bit Differential Nonlinearity
(DNL) (LTC2642-12) IREF vs Code (Bipolar LTC2642)
TEMPERATURE (°C)
–40
BGE (LSB)
1
3
60
26412 G10
–1
–3
0
2
4
5
–2
–4
–5 –15 10 35 85
VREF = 2.5V
VDD = 5V
TEMPERATURE (°C)
–40
ZSE (LSB)
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
60
26412 G11
0
–1.0 –15 10 35 85
TEMPERATURE (°C)
–40
FSE (LSB)
60
26412 G12
–15 10 35 85
1.0
0.8
0.6
0.4
0.2
–0.2
0
–0.4
–0.6
–0.8
–1.0
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
26412 G13
–0.6
0.6
0.8
0.2
12288 16383
LTC2642-14
VREF = 2.5V
VDD = 5V
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
26412 G14
–0.6
0.6
0.8
0.2
12288 16383
LTC2642-14
VREF = 2.5V
VDD = 5V
CODE
0
IREF (µA)
100
150
65535
26412 G15
50
016384 32768 49152
250
200
VREF = 2.5V
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
26412 G16
–0.6
0.6
0.8
0.2
3072 4095
LTC2642-12
VREF = 2.5V
VDD = 5V
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
26412 G17
–0.6
0.6
0.8
0.2
3072 4095
LTC2642-12
VREF = 2.5V
VDD = 5V
CODE
0
IREF (µA)
100
150
65535
26412 G18
50
016384 32768 49152
250
200
VREF = 2.5V
LTC2641/LTC2642
8
26412fd
For more information www.linear.com/LTC2641
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current (IDD) vs
Temperature
Supply Current (IDD) vs Supply
Voltage (VDD)
Supply Current (IDD) vs VREF
,
VDD = 5V
Supply Current (IDD) vs VREF
,
VDD = 3V Midscale Glitch Impulse
Full-Scale Transition Full-Scale Settling (Zoomed In)
VOUT vs VDD = 0V to 5.5V
(POR Function) LTC2641
Supply Current (IDD) vs Digital
Input Voltage
TEMPERATURE (°C)
–40
0
IDD (µA)
25
50
75
100
125
150
–15 10 35 60
26412 G19
85
VREF = 2.5V
VDD = 5V
VDD = 3V
VDD (V)
2.5
0
IDD (µA)
25
50
75
100
150
33.5 4 4.5
26412 G20
5 5.5
125
VREF = 2.5V
DIGITAL INPUT VOLTAGE (V)
0
0
IDD (µA)
100
300
400
500
3 3.5 4 4.5
900
26412 G21
200
0.5 1 1.5 2 2.5 5
600
700
800
VDD = 5V
VDD = 3V
VREF (V)
1
0
IDD (µA)
25
50
75
100
2 3 45
26412 G22
125
150
1.5 2.5 3.5 4.5
VDD = 5V
VREF (V)
1
0
I
DD
(µA)
25
50
75
100
1.5 2 2.5 3
26412 G23
125
150 VDD = 3V CS
5V/DIV
VOUT
20mV/DIV
CODE
32767
CODE
32768
CODE
32767
500ns/DIV 26412 G24
LTC2641-16
UNBUFFERED
CL = 10pF
CS
5V/DIV
VOUT
1V/DIV
500ns/DIV 26412 G25
LTC2641-16
UNBUFFERED
CL = 10pF
VREF = 2.5V
VDD = 5V
CS
5V/DIV
SETTLE
RESIDUE
250µV/DIV
500ns/DIVLTC2641-16
VREF = 2.5V
CONSULT FACTORY FOR
MEASUREMENT CIRCUIT
26412 G26
VOUT
10mV/DIV
VDD = VREF
0V TO 5.5V
2V/DIV
50ms/DIV 26412 G27
LTC2641-16
UNBUFFERED
CL = 10pF
LTC2641/LTC2642
9
26412fd
For more information www.linear.com/LTC2641
PIN FUNCTIONS
LTC2641 – MSOP, DFN Packages
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
CS (Pin 2): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 4): Serial Interface Data Input. Data is applied to
DIN for transfer to the device at the rising edge of SCLK.
CLR (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to code 0.
VOUT (Pin 6): DAC Output Voltage. The output range is
0V to VREF
.
VDD (Pin 7): Supply Voltage. Set between 2.7V and 5.5V.
GND (Pin 8): Circuit Ground.
Exposed Pad (DFN Pin 9): Circuit Ground. Must be sol-
dered to PCB ground.
LTC2641 – SO Package OBSOLETE
VOUT (Pin 1): DAC Output Voltage. The output range is
0V to VREF.
GND (Pin 2): Circuit Ground.
REF (Pin 3): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
CS (Pin 4): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 5): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 6): Serial Interface Data Input. Data is applied to
DIN for transfer to the device at the rising edge of SCLK.
GND (Pin 7): Circuit Ground Pin. Must be connected to
Pin 2 (GND).
VDD (Pin 8): Supply Voltage. Set between 2.7V and 5.5V.
LTC2642 – MSOP, DFN Packages
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
CS (Pin 2): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 4): Serial Interface Data Input. Data is applied to
DIN for transfer to the device at the rising edge of SCLK.
CLR (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to midscale.
VOUT (Pin 6): DAC Output Voltage. The output range is
0V to VREF
.
INV (Pin 7): Center Tap of Internal Scaling Resistors.
Connect to an external amplifier’s inverting input in bi-
polar mode.
RFB (Pin 8): Feedback Resistor. Connect to an external
amplifier’s output in bipolar mode. The bipolar output
range is –VREF to VREF
.
VDD (Pin 9): Supply Voltage. Set between 2.7V and 5.5V.
GND (Pin 10): Circuit Ground.
Exposed Pad (DFN Pin 11): Circuit Ground. Must be
soldered to PCB ground.
LTC2641/LTC2642
10
26412fd
For more information www.linear.com/LTC2641
BLOCK DIAGRAMS
LTC2641 - MSOP, DFN
LTC2642
16-BIT DATA LATCH
CONTROL
LOGIC
16-/14-/12-BIT DAC
VDD REF
VOUT
GND
2641 BD01a
16-BIT SHIFT REGISTER
POWER-ON
RESET
LTC2641-16
LTC2641-14
LTC2641-12
CS
SCLK
DIN
CLR
6
8
5
4
3
2
17
16-BIT DATA LATCH
CONTROL
LOGIC
16-/14-/12-BIT DAC
INV
RFB
VDD REF
VOUT
GND
2642 BD
16-BIT SHIFT REGISTER
POWER-ON
RESET
LTC2642-16
LTC2642-14
LTC2642-12
CS
SCLK
DIN
CLR
8
7
6
10
5
4
3
2
19
LTC2641 - SO
OBSOLETE PACKAGE
16-BIT DATA LATCH
CONTROL
LOGIC
16-/14-/12-BIT DAC
VDD REF
VOUT
GND
2641 BD01b
16-BIT SHIFT REGISTER
POWER-ON
RESET
LTC2641-16
CS
SCLK
DIN
GND
1
2
7
6
5
4
38
LTC2641/LTC2642
11
26412fd
For more information www.linear.com/LTC2641
OPERATION
TIMING DIAGRAM
General Description
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
±1LSB integral linearity error and less than ±1LSB differ-
ential linearity error, guaranteeing monotonic operation.
They operate from a single supply ranging from 2.7V to
5.5V, consuming 120µA (typical). An external voltage
reference of 2V to VDD determines the DAC’s full-scale
output voltage. A 3-wire serial interface allows the LTC2641/
LTC2642 to fit into a small 8-/10-pin MSOP or DFN 3mm
× 3mm package.
Digital-to-Analog Architecture
The DAC architecture is a voltage switching mode resis-
tor ladder using precision thin-film resistors and CMOS
switches. The LTC2641/LTC2642 DAC resistor ladders are
composed of a proprietary arrangement of matched DAC
sections. The four MSBs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
impulse is very low at 500pV•sec, CL = 10pF, ten times
lower than previous DACs of this type.
The digital-to-analog transfer function at the VOUT pin is:
VOUT(IDEAL) =k
2
N
VREF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and VREF is between 2.0V and
VDD (see Tables 1a, 1b and 1c).
The LTC2642 includes matched resistors that are tied
to an external amplifier to provide bipolar output swing
(Figure 2). The bipolar transfer function at the RFB pin is:
VOUT _BIPOLAR(IDEAL) =VREF
k
2
N–1 – 1
(see Tables 2a, 2b and 2c).
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
chip select input (CS) controls and frames the loading of
serial data from the data input (DIN). Following a CS high-
to-low transition, the data on DIN is loaded, MSB first, into
the shift register on each rising edge of the serial clock
t
1
SCK
SDI
CS/LD
t5t7
t2t6
t8
26412 TD
1 2 3 15 16
t3t4
LTC2641/LTC2642
12
26412fd
For more information www.linear.com/LTC2641
OPERATION
input (SCLK). After 16 data bits have been loaded into the
serial input register, a low-to-high transition on CS trans-
fers the data to the 16-bit DAC latch, updating the DAC
output (see Figures 1a, 1b, 1c). While CS remains high,
the serial input shift register is disabled. If there are less
than 16 low-to-high transitions on SCLK while CS remains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on SCLK while CS remains low, only the last 16 data bits
loaded from DIN will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justified) position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four “don’t-care” bits must
follow the LSB (Figure 1c).
Power-On Reset
The LTC2641/LTC2642 include a power-on reset circuit
to ensure that the DAC output comes up in a known
state. When VDD is first applied, the power-on reset cir-
cuit sets the output of the LTC2641 to zero-scale (code
0). The LTC2642 powers up to midscale (bipolar zero).
Depending on the DAC number of bits, the midscale code
is: 32,768 (LTC2642-16); 8,192 (LTC2642-14); or 2,048
(LTC2642-12).
Clearing the DAC
A low pulse meeting the t9 (minimum) specification on
the CLR pin asynchronously clears the DAC latch to code
zero (LTC2641) or to midscale (LTC2642).
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
D15
MSB
1
CS
SCLK
DIN
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D14 D13 D12 D11 D10 D9 D8
DATA (16 BITS)
D7 D6 D5 D4 D3 D2 D1 D0
DAC
UPDATED
LSB 26412 F01a
D13
MSB
1
CS
SCLK
DIN
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D12 D11 D10 D9 D8 D7 D6
DATA (14 BITS + 2 DON’T-CARE BITS)
D5 D4 D3 D2 D1 D0 X X
DAC
UPDATED
LSB 26412 F01b
MSB
1
CS
SCLK
DIN
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D11 D10 D9 D8 D7 D6
DATA (12 BITS + 4 DON’T-CARE BITS)
D5 D4 D3 D2 D1 D0 X X X X
DAC
UPDATED
LSB 26412 F01c
LTC2641/LTC2642
13
26412fd
For more information www.linear.com/LTC2641
APPLICATIONS INFORMATION
Unipolar Configuration
Figure 2 shows a typical unipolar DAC application for
the LTC2641. Tables 1a, 1b and 1c show the unipolar
binary code tables for 16-bit, 14-bit and 12-bit operation.
–
+
16-BIT DAC
1/2 LTC6078
5V/3V
5V/3V
V
REF
2.5V
VDD
LTC2641-16 UNIPOLAR VOUT
0V TO 2.5V
4.7µF
0.1µF
REF
1
6
8
VOUT
GND 26412 F02
0.1µF
0.1µF
7
5
4
3
2CS
SCLK
DIN
CLR
LT®1019CS8-2.5
GND
OUT 5VIN
The external amplifier provides a unity-gain buffer. The
LTC2642 can also be used in unipolar configuration by
tying RFB and INV to REF . This provides power-up and
clear to midscale.
Table 1b. 14-Bit Unipolar Binary Code Table
(LTC2641-14)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(VOUT)
MSB LSB
1111 1111 1111 11xx VREF (16,383/16,384)
1000 0000 0000 00xx VREF (8,192/16,384) = VREF/2
0000 0000 0000 01xx VREF (1/16,384)
0000 0000 0000 00xx 0V
Figure 2. 16-Bit Unipolar Output (LTC2641-16) Unipolar VOUT = 0V to VREF
Table 1a. 16-Bit Unipolar Binary Code Table
(LTC2641-16)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(VOUT)
MSB LSB
1111 1111 1111 1111 VREF (65,535/65,536)
1000 0000 0000 0000 VREF (32,768/65,536) = VREF/2
0000 0000 0000 0001 VREF (1/65,536)
0000 0000 0000 0000 0V
Table 1c. 12-Bit Unipolar Binary Code Table
(LTC2641-12)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(VOUT)
MSB LSB
1111 1111 1111 xxxx VREF (4,095/4,096)
1000 0000 0000 xxxx VREF (2,048/4,096) = VREF/2
0000 0000 0001 xxxx VREF (1/4,096)
0000 0000 0000 xxxx 0V
LTC2641/LTC2642
14
26412fd
For more information www.linear.com/LTC2641
APPLICATIONS INFORMATION
Bipolar Configuration
Figure 3 shows a typical bipolar DAC application for the
LTC2642. The on-chip bipolar offset/gain resistors, RFB
and RINV
, are connected to an external amplifier to produce
a bipolar output swing from –VREF to VREF at the RFB pin.
The amplifier circuit provides a gain of +2 from the VOUT
pin, and gain of –1 from VREF
. Tables 2a, 2b and 2c show
the bipolar offset binary code tables for 16-bit, 14-bit and
12-bit operation.
–
+
16-BIT DAC
1/2 LT1678
5V
–5V
5V/3V
V
REF
2.5V
VDD
LTC2642-16
BIPOLAR VOUT
–2.5V TO 2.5V
4.7µF
C1
10pF
0.1µF
0.1µF
REF
1
6
10
VOUT
7
INV
8
RFB
GND 26412 F02
0.1µF
0.1µF
9
5
4
3
2CS
SCLK
DIN
CLR
LT1019CS8-2.5
GND
OUT 5VIN
Table 2b. 14-Bit Bipolar Offset Binary
Code Table (LTC2642-14)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(VOUT)
MSB LSB
1111 1111 1111 11xx VREF (8,191/8,192)
1000 0000 0000 01xx VREF (1/8,192)
1000 0000 0000 00xx 0V
0111 1111 1111 11xx –VREF (1/8,192)
0000 0000 0000 00xx –VREF
Figure 3. 16-Bit Bipolar Output (LTC2642-16) VOUT = –VREF to VREF
Table 2a. 16-Bit Bipolar Offset Binary
Code Table (LTC2642-16)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(VOUT)
MSB LSB
1111 1111 1111 1111 VREF (32,767/32,768)
1000 0000 0000 0001 VREF (1/32,768)
1000 0000 0000 0000 0V
0111 1111 1111 1111 –VREF (1/32,768)
0000 0000 0000 0000 –VREF
Table 2c. 12-Bit Bipolar Offset Binary
Code Table (LTC2642-12)
DIGITAL INPUT
BINARY NUMBER
IN DAC LATCH
ANALOG OUTPUT
(VOUT)
MSB LSB
1111 1111 1111 xxxx VREF (2,047/2,048)
1000 0000 0001 xxxx VREF (1/2,048)
1000 0000 0000 xxxx 0V
0111 1111 1111 xxxx –VREF (1/2048)
0000 0000 0000 xxxx –VREF
LTC2641/LTC2642
15
26412fd
For more information www.linear.com/LTC2641
APPLICATIONS INFORMATION
Unbuffered Operation and VOUT Loading
The DAC output is available directly at the VOUT pin, which
swings from GND to VREF
. Unbuffered operation provides
the lowest possible offset, full-scale and linearity errors,
the fastest settling time and minimum power consumption.
However, unbuffered operation requires that appropriate
loading be maintained on the VOUT pin. The LTC2641/
LTC2642 VOUT can be modeled as an ideal voltage source
in series with a source resistance of ROUT
, typically 6.2k
(Figure 4). The DAC’s linear output impedance allows it to
drive medium loads (RL > 60k) without degrading INL or
DNL; only the gain error is increased. The gain error (GE)
caused by a load resistance, RL, (relative to full scale) is:
GE =
–1
1+ROUT
RL
In 16-bit LSBs:
GE =
–65536
1+ROUT
RL
LSB
ROUT has a low tempco (typically < ±50ppm/°C), and is
independent of DAC code. The variation of ROUT, part-to-
part, is typically less than ±20%.
Note on LSB units:
For the following error descriptions, “LSB” means 16-bit
LSB and 65,536 is rounded to 66k.
To convert to 14-bit LSBs (LTC2641-14/LTC2642-14)
divide by 4.
To convert to 12-bit LSBs (LTC2641-12/LTC2642-12)
divide by 16.
A constant current, IL, loading VOUT will produce an offset of:
VOFFSET = –IL • ROUT
For VREF = 2.5V, a 16-bit LSB equals 2.5V/65,536, or
38µV. Since ROUT is 6.2k, an IL of 6nA produces an offset
of 1LSB. Therefore, to avoid degrading DAC performance,
it is critical to protect the VOUT pin from any sources of
leakage current.
Unbuffered VOUT Settling Time
The settling time at the VOUT pin can be closely approxi-
mated by a single-pole response where:
t = ROUT • (COUT + CL)
(Figure 4). Settling to 1/2LSB at 16-bits requires about
12 time constants (ln(2 • 65,536)). The typical settling
time of 1µs corresponds to a time constant of 83ns, and
a total (COUT + CL) of about 83ns/6.2k = 13pF . The internal
capacitance, COUT is typically 10pF, so an external CL of
3pF corresponds to 1µs settling to 1/2LSB.
IL
VOUT
0V TO VREF
ROUT VOUT
COUT
LTC2641
LTC2642
V
REF
REF
GND
CODE
2N
VREF
( )
CL
26412 F04
RL
+
–
Figure 4. VOUT Pin Equivalent Circuit
Op Amp Selection
The optimal choice for an external buffer op amp depends
on whether the DAC is used in the unipolar or bipolar
mode of operation, and also depends on the accuracy,
speed, power dissipation and board area requirements of
the application. The LTC2641/LTC2642’s combination of
tiny package size, rail-to-rail single supply operation, low
power dissipation, fast settling and nearly ideal accuracy
specifications makes it impractical for one op amp type
to fit every application.
In bipolar mode (LTC2642 only), the amplifier operates
with the internal resistors to provide bipolar offset and
scaling. In this case, a precision amplifier operating from
dual power supplies, such as the the LT1678 provides the
±VREF output range (Figure 3).
In unipolar mode, the output amplifier operates as a unity
gain voltage follower. For unipolar, single supply applica-
tions a precision, rail-to-rail input, single supply op amp
LTC2641/LTC2642
16
26412fd
For more information www.linear.com/LTC2641
APPLICATIONS INFORMATION
such as the LTC6078 is suitable, if the application does
not require linear operation very near to GND, or zero scale
(Figure 2). The LTC6078 typically swings to within 1mV of
GND if it is not required to sink any load current. For an
LSB size of 38µV, 1mV represents 26 missing codes near
zero scale. Linearity will be degraded over a somewhat
larger range of codes above GND. It is also unavoidable
that settling time and transient performance will degrade
whenever a single supply amplifier is operated very close
to GND, or to the positive supply rail.
The small LSB size of a 16-bit DAC, coupled with the tight
accuracy specifications on the LTC2641/LTC2642, means
that the accuracy and input specifications for the external
op amp are critical for overall DAC performance.
Op Amp Specifications and Unipolar DAC Accuracy
Most op amp accuracy specifications convert easily to
DAC accuracy.
Op amp input bias current on the noninverting (+) input is
equivalent to an IL loading the DAC VOUT pin and therefore
produces a DAC zero-scale error (ZSE) (see Unbuffered
Operation):
ZSE = –IB(IN+) • ROUT [Volts]
In 16-bit LSBs:
ZSE =–IBIN+
( )
• 6.2k • 66k
VREF
LSB
Op amp input impedance, RIN, is equivalent to an RL
loading the LTC2641/LTC2642 VOUT pin, and produces
a gain error of:
GE =
–66k
1+6.2k
RIN
LSB
Op amp offset voltage, VOS, corresponds directly to DAC
zero code offset error, ZSE:
ZSEV k
VLSB
OS REF
=
[]
•66
Temperature effects also must be considered. Over the
–40°C to 85°C industrial temperature range, an offset
voltage temperature coefficient (referenced to 25°C) of
0.6μV/°C will add 1LSB of zero-scale error. Also, IBIAS and
the VOFFSET error it causes, will typically show significant
relative variation over temperature.
Op amp open-loop gain, AVOL, contributes to DAC gain
error (GE):
GE k
ALSB
VOL
=
[]
66
Op amp input common mode rejection ratio (CMRR) is an
input-referred error that corresponds to a combination of
gain error (GE) and INL, depending on the op amp archi-
tecture and operating conditions. A conservative estimate
of total CMRR error is:
Error =10
CMRR
20
•VCMRR_RANGE
VREF
• 66k LSB
where VCMRR_RANGE is the voltage range that CMRR (in
dB) is specified over. Op amp Typical Performance Char-
acteristics graphs are useful to predict the impact of CMRR
errors on DAC performance. Typically, a precision op amp
will exhibit a fairly linear CMRR behavior (corresponding
to DAC gain error only) over most of the common mode
input range (CMR), and become nonlinear and produce
significant errors near the edge of the CMR.
Rail-to-rail input op amps are a special case, because they
have 2 distinct input stages, one with CMR to GND and
the other with CMR to V+. This results in a “crossover”
CM input region where operation switches between the
two input stages.
The LTC6078 rail-to-rail input op amp typically exhibits
remarkably low crossover linearity error, as shown in the
VOS vs VCM Typical Performance Characteristics graphs
(see the LTC6078 data sheet). Crossover occurs at CM
inputs about 1V below V+, and an LTC6078 operating as
a unipolar DAC buffer with VREF = 2.5V and V+ = 5V will
typically add only about 1LSB of GE and almost no INL
error due to CMRR. Even in a full rail-to-rail application,
with VREF = V+ = 5V, a typical LTC6078 will add only about
1LSB of INL at 16-bits.
LTC2641/LTC2642
17
26412fd
For more information www.linear.com/LTC2641
Op Amp Specifications and Bipolar DAC Accuracy
The op amp contributions to unipolar DAC error discussed
above apply equally to bipolar operation. The bipolar ap-
plication circuit gains up the DAC span, and all errors, by
a factor of 2. Since the LSB size also doubles, the errors
in LSBs are identical in unipolar and bipolar modes.
One added error in bipolar mode comes from IB (IN–),
which flows through RFB to generate an offset. The full
bias current offset error becomes:
VOFFSET = (IB (IN–) • RFB – IB (IN+) • ROUT • 2) [Volts]
So:
VIIN kIIN kk
V
OFFSET BB REF
=
()
+
()•–()•. •
–28 12 4 33
[]
LSB
Settling Time with Op Amp Buffer
When using an external op amp, the output settling time
will still include the single pole settling on the LTC2641/
LTC2642 VOUT node, with time constant ROUT • (COUT +
CL) (see Unbuffered VOUT Settling Time). CL will include
the buffer input capacitance and PC board interconnect
capacitance.
The external buffer amplifier adds another pole to the output
response, with a time constant equal to (fbandwidth/2π).
For example, assume that CL is maintained at the same
value as above, so that the VOUT node time constant is
83ns = 1μs/12. The output amplifier pole will also have a
time constant of 83ns if the closed-loop bandwidth equals
(1/2π • 83ns) = 1.9MHz. The effective time constant of
two cascaded single-pole sections is approximately the
root square sum of the individual time constants, or √2
• 83ns = 117ns, and 1/2 LSB settling time will be ~12 •
117ns = 1.4μs. This represents an ideal case, with no slew
limiting and ideal op amp phase margin. In practice, it
will take a considerably faster amplifier, as well as careful
attention to maintaining good phase margin, to approach
the unbuffered settling time of 1μs.
The output settling time for bipolar applications (Fig-
ure 3) will be somewhat increased due to the feedback
resistor network RFB and RINV (each 28k nominal). The
parasitic capacitance, CP, on the op amp (–) input node
will introduce a feedback loop pole with a time constant
of (CP • 28k/2). A small feedback capacitor, C1, should be
included, to introduce a zero that will partially cancel this
pole. C1 should nominally be <CP
, typically in the range
of 5pF to 10pF . This will restore the phase margin and
improve coarse settling time, but a pole-zero doublet will
unavoidably leave a slower settling tail, with a time con-
stant of roughly (CP + C1) • 28k/2, which will limit 16-bit
settling time to be greater than 2µs.
Reference and GND Input
The LTC2641/LTC2642 operates with external voltage refer-
ences from 2V to VDD, and linearity, offset and gain errors
are virtually unchanged vs VREF
. Full 16-bit performance
can be maintained if appropriate guidelines are followed
when selecting and applying the reference. The LTC2641/
LTC2642’s very low gain error tempco of 0.1ppm/°C, typ-
ical, corresponds to less than 0.5LSB variation over the
–40°C to 85°C temperature range. In practice, this means
that the overall gain error tempco will be determined almost
entirely by the external reference tempco.
The DAC voltage-switching mode “inverted” resistor lad-
der architecture used in the LTC2641/LTC2642 exhibits a
reference input resistance (RREF) that is code dependent
(see the Typical Performance curves IREF vs Input Code).
In unipolar mode, the minimum RREF is 14.8k (at code
871Chex, 34,588 decimal) and the the maximum RREF is
300k at code 0000hex (zero scale). The maximum change
in IREF for a 2.5V reference is 160µA. Since the maximum
occurs near midscale, the INL error is about one half of the
change on VREF
, so maintaining an INL error of <0.1LSB
requires a reference load regulation of (1.53ppm • 2/160µA)
= 19 [ppm/mA]. This implies a reference output impedance
of 48mΩ, including series wiring resistance.
To prevent output glitches from occurring when resistor
ladder branches switch from GND to VREF
, the reference
input must maintain low impedance at higher frequencies.
A 0.1μF ceramic capacitor with short leads between REF
and GND provides high frequency bypassing. A surface
mount ceramic chip capacitor is preferred because it has
the lowest inductance. An additional 1μF between REF
and GND provides low frequency bypassing. The circuit
APPLICATIONS INFORMATION
LTC2641/LTC2642
18
26412fd
For more information www.linear.com/LTC2641
will benefit from even higher bypass capacitance, as long
as the external reference remains stable with the added
capacitive loading.
Digital Inputs and Interface Logic
All of the digital inputs include Schmitt-trigger buffers to
accept slow transition interfaces. This means that opto-
cuplers can interface directly to the LTC2641/LTC2642
without additional external logic. Digital input hysteresis
is typically 150mV.
The digital inputs are compatible with TTL/CMOS-logic
levels. However, rail-to-rail (CMOS) logic swings are
preferred, because operating the logic inputs away from
the supply rails generates additional IDD and GND current,
(see Typical Performance Characteristic graph Supply
Current vs Logic Input Voltage).
Digital feedthrough is only 0.2nV•s typical, but it is always
preferred to keep all logic inputs static except when loading
a new code into the DAC.
Board Layout for Precision
Even a small amount of board leakage can degrade
accuracy. The 6nA leakage current into VOUT needed to
generate 1LSB offset error corresponds to 833MΩ leakage
resistance from a 5V supply.
The VOUT node is relatively sensitive to capacitive noise
coupling, so minimum trace length, appropriate shielding
and clean board layout are imperative here.
Temperature differences at the DAC, op amp or reference
pins can easily generate tens of microvolts of thermocou-
ple voltages. Analog signal traces should be short, close
together and away from heat dissipating components. Air
currents across the board can also generate thermocouples.
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane.
A “star ground” area should be established by attaching
the LTC2641/LTC2642 GND pin, VREF GND and the DAC
VOUT GND reference terminal to the same area on the
GND plane. Care should be taken to ensure that no large
GND return current paths flow through the “star GND”
area. In particular, the resistance from the LTC2641 GND
pin to the point where the VREF input source connects to
the ground plane should be as low as possible. Excessive
resistance here will be multiplied by the code dependent
IREF current to produce an INL error similar to the error
produced by VREF source resistance. For the LTC2641 in
the S8 package both GND pins, Pin 2 and Pin 7 should
be tied to the same GND plane.
Sources of ground return current in the analog area include
op amp power supply bypass capacitors and the GND
connection for single supply amps. A useful technique
for minimizing errors is to use a separate board layer for
power ground return connections, and reserve one ground
plane layer for low current “signal” GND connections.
The “signal”, or “star” GND plane must connected to the
“power” GND plane at a single point, which should be
located near the LTC2641/LTC2642 GND pin.
If separate analog and digital ground areas exist it is neces-
sary to connect them at a single location, which should be
fairly close to the DAC for digital signal integrity. In some
systems, large GND return currents can flow between the
digital and analog GNDs, especially if different PC boards
are involved. In such cases the digital and analog ground
connection point should not be made right at the “star”
GND area, so the highly sensitive analog signals are not
corrupted. If forced to choose, always place analog ground
quality ahead of digital signal ground. (A few mV of noise
APPLICATIONS INFORMATION
LTC2641/LTC2642
19
26412fd
For more information www.linear.com/LTC2641
APPLICATIONS INFORMATION
on the digital inputs is imperceptible, thanks to the digital
input hysteresis)
Just by maintaining separate areas on the GND plane
where analog and digital return currents naturally flow,
good results are generally achieved. Only after this has
been done, it is sometimes useful to interrupt the ground
plane with strategically placed “slots”, to prevent the digital
ground currents from fringing into the analog portion of
the plane. When doing this, the gap in the plane should
be only as long as it needs to be to serve its purpose.
Caution: if a GND plane gap is improperly placed, so that
it interrupts a significant GND return path, or if a signal
traces crosses over the gap, then adding the gap may
greatly degrade performance! In this case, the GND and
signal return currents are forced to flow the long way
around the gap, and then are typically channeled directly
into the most sensitive area of the analog GND plane.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ±0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
(2 SIDES)2.10 ±0.05
0.50
BSC
0.70 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
LTC2641/LTC2642
20
26412fd
For more information www.linear.com/LTC2641
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC2641/LTC2642
21
26412fd
For more information www.linear.com/LTC2641
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
OBSOLETE PACKAGE
LTC2641/LTC2642
22
26412fd
For more information www.linear.com/LTC2641
PACKAGE DESCRIPTION
MSOP (MS8) 0213 REV G
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev G)
MSOP (MS) 0213 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ±0.152
(.193 ±.006)
0.497 ±0.076
(.0196 ±.003)
REF
8910 76
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC 0.1016 ±0.0508
(.004 ±.002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev F)
LTC2641/LTC2642
23
26412fd
For more information www.linear.com/LTC2641
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
C 12/13 Marked S8 package as Obsolete 2, 3, 9, 10, 18, 21
D 10/14 Added output voltage noise density specifications
Updated text under Clearing the DAC section
4
12
(Revision history begins at Rev C)
LTC2641/LTC2642
24
26412fd
For more information www.linear.com/LTC2641
LINEAR TECHNOLOGY CORPORATION 2007
LT 1014 REV D • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2641
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LTC1592
12-/14-/16-Bit SoftSpan
TM
Current Output DACs Software Programmable Output Ranges up to ±10V
LTC1595/LTC1596 Serial 16-Bit Current Output DACs Low Glitch, ±1LSB Maximum INL, DNL
LTC1591/LTC1597 Parallel 14-/16-Bit Current Output DACs ±1LSB Max INL, DNL, ±10V Output
LTC1599 16-Bit Current Output DAC ±1LSB Max INL, DNL, ±10V Output
LTC1650 16-Bit Voltage Output DAC 2nV•s Glitch Impulse, 30nV/√Hz Noise
LTC2621/LTC2611
LTC2601
12-/14-/16-Bit Serial Voltage Output DACs Single DACs, Single Supply, 0V to 5V Outputs in DFN10
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LTC2704-14
LTC2704-16
12-/14-/16-Bit Quad Voltage Output DACs Software Programmable Output Ranges up to ±10V, Serial I/O
Op Amps
LT
®
1678 Dual Low Noise Rail-to-Rail Precision Op Amp 3.9nV/√Hz at 1MHz
LTC2054 Micropower Zero Drift Op Amp 3µV Maximum Offset
LT6010 150µA 8nV/√Hz Rail-to-Rail Output Precision Op Amp Micropower
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References
LT1019 Precision Bandgap Reference 0.005% Max, 5ppm/°C Max
Wide Range Current Load Sinks 0A to 2.5A
–
+
16-BIT DAC
LTC2054HV
10V
V
REF 2.5V
1k
ISINK
0A TO 2.5A
5V
VDD
LTC2641-16
4.7µF
0.1µF
0.033µF
1Ω
10W
IRLZ44
REF
1
6
8
VOUT
GND
26412 TA02
0.1µF
0.1µF
7
5
4
3
2CS
SCLK
DIN
CLR
LT1019CS8-2.5
GND
OUT 5VIN
10k
