ANALOG DEVICES AN-387 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700 AD1847 Serial-Port Codec Interface Example for a Parallel Bus INTRODUCTION This document describes in detail an example of how the AD1847 Codec can be interfaced to a parallel! data bus utilizing interrupt driven data transfers. While simple, this design can serve as a starting point for more sophisticated bus interfaces. OVERALL DESCRIPTION OF THE SYSTEM The goal of the system described below is as follows: 1. The AD1847 is to be interfaced to a 16-bit parallel bus. 2. The AD1847 should operate in a 2-wire mode, with 16 slots per frame. 3. The bus interface logic will issue a bus interrupt when data and control information can be read/written. 4. Control data needs only be sent to the interface logic (by the CPU) when new AD1847 controls are to be implemented. Even though the system presented in this document de- scribes an ISA bus interface, most of the design is not bus specific and is therefore applicable to other paralle! busses. HARDWARE DESCRIPTION Figure 1 shows a block diagram of the system whereas Figures 2-9 show the individual blocks. As one might ex- pect from reading the specs on the AD1847 interface, the bulk of the system is composed of six 16-bit shift regis- ters. Three of these are dedicated to sending data to the AD1847 (PISO, Parallel-In-Seriai-Out registers) and the other three to receiving data from the AD1847 (SIPO, RORCAD trimux NOT GLOBAL INPUTC ENA RIGHT CHAD DATA "RDLCAD | oN ENABLE IN ; sipo16 Roa. ENB tri16 INPUT w ENABLE ISA soo L>"*- Jon AC (0.18) ENC SuTPUTO FENABLE_OUT ENABLE B(0..15)] ISA (0.15) SIDIR rsa (0.15) CLK D (0.15) Lc (0..15) DA (0..15) DOUT (0.15) O (0..15} - CLR = OB (0.15) RC (15) DC (0..15) NOTE THAT BITCNTR HAS A SYNCHRONOUS CLEAR INPUT shftentr LEFT CH A/D DATA CNTEN ENABLE clkekt sipol6 P iectn ontrexp SEXP CEXP CNTEN LCNTEN__ DIN SCLK ee CLK SdFs__f SDFS CLKINREG |_CLKINREG cLK =: {0...15) (RESET S/LOUTREG J ESET S/LOUTREG Fp pete SOK cou ipasniry | DASHIET LC (15) CONTROUSTATUS decoding sipot6 sors [> INPUT__SOFS_[[ars vdread [RDRCAD Veo RIGHT CH D/A DATA INPUT __RESET RDLCAD CLKINREG DIN (0.15 PISO16 RESET reset sdicad [7 _rnpew cLK (0-15) L Sw (1..0) [> INPUT gw (1.0) tdew |_ RESET LR DIN INPUT ICLKRCDA 0 (0.15) fOR INPUT fer etkreda | /CLKLCDA SHLD DOUT now uv fiow felkieds ICLKCW AEN INPUT aen iclkew -- CLR INPUT ALDCWBF ELKADCAT A x /SBHE pu Isbhe Adewbt -K-SEEES SA (11.0) [> INPUT ada (11..0) freset -RESET_OUTPUT >, meset S(LOUTREG | aig ito OUTPUT Ra LEFT CH D/A DATA LDASHIFT __J igashitt fiocs16 -/-CUTPUT > nocs16 PISO16 DIN ISA (0..15) D (0.15) SH/LO = DOUT ICLR ICLKLCDA] A CONTROL 168REG PISO1s 0 (0.15 DIN RESET _| rele 0 (0..15) CO (0.18) 0 (0..15) #LDCWBF . ek SHAD OUT | OUTPUT > spt recxew | oR _ CLK Figure 1. System Block DiagramSerial-In-Parallel-Out registers). An additional 16-bit reg- ister contains outgoing control information (to be sent to the AD1847). It is assumed that the bus can always re- spond to data requests (interrupts) well within 1/Fs, (where Fs is the sample rate). This eliminates the need for data buffers (FIFOs). To be more precise, the system has about 1/F, - 3 x 16/Fsc.x seconds to respond to an interrupt, where Fsctx is the frequency of the AD1847 se- rial clock (either 12.288 MHz or 16.9344 MHz depending on the sample rate selected). The AD1847 serial clock (SCLK) is used to clock data in and out of the shift registers. Note that the AD1847 input/output data is valid on the falling edge of SCLK and therefore an inverted version of SCLK (/SCLK) is used to clock the SIPOs. As the AD1847 data sheet explains, the SDFS output indicates the start of a new frame. Since the AD1847 will be configured for a two-wire, 16-frames-per-slot mode in this design, the shift registers only need to receive (SIPOs) or transmit (PISOs) the first three 16-bit words of a frame. The first word contains control information, the second left channel data, and the third the right channel data. This applies to both AD1847 data input (SDI) and output (SDO). Both the PISO and the SIPO registers are connected in series so that after 3 x 16 clocks all the bits are in proper positions. At that time the shift register clocks are dis- abled and an interrupt is generated as explained later. Shift Register Clock Control The SDFS signal indicates the beginning of a new frame and can therefore be used to synchronize a state machine or activate signals that control the AD1847 data stream. As Figure 8 shows, a flip-flop (CNTEN) is set when SDFS goes high, which in turn enables a 6-bit counter. This counter keeps track of how many data bits have: been shifted in/out of the AD1847. CNTEN also controls the clear function of the counter. Whenever CNTEN is low, counting is disabled and the counter is cleared upon receiving a clock signal. When CNTEN is set high the counter starts counting. Upon a count of 3 x 16, when all input bits have been shifted into their correct positions, a counter expiration signal (CEXP) is generated that results in CNTEN being brought low. Half a SCLK period later both the PISO and SIPO clocks are disabled. The cycle repeats when SDFS goes high again. Figures 8 and 9 show how the clocks for the shift regis- ters, PISOs and SIPOs are generated. These clocks are gated versions of SCLK and /SCLK. Also shown is a sig- nal called $/LOUTREG which controls whether the PISO registers perform shift or parallel load operations upon receiving a clock. Figure 10 shows one cycle of the SDFS, CNTEN, inter- rupt, PISO/SIPO clocks and other signals. 74166 INPUT pIN INPUT Do SER D(0..15) > oT A DD B c D3 D D4 D5 E F QH D6 G D7 H STLD O] CLAN GND CLKIH 5 cn CLK e SHIFT REG 74166 SER D8 A D9 B D10 c p11 D pi2_ |, OUTPUT DiS |e au}/L_> bout p14 G DI5 INPUT 4 SH/LO C>eur STLD clr LD O} CLAN GND 5 CLKIH CLK e INPUT cik L > [i SHIFT REG Figure 2. PISO16 74164 oa} Vcc D1 OB | p2 A oc INPUT D3 pn (_ > 8 oD of LO D5 oF - -O CLKIN, OG F_ CLK OH e OUTPUT INPUT cu L > SHIFT REG _1 0 00..15) 74164 OA ps Veo op 9 TI A oc Le? B oD on 012 OE D13 INPUT OF p14 icin ("> Q) CLKIN OG DIS CLK OH e SHIFT REG 4 Figure 3. SIPO16 Interrupts The interrupt generation is handled by a flip-flop called interrupt. The falling edge of S/LOUTREG is used to set the flip-flop. The output of the interrupt flip-flop can be connected directly to the bus interrupt line since the SIPO data is valid when the interrupt signal is generated and the PISO registers are ready to accept data. The bushas until half a SCLK period after the next SDPS signal, or about (I/Fs - 3 x 16/Fscix) seconds, to respond to the interrupt, i.e., read the SIPO registers and write to the PISO registers. The SDFS signal, RESET, or a bus access to any of the six registers clears the interrupt. Register Addressing The mapping: of the data registers to the bus 1/O memory space is obviously design specific. The system described in this document uses a couple of jumpers to determine the addresses of the PISO and SIPO registers. Depending on the state of these jumpers a base address of 200H, 220H or 240H is selected. The control registers (SIPO and PISO) sit at the base address. The state of the bus read (IORD) and write (IOW) signais determine whether the PISO or SIPO registers are selected. The PISO registers are write only registers, where as the SIPO registers are read only. The left channel data is mapped into base address +2, and the right channel data into base address +4. Note that in addition to a clock signal, the PISO registers need a signal, shift load contro! (SH/LD), indicating whether the register should be loaded from the bus or its contents shifted upon re- ceiving a clock signal. The SH/LD is generated by the clkckt module (S/LOUTREG) as shown in Figure 8. The signal ensures that the PISO data will get shifted prop- erly during an AD1847 frame. Subsequent clock signals (generated by a decoded IOW signal) will clock data on the bus into the PISO register being addressed. The PISO clocks are therefore a combination of a gated SCLK and a decoded IOW signal as shown in the text design file in Figure 9. 74273 INPUT Do Qo OUTPUT D(0..15) > or oS {> 0 (0.15) D2 o2 D2 a2 03 03 D3 a3 D4 04 D4 a4 Ds Ds 05 05 D 06 D6 as D7 D7 07 07 INPUT D8 08 cur [ > INPUT } CLRN c.k > CLK e OCTAL D-FF 74273 3 D1 o1 oe 010 be 02 a10 o11 p3 03 Qit p12 ba 04 Qi2 D13 pS 08 Q13 p14 Ds 06 a4 D15 o7 9 Qis 08 08 LO} CLAN CLK e OCTAL D-FF Figure 4. 16BREG Control Word Buffer Slot one of the AD1847 interface always contains control information to be received by the AD1847. These bits can therefore not be set arbitrarily. To relieve the bus from having to update the control PISO for every sample when they are not changing, a separate 16-bit buffer contains the most recent control word written by the bus master. The falling edge of SDFS loads this buffer into the control PISO. This ensures that the AD1847 always receives valid control data. Right Channel D/A SIPO Input As explained later, the AD1847 initialization procedure calls for shifting a one into the right channel D/A PISO. Its input is therefore tied to Vec. During digital loopback, the AD1847 A/D data is mixed with the D/A data sent from the CPU to form the final data sent to the D/A con- verters. If one only wants to loop data from the A/D to the D/A, shifting a logic one into the right channel D/A PISO does not cause a problem because the external D/A data input can be disabled while the internal loopback is still enabled. Consult the AD1847 data sheet for details. Configuring the AD1847 for Two Wire, 16 Slots per Frame Upon reset, the AD1847 is by default configured in a single line mode with 32 slots per frame. The first task the system software needs to do is to change the AD1847 from the default mode to the two-wire, 16-slots-per-frame mode by writing a hexadecimal word of 4CCOH to the Control Word Input Register (MCE=FRS=TSSEL=1). This will instruct the AD1847 to change to 2-wire, 16-slot-per-frame mode upon the gen- eration of next frame sync signal (SDFS). This will be the Voc 74163 LON A B OA r c OB [ D oc INPUT ENT =D y ENABLE [__>- ENP Ac -) CLRN CLK e COUNTER Vec 74163 LON A 4 OUTPUT 6 oa CNTREXP c 08 D ocf- ENT opt ENP Reg [- INPUT icctR D> NEUT | CLAN cikK > CLK e COUNTER Figure 5 SHFT CNTRINPUT _DA (0..15) DA (0..15) INPUT DB (0..15) DB (0.15) INPUT DC (0.15 DC (0..1) INPUT ENA eA OR ouTPUT ENB INPUT ENB ENABLE : uT ENC EN INP SOFT D(0..15) OUTPUT DOUT (0..15) 3TO 1 MUX 3TO 1 MUX ENA Ty ENA, DA (0) ~ DA (8) a ena {0-4 ena (0-4 EN_B D (0) EN_B pour | 2) eo TT Oo ENC | ne ENC lene DC (0) ~ DC (8) ~ Dc pec 3TO 1 MUX ENA EWA DA (1) + ENB DA D(1) D(a) DBD ene pout |?) Pee ENC | vec pc (1 - be) Ine 3TO 1 MUX ENA ena DA (2) 7 ena |O ENB pour | 02 D (10) DB?) toe ENC EN c be L (2) oe 310 1MUX ENA DA(it) |_ ena |O- pci pa (it) |oN- pour pee) Enc |0-8 De qty [EN D.c ENA 3101 MUX pA (12) ONS one 40.8 ENB pour |__Dw12) cafe pe (12) JON (12) pec 370 1 MUX ENA DA (13) ve ENB 4 ENB pia DB (13) a pour | 2.19) ENC ewe oc (13) | ~~ be 3101 MUX 370 1 MUX ENA og ENA Daw |, DA (14) on ENB ENB + 0) D (14) DB) rue pout L}*? pe (ia) |EN-8 pout (14) ENC | nc enc (0-8 pee | oN De gay [ENS oc pbc 3TO 1 MUX 3TO 1 MUX ENA ENA DAT) ~ pais) |EN-A ena {OA ens _|0-A EN.8 pour 2) EN.B pour |_("5) mB) |g 0B (15) | ~*~ - ENC nec ENC enc pc ~ Oc (15 - M toe Mtoe Figure 6. TRIMUX first 16-bit word shifted out to the AD1847 after the fall- ing edge of SDFS and the only control word sent to the AD1847 during this frame. Note, however, that since the AD1847 is configured for default mode it is expecting another contro! word (slot number 16). Since the PISO clocks are disabled after 3 x 16 clocks, all the bits of the remainder of the frame, including the contro! word in slot 16, will get the value shifted into the right channel D/A PISO (see Figure 1) at the first rising SCLK after SDFS. If this bit is 0, all the bits of the second control word, including MCE, will be 0. Bringing MCE low will place the part in autocalibration which is not desirable at this point. It is therefore important that the MCE bit of the second control word of this frame be 1. Since writ- ing all ones to the second control register will not have any effect at this point, it is acceptable to permanently tie the input to the right channel D/A PISO high. At the next frame sync (SDFS) the AD1847 serial interface is temporarily disabled. The INIT bit will be set to 1 to indicate this fact. The software should wait for the INIT bit to be set to 1 followed by 0 (an interrupt indi- cates the presence of new control information}. This in- dicates that the serial interface is alive again. At this point the interface will be configured properly. The soft- ware would typically proceed to configure the AD1847 controls to their desired value with the MCE bit still high to hold off autocalibration and only when fully config- ured (except for output muting) the MCE bit would be brought low. At that point the AD1847 will enter autocalibration mode. The AC! bit of the status register should be polled and the software should wait for ACI to be set to 1 and then to 0. When ACI is 0, autocalibration is finished and after muting the D/A outputs the part is ready for normal operations. APPENDIX Hardware Summary The design described above was implemented on an EPM7160LC84 using MaxPlus2 software. The Figures 1-9 show the modules that make up the design. The following summarizes the functions of the main modules.\ Decoding \ This text design file contains the description of the inter- rupt flipflop, along with decoding logic for the interface registers. The following lists the regctrl input and output signals: Name Origin sdfs AD1847 frame sync reset ISA bus sw 1-2 External jumpers that determine register base address /iord ISA bus /iowr ISA bus aen ISA bus /sbhe ISA bus addr0-11 ISA bus s/loutreg clkckt module /dashift clkckt module Output Destination and Purpose rdrcad trimux. Rdrcad controls the three-state buffer at the output of right channel A/D SIPO. The buffer is enabled when the bus reads the right channel A/D data. rdicad trimux. Same signal as rdrcad except for left channel. rdcw trimux. Same signal as rdrcad except for control data. /clkreda Right Channel! D/A Data PISO. This clock signal causes the PISO data to be shifted or data to be loaded from the bus into the PISO, depending on the status of the PISO SH/LD input. /cikicda Left Channel D/A Data PISO. Similar function as /clkrcda. clkcw Control PISO. Similar function as cikrcda except data is loaded from the control buffer (16BREG). /tdewbf 16BREG. This signal loads the bus contents into the control buffer. /reset Resets the AD1847. Inverted version of the ISA reset. irq ISA bus interrupt. /iocs16 ISA bus. /clkckt This module generates contro! and clock signals for the PISO and SIPO registers along with a shftcntr control signal. Output Destination and Purpose cnten shftentr. Controls when the shift counter is enabled, disabled and when it is cleared. clkinreg SIPO clock input. Enabled only when AD1847 data is being received. s/loutreg PISOs. This signal determines whether the PISO input clocks will result in shifting or loading. /dashift decoding. Used by the decoding module to generate the clock signals for the PISOs. shftcntr This synchronous counter (synchronous clear) keeps track of the number of bits being received or sent to the AD1847. Upon a count of 3 x 16 a counter expiration signal (cexp) is generated. trimux and trit6 These blocks implement three-statable buffers at the output of the SIPO registers. Whenever the bus reads one of the SIPO registers the proper buffer is enabled. SIPO Serial-In-Parallel-Out registers. These registers shift data in (control, left and right channels) from the AD1847. This data is then read by the bus. PISO Parallel-In-Serial-Out registers. These registers, after being loaded from the bus, shift data (control, left and right channels) to the AD1847. 16BREG This buffer is loaded by the bus with control information for the AD1847. The SDFS signal loads this information into the PISO control shift register.INPUT ENABLE oe CNTEN OUTPUT _ _TC CNTEN TRI > AND2 D(0..15) [> INPUT Da BO ours B (0..15) NOT OUTPUT Th , " CLKINREG D1 i B1 OFF, o2 Tl+ 32 | oD OUTPUT : - b> S/LOUTREG os NC Tos SDFS CLAN] | [CLAN CLAN L co Neur tT I T D4 mC Y B4 IRESET NOT uo TAI NOT or2 DS {> B5 weuT Ppt /DASHIFT TRI > Cc> pve 86 SCLK o REF 87 Mu be rps Figure 8. CLK CKT D9 7! B9 TRI p10 B10 uw TRI > q D111 B11 D12 TL Y B12 TRI > 4013 B13 p14 TA Pot nu D15 TAC B15 w Figure 7. TRI16 SUBDESIGN Decoding ( sdfs, reset, swi1. .0], /ior, /iow INPUT; aen /sbhe,addr[11. .0],sh/Id,/dashift :INPUT; rdrcead,rdicad,rdew,/clkrcda,/clkicda,/clkcew :OUTPUT; /Idewbf, /reset,irq,/iocs16 :OUTPUT; } VARIABLE adv, /cw, /Icd, /rcd :LCELL; interrupt :DFF; BEGIN %The following case statement decodes the bus address lines.% %The valid addresses depend on the status of two external %signals (juMpers)% Figure 9. (Continued on next page)CASE (SWI1. .0}) IS WHEN B00 => adv =(((addr[]==H 200) # (addr{]==H" 202) # (addr[]==H" 204")) & !aen & !/sbhe); /cw =!(addr[]J==H 200) # aen # /sbhe; /ied =!(addr[]==H 202) # aen # /sbhe; Ired . = \(addr[}==H"204") # aen # /sbhe; WHEN B01 => adv =(((addr[]J==H220") # (addr[]==H222") # (addr[J==H"224")) & !aen & !/sbhe); /cw =!(addr[]==H" 220) # aen # /sbhe; /icd =!(addr(]J==H222") # aen # /sbhe; /red =!(addr[]==H 224") # aen # /sbhe; WHEN B10 => adv =(((addr[]==H"240") # (addr{J==H"242") # (addr[]==H" 244")) & !aen & !/sbhe); iow =!(addr[]==H 240) # aen # /sbhe; /Icd =!(addr[]==H 242") # aen # /sbhe; /rcd =!(addr{J==H 244") # aen # /sbhe; END CASE; rdew = =!(/cw # /ior) ;%read (enable) signal for the control word three-state buffer% rdicad =!(/Icd # /ior) ;>%... left channel a/d... .% rdrcad_ =!(/rcd # /ior) ;%. .. right channel a/d . . .% Nidewbf =(/cw # /iow) ;%load signal for the control word buffer% %the following signals are the clock signals for the piso16 registers% %the clock signals are active during data being shifted to the AD1847% %and when the ISA bus Joads these registers% fclkcw = Isdfs & (/dashift) ; %control data piso clock% /clkicda =(/Icd # /iow) & (/dashift); %left ch d/a piso clock% /clkrcda =(/rcd # /iow) & (/dashift) ; Y%right ch d/a piso clock% %The following defines an interrupt flip flop that is set when% %three 16 bit words have been received/sent from/to the AD1847.% %The interrupt is cleared by accessing any register on the chip.% %by the sdfs signals or reset% interrupt.cirn = !(reset # sdfs # adv); interrupt.clk = !sh/ld; irq = interrupt.q; interrupt.d = VCC; /reset = (reset); /iocs16 = TRI (GND,adv) ;%indicates to ISA bus that data transfers are 16 bit% END; Figure 9. ADPLIR ATION AIATOO aL AQRESET SCLK SOFS S/LOUTREG CLKINREG /CLKRCDA {DASHIFT CNTEN CEXP | decoding:60 | interrupt. iCLKCW sol CO [15.0 /LDCWBF AOR AOW AOCSI6 /SBHE AEN swi swo SA [11.0] 220 000 ISA[15..0) 1538 XY 0000 X 19ca X 000 Figure 10.comments as a general good-practice guide for mixed signal designs. 1. a [ CODEC PCB & CIRCUIT APPLICATION GUIDELINES Extending the comments in the data sheets (e.g., AD1848) regarding grounding (and bypassing), include the following brief notes and The power supply decoupling and bypassing shown in the attached drawing (ref AD1848K) is okay. It needs to be emphasized that low ESL 10 nF to 100 nF surface mount ceramic capacitors must be mounted right at the leads of the chip (or at least within a couple of mm). Remember the rules-of-thumb for trace lengthL =~ 1nH/mm, R = 2mQ/mm (for common 250m wide traces, 38 um thick (1 02) foil). Avoid switch mode power supplies near ADCs, DACs and analog circuits. Sometimes it is easier to use a separate 5 V three terminal regulator (e.g., TO-39 metal can), at the chip, for the analog supply. A 10 uF Tantalum or aluminum ca- pacitor at the board edge helps to reduce power supply noise and the ESR damps ringing from decoupling chokes. ADI recommends extending the ground plane philoso- phy to include separate digital and analog power planes directly over their respective ground planesno overlap- ping of planes. The two plane pairs should be separated by a 2mm-3 mm gap. This means using a three or four layer board with the ground and power planes forming a high capacitive sandwich. This gives an extremely effective, low ESR, low ESL bypass capacitor consisting of the separate ground and power planes themselves, with an effective ca- pacitance of ~5 pF/cm?. The IC leads will have vias that go directly to the appropriate plane for power and ground. All digital components are mounted over the digital power/ ground plane sandwich and all analog components over the analog power/ground sandwich. This doesnt minimize the need for additional ceramic bypass capacitors at the pins as mentioned above. The importance and effective- ness of ground planes cannot be overemphasized. A single link between the two planes should be estab- lished, preferably close to the chip itself. This is necessary to prevent any potential difference due to ESD or fault cur- rents that could otherwise flow through the chip substrate with damaging affect. It may be useful to provide for re- movable links in several PCB locations, to permit debugging and testing for ground isolation. All digital signals and components should be located away from analog circuitry (and, naturally, vice versa). All high- speed traces should take the most direct route over the correct ground or power plane. \f this is not possible, a ground trace should be routed under the high speed trace wherever possible, to minimize self-inductance. Avoid the use of sockets. Don't overlook adjacent PLDs and VLSI logic chips on the same PC board. These chips frequently include lots of syn- chronous logic and generate large switching currents that can infiltrate the rest of the board. Make sure they are well bypassedat the chip pins! This wil! not only ensure their reliable operation but minimize impact on the supply lines. Be aware of problems that might occur due to multiple crystal oscillators, e.g., beats between harmonics that can enter the CODEC through either the analog or digital sup- plies or signal/reference pins. If possible, only enable a single oscillator on a PC board at a time or derive all the required frequencies from a single oscillator. 10. 11. 12. 13. 14. 15. Watch out for the traditional design problems. Ground loop area (inductive coupling}, minimize. Common im- pedance (current) coupling, minimize or use star points. Capacitive (voltage) coupling, separate, shield or lower cir- cuit impedance. Surface and/or bulk leakageseparate, guard, conformal coat. Parallel trace coupling (combina- tions of above)separate, terminate in characteristic im- pedance, use ground plane and/or intermediate grounded traces. Watch out for capacitive coupling from the body of large components. Use the outside foil ring, marked on capaci- tors, to identify which end to ground. Watch out for the external magnetic field of inductors and transformers. Use electrostatic and magnetically shielded components if necessary. RF decoupling chokes can be mounted at right angles to minimize mutual inductance. Power transformers should be mounted off the board and oriented, with the most intense area of their external field away from critical analog circuits. Use of toroidal power transformers will minimize external fields. Minimize capacitive loading on output pins. For digital sig- nals, driving long traces, it may be necessary to terminate the trace in its characteristic impedance, ~100 Q for most applications. Ensure that offset biased, analog CODEC/ADC input sig- nals, canNOT go above Vcc or below ground even momen- tarily. Use clamps or five-volt single rail op amps buffers to limit signal excursions. Consider EMI/RFI requirements for analog input and output lines. Input lines can radiate (and receive) RF and the CODEC line output contains many harmonic products of the sampling process. Finallyremember when debugging, that every assump- tion is suspect!! REFERENCES Additional, general high-speed and mixed signal design, infor- mation is available in our seminar handbooks and application manuals as noted below. They are recommended as a source of good techniques and inspiration. 1. Mixed Signal Processing Design Seminar, Devices, Inc., 1991, ISBN-0-916550-08-7. Analog High Speed Design Seminar, Analog Devices, Inc., 1990, ISBN 0-916550-07-9. Applications Reference Manual, Analog Devices, Inc., 1993. Especially refer to collected Application NotesSection 24, AN-214, AN-280, AN-282, AN-345, AN-346, AN-347, AN- 353, AN-362. Noise Reduction Techniques in Electronic Systems, 2nd Ed, Henry W. Ott, Wiley Interscience, 1988. Interfacing Techniques in Digital Design With Emphasis on Microprocessors, Ronald L. Krutz, John Wiley, 1938. Audio/Video Reference Manual, Analog Devices, !nc., 1992. Systems Application Guide, Analog Devices, Inc., 1993, ISBN 0-916550- 13-3.TO LINEAR REGULATOR 5Vde, 15% Vopp DIGITAL POWER PLANE v Voo pr c10 v Voo ci cg 100nF / DGNO 100nF / DGND 100nF /DGND Lt a _ = FERRITEOR py 1pH CHOKE 4po Vpp DIGITAL POWER PLANE Vop e e LION AN e . > c2 L C12 L c13_L. Vop Yoo Vop Voo L <n | 100nF 10pF 10pF ct ce c7 cs < GND | <> $ = mone Py pene mone {oan mon DGND mon Pawo c DGND LINK L2 FERRITE OR po 1pH CHOKE ipo DGND DIGITAL GROUND PLANE Voc ANALOG POWER PLANE tyr 100nF 10pF Veo Veo vu AGND ca c3 ANALOG GROUND PLANE 100nF | / AGND 100nF | , Figure 11. AGND