100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined by the DIR input. A LOW on the output enable input (OE) holds the ECL outputs in a cut-off state and the TTL outputs at a high impedance level. A HIGH on the latch enable input (LE) latches the data at both inputs even though only one output is enabled at the time. A LOW on LE makes the 100328 transparent. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is b2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100328 is designed with FASTE TTL output buffers, featuring optimal DC drive and capable of quickly charging and discharging highly capacitive loads. All inputs have 50 kX pull-down resistors. Features Y Y Y Y Y Y Y Y Y Identical performance to the 100128 at 50% of the supply current Bi-directional translation 2000V ESD protection Latched outputs FASTE TTL outputs TRI-STATEE outputs Voltage compensated operating range e b 4.2V to b 5.7V Available to industrial grade temperature range Available to MIL-STD-883 Logic Symbol Pin Names E0 -E7 T0 -T7 OE LE DIR TL/F/10219 - 1 Description ECL Data I/O TTL Data I/O Output Enable Input Latch Enable Input Direction Control Input All pins function at 100K ECL levels except for T0 -T7. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PCC 24-Pin Quad Cerpak TL/F/10219 - 4 TL/F/10219 - 3 TL/F/10219-2 FASTE and TRI-STATEE are registered trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/10219 RRD-B30M105/Printed in U. S. A. 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch July 1992 Functional Diagram Detail TL/F/10219 - 6 Truth Table TL/F/10219-5 Note: LE, DIR, and OE use ECL logic levels OE DIR LE ECL Port TTL Port L X L LOW (Cut-Off) Z L L H Input Z 1, 3 LOW (Cut-Off) Input 2, 3 L H H H L L L L 1, 4 H L L H H 1, 4 H L H X Latched 1, 3 H H L L L 2, 4 H H L H H 2, 4 H H H Latched X 2, 3 H e HIGH Voltage Level L e LOW Voltage Level X e Don't Care Z e High Impedance Note 1: ECL input to TTL output mode. Note 2: TTL input to ECL output mode. Note 3: Retains data present before LE set HIGH. Note 4: Latch is transparent. 2 Notes Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage Applied to Output in HIGH State TRI-STATE Output Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Current Applied to TTL Output in LOW State (Max) VEE Pin Potential to Ground Pin b 65 C to a 150 C a 175 C a 150 C ECL Input Voltage (DC) ECL Output Current (DC Output HIGH) TTL Input Voltage (Note 3) TTL Input Current (Note 3) Twice the Rated IOL (mA) ESD (Note 2) t 2000V Recommended Operating Conditions b 7.0V to a 0.5V VTTL Pin Potential to Ground Pin b 0.5V to a 5.5V Case Temperature (TC) Commercial Industrial Military b 0.5V to a 6.0V VEE to a 0.5V b 50 mA 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C ECL Supply Voltage (VEE) TTL Supply Voltage (VTTL) b 0.5V to a 6.0V b 30 mA to a 5.0 mA b 5.7V to b 4.2V a 4.5V to a 5.5V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Commercial Version TTL-to-ECL DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C, VTTL e a 4.5V to a 5.5V (Note 4) Parameter Min Typ Max Units Conditions VOH Symbol Output HIGH Voltage b 1025 b 955 b 870 mV VOL Output LOW Voltage b 1830 b 1705 b 1620 mV VIN e VIH(Max) or VIL(Min) Loading with 50X to b 2V b 2000 b 1950 mV Cutoff Voltage VOHC Output HIGH Voltage Corner Point High VOLC Output LOW Voltage Corner Point Low VIH Input HIGH Voltage VIL Input LOW Voltage IIH b 1035 mV OE or DIR Low, VIN e VIH(Max) or VIL(Min), Loading with 50X to b2V VIN e VIH(Min) or VIL(Max) Loading with 50X to b2V b 1610 mV 2.0 5.0 V 0 0.8 V Input HIGH Current 70 mA VIN e a 2.7V Breakdown Test 1.0 mA VIN e a 5.5V IIL Input LOW Current VFCD Input Clamp Diode Voltage IEE VEE Supply Current b 700 b 1.2 b 159 b 169 b 75 b 75 Over VTTL, VEE, TC Range Over VTTL, VEE, TC Range mA VIN e a 0.5V V IIN e b18 mA mA LE Low, OE and DIR High Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V Note 4: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 3 Commercial Version (Continued) ECL-to-TTL DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C, CL e 50 pF, VTTL e a 4.5V to a 5.5V (Note) Parameter Min Typ VOH Symbol Output HIGH Voltage 2.7 2.4 3.1 2.9 Max Units Conditions VOL Output LOW Voltage 0.5 V VIH Input HIGH Voltage b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs IIH Input HIGH Current 350 mA VIN e VIH (Max) IIL Input LOW Current mA VIN e VIL (Min) IOZHT TRI-STATE Current Output High mA VOUT e a 2.7V IOZLT TRI-STATE Current Output Low b 700 mA VOUT e a 0.5V IOS Output Short-Circuit Current b 150 b 60 mA VOUT e 0.0V, VTTL e a 5.5V ITTL VTTL Supply Current 74 49 67 mA mA mA TTL Outputs LOW TTL Outputs HIGH TTL Outputs in TRI-STATE V V 0.3 0.50 70 IOH e b3 mA, VTTL e 4.75V IOH e b3 mA, VTTL e 4.50V IOL e 24 mA, VTTL e 4.50V DIP TTL-to-ECL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V, VCC e VCCA e GND (Note) Symbol Parameter TC e 0 C TC e 25 C TC e 85 C Units Conditions 3.8 ns ns Figures 1 & 2 1.9 3.9 ns ns Figures 1 & 2 Min Max Min Max Min Max 1.1 3.5 1.1 3.6 1.1 1.7 3.6 1.7 3.7 tPLH tPHL TN to En (Transparent) tPLH tPHL LE to En tPZH OE to En (Cutoff to High) 1.3 4.2 1.5 4.4 1.7 4.8 ns Figures 1 & 2 tPHZ OE to En (High to Cutoff) 1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1 & 2 tPHZ DIR to En (High to Cutoff) 1.6 4.3 1.6 4.3 1.7 4.5 ns Figures 1 & 2 tset Tn to LE 1.1 1.1 1.1 ns Figures 1 & 2 thold Tn to LE 1.1 1.1 1.1 ns Figures 1 & 2 tpw(H) Pulse Width LE 2.1 2.1 2.1 ns Figures 1 & 2 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.6 ns Figures 1 & 2 1.6 0.6 1.6 0.6 1.6 Note: The specified limits represent the ``worst'' case value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 4 Commercial Version (Continued) DIP ECL-to-TTL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V, VCC e VCCA e GND, CL e 50 pF Symbol Parameter TC e 0 C TC e 25 C TC e 85 C Units Conditions 5.9 ns Figures 3 & 4 Min Max Min Max Min Max 2.3 5.6 2.4 5.6 2.6 tPLH tPHL En to Tn (Transparent) tPLH tPHL LE to Tn 3.1 7.2 3.1 7.2 3.3 7.7 ns Figures 3 & 4 tPZH tPZL OE to Tn (Enable Time) 3.4 3.8 8.45 9.2 3.7 4.0 8.95 9.2 4.0 4.3 9.7 9.95 ns Figures 3 & 5 tPHZ tPLZ OE to Tn (Disable Time) 3.2 3.0 8.95 7.7 3.3 3.4 8.95 8.7 3.5 4.1 9.2 9.95 ns Figures 3 & 5 tPHZ tPLZ DIR to Tn (Disable Time) 2.7 2.8 8.2 7.45 2.8 3.1 8.7 7.95 3.1 4.0 8.95 9.2 ns Figures 3 & 6 tset En to LE 1.1 1.1 1.1 ns Figures 3 & 4 thold En to LE 2.1 2.1 2.6 ns Figures 3 & 4 tpw(H) Pulse Width LE 4.1 4.1 4.1 ns Figures 3 & 4 5 SOIC, PCC and Cerpak TTL-to-ECL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V Symbol Parameter TC e 0 C TC e 25 C TC e 85 C Units Conditions 3.6 ns ns Figures 1 & 2 1.9 3.7 ns ns Figures 1 & 2 Min Max Min Max Min Max 1.1 3.3 1.1 3.4 1.1 1.7 3.4 1.7 3.5 tPLH tPHL Tn to En (Transparent) tPLH tPHL LE to En tPZH OE to En (Cutoff to High) 1.3 4.0 1.5 4.2 1.7 4.6 ns Figures 1 & 2 tPHZ OE to En (High to Cutoff) 1.5 4.3 1.6 4.3 1.6 4.4 ns Figures 1 & 2 tPHZ DIR to En (High to Cutoff) 1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1 & 2 tset Tn to LE 1.0 1.0 1.0 ns Figures 1 & 2 thold Tn to LE 1.0 1.0 1.0 ns Figures 1 & 2 tpw(H) Pulse Width LE 2.0 2.0 2.0 ns Figures 1 & 2 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.6 1.6 ns Figures 1 & 2 tOSHL Maximum Skew Common Edge Output-to-Output Variation Data to Output Path 200 200 200 ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation Data to Output Path 200 200 200 ps PCC Only (Note 1) Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path 650 650 650 ps PCC Only (Note 1) Maximum Skew Pin (Signal) Transition Variation Data to Output Path 650 650 650 ps PCC Only (Note 1) tOSLH tOST tps 1.6 0.6 1.6 0.6 Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design. 6 Commercial Version (Continued) SOIC, PCC and Cerpak ECL-to-TTL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V, CL e 50 pF Symbol Parameter TC e 0 C TC e 25 C TC e 85 C Units Conditions 5.7 ns Figures 3 & 4 Min Max Min Max Min Max 2.3 5.4 2.4 5.4 2.6 tPLH tPHL En to Tn (Transparent) tPLH tPHL LE to Tn 3.1 7.0 3.1 7.0 3.3 7.5 ns Figures 3 & 4 tPZH tPZL OE to Tn (Enable Time) 3.4 3.8 8.25 9.0 3.7 4.0 8.75 9.0 4.0 4.3 9.5 9.75 ns Figures 3 & 5 tPHZ tPLZ OE to Tn (Disable Time) 3.2 3.0 8.75 7.5 3.3 3.4 8.75 8.5 3.5 4.1 9.0 9.75 ns Figures 3 & 5 tPHZ tPLZ DIR to Tn (Disable Time) 2.7 2.8 8.0 7.25 2.8 3.1 8.5 7.75 3.1 4.0 8.75 9.0 ns Figures 3 & 6 tset En to LE 1.0 1.0 1.0 ns Figures 3 & 4 thold En to LE 2.0 2.0 2.5 ns Figures 3 & 4 tpw(H) Pulse Width LE 4.0 4.0 4.0 ns Figures 3 & 4 tOSHL Maximum Skew Common Edge Output-to-Output Variation Data to Output Path 600 600 600 ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation Data to Output Path 850 850 850 ps PCC Only (Note 1) Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path 1350 1350 1350 ps PCC Only (Note 1) Maximum Skew Pin (Signal) Transition Variation Data to Output Path 950 950 950 ps PCC Only (Note 1) tOSLH tOST tps Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design. 7 Industrial Version PCC TTL-to-ECL DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40 C to a 85 C, VTTL e a 4.5V to a 5.5V (Note) Symbol TC e b40 C Parameter TC e 0 C to a 85 C Min Max Min Max Units Conditions VIN e VIH(Max) or VIL(Min) Loading with 50X to b2V VOH Output HIGH Voltage b 1085 b 870 b 1025 b 870 mV VOL Output LOW Voltage b 1830 b 1575 b 1830 b 1620 mV b 1950 mV Cutoff Voltage b 1900 VOHC Output HIGH Voltage Corner Point High VOLC Output LOW Voltage Corner Point Low VIH Input HIGH Voltage 2.0 5.0 VIL Input LOW Voltage 0 0.8 IIH Input HIGH Current 70 Breakdown Test 1.0 IIL b 1095 mV b 1035 b 1565 OE or DIR Low, VIN e VIH(Max) or VIL(Min), Loading with 50X to b2V VIN e VIH(Min) or VIL(Max) Loading with 50X to b2V b 1610 mV 2.0 5.0 V Over VTTL, VEE, TC Range 0 0.8 V Over VTTL, VEE, TC Range 70 mA VIN e a 2.7V 1.0 mA VIN e a 5.5V Input LOW Current b 700 b 700 mA VIN e a 0.5V VFCD Input Clamp Diode Voltage b 1.2 b 1.2 V IIN e b18 mA IEE VEE Supply Current b 159 b 169 b 70 b 70 b 159 b 169 b 75 b 75 mA LE Low, OE and DIR High Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V PCC ECL-to-TTL DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40 C to a 85 C, CL e 50 pF, VTTL e a 4.5V to a 5.5V (Note) Symbol Parameter TC e b40 C Min VOH Output HIGH Voltage VOL Output LOW Voltage Max 2.7 2.4 TC e 0 C to a 85 C Min 2.7 2.4 0.5 VIH Input HIGH Voltage b 1170 VIL Input LOW Voltage b 1830 IIH Input HIGH Current IIH Input LOW Current IOZHT TRI-STATE Current Output High IOZLT TRI-STATE Current Output Low b 700 IOS Output Short-Circuit Current b 150 ITTL VTTL Supply Current Units Conditions Max 0.5 V V IOH e b3 mA, VTTL e 4.75V IOH e b3 mA, VTTL e 4.50V V IOL e 24 mA, VTTL e 4.50V b 870 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1480 b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs 350 mA VIN e VIH (Max) mA VIN e VIH (Min) mA VOUT e a 2.7V mA VOUT e a 0.5V b 60 mA VOUT e 0.0V, VTTL e a 5.5V 74 49 67 mA mA mA TTL Outputs LOW TTL Outputs HIGH TTL Outputs in TRI-STATE 425 0.50 0.50 70 70 b 700 b 60 b 150 74 49 67 Note: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 8 Industrial Version (Continued) PCC TTL-to-ECL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V Symbol TC e b40 C Parameter TC e 25 C TC e 85 C Units Conditions 3.6 ns ns Figures 1 & 2 1.9 3.7 ns ns Figures 1 & 2 Min Max Min Max Min Max 1.0 3.3 1.1 3.4 1.1 1.7 3.4 1.7 3.5 tPLH tPHL Tn to En (Transparent) tPLH tPHL LE to En tPZH OE to En (Cutoff to High) 1.2 4.0 1.5 4.2 1.7 4.6 ns Figures 1 & 2 tPHZ OE to En (High to Cutoff) 1.5 4.5 1.6 4.3 1.6 4.4 ns Figures 1 & 2 tPHZ DIR to En (High to Cutoff) 1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1 & 2 tset Tn to LE 2.5 1.0 1.0 ns Figures 1 & 2 thold Tn to LE 1.0 1.0 1.0 ns Figures 1 & 2 tpw(H) Pulse Width LE 2.5 2.0 2.0 ns Figures 1 & 2 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.4 ns Figures 1 & 2 2.3 0.6 1.6 0.6 1.6 PCC ECL-to-TTL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V, CL e 50 pF Symbol Parameter TC e 0 C TC e 25 C TC e 85 C Units Conditions 5.7 ns Figures 3 & 4 Min Max Min Max Min Max 2.3 5.4 2.4 5.4 2.6 tPLH tPHL En to Tn (Transparent) tPLH tPHL LE to Tn 3.1 7.4 3.1 7.0 3.3 7.5 ns Figures 3 & 4 tPZH tPZL OE to Tn (Enable Time) 3.4 3.7 8.3 9.0 3.7 4.0 8.75 9.0 4.0 4.3 9.5 9.75 ns Figures 3 & 5 tPHZ tPLZ OE to Tn (Disable Time) 3.2 3.0 9.0 7.5 3.3 3.4 8.75 8.5 3.5 4.1 9.0 9.75 ns Figures 3 & 5 tPHZ tPLZ DIR to Tn (Disable Time) 2.7 2.8 8.0 7.3 2.8 3.1 8.5 7.75 3.1 4.0 8.75 9.0 ns Figures 3 & 6 tset En to LE 2.5 1.0 1.0 ns Figures 3 & 4 thold En to LE 2.3 2.0 2.5 ns Figures 3 & 4 tpw(H) Pulse Width LE 4.0 4.0 4.0 ns Figures 3 & 4 9 Military Version TTL-to-ECL DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C, VTTL e a 4.5V to a 5.5V Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage Min Max Units b 1025 b 870 mV b 1085 b 870 mV b 1830 b 1620 mV b 1830 b 1555 mV b 1950 mV b 1850 mV Cutoff Voltage VOHC Output HIGH Voltage b 1035 VIL Input LOW Voltage IIH Input HIGH Current Input LOW Current VFCD Input Clamp Diode Voltage IEE VEE Supply Current b 55 C 0 C to VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V a 125 C 1, 2, 3 b 55 C 0 C to a 125 C OE or DIR Low b 55 C 0 C to a 125 C b 55 C 0 C to a 125 C mV b 55 C V b 55 C to a 125 C Over VTTL, VEE, TC Range 1, 2, 3, 4 0.8 V b 55 C to a 125 C Over VTTL, VEE, TC Range 1, 2, 3, 4 70 mA 1.0 mA b 55 C to a 125 C b 1.0 mA b 55 C to a 125 C VIN e a 0.5V 1, 2, 3 b 1.2 V b 55 C to a 125 C IIN e b18 mA 1, 2, 3 b 1610 2.0 Breakdown Test IIL 0 C to mV b 1555 Input HIGH Voltage Notes mV Output LOW Voltage VIH Conditions a 125 C mV b 1085 VOLC TC b 165 b 175 b 65 b 65 b 55 C to 125 C b 55 C to a 125 C mA 10 VIN e VIH (Min) or VIL (Max) Loading with 50X0 to b2.0V 1, 2, 3 VIN e a 2.7V 1, 2, 3 VIN e a 5.5V LE Low, OE and DIR High Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V 1, 2, 3 Military Version (Continued) ECL-to-TTL DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C, CL e 50 pF, VTTL e a 4.5V to a 5.5V Parameter Min VOH Symbol Output HIGH Voltage 2.5 2.4 VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current Max Units TC mV 0 C to a 125 C b 55 C 0.5 mV b 55 C a 125 C IOL e 24 mA, VTTL e 4.50V b 1165 b 870 mV b 55 C a 125 C Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4 b 1830 b 1475 mV b 55 C to a 125 C Guaranteed LOW Signal for All Inputs 1, 2, 3, 4 350 500 mA IIL Input LOW Current IOZHT TRI-STATE Current Output High IOZLT TRI-STATE Current Output Low b 1.0 IOS Output Short-Circuit CURRENT b 150 ITTL VTTL Supply Current Conditions 1, 2, 3 a 125 C VEE e b5.7V VIN e VIH (Max) 1, 2, 3 mA b 55 C to a 125 C VEE e b4.2V VIN e VIL (Min) 1, 2, 3 mA b 55 C to a 125 C VOUT e a 2.7V 1, 2, 3 mA b 55 C to a 125 C VOUT e a 0.5V 1, 2, 3 b 60 mA b 55 C to a 125 C VOUT e 0.0V, VTTL e a 5.5V 1, 2, 3 75 50 70 mA mA mA b 55 C to a 125 C TTL Outputs Low TTL Output High TTL Output in TRI-STATE 1, 2, 3 0.50 70 0 C to Notes IOH e b1 mA, VTTL e 4.50V IOH e b3 mA, VTTL e 4.50V Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at b 55 C, a 25 C, and a 125 C, Subgroups, 1, 2 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b 55 C, a 25 C, and a 125 C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input condition and testing VOH/VOL. TTL-to-ECL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V, VCC e VCCA e GND Symbol Parameter TC e b55 C TC e 25 C TC e a 125 C Units Conditions 3.7 ns ns Figures 1 & 2 1.1 3.8 ns ns Figures 1 & 2 Min Max Min Max Min Max 0.8 3.4 1.1 3.6 0.8 1.2 3.8 1.4 3.7 Notes tPLH tPHL TN to En (Transparent) tPLH tPHL LE to En tPZH OE to En (Cutoff to HIGH) 0.8 3.6 1.5 4.0 2.0 5.2 ns Figures 1 & 2 tPHZ OE to En (HIGH to Cutoff) 1.5 4.6 1.6 4.2 1.6 4.3 ns Figures 1 & 2 tPHZ DIR to En (HIGH to Cutoff) 1.6 4.7 1.6 4.3 1.7 4.3 ns Figures 1 & 2 tset Tn to LE 2.5 2.0 2.5 ns Figures 1 & 2 thold Tn to LE 2.5 2.0 2.5 ns Figures 1 & 2 tpw(H) Pulse Width LE 2.5 2.0 2.5 ns Figures 1 & 2 4 tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.4 ns Figures 1 & 2 4 2.3 0.5 11 2.1 0.4 2.4 1, 2, 3 1, 2, 3 4 Military Version (Continued) ECL-to-TTL AC Electrical Characteristics VEE e b4.2V to b5.7V, VTTL e a 4.5V to a 5.5V, VCC e VCCA e GND, CL e 50 pF Symbol Parameter TC e b55 C TC e 25 C TC e a 125 C Units Conditions 6.3 ns Figures 3 & 4 Min Max Min Max Min Max 2.1 6.0 2.0 5.6 2.2 tPLH tPHL En to Tn (Transparent) tPLH tPHL LE to Tn 3.1 7.0 3.1 6.5 3.3 7.5 ns Figures 3 & 4 tPZH tPZL OE to Tn (Enable Time) 3.2 3.6 8.0 8.0 3.7 4.0 8.0 8.5 4.0 4.3 9.2 9.6 ns Figures 3 & 5 tPHZ tPLZ OE to Tn (Disable Time) 3.2 3.0 8.5 8.0 3.3 3.4 8.0 7.5 3.5 4.1 8.4 10.0 ns Figures 3 & 5 tPHZ tPLZ DIR to Tn (Disable Time) 2.6 2.7 7.0 7.0 2.6 3.1 7.0 7.0 2.9 4.0 8.0 10.0 ns Figures 3 & 6 tset En to LE 2.5 2.0 2.5 ns Figures 3 & 4 thold En to LE 3.0 2.5 3.0 ns Figures 3 & 4 tpw(H) Pulse Width LE 2.5 2.0 5.0 ns Figures 3 & 4 Notes 1, 2, 3 1, 2, 3 4 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at a 25 C, temperature only, Subgroup A9. Note 3: Sample tested (Method 5005, Table I) on each mfg. lot at a 25 C, Subgroup A9, and at a 125 C and b 55 C temperatures, Subgroups A10 and A11. Note 4: Not tested at a 25 C, a 125 C and b 55 C temperature (design characterization data). 12 Test Circuitry (TTL-to-ECL) TL/F/10219 - 7 Note 1: Rt e 50X termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50X resistance. When an input or output is not being monitored, an external 50X resistance must be applied to serve as Rt. Note 2: TTL and ECL force signals are brought to the DUT via 50X coax lines. Note 3: VTTL is decoupled to ground with 0.1 mF to ground, VEE is decoupled to ground with 0.01 mF and VCC is connected to ground. Note 4: For ECL input pins, the equivelent force/sense circuitry is optional. FIGURE 1. TTL-to-ECL AC Test Circuit Switching Waveforms (TTL-to-ECL) TL/F/10219 - 9 FIGURE 2. TTL to ECL TransitionPropagation Delay and Transition Times 13 Test Circuitry (ECL-to-TTL) TL/F/10219 - 10 Note 1: Rt e 50X termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50X resistance. When an input or output is not being monitored, an external 50X resistance must be applied to serve as Rt. Note 2: The TTL Tri-State pull up switch is connected to a 7V only for ZL and LZ tests. Note 3: TTL and ECL force signals are brought to the DUT via 50X coax lines. Note 4: VTTL is decoupled to ground with 0.1 mF, VEE is decoupled to ground with 0.01 mF and VCC is connected to ground. FIGURE 3. ECL-to-TTL AC Test Circuit 14 Switching Waveforms (ECL-to-TTL) TL/F/10219 - 11 Note: DIR is LOW, and OE is HIGH FIGURE 4. ECL-to-TTL TransitionPropagation Delay and Transition Times Note: DIR is LOW, LE is HIGH TL/F/10219 - 14 FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times Note: OE is HIGH, LE is HIGH TL/F/10219 - 15 FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time 15 Applications TL/F/10219 - 12 FIGURE 7. Applications DiagramMOS/TTL SRAM Interface Using 100328 ECL - TTL Latched Translator Ordering Information The device number is used to form part of a simplified purchasing code where A package type and temperature range are defined as follows: 100328 D Device Type (Basic) C QB Special Variation QB e Military grade device with environmental and burn-in processing Package Code D e Ceramic DIP F e Quad Cerpak P e Plastic DIP Q e Plastic Leaded Chip Carrier (PCC) S e Small Outline (SOIC) Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC Only) M e Military (b55 C to a 125 C) 16 17 Physical Dimensions inches (millimeters) 24-Lead Ceramic Dual-In-Line Package (0.400x Wide) (D) NS Package Number J24E 24-Lead Molded Package (0.300x Wide) (S) NS Package Number M24B 18 Physical Dimensions inches (millimeters) (Continued) 24-Lead Plastic Dual-In-Line Packakge (P) NS Package Number N24E 28-Lead Plastic Chip Carrier (V) NS Package Number V28A 19 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch Physical Dimensions inches (millimeters) (Continued) 24-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.