100328PC - National Semiconductor

TL/F/10219

100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch

July 1992

100328

Low Power Octal ECL/TTL

Bi-Directional Translator with Latch

General Description

The 100328 is an octal latched bi-directional translator de-

signed to convert TTL logic levels to 100K ECL logic levels

and vice versa. The direction of this translation is deter-

mined by the DIR input. A LOW on the output enable input

(OE) holds the ECL outputs in a cut-off state and the TTL

outputs at a high impedance level. A HIGH on the latch

enable input (LE) latches the data at both inputs even

though only one output is enabled at the time. A LOW on LE

makes the 100328 transparent.

The cut-off state is designed to be more negative than a

normal ECL LOW level. This allows the output emitter-fol-

lowers to turn off when the termination supply is b2.0V,

presenting a high impedance to the data bus. This high im-

pedance reduces termination power and prevents loss of

low state noise margin when several loads share the bus.

The 100328 is designed with FASTÉTTL output buffers,

featuring optimal DC drive and capable of quickly charging

and discharging highly capacitive loads. All inputs have

50 kXpull-down resistors.

Features

YIdentical performance to the 100128 at 50% of the

supply current

YBi-directional translation

Y2000V ESD protection

YLatched outputs

YFASTÉTTL outputs

YTRI-STATEÉoutputs

YVoltage compensated operating range e

b4.2V to b5.7V

YAvailable to industrial grade temperature range

YAvailable to MIL-STD-883

Logic Symbol

TL/F/10219–1

Pin Names Description

E0–E7ECL Data I/O

T0–T7TTL Data I/O

OE Output Enable Input

LE Latch Enable Input

DIR Direction Control Input

All pins function at 100K ECL levels except for T0–T7.

Connection Diagrams

24-Pin DIP/SOIC

TL/F/10219–2

28-Pin PCC

TL/F/10219–3

24-Pin Quad Cerpak

TL/F/10219–4

FASTÉand TRI-STATEÉare registered trademarks of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Functional Diagram

TL/F/10219–5

Note: LE, DIR, and OE use ECL logic levels

Detail

TL/F/10219–6

Truth Table

OE DIR LE ECL TTL Notes

Port Port

LXL LOW Z

(Cut-Off)

L L H Input Z 1, 3

LHH LOW Input 2, 3

(Cut-Off)

HLL L L 1,4

HLL H H 1,4

H L H X Latched 1, 3

HHL L L 2,4

HHL H H 2,4

H H H Latched X 2, 3

HeHIGH Voltage Level

LeLOW Voltage Level

XeDon’t Care

ZeHigh Impedance

Note 1: ECL input to TTL output mode.

Note 2: TTL input to ECL output mode.

Note 3: Retains data present before LE set HIGH.

Note 4: Latch is transparent.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Storage Temperature (TSTG)b65§Ctoa

150§C

Maximum Junction Temperature (TJ)

Ceramic a175§C

Plastic a150§C

VEE Pin Potential to

Ground Pin b7.0V to a0.5V

VTTL Pin Potential to

Ground Pin b0.5V to a6.0V

ECL Input Voltage (DC) VEE to a0.5V

ECL Output Current

(DC Output HIGH) b50 mA

TTL Input Voltage (Note 3) b0.5V to a6.0V

TTL Input Current (Note 3) b30 mA to a5.0 mA

Note 1: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Note 3: Either voltage limit or current limit is sufficient to protect inputs.

Voltage Applied to Output

in HIGH State

TRI-STATE Output b0.5V to a5.5V

Current Applied to TTL

Output in LOW State (Max) Twice the Rated IOL (mA)

ESD (Note 2) t2000V

Recommended Operating

Conditions

Case Temperature (TC)

Commercial 0§Ctoa

85§C

Industrial b40§Ctoa

85§C

Military b55§Ctoa

125§C

ECL Supply Voltage (VEE)b5.7V to b4.2V

TTL Supply Voltage (VTTL)a4.5V to a5.5V

Commercial Version

TTL-to-ECL DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa

85§C, VTTL ea

4.5V to a5.5V (Note 4)

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage b1025 b955 b870 mV VIN eVIH(Max) or VIL(Min)

VOL Output LOW Voltage b1830 b1705 b1620 mV Loading with 50Xto b2V

Cutoff Voltage OE or DIR Low,

b2000 b1950 mV VIN eVIH(Max) or VIL(Min),

Loading with 50Xto b2V

VOHC Output HIGH Voltage b1035 mV VIN eVIH(Min) or VIL(Max)

Corner Point High Loading with 50Xto b2V

VOLC Output LOW Voltage b1610 mV

Corner Point Low

VIH Input HIGH Voltage 2.0 5.0 V Over VTTL,V

EE,T

CRange

VIL Input LOW Voltage 0 0.8 V Over VTTL,V

EE,T

CRange

IIH Input HIGH Current 70 mAV

IN ea

2.7V

Breakdown Test 1.0 mA VIN ea

5.5V

IIL Input LOW Current b700 mAV

IN ea

0.5V

VFCD Input Clamp b1.2 V IIN eb

18 mA

Diode Voltage

IEE VEE Supply Current LE Low, OE and DIR High

Inputs Open

b159 b75 mA VEE eb

4.2V to b4.8V

b169 b75 VEE eb

4.2V to b5.7V

Note 4: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

Commercial Version (Continued)

ECL-to-TTL DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa

85§C, CLe50 pF, VTTL ea

4.5V to a5.5V (Note)

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage 2.7 3.1 V IOH eb

3 mA, VTTL e4.75V

2.4 2.9 V IOH eb

3 mA, VTTL e4.50V

VOL Output LOW Voltage 0.3 0.5 V IOL e24 mA, VTTL e4.50V

VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal for All Inputs

IIH Input HIGH Current 350 mAV

IN eVIH (Max)

IIL Input LOW Current 0.50 mAV

IN eVIL (Min)

IOZHT TRI-STATE Current 70 mAV

OUT ea

2.7V

Output High

IOZLT TRI-STATE Current b700 mAV

OUT ea

0.5V

Output Low

IOS Output Short-Circuit b150 b60 mA VOUT e0.0V, VTTL ea

5.5V

Current

ITTL VTTL Supply Current 74 mA TTL Outputs LOW

49 mA TTL Outputs HIGH

67 mA TTL Outputs in TRI-STATE

DIP TTL-to-ECL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V, VCC eVCCA eGND (Note)

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH TNto En1.1 3.5 1.1 3.6 1.1 3.8 ns

Figures1&2

PHL (Transparent) ns

tPLH LE to En1.7 3.6 1.7 3.7 1.9 3.9 ns

Figures1&2

PHL ns

tPZH OE to En1.3 4.2 1.5 4.4 1.7 4.8 ns

Figures1&2

(Cutoff to High)

tPHZ OE to En1.5 4.5 1.6 4.5 1.6 4.6 ns

Figures1&2

(High to Cutoff)

tPHZ DIR to En1.6 4.3 1.6 4.3 1.7 4.5 ns

Figures1&2

(High to Cutoff)

tset Tnto LE 1.1 1.1 1.1 ns

Figures1&2

hold Tnto LE 1.1 1.1 1.1 ns

Figures1&2

pw(H) Pulse Width LE 2.1 2.1 2.1 ns

Figures1&2

TLH Transition Time 0.6 1.6 0.6 1.6 0.6 1.6 ns

Figures1&2

THL 20% to 80%, 80% to 20%

Note: The specified limits represent the ‘‘worst’’ case value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

Commercial Version (Continued)

DIP ECL-to-TTL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V, VCC eVCCA eGND, CLe50 pF

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Ento Tn2.3 5.6 2.4 5.6 2.6 5.9 ns

Figures3&4

PHL (Transparent)

tPLH LE to Tn3.1 7.2 3.1 7.2 3.3 7.7 ns

Figures3&4

PHL

tPZH OE to Tn3.4 8.45 3.7 8.95 4.0 9.7 ns

Figures3&5

PZL (Enable Time) 3.8 9.2 4.0 9.2 4.3 9.95

tPHZ OE to Tn3.2 8.95 3.3 8.95 3.5 9.2 ns

Figures3&5

PLZ (Disable Time) 3.0 7.7 3.4 8.7 4.1 9.95

tPHZ DIR to Tn2.7 8.2 2.8 8.7 3.1 8.95 ns

Figures3&6

PLZ (Disable Time) 2.8 7.45 3.1 7.95 4.0 9.2

tset Ento LE 1.1 1.1 1.1 ns

Figures3&4

hold Ento LE 2.1 2.1 2.6 ns

Figures3&4

pw(H) Pulse Width LE 4.1 4.1 4.1 ns

Figures3&4

SOIC, PCC and Cerpak TTL-to-ECL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Tnto En1.1 3.3 1.1 3.4 1.1 3.6 ns

Figures1&2

PHL (Transparent) ns

tPLH LE to En1.7 3.4 1.7 3.5 1.9 3.7 ns

Figures1&2

PHL ns

tPZH OE to En1.3 4.0 1.5 4.2 1.7 4.6 ns

Figures1&2

(Cutoff to High)

tPHZ OE to En1.5 4.3 1.6 4.3 1.6 4.4 ns

Figures1&2

(High to Cutoff)

tPHZ DIR to En1.6 4.1 1.6 4.1 1.7 4.3 ns

Figures1&2

(High to Cutoff)

tset Tnto LE 1.0 1.0 1.0 ns

Figures1&2

hold Tnto LE 1.0 1.0 1.0 ns

Figures1&2

pw(H) Pulse Width LE 2.0 2.0 2.0 ns

Figures1&2

TLH Transition Time 0.6 1.6 0.6 1.6 0.6 1.6 ns

Figures1&2

THL 20% to 80%, 80% to 20%

tOSHL Maximum Skew Common Edge PCC Only

Output-to-Output Variation 200 200 200 ps (Note 1)

Data to Output Path

tOSLH Maximum Skew Common Edge PCC Only

Output-to-Output Variation 200 200 200 ps (Note 1)

Data to Output Path

tOST Maximum Skew Opposite Edge PCC Only

Output-to-Output Variation 650 650 650 ps (Note 1)

Data to Output Path

tps Maximum Skew PCC Only

Pin (Signal) Transition Variation 650 650 650 ps (Note 1)

Data to Output Path

Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both

HL and LH (tOST). Parameters tOST and tps guaranteed by design.

Commercial Version (Continued)

SOIC, PCC and Cerpak ECL-to-TTL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V, CLe50 pF

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Ento Tn2.3 5.4 2.4 5.4 2.6 5.7 ns

Figures3&4

PHL (Transparent)

tPLH LE to Tn3.1 7.0 3.1 7.0 3.3 7.5 ns

Figures3&4

PHL

tPZH OE to Tn3.4 8.25 3.7 8.75 4.0 9.5 ns

Figures3&5

PZL (Enable Time) 3.8 9.0 4.0 9.0 4.3 9.75

tPHZ OE to Tn3.2 8.75 3.3 8.75 3.5 9.0 ns

Figures3&5

PLZ (Disable Time) 3.0 7.5 3.4 8.5 4.1 9.75

tPHZ DIR to Tn2.7 8.0 2.8 8.5 3.1 8.75 ns

Figures3&6

PLZ (Disable Time) 2.8 7.25 3.1 7.75 4.0 9.0

tset Ento LE 1.0 1.0 1.0 ns

Figures3&4

hold Ento LE 2.0 2.0 2.5 ns

Figures3&4

pw(H) Pulse Width LE 4.0 4.0 4.0 ns

Figures3&4

OSHL Maximum Skew Common Edge PCC Only

Output-to-Output Variation 600 600 600 ps (Note 1)

Data to Output Path

tOSLH Maximum Skew Common Edge PCC Only

Output-to-Output Variation 850 850 850 ps (Note 1)

Data to Output Path

tOST Maximum Skew Opposite Edge PCC Only

Output-to-Output Variation 1350 1350 1350 ps (Note 1)

Data to Output Path

tps Maximum Skew PCC Only

Pin (Signal) Transition Variation 950 950 950 ps (Note 1)

Data to Output Path

Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both

HL and LH (tOST). Parameters tOST and tps guaranteed by design.

Industrial Version

PCC TTL-to-ECL DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

40§Ctoa

85§C, VTTL ea

4.5V to a5.5V (Note)

Symbol Parameter TCeb

40§CT

Ctoa

85§CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage b1085 b870 b1025 b870 mV VIN eVIH(Max) or VIL(Min)

VOL Output LOW Voltage b1830 b1575 b1830 b1620 mV Loading with 50Xto b2V

Cutoff Voltage OE or DIR Low,

b1900 b1950 mV VINeVIH(Max) or VIL(Min),

Loading with 50Xto b2V

VOHC Output HIGH Voltage b1095 b1035 mV VIN eVIH(Min) or VIL(Max)

Corner Point High Loading with 50Xto b2V

VOLC Output LOW Voltage b1565 b1610 mV

Corner Point Low

VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 V Over VTTL,V

EE,T

CRange

VIL Input LOW Voltage 0 0.8 0 0.8 V Over VTTL,V

EE,T

CRange

IIH Input HIGH Current 70 70 mAV

IN ea

2.7V

Breakdown Test 1.0 1.0 mA VIN ea

5.5V

IIL Input LOW Current b700 b700 mAV

IN ea

0.5V

VFCD Input Clamp Diode Voltage b1.2 b1.2 V IIN eb

18 mA

IEE VEE Supply Current LE Low, OE and DIR High

Inputs Open

b159 b70 b159 b75 mA VEE eb

4.2V to b4.8V

b169 b70 b169 b75 VEE eb

4.2V to b5.7V

PCC ECL-to-TTL DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

40§Ctoa

85§C, CLe50 pF, VTTL ea

4.5V to a5.5V (Note)

Symbol Parameter TCeb

40§CT

Ctoa

85§CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage 2.7 2.7 V IOH eb

3 mA, VTTL e4.75V

2.4 2.4 V IOH eb

3 mA, VTTL e4.50V

VOL Output LOW Voltage 0.5 0.5 V IOL e24 mA, VTTL e4.50V

VIH Input HIGH Voltage b1170 b870 b1165 b870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW Voltage b1830 b1480 b1830 b1475 mV Guaranteed LOW Signal for All Inputs

IIH Input HIGH Current 425 350 mAV

IN eVIH (Max)

IIH Input LOW Current 0.50 0.50 mAV

IN eVIH (Min)

IOZHT TRI-STATE Current 70 70 mAV

OUT ea

2.7V

Output High

IOZLT TRI-STATE Current b700 b700 mAV

OUT ea

0.5V

Output Low

IOS Output Short-Circuit b150 b60 b150 b60 mA VOUT e0.0V, VTTL ea

5.5V

Current

ITTL VTTL Supply Current 74 74 mA TTL Outputs LOW

49 49 mA TTL Outputs HIGH

67 67 mA TTL Outputs in TRI-STATE

Note: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise

immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to

guarantee operation under ‘‘worst case’’ conditions.

Industrial Version (Continued)

PCC TTL-to-ECL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V

Symbol Parameter TCeb

40§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Tnto En1.0 3.3 1.1 3.4 1.1 3.6 ns

Figures1&2

PHL (Transparent) ns

tPLH LE to En1.7 3.4 1.7 3.5 1.9 3.7 ns

Figures1&2

PHL ns

tPZH OE to En1.2 4.0 1.5 4.2 1.7 4.6 ns

Figures1&2

(Cutoff to High)

tPHZ OE to En1.5 4.5 1.6 4.3 1.6 4.4 ns

Figures1&2

(High to Cutoff)

tPHZ DIR to En1.6 4.1 1.6 4.1 1.7 4.3 ns

Figures1&2

(High to Cutoff)

tset Tnto LE 2.5 1.0 1.0 ns

Figures1&2

hold Tnto LE 1.0 1.0 1.0 ns

Figures1&2

pw(H) Pulse Width LE 2.5 2.0 2.0 ns

Figures1&2

TLH Transition Time 0.4 2.3 0.6 1.6 0.6 1.6 ns

Figures1&2

THL 20% to 80%, 80% to 20%

PCC ECL-to-TTL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V, CLe50 pF

Symbol Parameter TCe0§CT

25§CT

85§CUnits Conditions

Min Max Min Max Min Max

tPLH Ento Tn2.3 5.4 2.4 5.4 2.6 5.7 ns

Figures3&4

PHL (Transparent)

tPLH LE to Tn3.1 7.4 3.1 7.0 3.3 7.5 ns

Figures3&4

PHL

tPZH OE to Tn3.4 8.3 3.7 8.75 4.0 9.5 ns

Figures3&5

PZL (Enable Time) 3.7 9.0 4.0 9.0 4.3 9.75

tPHZ OE to Tn3.2 9.0 3.3 8.75 3.5 9.0 ns

Figures3&5

PLZ (Disable Time) 3.0 7.5 3.4 8.5 4.1 9.75

tPHZ DIR to Tn2.7 8.0 2.8 8.5 3.1 8.75 ns

Figures3&6

PLZ (Disable Time) 2.8 7.3 3.1 7.75 4.0 9.0

tset Ento LE 2.5 1.0 1.0 ns

Figures3&4

hold Ento LE 2.3 2.0 2.5 ns

Figures3&4

pw(H) Pulse Width LE 4.0 4.0 4.0 ns

Figures3&4

Military Version

TTL-to-ECL DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

55§Ctoa

125§C, VTTL ea

4.5V to a5.5V

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage b1025 b870 mV 0§Cto

125§C

b1085 b870 mV b55§CV

IN eVIH (Max)

VOL Output LOW Voltage b1830 b1620 mV 0§Cto or VIL (Min)

Loading with

a125§C50Xto b2.0V 1, 2, 3

b1830 b1555 mV b55§C

Cutoff Voltage b1950 mV 0§Cto

125§C OE or DIR Low

b1850 mV b55§C

VOHC Output HIGH Voltage b1035 mV 0§Cto

125§C

b1085 mV b55§CV

IN eVIH (Min) Loading with 1, 2, 3

VOLC Output LOW Voltage b1610 mV 0§Cto or VIL (Max) 50X0tob

2.0V

a125§C

b1555 mV b55§C

VIH Input HIGH Voltage 2.0 V b55§C to Over VTTL,V

EE,T

CRange 1, 2, 3, 4

a125§C

VIL Input LOW Voltage 0.8 V b55§C to Over VTTL,V

EE,T

CRange 1, 2, 3, 4

a125§C

IIH Input HIGH Current 70 mAb55§Cto V

IN ea

2.7V

125§C1, 2, 3

Breakdown Test 1.0 mA b55§Cto V

IN ea

5.5V

a125§C

IIL Input LOW Current b1.0 mA b55§Cto V

IN ea

0.5V 1, 2, 3

a125§C

VFCD Input Clamp b1.2 V b55§Cto I

IN eb

18 mA 1, 2, 3

Diode Voltage a125§C

IEE VEE Supply Current LE Low, OE and DIR High

b55§C to Inputs Open 1, 2, 3

b165 b65 mA a125§CV

EE eb

4.2V to b4.8V

b175 b65 VEE eb

4.2V to b5.7V

Military Version (Continued)

ECL-to-TTL DC Electrical Characteristics

VEE eb

4.2V to b5.7V, VCC eVCCA eGND, TCeb

55§Ctoa

125§C, CLe50 pF, VTTL ea

4.5V to a5.5V

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage 2.5 mV 0§Ctoa

125§CI

OH eb

1 mA, VTTL e4.50V

2.4 b55§CI

OH eb

3 mA, VTTL e4.50V 1, 2, 3

VOL Output LOW Voltage 0.5 mV b55§CIOL e24 mA, VTTL e4.50V

a125§C

VIH Input HIGH Voltage b1165 b870 mV b55§C Guaranteed HIGH Signal 1, 2, 3, 4

a125§C for All Inputs

VIL Input LOW Voltage b1830 b1475 mV b55§C to Guaranteed LOW Signal 1, 2, 3, 4

a125§C for All Inputs

IIH Input HIGH Current 350 mA0§Cto V

EE eb

5.7V 1, 2, 3

500 a125§CV

IN eVIH (Max)

IIL Input LOW Current 0.50 mAb55§Cto V

EE eb

4.2V 1, 2, 3

a125§CV

IN eVIL (Min)

IOZHT TRI-STATE Current 70 mAb55§Cto V

OUT ea

2.7V 1, 2, 3

Output High a125§C

IOZLT TRI-STATE Current b1.0 mA b55§Cto V

OUT ea

0.5V 1, 2, 3

Output Low a125§C

IOS Output Short-Circuit b150 b60 mA b55§Cto V

OUT e0.0V, VTTL ea

5.5V 1, 2, 3

CURRENT a125§C

ITTL VTTL Supply Current 75 mA b55§Cto TTL Outputs Low

50 mA a125§CTTL Output High 1, 2, 3

70 mA TTL Output in TRI-STATE

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be

considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups, 1, 2 3, 7, and 8.

Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, and a125§C, Subgroups A1, 2, 3, 7, and 8.

Note 4: Guaranteed by applying specified input condition and testing VOH/VOL.

TTL-to-ECL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V, VCC eVCCA eGND

Symbol Parameter TCeb

55§CT

25§CT

125§CUnits Conditions Notes

Min Max Min Max Min Max

tPLH TNto En0.8 3.4 1.1 3.6 0.8 3.7 ns

Figures1&2

PHL (Transparent) ns 1, 2, 3

tPLH LE to En1.2 3.8 1.4 3.7 1.1 3.8 ns

Figures1&2

PHL ns

tPZH OE to En0.8 3.6 1.5 4.0 2.0 5.2 ns

Figures1&2

(Cutoff to HIGH)

tPHZ OE to En1.5 4.6 1.6 4.2 1.6 4.3 ns

Figures1&2

(HIGH to Cutoff)

tPHZ DIR to En1.6 4.7 1.6 4.3 1.7 4.3 ns

Figures1&2

1, 2, 3

(HIGH to Cutoff)

tset Tnto LE 2.5 2.0 2.5 ns

Figures1&2

hold Tnto LE 2.5 2.0 2.5 ns

Figures1&2

pw(H) Pulse Width LE 2.5 2.0 2.5 ns

Figures1&2

TLH Transition Time 0.4 2.3 0.5 2.1 0.4 2.4 ns

Figures1&2

THL 20% to 80%, 80% to 20%

Military Version (Continued)

ECL-to-TTL AC Electrical Characteristics

VEE eb

4.2V to b5.7V, VTTL ea

4.5V to a5.5V, VCC eVCCA eGND, CLe50 pF

Symbol Parameter TCeb

55§CT

25§CT

125§CUnits Conditions Notes

Min Max Min Max Min Max

tPLH Ento Tn2.1 6.0 2.0 5.6 2.2 6.3 ns

Figures3&4

PHL (Transparent) 1, 2, 3

tPLH LE to Tn3.1 7.0 3.1 6.5 3.3 7.5 ns

Figures3&4

PHL

tPZH OE to Tn3.2 8.0 3.7 8.0 4.0 9.2 ns

Figures3&5

PZL (Enable Time) 3.6 8.0 4.0 8.5 4.3 9.6

tPHZ OE to Tn3.2 8.5 3.3 8.0 3.5 8.4 ns

Figures3&5

1, 2, 3

tPLZ (Disable Time) 3.0 8.0 3.4 7.5 4.1 10.0

tPHZ DIR to Tn2.6 7.0 2.6 7.0 2.9 8.0 ns

Figures3&6

PLZ (Disable Time) 2.7 7.0 3.1 7.0 4.0 10.0

tset Ento LE 2.5 2.0 2.5 ns

Figures3&4

hold Ento LE 3.0 2.5 3.0 ns

Figures3&4

pw(H) Pulse Width LE 2.5 2.0 5.0 ns

Figures3&4

Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing

immediately after power-up. This provides ‘‘cold start’’ specs which can be considered a worst case condition at cold temperatures.

Note 2: Screen tested 100% on each device at a25§C, temperature only, Subgroup A9.

Note 3: Sample tested (Method 5005, Table I) on each mfg. lot at a25§C, Subgroup A9, and at a125§C and b55§C temperatures, Subgroups A10 and A11.

Note 4: Not tested at a25§C, a125§C and b55§C temperature (design characterization data).

Test Circuitry (TTL-to-ECL)

TL/F/10219–7

Note 1: Rte50Xtermination. When an input or output is being monitored by a scope, Rtis supplied by the scope’s 50Xresistance. When an input or output is not

being monitored, an external 50Xresistance must be applied to serve as Rt.

Note 2: TTL and ECL force signals are brought to the DUT via 50Xcoax lines.

Note 3: VTTL is decoupled to ground with 0.1 mF to ground, VEE is decoupled to ground with 0.01 mF and VCC is connected to ground.

Note 4: For ECL input pins, the equivelent force/sense circuitry is optional.

FIGURE 1. TTL-to-ECL AC Test Circuit

Switching Waveforms (TTL-to-ECL)

TL/F/10219–9

FIGURE 2. TTL to ECL TransitionÐPropagation Delay and Transition Times

Test Circuitry (ECL-to-TTL)

TL/F/10219–10

Note 1: Rte50Xtermination. When an input or output is being monitored by a scope, Rtis supplied by the scope’s 50Xresistance. When an input or output is not

being monitored, an external 50Xresistance must be applied to serve as Rt.

Note 2: The TTL Tri-State pull up switch is connected to a7V only for ZL and LZ tests.

Note 3: TTL and ECL force signals are brought to the DUT via 50Xcoax lines.

Note 4: VTTL is decoupled to ground with 0.1 mF, VEE is decoupled to ground with 0.01 mF and VCC is connected to ground.

FIGURE 3. ECL-to-TTL AC Test Circuit

Switching Waveforms (ECL-to-TTL)

TL/F/10219–11

Note: DIR is LOW, and OE is HIGH

FIGURE 4. ECL-to-TTL TransitionÐPropagation Delay and Transition Times

Note: DIR is LOW, LE is HIGH TL/F/10219–14

FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times

Note: OE is HIGH, LE is HIGH TL/F/10219–15

FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time

Applications

TL/F/10219–12

FIGURE 7. Applications DiagramÐMOS/TTL SRAM Interface Using 100328 ECL– TTL Latched Translator

Ordering Information

The device number is used to form part of a simplified purchasing code where A package type and temperature range are

defined as follows:

100328 D C QB

Device Type (Basic) Special Variation

QB eMilitary grade device with

Package Code environmental and burn-in

DeCeramic DIP processing

FeQuad Cerpak

PePlastic DIP Temperature Range

QePlastic Leaded Chip Carrier (PCC) C eCommercial (0§Ctoa

85§C)

SeSmall Outline (SOIC) I eIndustrial (b40§Ctoa

85§C)

(PCC Only)

MeMilitary (b55§Ctoa

125§C)

Physical Dimensions inches (millimeters)

24-Lead Ceramic Dual-In-Line Package (0.400×Wide) (D)

NS Package Number J24E

24-Lead Molded Package (0.300×Wide) (S)

NS Package Number M24B

Physical Dimensions inches (millimeters) (Continued)

24-Lead Plastic Dual-In-Line Packakge (P)

NS Package Number N24E

28-Lead Plastic Chip Carrier (V)

NS Package Number V28A

100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch

Physical Dimensions inches (millimeters) (Continued)

24-Lead Quad Cerpak (F)

NS Package Number W24B

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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