MT28C128532W18EBW--F605P706KTBWTES - Micron

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef80df9a45

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

FLASH AND CellularRAM™

COMBO MEMORY

MT28C128532W18/W30E

MT28C128564W18/W30E

Low Voltage, Wireless Temperature

Features

Stacked die Combo package

• Includes two 64Mb Flash devices

• Choice of either one 32Mb or one 64Mb CellularRAM

device

Basic configuration

Flash

• Flexible multibank architecture

• 4 Meg x 16 configuration

• Async/Page/Burst interface

• Support for true concurrent operations with no latency

CellularRAM

• Low-power, high-density design

• 2 Meg x 16 or 4 Meg x 16 configurations

•Burst interface

F_VCC, VCCQ, F_VPP, C_VCC voltages

• 1.70V (MIN)/1.95V (MAX) F_VCC, C_VCC

• 1.70V (MIN)/2.24V (MAX) VCCQ (W18)

• 2.20V (MIN)/3.30V (MAX) VCCQ (W30)

• 1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)

•12V ±5% (HV) F_VPP tolerant (factory programming

compatibility)

Fast programming Algorithm (FPA)

Enhanced suspend options

• ERASE-SUSPEND-to-READ within same bank

• PROGRAM-SUSPEND-to-READ within same bank

• ERASE-SUSPEND-to-PROGRAM within same bank

Each Flash contains two 64-bit chip protection registers for

security purposes

100,000 ERASE cycles per block

Cross-compatible command set support

• Extended command set

• Common Flash interface (CFI) compliant

Manufacturer’s Identification Code (ManID)

•Micron

•Intel

Options

Flash Timing

•60ns

1 (W18)

• 70ns (W18/W30)

Flash Burst Frequency

•66 MHz

1 (W18)

• 54 MHz (W18/W30)

Flash Boot Block Configuration

•Top/Top

•Top/Bottom

•Bottom/Top

•Bottom/Bottom

CellularRAM Timing

•70ns

•85ns

CellularRAM Burst Frequency

•66 MHz

I/O Voltage Range

• VccQ 1.70V–2.24V (W18)

• VccQ 2.20V–3.30V (W30)

Manufacturer’s Identification Code (ManID)

•Micron (0x2Ch)

• Intel (0x89h)

Operating Temperature Range

• Wireless Temperature (-25°C to +85°C)

Package

• 77-ball FBGA (Standard) 8 x 10 grid

• 77-ball FBGA (Lead-free) 8 x 10 grid2

NOTE: 1. Contact factory for availability.

2. Contact factory for details.

1 2 3 4 5 6 7 8

Top View

(Ball Down)

C_VSS

F_VPP

F_RST#

DQ10

DQ3

DQ11

F_VCC

A19

C_UB#

DQ2

DQ1

DQ9

VCCQ

C_OE#

F_CE1#

C_VSS

F_VCC

CLK

C_CE#

A20

DQ13

DQ14

DQ6

F_VCC

VSSQ

A11

A12

A13

A15

A16

F_CE2#

F_OE2#

VCCQ

C_CRE

C_VSS

F_VCC

F_WE#

DQ5

DQ12

DQ4

C_VCC

C_VSS

A18

C_LB#

A17

DQ8

DQ0

F_OE1#

VSSQ

RFU

A10

A14

AIT#

DQ7

DQ15

VCCQ

F_VSS

A21

Figure 1: 77-Ball FBGA

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Device General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Flash General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

CellularRAM General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Part Number Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Figures

Figure 1: 77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 5: 77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

List of Tables

Table 1: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 2: Possible Boot Configurations for Flash Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 3: Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 4: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 5: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 6: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 7: DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 8: CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 9: References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Device General Description

The MT28C128532W18/W30E/MT28C128564W18/

W30E combination Flash and CellularRAM devices are

a high-performance, high-density, memory solution

that can significantly improve system performance.

This memory solution is comprised of two 64Mb Flash

devices and one 32Mb or one 64Mb CellularRAM

device.

It is important to note that the specifications con-

tained in this document supersede the specifications

listed in the referenced individual Flash and Cellular-

RAM data sheets.

Flash General Description

The Flash architecture features a multipartition

configuration that supports READ-While-PROGRAM/

ERASE operations with no latency. A 4Mb partition size

enables optimal design flexibility.

Two Flash devices are stacked to achieve the 128Mb

density. Each Flash die has a dedicated CE# and OE#

control.

The stacked Flash device enables soft protection for

blocks, as read only, by configuring soft protection reg-

isters with dedicated command sequences. For secu-

rity purposes, two user-programmable 64-bit chip

protection registers are provided for each Flash device.

The embedded WORD PROGRAM and BLOCK

ERASE functions are fully automated by an on-chip

write state machine (WSM). An on-chip device status

determine the progress of the PROGRAM/ERASE tasks.

Each Flash device has a read configuration register

(RCR) that defines how the Flash interacts with the

memory bus. For device specifications and additional

documentation concerning Flash features, please refer

to the MT28F644W18 data sheet at www.micron.com/

flash.

Flash Configurations

Each Flash memory implements a multibank archi-

tecture (16 banks of 4Mb each) to allow concurrent

operations. Any address within a block address range

selects that block for the required READ, PROGRAM, or

ERASE operation.

Each Flash memory features eight 4K-word sectors

(8 x 65,536 bits), designated as parameter blocks, and

the remaining part is organized in main blocks of 32K

words each (524,288 bits). The parameter blocks are

addressed either by the low order addresses (bottom

boot) or by the higher order addresses (top boot).

The two Flash devices can be supplied with any

combination of top or bottom boot (e.g., top/top, bot-

tom/bottom, top/bottom, or bottom/top).

CellularRAM General Description

The CellularRAM architecture features high-speed

CMOS, dynamic random-access memories developed

for low-power portable applications The CellularRAM

device is available in either 32Mb or 64Mb densities.

Two user-accessible control registers define the

device operation. The bus configuration register (BCR)

defines how the CellularRAM device interacts with the

system memory bus and is nearly identical to its

counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how

refresh is performed on the CellularRAM array. These

registers are automatically loaded with default settings

during power-up and can be updated anytime during

normal operation.

To operate seamlessly on a burst Flash bus,

CellularRAM products have incorporated a

transparent self-refresh mechanism. The hidden

refresh requires no additional support from the system

memory controller and has no significant impact on

device read/write performance.

CellularRAM products include three system-acces-

sible mechanisms used to minimize standby current.

Partial array refresh (PAR) limits refresh to the portion

of the memory array being used. Temperature com-

pensated refresh (TCR) is used to adjust the refresh

rate according to the ambient temperature. The

refresh rate can be decreased at lower temperatures to

minimize current consumption during standby. Deep

sleep mode halts the refresh operation altogether and

is used when no vital information is stored in the

device. These three refresh mechanisms are adjusted

through the refresh configuration register (RCR).

For device specifications and additional documen-

tation concerning CellularRAM features, please refer to

the MT45W2MW16BFB, MT45W2ML16BFB,

MT45M4MW16BFB, and MT45W4ML16BFB data

sheets at www.micron.com/cellularram.

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 2: Flash Memory Map

NOTE:

Figure 2 shows a TB (top/bottom) dual Flash configuration.

Parameter

Blocks –

Top Boot

F_CE2#/F_OE2#

controlled upper address space

(64Mb to 128Mb)

Main

Parameter

Blocks –

Bottom Boot

F_CE1#/F_OE1#

controlled lower address space

(0Mb to 64Mb)

Main

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Block Diagram

C_OE#

C_CRE

C_CE#

C_WE#

DQ0

–

DQ15

–

A21

F_WE#

WP#

WAIT

FLASH #2

CellularRAM

F_RST#

C_UB#

C_LB#

4,096K x 16

2,048K x 16

4,096K x 16

Bank 31

Bank 16

C_VCC

F_OE2#

F_CE2#

ADV#

C_VSS

FLASH #1

4,096K x 16

Bank 15

Bank 0

VCCQ

VSSQ

F_VCC

F_VSS

F_VPP

CLK

F_OE1#

F_CE1#

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Part Number Information

Micron’s combination memory devices are available

with several different combinations of features (see

Figure 4).

Figure 4: Part Number Chart

NOTE:

1. The first character in this field refers to Flash die #2. The second character in this field refers to Flash die #1.

2. Contact factory for availability.

Valid Part Number Combinations

After building the part number from the part num-

ber chart above, please go to Micron’s Part Marking

Decoder Web site at www.micron.com/decoder to ver-

ify that the part number is offered and valid. If the

device required is not on this list, please contact the

factory.

Device Marking

Due to the size of the package, the Micron standard

part number is not printed on the top of each device.

Instead, an abbreviated device mark comprised of a

five-digit alphanumeric code is used. The abbreviated

device marks are cross-referenced to the Micron part

numbers at www.micron.com/decoder. To view the

location of the abbreviated mark on the device, please

refer to customer service note CSN-11, “Product Mark/

Label,” at www.micron.com/csn.

Micron Technology

Flash Family

28C = Dual-Supply Flash/CellularRAM Combo

Density/Organization/Banks

128 = two 64Mb (4,096K x 16)

bank x = 5 Multibank 32 Banks

(all banks have the same dimensions)

Flash Access Time

F60 = 60ns2

F70 = 70ns

CellularRAM Density

32 = 32Mb CellularRAM (2 Meg x 16)

64 = 64Mb CellularRAM (4 Meg x 16)

Flash Read Operation

W = Flash Async/Page/Burst

Package Code

FW = 77-ball FBGA (Standard) 8 x 10 grid

BW = 77-ball FBGA (Lead-free) 8 x 10 grid2

Operating Temperature Range

WT = Wireless (-25ºC to +85ºC)

Flash Burst Frequency

5 = 54 MHz

6 = 66 MHz2

Flash Boot Block Starting Address1

TT = Top boot/Top boot

TB = Top boot/Bottom boot

BT = Bottom boot/Top boot

BB = Bottom boot/Bottom boot

Operating Voltage Range

VCC = 1.70V–1.95V

VCCQ = 1.70V–2.24V

VCC = 1.70V–1.95V

VCCQ = 2.20V–3.30V

CE Select/Special Mark

E = Dual CE Flash with Burst CellularRAM Memory

Production Status

Blank = Production

ES = Engineering Samples

QS = Qualification Samples

MT28C 1285 64 W18 E FW -F70 5 -P85 6 BB WT ES

Flash Manufacturer's

Identification Code

None = Micron (2Ch)

K = Intel (89h)

CellularRAM Access Time

P70 = 70ns

P85 = 85ns

CellularRAM Burst Frequency

6 = 66 MHz

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 1: Ball Descriptions

77-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTIONS

F1, E1, D1, C1, A1,

B1, E2, D2, E6, C7,

D7, A8, B8, C8, E7,

D8, E8, C2, A2, A3,

D6, A7

A0–A21 Input Addresses:

Flash: A0–A21 (128Mb).

CellularRAM: A0–A21 (64Mb).

CellularRAM: A0–A20 (32Mb).

J1 F_CE1# Input Flash Chip Enable #1.

F8 F_CE2# Input Flash Chip Enable #2.

H2 F_OE1# Input Flash Output Enable #1.

G8 F_OE2# Input Flash Output Enable #2.

E5 F_WE# Input Flash Write Enable.

D4 F_WP# Input Flash Write Protect.

E4 F_RST# Input Flash Reset.

B2 C_LB# Input CellularRAM Lower Byte Control.

E3 C_UB# Input CellularRAM Upper Byte Control.

C5 C_WE# Input CellularRAM Write Enable.

G1 C_OE# Input CellularRAM Output Enable.

C6 C_CE# Input CellularRAM Chip Enable.

J8 C_CRE Input CellularRAM Deep Sleep Mode and Configuration Mode.

D5 ADV# Input Address Valid (burst operation only).

B6 CLK Input Clock (burst operation only).

G2, G3, F3, G4, H5,

F5, H6, G7, F2, H3,

F4, H4, G5, F6, G6,

DQ0–DQ15 I/O Flash/CellularRAM Data Input/Output.

F7 WAIT# Output WAIT#. See “WAIT Ball Operation” on page 10.

K7 F_VSS Supply Flash Core Ground.

C4 F_VPP Supply Flash VPP.

A5, A6, J6, K4 F_VCC Supply Flash Core Power Supply.

A4, B4, K1, K5, K8 C_VSS Supply CellularRAM Core Ground.

J5 C_VCC Supply CellularRAM Core Power Supply.

H8, J7, K3 VCCQ Supply Flash/CellularRAM I/O Supply.

K2, K6 VSSQ Supply Flash/CellularRAM I/O Ground.

B5, H1, J2, J3, J4 NC –No Connect. Not internally connected to the die.

B7 RFU – Reserved for Future Use (A22).

B3, C3, D3 – – Ball not Mounted. Reserved for Future Use (A23, A24, A25).

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Boot Configurations

The possible configurations for Flash die are shown

in Table 2 below. This table shows the possible config-

urations of the two Flash devices for either top boot or

bottom boot: F_CE1# and F_CE2# indicate to which

Flash die the configuration is referred.

MultiChip Packaging Considerations

Multichip packaging presents unique chal-

lenges when controlling complex memory devices.

The MT28C128532W18/W30E and

MT28C128564W18/W30E devices combine two

Micron Flash devices with a single CellularRAM

device.

Unique IDs, State Machines, and

Registers

Each Flash device has a separate command state

machine (CSM) and status register (SR) and read con-

figuration register (RCR). The read configuration regis-

ter (RCR) settings are separate and can be different for

the upper and lower device. Each Flash device has its

own OTP, CFI, and device code. Depending on the boot

configuration of each Flash device, the OTP, CFI, and

device code information may differ.

Both Flash devices will share the same ManID,

either Micron (0x2Ch) or Intel (0x89h), which is

defined by the part number.

The CellularRAM memory has a refresh configura-

tion register (RCR) that defines how the device per-

forms self refresh, and a bus configuration register

(BCR) to define the interface configuration.

Command Codes

All Flash command codes are independent

within each device. Care must be taken when

crossing the array boundary between the upper

and lower Flash and the CellularRAM memory to

ensure that only one device is enabled at one time.

In a two-cycle command sequence such as word

program (0x40/data), it is required that both com-

mands be issued to the same device.

It is not recommended that simultaneous READ,

simultaneous WRITE, or simultaneous ERASE opera-

tions occur on both Flash devices.

READ Operation

All READ operations are limited to the address

boundaries of each device. A new READ operation

must be started when crossing a device boundary.

Flash Reset

The reset control is shared by both Flash die.

Bringing F_RST# control LOW will reset both the

upper and lower device.

WAIT Ball Operation

It is important to note that the Flash and Cellular-

RAM devices share the WAIT ball functionality and

must be configured correctly for proper burst mode

operation. The Flash and CellularRAM devices use dif-

ferent registers to configure the WAIT polarity and

have opposite default values.

The WAIT ball polarity for the Flash device is config-

ured by programming bit 10 in the read configuration

The WAIT ball polarity for the CellularRAM device is

configured by programming bit 10 in the bus configu-

ration register (BCR). The default is active HIGH.

Both the Flash and CellularRAM WAIT ball polarities

must be set to the same active level for proper opera-

tion.

Power Consumption

Multiple chip packaging requires that power

calculations consider the active operation of the

upper and lower Flash as well as that of the

CellularRAM device. Total power consumed will be

the sum of the currents associated with the state

of each device.

Table 2: Possible Boot Configurations

for Flash Die

CONFIGURATION F_CE2# F_CE1#

ORDER

CODE

Top/Top Top Top TT

Top/Bottom Top Bottom TB

Bottom/Top Bottom Top BT

Bottom/Bottom Bottom Bottom BB

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. WAIT status is only valid for burst mode operation. WAIT should be ignored for all other operating modes.

Table 3: Truth Table

MODES

FLASH SIGNALS SHARED SIGNALS CellularRAM SIGNALS MEMORY OUTPUT

F_CE1# F_CE2# F_OE1# F_OE2# F_WE# F_RST# ADV# WAIT# C_CE# C_CRE C_OE# C_UB/LB# C_WE#

MEMORY

BUS

CONTROL

DQ0–

DQ15

FLASH F_CE1#

Read LHL XHH L

Active1

CellularRAM memory must be in High-Z Flash DOUT

Write L H H X L H X Asserted Flash DIN

Standby HX X XXH XHigh-Z

CellularRAMmemory any mode allowable

Other High-Z

Output

Disable LXHXHH X

Active1Other High-Z

Reset X X X X X L X High-Z None High-Z

FLASH F_CE2#

Read HLX LHH L

Active1

CellularRAM memory must be in High-Z Flash DOUT

Write H L X H L H X Asserted Flash DIN

Standby XHX XXH XHigh-Z

CellularRAM memory any mode allowable

Other High-Z

Output

Disable XLXHHH X

Active1Other High-Z

Reset X X X X X L X High-Z None High-Z

CELLULARRAM MEMORY

Read

Flash must be in High-Z

LActive1LLL L H

Cellular

RAM DOUT

Write LActive1LLH L L

Cellular

RAM DIN

Standby

Flash any mode allowable

XXHLXXXOtherHigh-Z

Output

Disable XXLLHXHOtherHigh-Z

Deep

Sleep

Mode

XXHHXXXOtherHigh-Z

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Electrical Specifications

NOTE:

1. Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sec-

tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. See technical note TN-00-15 for more information.

Table 4: Absolute Maximum Ratings

Note 1

PARAMETERS/CONDITIONS MIN MAX UNITS NOTES

Operating Temperature Range -25 +85 °C

Storage Temperature Range -55 +125 °C

Soldering Cycle +260 °C 2

Table 5: Recommended Operating Conditions

PARAMETER SYMBOL MIN TYP MAX UNITS

VCC Supply Voltage (F_VCC and C_VCC)VCC 1.70 – 1.95 V

I/O Supply Voltage VccQ (W18) 1.70 –2.24 V

VccQ (W30) 2.20 3.30

Table 6: Capacitance

TA = +25°C; f = 1 MHz

PARAMETER/CONDITION SYMBOL TYP MAX UNITS

Input Capacitance CIN 13 17 pF

Output Capacitance COUT 18 20 pF

Clock Capacitance CCLK 22 23 pF

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. C_CRE ball HIGH, CR4 bit in the CellularRAM refresh configuration register set to zero. Measured at 25°C, this

standby current is the sum of the Flash standby current and the CellularRAM deep-power down mode current.

2. ICCES and ICCWS values are valid when the device is deselected. Any READ operation performed while in suspend

mode will have an additional current draw of suspend current.

3. Automatic power save (APS) mode reduces ICC to approximately ICCS levels.

4. Currents are measured using CellularRAM full array self-refresh. Currents may be further reduced by using the TCR

or PAR features.

Table 7: DC Characteristics

It is important to note that the specifications contained in this document supersede the specifications listed in the

referenced individual Flash and CellularRAM data sheets. All currents are in RMS unless otherwise noted.

PARAMETER SYMBOL

W18/W30

UNITS NOTESTYP MAX

VCC Standby Current

with 32Mb CellularRAM device

with 64Mb CellularRAM device

ICCS 160

170

µA 4

VCC Standby with CellularRAM device in deep power-

down (DPD) mode

with 32Mb CellularRAM device

with 64Mb CellularRAM device

ISBZZ 60

µA 1, 4

VCC Program Suspend Current

with 32Mb CellularRAM device

with 64Mb CellularRAM device

ICCWS 160

170

µA 2, 4

VCC Erase Suspend Current

with 32Mb CellularRAM device

with 64Mb CellularRAM device

ICCES 160

170

µA 2, 4

VCC Automatic Power Save Current

with 32Mb CellularRAM device

with 64Mb CellularRAM device

ICCAPS 160

170

µA 3, 4

Table 8: CFI

It is important to note that the specifications contained in this document supersede the specifications listed in the

referenced individual Flash and CellularRAM data sheets.

OFFSET DATA DESCRIPTION

78 32Mb: 0020 CellularRAM Density

64Mb: 0040

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice..

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S.

All other trademarks are the property of their respective owners.

Figure 5: 77-Ball FBGA

NOTE:

1. All dimensions in millimeters.

Data Sheet Designation

Production: This data sheet contains minimum and maximum limits specified over the complete power supply

and temperature range for production devices. Although considered final, these specifications are subject to

change, as further product development and data characterization sometimes occur.

For additional documentation concerning Flash and CellularRAM features, functional descriptions, program-

ming, and timing, please refer to the table below.

BALL A1 ID

1.025 ±0.075

SEATING PLANE

0.10 C

1.40 MAX

BALL A8

BALL A1 ID

0.80

TYP

0.80 TYP

2.80 ±0.05

5.60

BALL A1

8.00 ±0.10

4.00 ±0.05

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-REFLOW

DIAMETER IS Ø 0.35mm ON A

0.30mm SMD BALL PAD.

77X ∅0.35

SOLDER BALL MATERIAL:

EUTECTIC 62% Sn, 36% Pb, 2% Ag

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

7.20

3.60 ±0.05

5.00 ±0.05

10.00 ±0.10

Table 9: References

DEVICE PART NUMBER LINK

Flash MT28F644W18/W30 www.micron.com/flash

CellularRAM MT45W2MW16BFB, MT45W2ML16BFB,

MT45M4MW16BFB, MT45W4ML16BFB

www.micron.com/cellularram

128Mb MULTIBANK BURST FLASH

32Mb/64Mb BURST CellularRAM COMBO

09005aef80df9a45 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Revision History

Rev C, Production............................................................................................................................................................2/04

• Removed Preliminary status/designation

• Updated standby current specifications in the DC Characteristics Table

Rev B, Preliminary .........................................................................................................................................................11/03

Original document, Rev. A, Preview...............................................................................................................................8/03