DS1646/0S1646LPM PRELIMINARY DALLAS DS1646/DS1646LPM SEMICONDUCTOR Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT Optional low profile socketable module Fits into a standard 68-pin PLCC surface mountable socket 250 mil package height Integrated NV SRAM, real time clock, crystal, power fail control circuit and lithium energy source 1 2 3 4 5 6 7 8 Standard JEDEC bytewide 128K x 8 static RAM pin- out Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations. Totally nonvolatile with over 10 years of operation in the absence of power 128K XB 32-Pin Encapsulated Package @ Access times of 120 ns and 150 ns Quartz accuracy +1 minute a month @ 25C, factory NC 1 34 NC i AIS 2 33 NC calibrated AN 3 32 Ata BCD coded year, month, date, day, hours, minutes, ie 30 Ate and seconds WE 6 29 All OE 7 28 A10 Power fail write protection allows for +10% Vcc power oor 8 a7 ne supply tolerance Dos 10 25 AT DOS "1 24 AG Das 12 23 AS 0a3 13 22 A4 pa2 14 24 A3 ORDERING INFORMATION pao ie * DS1646-XX = (32pin DIP module) GND 17 18 AO -12 120 ns access 34-Pin Low Profile Module -15 150 ns access (Scheduled Availability is QTR 3 1994) DS1646L-XX (Low Profile Module) PIN DESCRIPTION AO-A16 Address Input -12 120 ns access aE : -15 150 ns access CE ~ Chip Enable OE ~ Output Enable WE Write Enable Voc +5 Volts GND Ground DQ0-DQ7 Data Input/Output NC No Connect PFO Power Fail Output (DS1646LPM only) 1995 by Dallas Semiconductor Corporation 090895 1/11 o . patents and atvor miekectoel propery nigh, please re to 561 Batas Semiconductor Gata Books. my otis,0S1646/DS1646LPM DESCRIPTION The DS1646LPM is a low profile module that fits into a standard 68-pin PLCC surface mountabie socket andis functionally equivalent to the DS1646. The DS 1646 is a 128K x 8 nonvolatile static RAM with a full function real time clock which are both accessible in a bytewide for- mat. The nonvolatile time keeping RAM is pin and func- tion equivalent to any JEDEC standard 128K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and EEPROM sockets providing read/write nonvolatility and the addition of the real time clock func- tion. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The 0S1646 also con- tains its own power fail circuitry which deselects the de- vice when the Voc supply is in an out of tolerance condi- tion. This feature prevents loss of data from BLOCK DIAGRAM DS1646 Figure 1 32.768 KHz [_] OSCILLATOR AND CLOCK COUNTDOWN CY CHAIN unpredictable system operation brought on by low Voc as errant access and update cycles are avoided. CLOCK OPERATIONS-READING THE CLOCK While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1646 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the seventh most significant bit in the contro! register. As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock reg- isters of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1646 registers are updated simul- taneously after the clock status is reset. Updating is within a second after the read bit is written to zero. CLOCK REGISTERS POWER MONITOR, POWER GOOD 12BK X 8 NV SRAM SWITCHING, AND WRITE PROTECTION Vec = 090895 2/11DS1646/DS1646LPM TRUTH TABLE DS1646 Table 1 Vec CE | OF | WE MODE DQ POWER Vin X x DESELECT HIGH Z STANDBY Xx X x DESELECT HIGH Z STANDBY 5 VOLTS + 10% Vit Xx ViL WRITE DATA IN ACTIVE Vit Viiv | Vin READ DATA OUT ACTIVE Vit Vin Vin READ HIGH Z ACTIVE <4.5 VOLTS xX x X DESELECT HIGH 2 CMOS STANDBY >VBaT <Vpat X X X DESELECT HIGH Z DATA RETENTION MODE SETTING THE CLOCK FREQUENCY TEST BIT The eighth bit of the control register is the write bit. Set- ting the write bit to a 1, like the read bit, halts updates to the DS 1646 registers. The user can then load them with the correct day, date and time data in 24 hour BCD for- mat. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. Note that both the read bit and write bit perform similar functions and setting both bits during the same access cycle will prevent the clock reg- isters from updating. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To in- crease the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting itto a 1 stops the oscillator. Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQO line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable). CLOCK ACCURACY The DS1646 is guaranteed to keep time accuracy to within +1 minute per month at 25C. The clock is cali- brated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS1646 does not require additional calibration and tem- perature deviations will have a negligible effect in most applications. For this reason, methods of field clock cal- ibration are not available and not necessary. 563 090895 3/11DS1646/DS1646LPM DS1646 REGISTER MAP - BANK1 Table 2 DATA ADDRESS B, Be Bs B, B, Bp B, By FUNCTION 1FEFF - - - - - - - - YEAR 00-99 1FFFE xX x x - - - - - MONTH = 01-12 1FFFD x x - - - - - - DATE 01-31 1FFFC x FT x x X - - - DAY 01-07 1FFFB X X : : : - - : HOUR 00-23 41FFFA x - - - - - - - MINUTES 00-59 1FFFS Osc - - - - - - - SECONDS 00-59 1FFF8 w R - - - - - - CONTROL A OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST Ws = WRITE BIT X = UNUSED NOTES: X bits are unused but must be set to zero during write cycle to insure proper clock operation. Bits 0 through 5 of control register A are not dedicated to any particular function and can be used as normal RAM bits. RETRIEVING DATA FROM RAM OR CLOCK The DS1646 is in the read mode whenever WE (write enable) is high, CE (chip enable) is low. The device ar- chitecture allows ripple-through access to any of the ad- dress locations in the NV SRAM. Valid data will be avail- able at the DQ pins within ta, after the last address input is stable, providing that the CE and OE access times are satisfied. if CE or OE access times are not met, valid data will be available at the latter of chip enable access (tcea) or at output enable access time (toga). The state of the data input/output pins (DQ) is controlled by CE and OE. ifthe outputs are activated before ta,, the data lines are driven to an intermediate state until tag. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (to}4) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK _ __ The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring high to low transition of WE and CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of twr Prior to the initiation of another read or write cycle. Data in must be valid tog prior to the end of write and re- main valid for tp afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. Alowtran- sition on WE will then disable the outputs twez after WE goes active. 090895 4/11 564DS1646/0S1646LPM DATA RETENTION MODE When Vcc is within nominal limits (Vec > 4.5 volts) the DS1646 can be accessed as described above with read or write cycles. However, when Vcc is below the power fail point Vp (point at which write protection occurs) the internal clock registers and RAM is blocked from ac- cess. This is accomplished internally by inhibiting ac- cess via the CE signal. At this time the power fail output signal (PFO) will be driven active low and will remain active until Voc returns to nominal levels. When Voc falls below the level of the internal battery supply, power input is switched from the Vcc pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until Vcc is returned to nominal level. INTERNAL BATTERY LONGEVITY The DS1646 has a self contained lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the Vcc supply is not present. The capability of this internal power supply is sufficient to power the DS1646 continuously for the life of the equipment in which it is installed. For specifi- cation purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of Voc power. The DS1646 is shipped from Dallas Semiconductor with the clock oscillator turned off, so the expected life should be considered to start from the time the clock oscillator is first turned on. Actual life ex- pectancy of the DS1646 will be much longer than 10 years since no internal lithium battery energy is con- sumed when Vcc is present. In fact, in most applica- tions, the life expectancy of the DS 1646 will be approxi- mately equal to the shelf life (expected useful life of the lithium battery with no load attached) of the lithium bat- tery which may prove to be as long as 20 years. 565 090895 5/110S1646/DS1646LPM ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0C to 70C Storage Temperature 20C to +70C Soldering Temperature 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage Voc 4.5 5.0 5.5 Vv 1 Logic 1 Voltage All Inputs Vin 2.2 Voct0.3 Vv Logic 0 Voltage All inputs ViL -0.3 0.8 Vv DC ELECTRICAL CHARACTERISTICS (OC <ta S$ 70C; Voc=5.0V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Average Vcc Power Supply loci 30 55 mA 2,3 Current TTL Standby Current (CE = Vi) loca 3 6 mA 2,3 CMOS Standby Current locs 2 4.0 mA 2,3 (CE=Vcoc-0.2V) Input Leakage Current (any input) Nie -1 +1 pA Output Leakage Current lot -1 +1 pA Output Logic 1 Voltage Vou 2.4 Vv (lout = -1.0 mA) Output Logic 0 Voltage VoL 0.4 Vv (lout = +2.1 mA) Write Protection Voltage Ver 4.0 4.25 4.5 Vv 090895 6/11 5660S1646/0S1646LPM AC ELECTRICAL CHARACTERISTICS (0C to 70C; Voc = 5.0V + 10%) DS1646-12 DS1646-15 PARAMETER SYMBOL UNITS | NOTES MIN MAX MIN MAX Read Cycle Time tac 120 150 ns Address Access Time taa 120 150 ns CE Access Time tcea 120 150 ns CE Data Off Time tcEz 40 50 ns Output Enable Access Time toEA 100 120 ns i} Output Enable Data Off Time toez 40 50 ns Output Enable to DQ Low-Z toEL 5 5 ns CE to DQ Low-Z tceL 5 5 ns Output Hold from Address ton 5 5 ns Write Cycie Time twe 120 150 ns Address Setup Time tas 0 0 ns CE Pulse Width tcew 100 120 ns Address Hold from End of Write taH 15 20 ns Write Pulse Width twew 120 150 ns WE Data Off Time twez 40 50 ns WE or CE Inactive Time twr 10 15 ns Data Setup Time tos 85 110 ns Data Hold Time High tou 15 20 ns AC TEST CONDITIONS Input Levels: OV to 3V Transition Times: 5 ns CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Capacitance on all pins Cy 7 pF (except DQ) Capacitance on DQ pins Coa 10 pF 567 090895 7/110S1646/DS1646LPM AC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TIMING) (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at Vi, before Power tpp ) ps Down Vpr (Max) to Vpg (Min) Voc Fall te 300 ps Time Vpg (Min) to Vso Voc Fall Time tee 10 Ls Vgo to Vpg (Min) Vcc Rise Time tre 1 us Vpr (Min) to Vpg (Max) Voc Rise tr 0 ys Time Power Up tRec 15 25 35 ms Expected Data Retention Time tor 10 years 4 (Oscillator On) DS1646 READ CYCLE TIMING READ READ WRITE M. tag 7 L-___ tac twe eo 4 4 AQ-A16 x ; 4 k tas p _ tay tcea w] wr fe tas CE tceL K twa _ 1 ~~ twew 7 WE toEL y toy toez noe ({enoar Kf woo} (wo) q VALID OUT VALID OUT/ VALID IN 090895 8/11 568DS1646/0S1646LPM DS1646 WRITE CYCLE TIMING WRITE WRITE READ a$__. two oe. tw - op _ tr AD-AI6 Kw yw K tas twa i ta, ty a a xc 4 ft ten >| aE ] tcew "| /| \ [# toca OE _| / twr oe twew > | WE r tou tcez ] tos twez tos <a Dao- VALID Dao- Yall . VALID IN |} _J y VALID IN }4 VALID OUT POWER DOWN/POWER UP TIMING Vec Vpr (MAX) Vpe (MIN) J te tr Vso Vso FE tep \ tre 7 A 4 tpp = j} m trec / Z N ze yo cE \ i # / ; um / Z N BATT / \ DATA RETENTION tbr 090895 9/11 5690S1646/DS1646LPM NOTES: 1. All voltages are referenced to ground. 2. Typical values are at 25C and nominal! supplies. 3. Outputs are open. 4. Data retention time is at 25C and is calculated from the date code on the device package. The date code XXYY is the year followed by the week of the year in which the device was manufactured. For example, 9225, would mean the 25th week of 1992. DS1646 32PIN PACKAGE ole If or OUTPUT LOAD +5 VOLTS 1.8KQ D.U.T. 1KQ 100 pF PKG 32-PIN DIM MIN MAX A IN. 1.670 1.690 MM 38.42 38.93 BIN. 0.715 0.740 MM 18.16 18.80 Cc IN. 0.335, 0.365 MM 8.51 9.27 D IN. 0.075 0.105 MM 1.91 0.67 E IN, 0.015 0.030 MM 0.38 0.76 F IN. 0.140 0.180 MM 3.56 4.57 G IN. 0.090 0.110 MM 2.29 2.79 HIN. 0.590 0.630 MM 14.99 16.00 JIN. 0.010 0.018 MM 0.25 0.45 KIN. 0.015 0.025, MM 0.38 0.64 090895 10/11 5700S1646/0S1646LPM DS1646LPM 34-PIN LOW PROFILE MODULE PKG INCHES DIM MIN MAX A 0.955 0.970 B 0.840 0.855 { Cc 0.230 0.250 A DB 0.975 0.995 E J E 0.047 0.053 F 0.015 0.025 fc B | NOTE: The recommended 68-pin PLCC surface mountable socket to be used with this 34pin module is: McKenzie P/N# 34P-SMT-3. The McKenzie socket plus the DS1646LPM has the following approximate dimen- sions: Jength, width = 1.22, height = 0.255. 090895 11/11 571