HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM Features: True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access - Commercial: 15/20/25/35/55ns (max.) - Industrial: 20/35ns (max.) Low-power operation - IDT70V27S Active: 500mW (typ.) Standby: 3.3mW (typ.) - IDT70V27L Active: 500mW (typ.) Standby: 660W (typ.) Separate upper-byte and lower-byte control for bus matching capability Dual chip enables allow for depth expansion without external logic IDT70V27S/L IDT70V27 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (0.3V) power supply Available in 100-pin Thin Quad Flatpack (TQFP), and 144pin Fine Pitch BGA (fpBGA) Industrial temperature range (-40C to +85C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/W L UBL R/WR UBR CE0L CE0R CE1L CE1R OEL OER LBL LBR I/O 8-15L I/O8-15R I/O Control I/O0-7L BUSYL I/O Control A14L (1,2) , BUSYR Address Decoder A0L 32Kx16 MEMORY ARRAY 70V27 A14L A0L CE0L CE1L OEL ARBITRATION INTERRUPT SEMAPHORE LOGIC R/WL Address Decoder A14R A0R A14R A0R CE0R CE1R OER R/WR SEM L INT L I/O 0-7R (1,2) (2) M/S NOTES: 1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2) BUSY and INT are non-tri-state totem-pole outputs (push-pull). (2) SEMR (2) INTR 3603 drw 01 SEPTEMBER 2012 6.01 1 (c)2012 Integrated Device Technology, Inc. DSC 3603/12 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Description: reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 500mW of power. The IDT70V27 is packaged in a 100-pin Thin Quad Flatpack (TQFP) and a 144-pin Fine Pitch BGA (fp BGA). The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM, designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for Pin Configurations(1,2,3) A8L A7L A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL VSS M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R A7R A8R 07/29/04 INDEX A9L A10L A11L A12L A13L A14L NC NC NC LBL UBL CE0L CE1L SEML VDD R/WL OEL VSS VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 11 12 13 14 IDT70V27PF PN100-1(4) 100-PIN TQFP TOP VIEW(5) 66 65 64 63 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A9R A10R A11R A12R A13R A14R NC NC NC LBR UBR CE0R CE1R SEMR VSS R/WR OER VSS VSS I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R I/O9L I/O8L VDD I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L VSS I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VDD I/O7R I/O8R I/O9R NC 3603 drw 02 NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Pin Configurations(1,2,3) (con't.) 07/29/04 A1 NC B1 A2 NC B2 A10L D1 A14L E1 C2 B3 NC C3 A9L D2 A13L E2 LBL F1 A8L NC NC C1 A3 NC D3 A12L E3 NC F2 F3 G1 G3 H1 NC J1 VSS K1 I/O12L L1 VDD H2 I/O9L N1 NC C6 A3L D5 A11L C7 D6 A4L B9 INTR C8 NC D7 A0L BUSYR A1R B8 M/S NC A9 A8 VSS B7 NC C5 A7L D4 B6 A2L A2R C9 A3R NC D8 D9 BUSYL A0R A4R E4 H3 NC L2 144-Pin fpBGA Top View(5) M2 NC N2 NC NC M4 VDD N3 N4 I/O8L I/O7L K6 I/O6L I/O3L L6 I/O2L I/O5L M5 M6 V SS I/O4L N5 N6 NC I/O1L K7 K8 K9 I/O0R I/O3R L7 L8 VSS C13 A10R A11R D11 A8R A12R E11 D12 F11 D13 A 13R E12 NC M7 M8 I/O0L N7 M9 I/O2R N8 VDD I/O5R G11 NC H11 OER J11 K10 K11 E13 NC F12 I/O1R NC LBR F13 G12 G13 VSS H12 L10 L11 NC J12 M10 M11 N10 N11 VDD NC VSS K13 NC L12 I/O12R , L13 NC M12 I/O8R VSS J13 K12 NC VSS H13 R/WR NC I/O4R I/O7R N9 A14R CE0R CE1R SEMR I/O6R I/O11R L9 VDD NC C12 I/O13R I/O14R I/O15R L5 NC B13 NC A9R NC K5 L4 M3 D10 J10 NC B12 NC C11 A7R H10 NC K4 NC C10 A13 NC NC NC H4 NC L3 B11 A6R G10 NC J4 K3 B10 UBR IDT70V27BF BF144-1(4) A12 NC F10 I/O15L I/O14L I/013L K2 A11 A5R NC UBL OEL A10 E10 NC G4 J3 I/O11L I/O10L M1 C4 A7 INTL B5 A 6L VDD R/WL J2 B4 A6 A1L F4 CE0L VDD A5 A5L NC SEML CE1L G2 A4 I/O10R M13 NC N12 I/O9R N13 NC NC 3603 drw 02a NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 12mm x 12mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A14L A0R - A14R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VDD Power (3.3V) Vss Ground (0V) 3603 tbl 01 3 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Truth Table I - Chip Enable(1,2,3) CE0 CE1 VIL VIH < 0.2V >VDD -0.2V Port Selected (CMOS Active) VIH X Port Deselected (TTL Inactive) X VIL Port Deselected (TTL Inactive) >VDD -0.2V X Port Deselected (CMOS Inactive) X <0.2V Port Deselected (CMOS Inactive) CE L H Mode Port Selected (TTL Active) 3603 tbl 02 NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only. 2. Port "A" and "B" references are located where CE is used. 3. "H" = VIH and "L" = VIL Truth Table II - Non-Contention Read/Write Control Inputs(1) Outputs CE(2) R/W OE UB LB SEM I/O8-15 I/O0-7 H X X X X H High-Z High-Z Deselected: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATA IN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATAOUT Read Lower Byte Only L H L L L H DATAOUT DATA OUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled Mode 3603 tbl 03 NOTES: 1. A0L -- A14L A 0R -- A14R. 2. Refer to Chip Enable Truth Table. Truth Table III - Semaphore Read/Write Control Inputs(1) Outputs CE(2) R/W OE UB LB SEM I/O8-15 I/O0-7 H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag H X X X L DATAIN DATAIN Write I/O0 into Semaphore Flag X X H H L DATAIN DATAIN Write I/O0 into Semaphore Flag L X X L X L ______ ______ Not Allowed L X X X L L ______ ______ Not Allowed Mode NOTES: 1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O15). These eight semaphore flags are addressed by A 0-A2. 2. Refer to Chip Enable Truth Table. 4 3603 tbl 04 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Commercial & Industrial Unit -0.5 to +4.6 V Terminal Voltage with Respect to GND Maximum Operating Temperature and Supply Voltage(1) Ambient Temperature GND VDD 0 C to +70 C 0V 3.3V + 0.3V -40 C to +85 C 0V 3.3V + 0.3V Grade Commercial TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -65 to +150 o IOUT DC Output Current 50 O Industrial C O O O NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. C 3603 tbl 06 mA 3603 tbl 05 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. Recommended DC Operating Conditions(1) Symbol Parameter Input Capacitance CIN (2) COUT Output Capacitance Supply Voltage VSS Ground VIH Input High Voltage Conditions Max. Unit VIN = 0V 9 pF V OUT = 0V 10 pF Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 2.0 ____ (1) Input Low Voltage -0.3 V VDD+0.3V (2) 0.8 ____ V V 3603 tbl 07 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VDD + 0.3V. (TA = +25C, f = 1.0mhz)TQFP ONLY Symbol VDD VIL Capacitance(1) Parameter NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. COUT also reference CI/O. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V 0.3V) 70V27S Symbol Parameter Test Conditions 70V27L Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) VDD = 3.6V, VIN = 0V to V DD ___ 10 ___ 5 A |ILO | Output Leakage Current CE = VIH, VOUT = 0V to VDD ___ 10 ___ 5 A VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V NOTE: 1. At VDD 3603 tbl 09 < 2.0V, input leakages are undefined. 5 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6) (VDD = 3.3V 0.3V) 70V27X15 Com'l Only Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) Standby Current CEL = CER = VIH (Both Ports - TTL Level SEMR = SEML = VIH Inputs) f = fMAX(3) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) CE"A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = V IH Version 70V27X20 Com'l & Ind 70V27X25 Com'l Only Typ.(2) Max. Typ. (2) Max. Typ. (2) Max. Unit 165 165 255 220 145 145 245 210 mA COM'L S L 170 170 260 225 IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 165 230 ____ ____ COM'L S L 44 44 70 60 39 39 60 50 27 27 50 40 IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 39 55 ____ ____ COM'L S L 115 115 160 145 105 105 155 140 90 90 150 135 IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 105 150 ____ ____ Both Ports CEL and CER > V DD - 0.2V V IN > VDD - 0.2V or V IN < 0.2V, f = 0(4) SEMR = SEML > V DD - 0.2V COM'L S L 1.0 0.2 6 3 1.0 0.2 6 3 1.0 0.2 6 3 IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 0.2 6 ____ ____ CE"A" < 0.2V and CE"B" > VDD - 0.2V (5) SEMR = SEML > VDD - 0.2V V IN > VDD - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 115 115 155 140 105 105 150 135 90 90 145 130 IND'L S L ____ ____ ____ ____ ____ ____ ____ ____ 145 ____ ____ 105 mA mA mA mA 3603 tbl 10a NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VDD = 3.3V, TA = +25C, and are not production tested. IDD DC = 90mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to Chip Enable Truth Table. 6 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6) (VDD = 3.3V 0.3V) 70V27X35 Com'l & Ind Symbol Parameter IDD Dynamic Operating Current (Both Ports Active) ISB1 ISB2 ISB3 ISB4 Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition Version CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CEL = CER = V IH SEMR = SEML = V IH f = fMAX(3) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH 70V27X55 Com'l Only Typ. (2) Max. Typ. (2) Max. Unit 235 190 125 125 225 180 mA COM'L S L 135 135 IND'L S L ____ ____ ____ ____ 135 235 ____ ____ COM'L S L 22 22 45 35 15 15 40 30 IND'L S L ____ ____ ____ ____ 22 45 ____ ____ COM'L S L 85 85 140 125 75 75 140 125 IND'L S L ____ ____ ____ ____ 85 140 ____ ____ mA mA mA Both Ports CEL and CER > VDD - 0.2V VIN > VDD - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > V DD - 0.2V COM'L S L 1.0 0.2 6 3 1.0 0.2 6 3 IND'L S L ____ ____ ____ ____ 0.2 6 ____ ____ CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) SEMR = SEML > V DD - 0.2V VIN > VDD - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 85 85 135 120 75 75 135 120 IND'L S L ____ ____ ____ ____ 85 135 ____ ____ mA 3603 tbl 10b NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VDD = 3.3V, TA = +25C, and are not production tested. IDD DC = 90mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to Chip Enable Truth Table. AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.3V GND to 3.0V 3.3V 590 3ns Max. DATAOUT BUSY INT 1.5V 1.5V 590 DATAOUT 435 30pF 435 5pF* Figures 1 and 2 3603 tbl 11 3603 drw 04 Figure 1. AC Output Test Load 7 Figure 2. Output Test Load (for t LZ, tHZ, tWZ, tOW) *Including scope and jig IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70V27X15 Com'l Only Symbol Parameter 70V27X20 Com'l & Ind 70V27X25 Com'l Only Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 20 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tABE Byte Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 12 ____ 15 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ 3 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 12 ____ 15 ns tPU Chip Enable to Power Up Time (2,5) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2,5) ____ 15 ____ 20 ____ 25 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 15 ____ 20 ____ 35 ns 3603 tbl 12a 70V27X35 Com'l & Ind Symbol Parameter 70V27X55 Com'l Only Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 ____ 55 ____ ns tAA Address Access Time ____ 35 ____ 55 ns tACE Chip Enable Access Time (3) ____ 35 ____ 55 ns tABE Byte Enable Access Time (3) ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns 3 ____ 3 ____ ns ____ 20 ____ 25 ns 0 ____ 0 ____ ns (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enable to Power Up Time (2,5) tPD Chip Disable to Power Down Time (2,5) ____ 45 ____ 50 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 15 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 45 ____ 65 ns NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 5. Refer to Chip Enable Truth Table. 8 3603 tbl 12b IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Waveform of Read Cycles(5) tRC ADDR (4) tAA tACE (4) (6) CE tAOE (4) OE tABE (4) UB, LB R/W tOH tLZ (1) (4) DATAOUT VALID DATA tHZ(2) BUSYOUT tBDD (3,4) 3603 drw 05 Timing of Power-Up Power-Down (6) CE tPU tPD ICC 50% 50% ISB 3603 drw 06 , NOTES: 1. Timing depends on which signal is asserted last: CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD . 5. SEM = VIH. 6. Refer to Chip Enable Truth Table. 9 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 70V27X15 Com'l Only Symbol Parameter 70V27X20 Com'l & Ind 70V27X25 Com'l Only Min. Max. Min. Max. Min. Max. Unit 15 ____ 20 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 12 ____ 15 ____ 20 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ 15 ____ ns ____ 10 ____ 10 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 10 ____ 10 ____ 15 ns 0 ____ 0 ____ 0 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ 5 ____ WRITE CYCLE tWC Write Cycle Time (1,2) tHZ Output High-Z Time tDH Data Hold Time tWZ Write Enable to Output in High-Z (1,2) tOW Output Active from End-of-Write tSWRD tSPS (4) (1,2,4) ns 3603 tbl 13a 70V27X35 Com'l & Ind Symbol Parameter 70V27X55 Com'l Only Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ ns tWP Write Pulse Width 25 ____ 40 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 20 ____ 30 ____ ns ____ 20 ____ 25 ns 0 ____ 0 ____ ns ____ 20 ____ 25 ns 0 ____ 0 ____ ns 5 ____ ns 5 ____ (1,2) tHZ Output High-Z Time tDH Data Hold Time tWZ Write Enable to Output in High-Z (1,2) tOW (1,2,4) (4) Output Active from End-of-Write tSWRD SEM Flag Write to Read Time 5 ____ tSPS SEM Flag Contention Window 5 ____ ns 3603 tbl 13b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire t EW time. Refer to Chip Enable Truth Table. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 10 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range (1,5,8) Timing Waveform of Write Cycle No. 1, R/W Controlled Timing tWC ADDRESS tHZ (7) OE tAW CE or SEM UB or LB (9,10) (9) tAS(6) tWP (2) tWR (3) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 3603 drw 07 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9,10) tAS(6) tWR (3) tEW(2) (9) UB or LB R/W tDW tDH DATAIN 3603 drw 08 NOTES: 1. R/W or CE or UB and LB must be HIGH during all address transitions. 2. A write occurs during the overlap (t EW or tWP ) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10. Refer to Chip Enable Truth Table. 11 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range (1) Timing Waveform of Semaphore Read after Write Timing, Either Side tSAA A0-A2 VALID ADDRESS tAW VALID ADDRESS tWR tACE tEW SEM I/O DATA OUT(2) VALID DATAIN VALID tAS tWP tOH tSOP tDW tDH R/W tSWRD tAOE OE Write Cycle Read Cycle 3603 drw 09 NOTES: 1. CE = V IH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table. 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15 ) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 3603 drw 10 NOTES: 1. DOR = D OL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. 12 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 70V27X15 Com'l Only Symbol Parameter 70V27X20 Com'l & Ind 70V27X25 Com'l Only Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 15 ____ 20 ____ 25 ns BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 25 ns tBAC BUSY Access Time from Chip Enable Low ____ 15 ____ 20 ____ 25 ns tBDC BUSY Disable Time from Chip Enable High ____ 15 ____ 20 ____ 25 ns 5 ____ 5 ____ 5 ____ ns ____ 17 ____ 35 ____ 35 ns 12 ____ 15 ____ 20 ____ ns 0 ____ 0 ____ 0 ____ ns 12 ____ 15 ____ 20 ____ ns ns BUSY TIMING (M/S=VIH) tBAA tBDA tAPS Arbitration Priority Set-up Time tBDD BUSY Disable to Valid Data tWH Write Hold After BUSY(5) (2) (3) BUSY TIMING (M/S=VIL ) tWB tWH BUSY Input to Write (4) (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 30 ____ 45 ____ 55 tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 30 ____ 50 ns 3603 tbl 14a 70V27X35 Com'l & Ind Symbol Parameter 70V27X55 Com'l Only Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 35 ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 35 ____ 45 ns tBAC BUSY Access Time from Chip Enable Low ____ 35 ____ 45 ns tBDC BUSY Disable Time from Chip Enable High ____ 35 ____ 45 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 40 ____ 50 ns tWH Write Hold After BUSY(5) 25 ____ 25 ____ ns BUSY TIMING (M/S=VIH) tBAA BUSY TIMING (M/S=VIL) tWB BUSY Input to Write (4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 25 ____ 25 ____ ns ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 65 ____ 85 tDDD Write Data Valid to Read Data Delay (1) ____ 60 ____ 80 ns 3603 tbl 14b NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 13 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range (2,5) (4) Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tDH VALID tAPS (1) ADDR"B" MATCH tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) 3603 drw 11 NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL (refer to Chip Enable Truth Table). 3. OE = VIL for the reading port. 4. If M/S = VIL (SLAVE), then BUSY is an input. Then for this example BUSY "A"= VIH and BUSY "B"= input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform Write with BUSY (M/S = VIL) tWP R/W"A" tWB (3) BUSY"B" tWH R/W"B" (1) (2) , 3603 drw 12 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the "Slave" version. 14 , IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range (1,3) Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 3603 drw 13 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) ADDRESS "N" ADDR"A" tAPS(2) MATCHING ADDRESS "N" ADDR"B" tBAA tBDA BUSY"B" 3603 drw 14 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 3. Refer to Chip Enable Truth Table. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 70V27X15 Com'l Only Symbol Parameter 70V27X20 Com'l & Ind 70V27X25 Com'l Only Min. Max. Min. Max. Min. Max. Unit ns INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 20 ____ 25 ns tINR Interrupt Reset Time ____ 25 ____ 20 ____ 35 ns 3603 tbl 15a 70V27X35 Com'l & Ind Symbol Parameter 70V27X55 Com'l Only Min. Max. Min. Max. Unit ns INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 30 ____ 40 ns tINR Interrupt Reset Time ____ 35 ____ 45 ns 3603 tbl 15b NOTES: 1. 'X' in part numbers indicates power rating (S or L). 15 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Waveform of Interrupt Timing Commercial and Industrial Temperature Range (1,5) tWC ADDR"A" INTERRUPT SET ADDRESS tAS (2) (3) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 3603 drw 15 tRC INTERRUPT CLEAR ADDRESS ADDR"B" tAS (2) (3) CE"B" OE"B" tINR (3) INT"B" 3603 drw 16 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 5. Refer to Chip Enable Truth Table. Truth Table IV -- Interrupt Flag(1,4) Left Port Right Port R/WL CEL OEL A14L-A0L INTL R/WR CER OER A14R-A0R INTR L L X 7FFF X X X X X L(2) (3) Function Set Right INTR Flag X X X X X X L L 7FFF H X X X X L(3) L L X 7FFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag X L L 7FFE H Reset Right INTR Flag 3603 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. Refer to Chip Enable Truth Table. 16 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range (4) Truth Table V -- Address BUSY Arbritration Inputs Outputs CEL CER A0L-A14L A0R-A14R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 3603 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V27 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. Refer to Chip Enable Truth Table. Truth Table VI -- Example of Semaphore Procurement Sequence(1,2) Functions D0 - D15 Left D0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V27. 2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0 - A 2. Functional Description The IDT70V27 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V27 has an automatic power down feature controlled by CE0 and CE1. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table IV. The left port clears the interrupt through access of address location 3603 tbl 18 7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table IV for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The BUSY pin can then be used to stall the access until the operation on 17 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Semaphores the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 70V27 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with BUSY Logic Master/Slave Arrays A15 CE0 MASTER Dual Port RAM BUSYL BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR CE1 MASTER Dual Port RAM CE1 SLAVE Dual Port RAM BUSYL BUSYL BUSYR BUSYR BUSYR , 3603 drw 17 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V27 RAMs. When expanding an IDT70V27 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT70V27 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part is used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. The IDT70V27 is a fast Dual-Port 32K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer's software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table II where CE and SEM are both HIGH. Systems which can best use the IDT70V27 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V27's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V27 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called "Token Passing Allocation." In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore's status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. 18 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM The semaphore flags are active low. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V27 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 - A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table VI). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side's output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as a one, a fact which the processor will verify by the subsequent read (see Table VI). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during the subsequent read. Had a sequence of READ/WRITE been Commercial and Industrial Temperature Range used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D SEMAPHORE READ Q SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ Figure 4. IDT70V27 Semaphore Logic 3603 drw 18 reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. This condition will continue until a one is written to the same semaphore request latch. Should the other side's semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side's request latch. The second side's flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. 19 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Ordering Information XXXXX A 999 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I(1) Commercial (0C to +70C) Industrial (-40C to +85C) G(2) Green BF PF 144-pin fpBGA (BF144-1) 100-pin TQFP (PN100-1) 15 20 25 35 55 Commercial Only Commercial & Industrial Commercial Only Commercial & Industrial Commercial Only S L Standard Power Low Power 70V27 512K (32K x 16) 3.3V Dual-Port RAM Speed in nanoseconds 3603drw19 NOTES: 1. Industrial temperature range is available on selected TQFP packages in low power. For other speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History 12/03/98: 04/02/99: 08/01/99: 08/30/99: 04/25/00: Initiated Document History Converted to new format Typographical and cosmetic changes Added fpBGA information Added 15ns and 20ns speed grades Updated DC Electrical Characteristics Added additional notes to pin configurations Page 5 Fixed typo in Table III Page 3 Changed package body height from 1.1mm to 1.4mm Page 1 Changed 660mW to 660W Replaced IDT logo Page 2 Made pin correction Changed 200mV to 0mV in notes Datasheet Document History continued on page 21 20 IDT 70V27S/L High-Speed 3.3V 32K x 16 Dual-Port Static RAM Commercial and Industrial Temperature Range Datasheet Document History(cont'd) 01/12/01: Page 1 Page 6 Page 7 & 8 08/02/04: 01/20/06: 09/21/06: 10/23/08: 09/27/12: Page 1, 4 & 20 Page 2 & 3 Page 2 - 7 Page 5 Page 6 Page 6 - 7 Page 7 Page 8, 10, 13 & 15 Page 6 - 8, 10, 13 & 15 Page 1 Page 20 Page 20 Page 20 Page 20 Page 2,17 & 19 Fixed page numbering; copyright Increased storage temperature parameter Clarified TA Parameter DC Electrical parameters-changed wording from "open" to "disabled" Removed Preliminary status Removed GU-108 package offering Added date revision for pin configurations Changed naming convention from VCC to VDD and from GND to VSS Updated Capacitance table Added I- temp for low power for 20ns speed to DC Electrical Characteristics Removed I-temp for 25ns & 55ns speeds and removed I-temp for 35ns standard power from DC Electrical Characteristics Changed Input Rise/Fall Times from 5ns to 3ns Removed I-temp for 25ns & 55ns speeds from AC Electrical Characteristics for Read, Write, Busy and Interrupt Removed I-temp note from all table footnotes Added green availability to features Added green indicator to ordering information Added die stepping indcator to ordering information Removed "IDT" from orderable part number Added T&R indicator to and removed W stepping from ordering information Corrected miscellaneous typo's CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 21 for Tech Support: 408-284-2794 DualPortHelp@idt.com