QS5805BTSOX - Integrated Device Technology, Inc.

QS5805/A/B

GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE

JULY 2000

1999 Integrated Device Technology, Inc. DSC-4579/-c

QS5805/A/B

INDUSTRIAL TEMPERATURE RANGE

GUARANTEED LOW SKEW

CMOS CLOCK

DRIVER/BUFFER

FUNCTIONAL BLOCK DIAGRAM

OEA

INA

INB

OA5 OA1

MON

OB5 OB1

OEB

DESCRIPTION

The QS5805 clock buffer/driver circuits can be used for clock buffering

schemes where low skew is a key parameter. This device offers two banks

of five non-inverting outputs. The QS5805 device provides low propagation

delay buffering with on-chip skew of 0.7ns for same-transition, same-bank

signals.

The QS5805 is characterized for operation at -40°C to +85°C.

FEATURES:

− 10 CMOS outputs

− Monitor output

− Rail-to-rail output voltage swing

− Input hysteresis for better noise margin

− Guaranteed low skew:

• 0.7ns output skew (same bank)

• 0.8ns output skew (different banks)

• 1.2ns part-to-part skew

− Std., A, and B speed grades

− Available in QSOP and SOIC packages

INDUSTRIAL TEMPERATURE RANGE

QS5805/A/B

GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

PIN CONFIGURATION

QSOP/ SOIC

TOP VIEW

OA1

OA2

OA3

GNDA

OA4

OA5

GNDQ

OEA

INA

OB1

OB2

OB3

GNDB

OB4

OB5

MON

OEB

INB

VCCA VCCB

SO20-2

SO20-8

ABSOLUTE MAXIMUM RATINGS (1)

Symbol Description Max. Unit

TERM(2) Supply Voltage to Ground – 0.5 to +7 V

DC Output Voltage VOUT – 0.5 to +7 V

TERM(3) DC Input Voltage VIN – 0.5 to +7 V

VAC AC Input Voltage (pulse width ≤20ns) -3 V

IOUT DC Output Current VIN < 0 -20 mA

DC Output Current Max. Sink Current/Pin 120 mA

TSTG Storage Temperature – 65 to +150 °C

TJJunction Temperature 150 °C

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other c onditions abov e those i ndicated in the ope rational s ections

of this specification is not implied. Exposure to absolute maximum

rating conditions f or ex tended periods may affect reliability.

2. Vcc Terminals.

3. Al l terminals except Vcc.

CAPACITANCE (TA = +25OC, f = 1.0MHz, VIN = 0V)

QSOP SOIC

Pins Typ. Max. (1) Typ. Max. (1) Unit

CIN 4657pF

OUT 7979pF

NOTE:

1. This parameter is guaranteed but not producti on tested.

PIN DESCRIPTION

Pin Names I/O Description

OEA, OEB I Output Enable Inputs

INA, INB I Clock Inputs

OAn, OBn O Clock Outputs

MON O Monitor Outputs (non-disable)

QS5805/A/B

GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 10%, VHC = VCC - 0.2V, VLC = 0.2V

Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit

VIH Input HIGH Voltage Guaranteed Logic HIGH for All Inputs 2 — — V

VIL Input LOW Voltage Guaranteed Logic LOW for All Inputs — — 0.8 V

VIC Clamp Diode Voltage (3) Vcc = Min., IIN = -18mA — –0.7 –1.2 V

VOH Output HIGH Voltage Vcc = Min., VIN = VIH or VIL, IOH = -300µAVHC Vcc —

Vcc = Min., VIN = VIH or VIL, IOH = -15mA 3.6 4.3 — V

Vcc = Min., VIN = VIH or VIL, IOH = -24mA 2.4 3.8 —

VOL Output LOW Voltage Vcc = Min., VIN = VIH or VIL, IOL = 300µA—GNDV

LC V

Vcc = Min., VIN = VIH or VIL, IOL = 64mA — 0.3 0.55

IIN Input Leakage Current Vcc = Max., VIN = Vcc or GND — — ±1 µA

IOZ Output Leakage Current Vcc = Max., VOUT = Vcc or GND — — ±1 µA

IOFF Input Power Off Leakage Vcc = 0V, VIN = Vcc or GND — — ±1 µA

IOS Short Circuit Current (2,3) Vcc = Max., VOUT = GND –60 ——mA

∆V

TInput Hysteresis VTLH - VTHL for All Inputs — 0.2 — V

NOTES:

1. Typical values are at V CC = 5.0V, TA = 25°C.

2. Not m ore than one output should be used t o test t hi s high power condi t i on. Duration is less than one second.

3. Guaranteed by design but not tested.

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions (1) Typ. (3) Max. Unit

ICC Quiescent Power Supply Current VCC = Max., VIN = GND or Vcc 0.005 0.5 mA

∆ICC Supply Current per Input HIGH VCC = Max., VIN = 3.4V 0.5 2.5 mA

ICCD Dynamic Power Supply Current per Output (2) VCC = Max., OEA = OEB = GND

Outputs Enabled, 50% duty cycle 0.1 0.2 mA/MHz

ICTotal Supply Current Examples (2,4) VCC = Max.,

OEA = OEB = GND VIN = GND or Vcc 8.5 15.5

50% duty cycle, fI = 10MHz

Five outputs toggling VIN = GND or 3.4V 9 16.8 mA

VCC = Max.,

OEA = OEB = GND VIN = GND or Vcc 5 8.8

50% duty cycle, fI = 2.5MHz

All outputs toggling VIN = GND or 3.4V 6 11.3

NOTES:

1. For conditi ons shown as M i n. or Max. , use the appropri ate values specif i ed under DC E l ectric al Characteris tics .

2. Guaranteed by des i gn but not tested. CL = 0pF.

3. Typical values are f or reference only . Conditions are VCC = 5.0V , TA = 25°C.

4. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO)

where:

DH = Input Dut y Cycle

NT = Number of TTL HIGH inputs at DH

fO = Output Frequency

NO = Number of output s at f O

INDUSTRIAL TEMPERATURE RANGE

QS5805/A/B

GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

SKEW CHARACTERISTICS OVER OPERATING RANGE

TA = -40°C to +85°C, VCC = 5.0V ± 10%

CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted. QS5805 QS5805A QS5805B

Symbol Parameter (1) Min. Max. Min. Max. Min. Max. Unit

tSK(01) Skew between all outputs, same transition, same bank — 0.7 — 0.7 — 0.7 ns

tSK(02) Skew between outputs of all banks, same transition — 0.8 — 0.8 — 0.8 ns

tSK(P) Pulse Skew; skew between opposite transitions of the same

output (tPHL - tPLH)—1—1—1

tSK(T) Part-to-part skew (2) — 1.5 — 1.5 — 1.2 ns

NOTES:

1. Skew parameters are guaranteed across temperat ure range, but not t ested. Skew paramet ers are measured at 0.5Vcc .

2. tSK(T) onl y applies to devic es of the same trans i tion, part t ype, tem perature, power suppl y volt age, loading, package, and speed grade.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

TA = -40°C to +85°C, VCC = 5.0V ± 10%

CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted. QS5805 QS5805A QS5805B

Symbol Parameter (1) Min. Max. Min. Max. Min. Max. Unit

tPLH

tPHL Propagation Delay (2)

INA to OAn, INB to OBn 1.5 5.6 1.5 5.3 1.5 5 ns

tPZL

tPZH Output Enable Time 1.5 8 1.5 8 1.5 7 ns

tPLZ

tPHZ Output Disable Time 1.5 7 1.5 7 1.5 6 ns

tROutput Rise Time 0.8V to 2V (3) — 1.5 — 1.5 — 1.5 ns

0.2Vcc to 0.8Vcc — 3 — 3 — 3 ns

tFOutput Fall Time 0.8V to 2V (3) — 1.5 — 1.5 — 1.5 ns

0.2Vcc to 0.8Vcc — 3 — 3 — 3 ns

NOTES:

1. Mi ni m um s guaranteed but not production t ested. Ti m i ng param eters are meas ured at 0.5Vcc.

2. The propagati on del ay other range indicated by M i n. and Max. specif i cations results from proces s and environmental vari abl e s. These propagation

delays do not imply l i m i t skew.

3. This param eter is guarant eed but not production tes t ed.

QS5805/A/B

GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE

Pulse

Generator 500Ω

500Ω

VCC

VOUT

VIN

DUT

50Ω50pF

7.0 V

Parameter

Tested Switch

Position

A ll Others Closed

Open

tPLZ, tPZL

CONTROL

INPUT

ENABLE DISABLE 3V

1.5V

OUTPUT

NORMALLY

LOW SWITCH

CLOSED 0.3V

0.3V

INPUT

OUPUT 1

1.5V

OUPUT 2

INPUT

OUPUT

1.5V

0.5Vcc

2.0V

0.8V

INPUT

PART 1 OUTPUT

1.5V

PART 2 OUTPUT

INPUT

OUPUT A

tPLHA

1.5V

OUPUT B

INPUT

OUPUT

tPLH tPHL

1.5V

VOH

VOL

tSK(p) = tPHL - tPLH

tSK(02) = tPLHB - tPLHA or tPHLB - tPHLA

P ulse genera tor f or all pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

VOH

VOL

VOH

VOL

tPHLA

tSK(02) tSK(02)

tPLHB tPHLB

VOH

VOL

VOH

VOL

tSK(01) tSK(01)

tSK(01) = tPLH2 - tPLH1 or t PHL2 - tPHL1

tPLH1 tPHL1

tPLH2 tPHL2

VOH

VOL

VOH

VOL

tPLH tPHL

tRtF

OUTPUT

NORMALLY

HIGH

tPZL tPLZ

tPHZ

tPZH

SWITCH

OPEN

tPLH1 tPHL1

tSK(t) tSK(t)

tPLH2 tPHL2

tSK(t) = tPLH2 - tPLH1 or tPHL2 - tPHL1

VOH

VOL

VOH

0.5Vcc

TEST CIRCUITS AND WAVEFORMS

PROPAGATION DELAY PULSE SKEW — tSK(P)

OUTPUT SKEW (SAME BANK) — tSK(O1) OUPUT SKEW (DIFFERENT BANKS) — tSK(O2)

ENABLE AND DISABLE TIMES PART-TO-PART SKEW — tSK(T)

INDUSTRIAL TEMPERATURE RANGE

QS5805/A/B

GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES:

2975 Stender Way 800-345-7015 or 408-727-6116

Santa Clara, CA 95054 fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.

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D evice T ype

Package

5805

5805A

5805B

Qua rter Size Small Outline Pacakge (SO 20-8)

Sm all O utline IC (SO20-2)

Gua ranteed Low Skew CM O S Clock Driver/Buffer