eee rere eer DATA SIA 74LV86 = = | Quad 2-input EXCLUSIVE-OR gate Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook Philips Semiconductors 1998 Apr 20 PHILIPSPhilips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 FEATURES DESCRIPTION @ Wide Operating voltage: 1.0 to-5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Voc = 2.7 V and Veco = 3.6 V Typical Vo_p (output ground bounce) < 0.8 V at Voc = 3.3 V, Tamb = 25C Typical Vowy (output Voy undershoot) > 2 V at Voc = 3.3 V, Tamp = 26C Output capability: standard Iec category: SSI The 74LV86 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT8E. The 74LV86 provides the 2-input EXCLUSIVE-OR function. QUICK REFERENCE DATA GND = 0 V; Tamp = 25C; t, = $2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay C, = 15 pF; tPHutPLH nA, nB to nY Voc =3.3V " ns Cc, input capacitance 3.5 pF Cpp Power dissipation capacitance per gate | V; = GND to Vcc! 30 pF NOTE: 1. Cpp is used to determine the dynamic power dissipation (Pp in pW) Pp = Cpp x Voc? x fj + 3 (CL x Voc? x fy) where: f, = input frequency in MHz; C_ = output load capacitance in pF; fp = output frequency in MHz: Voc = supply voltage in V; (Cy x Voc? f.) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA |. NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL ~-40C to +125C 74LV86 N 74186 N SOT27-1 14-Pin Plastic SO ~-40C to +125C 74LV86 D 74Lve6 D SOT108-1 14-Pin Plastic SSOP Type Il 40C to +125C 74LV86 DB 74LN86 DB SOT337-1 14-Pin Plastic TSSOP Type | ~40C to +125C 74LV86 PW 74LV86PW DH SOT402-1 PIN CONFIGURATION LOGIC SYMBOL (IEEE/AEC) 1 T 1A | 1 aly 3 Cc] U Pa%c 8 [2] a] 48 4 = vo fi2 | 4A Tat 6 2a [4 | at} ay 20 [5] Fo] 28 > ay [8 | [9 ]3a 19 - GND [7 | 8 | 3y 12 a svooss1 13 Lo sv00479 1998 Apr 20 2 853-1892 19255Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 PIN DESCRIPTION FUNCTION TABLE PIN INPUTS OUTPUTS NUMBER SYMBOL FUNCTION <= = n 1,4,9,12 | 1A-4A | Data inputs L L 7 2,5, 10,13 | 1B-4B | Data inputs L H H 3,6,8,11 | 1-4Y |} Data outputs H L H 7 GND Ground (0-V) H H L 14 Voc Positive supply voltage NOTES: H =HIGH voltage level LOGIC SYMBOL L =LOW voltage level etsy) >t 3 LOGIC DIAGRAM (ONE GATE) 4_ [2A 9 Dy S00480 vous RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT Vec DC supply voltage See Note 1 1.0 3.3 5.5 v vi Input voltage 0 Voc v Vo Output voltage 0 Voc Vv Tamb Operating ambient temperature range in free air See pe ana ac 40 S C Voc = 1.0V to 2.0 V 00 th ty input rise and fall times i - a e eo y +00 ns/V Veo = 3.6V 05.5 V 50 NOTE: 1. The LV is guaranteed to function down to Voc = 1.0V (input levels GND or Vcc); DC characteristics are guaranteed from Voc = 1.2V to Vocg = 5.5 V. ABSOLUTE MAXIMUM RATINGS? 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referanced to GND {ground = OV). SYMBOL PARAMETER CONDITIONS RATING UNIT Vec DC supply voltage ~0.5 to +7.0 v +h DC. input diode current V; <-05 or V; > Veo + 0.5V 20 mA tlox DC output diode current Vo < ~-0.5 or Vo > Voc + 0.5V 50 mA DC output source or sink current tlo standard outputs ~0.5V < Vo < Voc + 0.5V 25 mA DC Vec or GND current for types with * kano. standard outputs 50 mA cc Tstg Storage temperature range -65 to +150 C Power dissipation per package for temperature range: 40 to +125C P. plastic DIL above +70C derate linearly with 12 mMW/K 750 mw TOT - plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 plastic shrink mini-pack (SSOP and TSSOP) | above +60C derate linearly with 5.5 mW/K 400 NOTES: . 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other Conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions tor extended periods may affect device reliabitity. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Anr 20Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS ~40C to +85C -40C to +125C UNIT MIN TYP? MAX MIN MAX Veco =#12V 0.9 0.9 Vv HIGH level Input = | Voc =2.0V 1.4 1.4 1H | volta V voltage Voc =2.7 t03.6V 2.0 2.0 Veco = 4.5 to 5.5 V 0.7 *Voc 0.7 * Voc Voec=l2v 03 03 Vv LOW level Input Veco =2.0V 0.6 0.6 tL ita V voltage Voc =2.7t036V 08 08 Veco = 4.5 to 5.5 0.3 * Voc 0.3 * Veg Voc = 1.2. V; Vi = yy or Vig. lo = 100pA 1.2 Voc = 2.0 V; V, = Viq oF Vit. Io = 100HA i) 2.0 1.8 HIGH level output 7 " Vou voltage: all outputs Voc = 2.7. Vi V) = Vin. or Viz: lo = 100pA 2.5 2.7 2.5 v Voc = 3.0 V; V = Vig or Vi. Ig = 100nA 2.8 3.0 2.8 Voc = 4.5 Vi V) = Vin-or Vit. -lp = 100HA 4.3 45 43 volage output 1 Vg = 3.0.V: Vj = Vin OF Viz;lo = mA 2.40 | 2.82 2.20 Vou | STANDARD V outputs Veco = 4.5 Vi Vy = Vip or Vip. lo = 12MA 3.60 4.20 3.50 Voc = 1.2 Vi Vi. = Vig or Vit: lo = 100pA 0 Voc = 2.0 V; Vj = Vin OF Vit. Io = 100pA 6 0.2 0.2 Vor Voltage: all ute Veo =2.7 VV) = Vin oF Vip Ip = 100pA 0 02 02 v Vec =3.0V; vi = Vi or Vit; lo = 100nA 0 0.2 0.2 Veco =456VjV)= Viy or Vie; lo = 100nA 0 0.2 0.2 soe oe output | Veg = 3.0 V: V) = Vi OF Viz: lo = MA 0.25 | 0.40 0.50 Vo. | STANDARD v outputs Veco = 4.8 Vi V) = Vin or Viz. lo = 12mMA 0.35 0.55 0.65 | Input leakage Voc = 5.5 V; Vj = Voc or GND 1.0 10 | pA loo | Quiescent supply | Vcc = 5.5V; Vi = Voc or GND; Ip =0 20.0 40 pA Additional Alec quiescent supply Voc = 2.7 V to 3.6 V; Vi = Voc -0.6 V 500 850 pA current per input NOTE: 1. All typical values are measured at Tamp = 25C. AC CHARACTERISTICS GND = OV; t, = 4 < 2.5ns; C, = 50pF; Ry = 1KQ LIMITS CONDITION SYMBOL PARAMETER WAVEFORM ~40 to +85 C 40 to +125 C UNIT Voc(V) MIN | TYP? | MAX | MIN | MAX 1.2 70 2.0 24 32 41 tpuutern | ppchagation delay Figure 1 27 18 24 30 ns 3.01036 134 19 24 4.5to5.5 16 20 NOTES: 1. Unless otherwise stated, ail typical values are measured at Tamp = 26C. 2. Typical values are measured at Voc = 3.3 V. 1998 Apr 20Philips Semiconductors. Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 AC WAVEFORMS TEST CIRCUIT Vu = 1.5V at Vec 2 2.7 V and $3.6 V; Vt = 0.5 x Voc at Voc < 2.7 V and 2 4.5 V; Vor Vox and Voy are the typical output voltage drop that occur with the output load. vi Vo vy PULSE 0A, 1B INPUT GENERATOR on Ar T CL SOpF Fy = 1k GND .--- L T Vou oo . - - - Test Circuit for Outputs ny OUTPUT y DEFINITIONS OL Fy = Load resistor SV00477 C,, = Load capacitance includes jig and probe capacitiance Figure 1. input (n A, nB) to output (nY) tion deta ys Ry = Termination resistance should ba aqual to Zour of pulse generators. and the output transition times. TEST Vec vi terytPHE <2.7V Voc 2.7-3.6V 2.7 1998 Apr 20 245V Veco Svoo0s02 Figure 2, Load circuitry for switching times.Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 Oo D "| Me & a La} c i | a A 4 i -_I i i i i ! | i | J y c My 0 5 10 mm Cael! scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A A A a UNIT | max. | min. | max b by c po | eM] e ey L Me | My w nex. 1.73 | 053 | 0.36 | 19.50 | 6.48 3.60 | 825 | 10.0 mmo | 42 | 051 | 32 | 443 | o38-| 023 | 1855] 620 | 254 | 782 | 305 | 7a] a3 | 0754 | 22 . 0.068 | 0.021 | 0.014 | 0.77 | 0.26 0.14 | 032 | 0.39 inches | 0.17 | 0.020 | 9.43 | oo44 | 0015 | 0009 | 0.73 | 024 | 1 | 939 | or | O37 | 033 | 201 | 9987 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE soT27-1 050G04 MO-001AA E60 cane 1998 Apr 20Philips Semiconductors Quad 2-input EXCLUSIVE-OR gate Product specification 74LV86 $014: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 pin 1 index ! Mt J. 6 t Lo Oe Fo cc, 2 [I | Leroy Pp 6 25 &Smm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT ma. Ai | Az | As | bp | c | OM | eM) e | He | EL | tp} @ tv | wl y | 2] 6 0.25 | 1.45 0.49 | 0.25 | 8751 40 62 10 | 07 07 mm 1 175 | 540 | 1.25 | 75 | ose | o19 | ass] a9 | 1?) 5a} 3) o4 | os | 975) 925] 91 | O35 | go 0.010 | 0.057 0.019 10.0100] 0.35 | 0.16 0.244 0.039 | 0.028 0.028| 0 inches | 0.069 | 9 on4 | 0.049 | 9-91 | 0.014 Jo.0078| 0.94 | 0.15 | 291 o.228 | 941} oo1e | 0.024] 99% | 0.01 | 0.0041 9 415 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION ee WEDEG pias PROJECTION SOT108-1 o76E06S MS-012AB E+@ or one 1998 Apr 20Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 71 al PU td Oly] ey eZ 4 6 a. i F i | | 0 25 5mm ll inches scale DIMENSIONS (mm are the original dimensions) UNIT | ot Ay | Az | As | be | | OM] eM) e fue | ef ue} @ tv | wl y | 2m] oe 6.21 | 1.80 0.38 | 020]; 64 | 54 79 1.03 | O9 1.4 8 mm | 20 | o05 | 165 | %25 | 025] 009] 60 | 52 | 28) 76 | 125] oes | o7 | OF | 919] O71 | Og | p92 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES ours Sunerean, | sesue pare IEC JEDEC EAL SOT337-1 MO-150AB E+ sen 1998 Apr 20 8Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 TSSOP14: plastic thin shrink smail outline package; 14 leads; body width 4.4 mm SOT402-1 D j 1 ily] . | Zz 14 8 { | ees ' A2 (Ay) 4 - -+-- r | Ay ~) A pin 1 index | on | | r79 $ _ Lo] 4 }e | -] 1 7 Leroy [e] Pp G 25 Smm scale DIMENSIONS (mm are the original dimensions) unt | ee | Ar | Ae | As | bp | ce fom fe@) e [ref cfu] atvi wi y | zm] o 0.15 | 0.95 0.30} 0.2 | 54 1 45 6.6 0.75 | 0.4 0.72 | 8 ma 11-19) oo5 | 080 | 22] 0191 01 | 49 | 43 | 2] 62 ft J osof o3 | %2 12 | Ot | gag] oe Notes 1. Plastic or metal protrusions of 0.45 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION lec JEDEC EIAJ PROJECTION 4-07-42 soT402-1 MO-153 E+ 6 oe 0404 1998 Apr 20 9Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74LV86 Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without notice. Preliminary Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product. {t] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any ot these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors Copyright Philips Electronics:North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. Box 3409 Sunnyvale, California 94088-3409 print code Date of release: 10-98 Telephone 800-234-7381 Document order number: 9397-750-04415 PHILIPS Philips Semiconductors