Wireless Components
FM Car Radi o IC with PLL
TUA 4401K V 2.1
Specif ication 17.02.00
DS 1
Edition 03.99
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Revision History: Current Version: 02.00
Previous Version:Data Sheet 23.09.1999
Page
(in previous
Version)
Page
(in current
Version)
Subjects (ma jor cha n g es si nce last rev is ion )
3-7 3-7 Functional description pin 41 corrected
3-11 3-11 Functional description pin 41 corrected
5-3 5-3 Sequence tests 310 to 317 changed (Item)
5-5 5-5 Values attack current changed
5-5 5-5 Values recovery current changed
5-5 5-5 Values detector characteristic changed
Productinfo
Product Info
Wireless Components
Specification, 17.02.00
Package
TUA 4401K
Productinfo
General Description The TUA 4401K is the first Infineon
Carradio IC using BICMOS technol-
ogy.
The combination of an analog FM
receiver circuit and a digital PLL syn-
thesi zer on th e same chip reduce s the
ov er all pin count in comparison to two
separate IC’s and in addition the
number of necessary external compo-
nents. This gives the flexibility both f or
high performance and low cost appli-
cations.
The recommended applications for this
device are FM only carradios and back-
ground receivers, capable for all world
standards.
Features
Double balanced RF mixer with low
noise figure, high IP3 and wide
dynamic range
Strictly symmetrical RF circuitry
IF amplifier with adj ustabl e gai n
Double frequency 1st LO option
7 stage limiter amplifier with dB
linear fieldstrength output
Low distortion coincidence
demodulator
Multipath detector with analo g
output
CMOS PLL-Synthesizer
Resolution between 100 kHz and
6.25kHz
Search tuning stop with IF counter
and Fieldstrength/Multipath
evaluation
ADC’s for fieldstr. and multipath
detector
I2C Bus operation
Applications
FM only car radio receiver, back-
ground receiver
Ordering Information
Type Ordering Code Package
TUA 4401K MQFP-44
1Table of Contents
1 Table of Contents 1-1
2 Product Description 2-1
2.1 Gener al Descri pti on 2-2
2.2 Applications 2-3
2.3 Features 2-3
2.4 Package Outlines 2-4
3 Functional Description 3-1
3.1 Pin Configuration 3-2
3.2 Block Diagram 3-12
3.3 Fun ct ion al Bl oc k D iag ra m 3-13
3.4 Circuit Description 3-14
4 Applications 4-1
4.1 Application and Circuits 4-2
5 Reference 5-1
5.1 Electrical Data 5-2
5.1.1 Absolute Maximum Range 5-2
5.1.2 Operating Range 5-2
5.1.3 AC/DC Characteristics 5-3
5.2 Phase detector outputs 5-7
5.3 Bus Interface 5-8
5.4 I2C Bus Timing 5-13
2Product Description
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Contents of this Chapter
Product Description
2 - 2
TUA 4401K
Wireless Components
Specification, 17.02.00
2.1 General Description
The TUA 4401K is the first Infineon Carradio IC using BICMOS technology.
The combination of an analog FM receiver circuit and a digital PLL synthesizer
on the same chip reduces the over all pin count in comparison to two separate
IC’s and in addition the number of necessary external components. This gives
the flexibility both for high performance and low cost applications.
The recommended applications for this device are FM only carradios and back-
ground receivers, capable for all world standards.
TUA 4401K feature s:
Frontend
High level, high impedance mixer input with improved dynamic range
High input / output 3rd order intercept point
Integrated prestage AGC generation and control for PIN diodes and MOS
tetrode
Bus controlled AGC threshold
2 pin 1st local oscillator with improved low phase noise, internally coupled to
PLL. Double frequency operation possible
Strictly symmetrical RF parts
PLL with fast acquisition mode
Resolution 100 kHz, 50 kHz, 25 kHz, 12,5 kHz, 10 kHz and 6.25 kHz
High running (61.5 MHz) crystal oscillator to avoid interference with bus
controlled adjustment
IF amplification, demodulation and STS
Low noise IF amplifier
Gain adjust with DC control voltage or serial bus possible
7 stage IF limiter with extended fieldstrength range suitable for the IF fre-
quency range of 10.7 MHz ... 21.4 MHz
Fieldstrength DC output and ADC output available
Low distortion coincidence demodulator (using short loop AFC principle)
with MPX outpu t
Wideband multipath detector with analog output and ADC output
IF counter for search tuning stop with selectable IF center frequency,
window width and programmable thresholds for fieldstrength and multipath
evaluation
STS informations -in window-,-below-,-beyond- available
Product Description
2 - 3
TUA 4401K
Wireless Components
Specification, 17.02.00
I2C Bus
I2C bus (2 wire, fast mode device with 400 kbit/s) operation possible
Bus interface with low threshold voltage Schmitt Trigger inputs for interfac-
ing 3V or 5V microp ro ce ss or s
2.2 Applications
FM only car radio receiver, background receiver
2.3 Features
Double balanced RF mixer with low noise figure, high IP3 and wide dynamic
range
Strictly symmetrical RF circuitry
Double frequency 1st LO option
IF amplifier with adj ustabl e gai n
7 stage limiter amplifier with dB linear fieldstrength output
Low distortion coincidence demodulator
Multipath detector with analog output
CMOS PLL-Synthesizer
Resolution between 100 kHz and 6.25kHz
Search tuning stop with IF counter and
Fieldstrength/Multipath evaluation
ADC’s for fieldstr. and multipath detector
I2C Bus operation
Product Description
2 - 4
TUA 4401K
Wireless Components
Specification, 17.02.00
2.4 Package Outlines
MQFP 44
3Functional Description
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Contents of this Chapter
Functional Description
3 - 2
TUA 4401K
Wireless Components
Specification, 17.02.00
3.1 Pin Configuration
Pin_config.wmf
Figure 3-1 IC Pin Configur atio n
FS_ADC
34
35
36
37
38
123456789
39
40
41
42
43
44 10 11
22
21
20
19
18
17
16
15
14
13
12
33 32 31 30 29 28 27 26 25 24 23
MQFP44
MPA_ADC
Station_Detect
SCL
SDA
VREFD5V
VREFD3V
XTAL_DIV6
PORT_2
QUARTZ1
QUARTZ2
VCCIF
IFAMPC
IFOUTFM
IFIN
IFINFM
GNDIF1
VREFRF
IF1
IF2
AGCOUT_P
FM2
FM1
PRE_CAP
VCCRF
OSC2
OSC1
GNDRF
PD_0
PDA
PORT_1
GNDD
VCCD
FMIFIN
FMIBIAS
GNDIF2
MPXOUT
FSOUT
MPA_IN
MPACAP
MPA_OUT
DEMAFC
PH02
PH01
Table 3-1 Pin Configuration
Pin No. Symbol Equivalent I/O-Schematic Function
1
2
FS_ADC
MPA_ADC
1:
ADC input fieldstrength
2:
ADC input multipath
detector
5 pF
GNDD
+5V
+5V
1
2
Functional Description
3 - 3
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
3Station_Detect 3:
IF counter output sta tio n
detector
4SCL 4:
I2C bus cloc k inp ut
5SDA 5:
I2C bus data in/output
6VREFD5V 6:
Reference voltage digital
section (5V)
7VREFD3V 7:
Reference voltage digital
section (3V)
8XTAL_DIV6 8:
Crystal oscillator auxil-
iary output (10.25 MHz)
+5V
GNDD
3
+5V
GNDD
+ 5V
4330
GNDD
+ 5V
5330
V+ 3V
GNDD
2k
200fF
8
Functional Description
3 - 4
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
9PORT_2 9:
Switch port ou tput 2(open
drain)
10
11
QUARTZ1
QUARTZ2
10:
Reference osc illator inp ut
/ Crystal
11:
Reference osc illator inp ut
/ Crystal
12 VCCD 12:
Positive power supply
voltage for serial bus and
synthesizer
13 GNDD 13:
Ground for ser ial b us and
synthesizer
14 PORT_1 14:
Swi tch port output 1
(open drain)
+ 5 V
GNDD
9
330
2,5 k
5k
5k
10
11
+ V
+ 5 V
GNDD
14
330
Functional Description
3 - 5
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
15 PDA 15:
PLL phasedetector output
analog (Tuningvoltage)
16 PD_0
16:
PLL chargepump output
(Phase detector tristate
chargepump output)
17 GNDRF 17:
Ground for RF part
GNDD
PD
VCCD
+5 V
15
3k
12
I
PDA
PD +5 V
+5 V
+5 V
16
NC
Functional Description
3 - 6
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
18
19
OSC1
OSC2
18:
1st local oscillator circuit
19:
1st local oscillator circuit
20 VCCRF 20:
Positive power supply
voltage for RF part
21 PRE_CAP
21:
Prestage AGC time con-
stant capa citor; o utput fo r
MOS tetrode gate 2
+ V
18
+ V
19
2,2V
+ V
21
6,4V
Functional Description
3 - 7
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
22
23
FM1
FM2
22:
FM 1st mixer symmetrical
input
23:
FM 1st mixer symmetrical
input
24 AGCOUT_P
24:
Prestage AGC current
output for PIN diode nor-
mal polarity
+ V
2,6 V
2,0k
2,0k
25 26
22
23
24 +V
Functional Description
3 - 8
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
25
26
IF2
IF1
25:
1st mixer output (open
collector)
26:
1st mixer output (open
collector)
27 VREFRF 27:
Reference voltage RF
section (4.8V)
28 GNDIF1 28:
Ground for IF amplifier
29
30
IFINFM
IFIN
29:
10.7 MHz IF amplifier
input
30:
10.7 MHz IF amplifier
operation point
+ V
2,6 V
2,0k
2,0k
25 26
22
23
30
29
+ V
17k
17k
330
3,8V
Functional Description
3 - 9
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
31 IFOUTFM 31:
10.7 MHz IF am pl ifie r out -
put
32 IFAMPC 32:
10.7 MHz IF amplifier DC
gain control adjust block-
ing capacitor
33 VCCIF 33:
Positive power supply
voltage for IF amplifier
34
35
FMIFIN
FMIFBIAS
34:
FM limiter input
35:
FM limiter input bias
decoupli ng cap ac itor
36 GNDIF2 36:
Ground for limiter ampli-
fier
+ V
330
31
+ V
32
8k
+ V
33033k
33k
35
34
5,5 V
Functional Description
3 - 10
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
37 MPXOUT 37:
FM MPX signal output
38 FSOUT 38:
Fieldstrength output
39 MPA_IN 39:
Multipath detector input
37
+V
34k 66k
+ V + V
38 NC
+ V
86k
39
Functional Description
3 - 11
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 3-1 Pin Configuration (continued)
Pin No. Symbol Equivalent I/O-Schematic Function
40 MPACAP 40:
Multipath detector rectifier
capacitor
41 MPA_OUT 41:
Multipath detector output
42 DEMAFC 42:
Demodulator AFC block-
ing capacitor
43
44
PH02
PH01
43:
Demodulator circuit
44:
Demodulator circuit
+ V
40
+ V
41
+ V
76k
3,5V
42
15p
+ V
4,8V
15k
43/44
Functional Description
3 - 12
TUA 4401K
Wireless Components
Specification, 17.02.00
34
35
36
37
38
123456
FMIFIN
FMIFBIAS
GNDIF2
MPXOUT
FSOUT
VCCIF
IFAMPC
IFOUTFM
IFIN
IFINFM
GNDIF1
FS_ADC
MPA_ADC
Station_Detect
SCL
SDA
VREFD5V
VREFRF
IF1
IF2
MPA_AIN
MPACAP
MPA_OUT
VREFD3V
XTAL_DIV6
PORT_2
789
39
40
41
DEMAFC
PH02
PH01
AGC_OUT_P
FM2
QUARTZ1
QUARTZ2
42
43
44 10 11
22
21
20
19
18
FM1
PRE_CAP
VCCRF
OSC2
OSC1
GNDRF
PD_0
PDA
17
16
15
PORT_1
GNDD
VCCD
14
13
12
33 32 31 30 29 28 27 26 25 24 23
IF A MPVref
FM Lim / Dem /
F S / MP -De t M ixer 1st LO
Preset A GC
PLL Synth.
Serial Bus
IF counter
ADC/DAC
Cryst
OSC
3.2 Block Diagram
Funct_block.wmf
Figure 3-2 Main Bloc k Diagram
Functional Description
3 - 13
TUA 4401K
Wireless Components
Specification, 17.02.00
3.3 Functional Block Diagr am
Funct_block.wmf
Figure 3-3 Functional Block Diagram
Gate2 FM
Pin Diode 1 prest
AGC
FM
OSC
Buffe r /
Div 2
OSC
1. LO
V
REF
RF
N counter
SOCCAR
Bus Charge
pump
PD
Port
R counter
adj crystal div/6 Clock
counter IF
counter 7 Bit ADC
Gate
time
counter
MP
det.
AfC
loop
Dem
FM IF
limiter
Field
strength
V
Ref
IF
IF amp
gain adj.
4 bit DAC
IF gain
2 bit DAC
Prest. AGC thresh.
21
24
22
23
25
26
20
18
19
27
17
54 15 16 14 9 10 11 8 12 67 3
1
2
38
41
40
39
4243
44
35
34
31
3633
283230
29
Data Bus
10.7 MHz
CER Filter
10.7 MHz
CER Filter
10.7 MHz
CER Filter
or Amp
External
MOS
tetrode
V
CC IF
MP det in
MPX out
MP det ou
t
Field-
strength
Station_Detect
V
CCD
P2
P1
SDA
SCL
V
CC RF
13
37
Functional Description
3 - 14
TUA 4401K
Wireless Components
Specification, 17.02.00
3.4 Circuit Description
The TUA 4401K is a one chip FM car radio system consisting of RF frontend,
gain adjustable IF amplifier, FM-IF limiter amplifier, demodulator, PLL synthe-
sizer, IF counter for STS and ADC’s for fieldstrength and multipath detector.
The serial bus is a I2C type.
1. FM frontend
The frontend consists of a two pin varactor tuned oscillator, a double bal-
anced mixer and a prestage AGC control circuit. The mixer has an improved
intermodulation behaviour and converts the RF signal to the 10,7 MHz IF
range . Two inputs allow both symmetrical and unsymmetrical operation.
The integrated AGC stage for prestage control drives MOSFETS as well as
PIN diodes a with cur- rent driver. The AGC threshold can be set with a serial
bus controlled 2 Bit DAC. For background receiver application the oscillator
is able run at double frequency, a subsequent frequency divider by 2 is acti-
vated by serial bus to provide the correct mixer frequency.
2. FM IF amplifier
After the mixer an IF amplifier is present for IF post amplification. Input and
output impedance are both 330 Ohms for matching with ceramic filters. For
adjusting the over all gain the IF amplifier gain can be adjusted with a serial
bus controlled 4 Bit DAC.
3. FM limiter and demodulator
The FM IF amplifier includes a seven stage capacitive coupled limiter ampli-
fier and a fieldstrength generator with high linearity and increased dynamic
range. The coincidence demodulator has an additional AFC short loop cir-
cuit with integrated varactor diode in parallel to the external tank circuit to
impro ve the distorti on bahav iou r in case of detun ing .
4. Multipath detector
A wideband multipath detector with analog output is available.
5. A/D converter for fieldstrength and multipath detector
The 7 bit A/D converter has two input channels and works as successive
approximation converter. The conversion time for both input signals is t = 32
µs. The 7-bit digital-words from both channels (14 bit) are read out together
via bus into two bytes with the read subaddress 82H. The input voltage
range for both channels is 0...VREFD5V.
6. IF counter and multipath/fieldstrength evaluation for STS
FM center frequencies ar available in two ranges set by bit D7 in subaddress
05H. For D7=1 the range of centerfrequency is 20.800 MHz...22.3875 MHz
in 128 steps (12.5 kHz per step). For D7=0 the range of centerfrequency is
10.400 MHz...11.1937 MHz in 128 steps (6.25 kHz per step).
The gate time is adjustable in 8 steps from 320us...40.96ms and the toler-
ance of the accepted count value, the window is adjustable in 5 steps from
+/- (6.25kHz...100kHz) for D7=0 in sub-address 05H and
Functional Description
3 - 15
TUA 4401K
Wireless Components
Specification, 17.02.00
+/- (12.5 kHz...200 kHz) for D7=1 in subaddress 05H. The results IF_CENT
and IF_WINDOW are read out via bus (read-subaddress 82H&83H) or pin
Station_Detect.
If the IF frequency is into the preselected window, Station_Detect goes from
high to low level. If the IF frequency is outside the pr eselected window,
Station_Detect is high. The bit IF_WINDOW is a hint IF-frequency that is to
low (IF_WINDOW=high) or is to high (IF_WINDOW=low).
In addition to the frequency measurement, thresholds for multipath and field-
strength voltages can be programmed via bus (subaddress 0BH).
Station_Detect will only go to low level in case of field-strength and multipath
voltages are beyond the thresholds and the frequency is inside the window.
When setting the thresholds to zero multipath and fieldstrength evaluation is
disabled.
7. Crystal oscill ator
A master crystal oscillator provides all necessary clock frequencies for the
whole IC. A 61.5 MHz crystal is used in 3rd harmonic mode.
The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A
converter.
The crystal frequency is used as reference frequency for the PLL oscillator
and IF counter. It is also used as clock for the ADC’s. Finally the crystal fre-
quency divided by 6 (10.25 MHz) is available at a pin as low pass filtered
voltage, it can be disabled with the serial bus.
8. O ut put por ts
PORT_1 / 2 are NMOS Open drain outputs.
9. I2C Bus
The TUA4401K supports the I2C bus protocol (2 wire). All bus pins ( SCL,
SDA) are Schmitt triggered input buffer for 3V or 5V µC.
The bit stream begins with the most significant bit (MSB), is shifted in (write
mode) on the low to high transition of CLK and is shifted out (read mode) on
the high to low transition of CLK
I2C bus mode:
Data Transition:
Data transition on the pin SDA must only occur when the clock SCL is low.
SDA transitions while SCL is high will be interpreted as start or stop condi-
tion.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while
SCL is at a stable high level.This start condition must precede any command
and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the
SCL line is at a stable high level. This condition terminate the communication
between the devices and forces the bus interface into the initial conditions.
Functional Description
3 - 16
TUA 4401K
Wireless Components
Specification, 17.02.00
Acknowledge (ACK):
Indicates a successful data transfer. The transmitter will release the bus
after sending 8 bit of data. During the 9th clock cycle the receiver will pull the
SDA line to low level to indicate it has receive the 8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition,
followed by the 8bit chip address (write). The chip address for the TUA 4401
is fixed as ”1100110” (MSB at first). The last bit (LSB=A0) of the chip
address byte defines the type of operation to be performed:
A0=1, a read operation is selected and A0=0, a write operation is selected.
After this comparison the TUA 4401 will generate an ACK.
After this device addressing the desired subaddress byte and data bytes
must be followed. The subaddresses determines which one of the 9 data
bytes (00H...07H, 0BH) is transmitted first. At the end of data transition the
master must be generate the stop condition.
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a
start condition, followed by the 8bit chip address (write: A0=0), followed by
the sub address read (82H/83H), followed by the chip address (read: A0=1).
After that procedure the 16bit/8bit data register 82H/83H is read out. After
the first 8 bit read out, the uP mandatory send LOW during the ACK-clock.
After the second 8 bit read out the uP mandatory send HIGH during the
ACK-clock. At the end of data transition the master must be generate the
stop condition.
10.PLL Synthesizer
R / N Counter
The TUA 4401K has 2 identical 16bit counter for R and N path. Input fre-
quency for the R-counter is the buffered XTAL-frequency (61.5MHz). Tuning
steps can be selected by the 16bit R-counter from fR= 6.25kHz...100kHz.
Input frequency for the N-counter is the buffered LO-frequency (in FM mode
98.2MHz...118.7MHz).
Three State Phase Comparator
The phase comparator generates a phase error signal according to phase
difference between fR (R counter output) and fN (N counter outp ut).T hi s
phase error signal drives the charge pump current generator.
Charge Pum p
The charge pump generates signed pulses of current. 4 current values are
available.
Loop Amp
The integrated rail to rail loop amplifier allows an active loop filter design with
external components.
Two modes are available with status bit D11: high speed and normal mode.
Applications
4 - 2
TUA 4401K
Wireless Components
Specification, 17.02.00
4.1 Appli cation and Circuits
FM only car radio receiver, background receiver
4401K_Test_circ.wmf
Figure 4-1 Test Circuit
TUA4401K
1 2 34 56 7 89 1011121314151617181920 2122
23
24
25262728293031323334353637383940414243
44
FS_ADC IF-CENT SCL SDA Vref5V Vref3V Xtal/6 Port1
R-counter
61.5MHz
VccD
Port2
N-counter PD PD_0
1n 1n
22k
22k
4,7k
BB914
1n
1uH
BAR63
local oscill VccRF FM1
FM2
PreCap
10uH1k
1n10n
100
AGCout_p
MIX1 MIX2VrefRF
IFinFM
IFin
IFout_FMIFampC
VccIFFMIFinFMIFbiasMPX-out
Fieldstrength
10n
10
330
+
-
33n
100
4,7k
22n
1k
1n
51
22n
1k
22n
330
+-
1k
100uH
22n22n
100
RF-source 10.7MHz
22n
51
22n
1k
1n
51
MDP-Cap
68p
TOKO 600BN S -A1004HM
DemAFC
1k
1uF
MPD-out MDP-in
47n
100
MPA_ADC
33n 33n
10k
10k
+
-
1k
6,8n
150p
33k
1k 10n
3,3k
22n
22n
3,3k
3,3k
51
200kHz audio measure system RF-measu re 10.7MHz RF-source 110.7MHz
RF-measure 10.7MHz
TOKO 218FC S -2166N
RF-sourc e 10.7MHz
RF-source
time meas ureme nttime measurementtime measurement
10n
ramp I2C-Bus
Applications
4 - 3
TUA 4401K
Wireless Components
Specification, 17.02.00
4401K_SPEC.eps
Figure 4-2 Application Circuit
5Reference
5.1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2 Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3 Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4 I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
Contents of this Chapter
Reference
5 - 2
TUA 4401K
Wireless Components
Specification, 17.02.00
5.1 Electrica l Data
5.1.1 Absolute Maximum Range
The maximal ratings may not be exceeded under any circumstances, not even
momentary and individual, as permanent damage to the IC will result.
All values are referred to ground (pin), unless stated otherwise.
All currents are designated according to the source and sink principle, i.e. if the device
pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it
has a negative sign, and if it is a source (the current flows from Vs across the designated
pin), it has a positive sign.
5.1.2 Operating Range
Within the operational range the IC operates as described in the circuit
description.
The AC / DC characteristic limits are not guaranteed.
Table 5-1 Absolute Maximum Range
Parameter Symbol Limit Values Unit
min max
ESD-Protection all bipolar pins
HBM ( R=1.5kΩ , C=100pF ) VESD - 1 1kV
ESD-Protec tion all CMOS pins
HBM ( R=1.5kΩ , C=100pF ) VESD -1 1kV
Total power dissipation Ptot 900 mW
Ambient temperature TA- 40 85 °C
Junction temperature Tj150 °C
Storage tempera ture Tstg - 40 125 °C
Thermal resistance P-MQFP-44 (sys-air) TthSA 65 K/W
Table 5-2 Operating Ratings
Parameter Symbol Limit Values Unit Test Conditions LItem
min max
Supply voltage VVCC 8 9 V
Current consumption Ivcc 111 mA
Ambient temperature TA- 40 85 °C
Reference
5 - 3
TUA 4401K
Wireless Components
Specification, 17.02.00
5.1.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V
Symbol Limit Values Unit Test Conditions LItem
min typ max
Power Supply
Total current consumption IVCC 85 111 mA
1st local oscillator
Frequency range f1st LO 50 250 MHz
Frequency range f1st LO 50 150 MHz Q factor of coil > 90
Frequency range f1st LO 160 250 MHz coil tbf; see
SUB06h
Negative input impedance Z18-19 - 1000 Ωf = 100 MHz L
RF mixer
Mixer current Imix 11 14 17 mA 101
Input frequency f22-23 60 140 MHz
Max input RF level V22-23 120 dBµV
Input impedance
single ended R22-23 1.8 kΩL
C22-23 2.5 pF L
Mixer gain Amix 12 15 18 dB 259
Input IP3 126 dBµV IM = 60 dB L
Noise Figure F 6 dB L
Reference voltage RF section V27 4.3 4.8 5.3 V104
Prestage AGC outputs
AGC threshold rang e V22-23 48 60 72 mV see diagram
SUB06h 310
311
AGC threshold rang e V22-23 36 45 54 mV see diagram
SUB06h 312
313
AGC threshold rang e V22-23 24 30 36 mV see diagram
SUB06h 314
315
AGC threshold rang e V22-23 10 15 20 mV see diagram
SUB06h 316
317
AGC voltage for MOSFET
Gate 2 V21 5.7 6.4 VV
22-23 = 0 mV 106
AGC voltage for MOSFET
Gate 2 V21 0.1 VV
22-23 = 200 m V 300
AGC current norm al polari ty I24 10 13 mA V22-23 = 0 mV 115
Reference
5 - 4
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V (continued)
Symbol Limit Values Unit Test Conditions LItem
min typ max
AGC current norm al polari ty I24 0.1 mA V22-23 = 200 mV 301
Integrator current I21 -75 -50 -25 µAV
22-23 = 0 mV;
Vm = 3V 117
Integrator current I21 25 50 75 µAV
22-23 = 200 mV;
Vm = 3V 303
IF amplifier
DC input voltage V29 3.4 3.7 4.0 V108
Input resistance R29 330 ΩL
Output resistance R31 330 ΩL
Max. Voltage gain A31-29 23 26 29 dB see
diagram SUB07h 403
Min. Voltage gain A31-29 10 13 16 dB see
diagram SUB07h 405
Noise figure F 7 dB RG = 330 Ω
IF limiter amplifier / fieldstrength gene rator
Input voltage for limiter
threshold V34 25 45 µVrm
sfin = 10.7 MHz;
V37 - 3 dB 470
AM suppression AAM 70 80 dB m = 30 %,
V34=100mV 469
Fieldstrength voltage V38 0.4 0.8 VV
34 = 0 mVrms 450
Fieldstrength voltage V38 1.5 1.9 2.3 VV
34 = 1 mVrms 451
Fieldstrength voltage V38 2.4 2.9 3.4 VV
34 = 10 mVrms 452
Fieldstrength voltage V38 3.6 4.2 4.8 VV
34 = 200 mVrms 471
Fieldstrength dynamic range V38dyn 90 dB
Fieldstrength linearity V38lin ±1 dB
Fieldstrength temperature
drift V38temp ±3 dB
FM demodulator
AF output voltage V37 500 600 720 mVrm
s∆F = 75 kHz;
fIF=10.7 MHz 455
AF output voltage V37 300 mVrm
s∆F = 75 kHz;
fIF= 21.4 MHz L
Total harmonic distortion THD37 0.3 0.6 %∆F = 75 kHz 456
Total harmonic distortion
detuned THD37 0.8 %f
in = 10.7 MHz
± 50 kHz;
∆F = 75 kHz
457
Reference
5 - 5
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V (continued)
Symbol Limit Values Unit Test Conditions LItem
min typ max
Multipath detector
Attack current I40*) 700 900 1200 µAV
39 = 350 mVrms;
Vm = 5 V 801
Recove r y cur r ent I40*) -8 -13 -18 µAV
39= 0 Vrms;
Vm = 3.6 V 802
Start voltage V41Def 4.7 VV
39 = 0 Vrms 114
Detector characteristic V41 V41Def
-3.1 V V41Def
-2.8 V V41Def
-2.5 V Vf
39 = 200 kHz
V39 = 40 mVrms
800
*) Detector currents are measured between the output pin (-pole) and a voltage source Vm
Crystal oscillator
Operating frequency f10-11 61.5 MHz 3rd harmonic
Negative input impedance Z10-11 - 250 Ωf = 61.5 MHz
Negative input impedance Z10-11 1.4 kΩf = 20.5 MHz
Input impedance crystal Rcr 70 Ω3rd harmonic
Spurious harmonics crystal asp - 20 dB f < 200 MHz
Bus controlled adjust range ∆fadj ± 40 ppm see diagram
SUB06h
Bus controlled output
XTAL_DIV6 VXTAL_DIV6
on AC 500 mVpp f = 10.25 MHz,
Cload = 10 pF
Bus controlled output
XTAL_DIV6 VXTAL_DIV6
on DC 1.0 1.5 2.0 VDC f = 10.25 MHz,
Cload = 10 pF 180
Bus controlled output
XTAL_DIV6 VXTAL_DIV6
off DC 50 mVDC Cload = 10 pF 197
Chargepump output (Loopfilter input)
DC voltage VPD_0 2.3 2.5 2.7 Vlocked 251
252
DC current ± IPD_03 3.2 45.2mA see Status,
Subaddres s 00H,
bit D1, D2
VPD_0 = 2.5V
220
to
227
DC current ± IPD_02 1.6 22.6mA
DC current ± IPD_01 0.8 11.3mA
DC current ± IPD_00 400 500 700 uA
Tristate output current ± IPD_0OFF 0.1 10 nA VPD_0 = 2.5V ,
guarant eed by
design
228
Loop amplifier tuningvoltage output (Loopfilter output)
LOW output voltage VPDA_L 0400 mV ITUNE = 100 uA 231
HIGH outp ut vol tag e VPDA_H VVCC
-0.5V VCC mV ITUNE = -100 uA 230
Reference
5 - 6
TUA 4401K
Wireless Components
Specification, 17.02.00
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V (continued)
Symbol Limit Values Unit Test Conditions LItem
min typ max
HIGH outp ut cur r ent so urc e IPDA_H -1.9 -2.4 -2.9 mA VTUNE = 4V,
VPD_0 = 0V
(see Status,
Subaddres s 00H,
bit D11)
232
233
LOW output cur rent sourc e IPDA_L -0.9 -1.2 -1.5 mA
PLL for synthesizer (see PLL Synthesizer on page 3-16)
PLL / VCO step size
(programmable via R-
counter)
fref 6.25 100 kHz f crystal = 61.5 MHz
N-counter divide ratio N2 65535 16-Bit 200
to
207
R-counter divide ratio R2 65535 16-Bit 210
to
216
Port outputs, PORT_1, PORT_2, IF_CENT, IF_WINDOW (see Output ports on page 3-15)
LOW output voltage VP0100 400 mV IP = 1 mA *1)
HIGH Lea ka ge curre nt IP_LEACK 0100 nA VP = 5 V *2)
*1) 830, 840, 831, 834
*2) 118, 119, 124, 125
I2C bus (SCL, SDA) (see I2C Bus Timing on page 5-12 and Bus Data Format on page 3-15)
H-input voltage VIH 2.10 5.50 V150
L-input voltage VIL -0.5 0.90 V150
Hysteresis of Schmitt trigger
inputs (SCL, SDA) Vhys 0.30 V
Input capacity CI5pF
I2C bus leakage current I_LEACK 0 1 µA Values only valid for
applied VCC
L
Ref voltages
Ref voltage V64.5 5.0 5.5 V102
Ref voltage V72.7 3.0 3.3 V103
Reference
5 - 7
TUA 4401K
Wireless Components
Specification, 17.02.00
5.2 Phase detector outputs
PD_O
fr
fn
P-Channel
Tri-State.
Polarity
pos.
Frequency fn > fr
or fV leading Frequency fn = fr
Frequency fn < fr
or fV lagging
N-Channel
Reference
5 - 8
TUA 4401K
Wireless Components
Specification, 17.02.00
5.3 Bus Interface
1. Bus Interface
I2C Bus
2. Bus Data Format
I2C Bus Write Mode
I2C Bus Read Mode
1): mandatory LOW send by uP, 2): mandatory HiGH send by uP
Chipaddress Organisation
Subaddress Organisation
MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (WRITE)
00H...07H, 0BH LSB MSB DATA IN X...0 (X=7 or 15) LSB
STA 11001100ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK DX ... D5 D4 D3 D2 D1 D0 ACK STO
MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (REA D) 82H/83H LSB MSB CHIP ADDRESS (READ) LSB
STA 11001100ACK 10000010ACK STA 11001101ACK
MSB DATA OUT FROM SUB ADD 82H LSB MSB DATA OUT FROM SUB ADD 82H/83H LSB
R15 R14 R13 R12 R11 R10 R9 R8 ACK1) R7 R6 R5 R4 R3 R2 R1 R0 ACK2) STO
Chip Address
MSB LSB Function
11001100Chip Address Write
11001101Chip Address Read
Sub Addresses of Data Registers Write
MSB Bin LSB Hex Function
0000000000HStatus
0000000101H R_Counter
0000001002H N_Counter
0000001103H Mute_DAC7
0000010004H IF_COUNT_P1
0000010105H IF_COUNT_P2
0000011006H Specials
0000011107H Gain_DAC4
000010110BH COMP-PRESET
Sub Address of Data Register Read
MSB Bin LSB Hex Function
1000001082H
Result Multipath,
Fieldstrength,
IF_Window and
IF_Center
1000001183HResult-MISC
Reference
5 - 9
TUA 4401K
Wireless Components
Specification, 17.02.00
Data Byte Specification
Status
Subaddress 00H R_Counter
Subaddress 01H N_Counter
Subaddr ess 02H
Results Fieldstrength, Multipath
and IF counter
Subaddress 82H (read address)
Bit Function Bit Function Bit Function Bit Function
MSB
D15 not used (must be=0) MSB
D15 215 MSB
D15 215 MSB
D15 IF_window
D14 P ort_2 (0=low, 1=high) D14 214 D14 214 D14 Multipath_26
D13 P ort_1 (0=low, 1=high) D13 213 D13 213 D13 Multipath_25
D12 not used (must be=0) D12 212 D12 212 D12 Multipath_24
D11 Loopamp current D11 211 D11 211 D11 Multipath_23
D10 not used (must be=0) D10 210 D10 210 D10 Multipath_22
D9 not used (must be=0) D9 29D9 29D9 Multipath_21
D8 not used (must be=0) D8 28D8 28D8 Multipath_20
D7 ADC_Single D7 27D7 27D7 IF_center
D6 ADC_Mode D6 26D6 26D6 Fieldstrength_26
D5 ADC_ON D5 25D5 25D5 Fieldstrength_25
D4 IF_DAC4 D4 24D4 24D4 Fieldstrength_24
D3 not used (must be=0) D3 23D3 23D3 Fieldstrength_23
D2 CP_Current 2 D2 22D2 22D2 Fieldstrength_22
D1 CP_Current 1 D1 21D1 21D1 Fieldstrength_21
D0
LSB CP_Mode D0
LSB 20D0
LSB 20D0
LSB Fieldstrength_20
Mute_DAC7
Subaddress 03H IF_Count_P1
Subaddress 04H IF_Count_P2
Subaddress 05H Specials
Subaddress 06H IF_DAC4
Subaddr ess 07H COMP_PRESET
Subaddress 0BH
Bit Function Bit Function Bit Function Bit Function Bit Function Bit Function
MSB
D7 Enable MSB
D7 Enable MSB
D7 CF_Mod
eMSB
D7 XTAL_DIV6 MSB
D7 not used MSB
D15 not used
D6 MDAC_6 D6 not used D6 CF_6 D6 VCO_2 D6 not used D14 Fieldstrength_26
D5 MDAC_5 D5Win_2 D5CF_5 D5AGC_1 D5not used D13 Fieldstrength_25
D4 MDAC_4 D4Win_1 D4CF_4 D4AGC_0 D4not used D12 Fieldstrength_24
D3 MDAC_3 D3 Win_0 D3 CF_3 D3 XTAL_3 D3 GDAC_3 D11 Fieldstrength_23
D2 MDAC_2 D2 Gate_2 D2 CF_2 D2 XTAL_2 D2 GDAC_2 D10 Fieldstrength_22
D1 MDAC_1 D1 Gate_1 D1 CF_1 D1 XTAL_1 D1 GDAC_1 D9 Fieldstrength_21
D0
LSB MDAC_0 D0
LSB Gate_0 D0
LSB CF_0 D0
LSB XTAL_0 D0
LSB GDAC_0 D8 Fieldstrength_20
D7 not used
Result Misc
Subaddress 83H D6 Multipath_26
Bit Function D5 Multipath_25
MSB
D7 IF_Window D4 Multipath_24
D6 IF_Center D3 Multipath_23
D5 Fieldstrength_Comp D2 Multipath_22
D4 Multipath_Comp D1 Multipath_21
D3 Res D0
LSB Multipath_20
D2 Res
Reference
5 - 10
TUA 4401K
Wireless Components
Specification, 17.02.00
D1 Res
D0
LSB Res
Status, Subaddress 00H
MSB LSB MSB LSB Function
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 these bits must be = 0
01 opendrain Port_2 ou tput = high level
00 opendrain Port_2 ou tput = low level
01 opendrain Port_1 ou tput = high level
00 opendrain Port_1 ou tput = low level
01 Loopamp currentsource high (ILOOPAMP=2.4mA) for
high speed tuning
0 0 Loopamp currentsource low (ILOOPAMP=1.2mA)
0 0 0 1 7 bit AD Converter enabled for single mode, stop
0101
7 bit AD Converter enabled for single mode start. To
restart single mode write the same bits once more.
0 0 1 1 7 bit AD Converter enabled for continuous mode run.
0xx1
7 bit AD Converter enabled for single or continuous
mode
0xx0
7 bit AD Converter disabled for single and continuous
mode
0 1 IF_DAC4 enabled (see subaddress 07H)
0 0 IF_DAC4 disabled (see subaddress 07H)
01 1 Chargepump current Icp3 = 4mA
01 0 Chargepump current Icp2 = 2mA
00 1 Chargepump current Icp1 = 1mA
00 0 Chargepump current Icp0 = 500uA
01 Chargepump enabled
00 Chargepump disabled
Subaddress 01H, R_Counter and
Subaddress 02H, N_Counter
MSB LSB MSB LSB Function
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 11 1 1111111 Divider by 65535
0 0 0 0 0 1 11 1 1010000 Divider by 2000
0 0 0 0 0 1 00 1 1001110 Divider by 1230
0 0 0 0 0 0 11 1 1101000 Divider by 1000
0 0 0 0 0 0 10 0 1100111 Divider by 615
0 0 0 0 0 0 00 0 1100100 Divider by 100
0 0 0 0 0 0 00 0 0001010 Divider by 10
0 0 0 0 0 0 00 0 0000010 Divider by 2
Reference
5 - 11
TUA 4401K
Wireless Components
Specification, 17.02.00
Subaddress 03H, Mute_DAC7 Subaddress 05H, IF_Count_P2,
Centerfrequency = CF, CFstep= 6.25kHz) / 12.5 kHz
MSB LSB Function MSB LSB Function
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 Centerfrequency CF1
0 Centerfrequency CF0
1 1111111 not used (must be 1) 1 1111111 CF1= 22.3875 MHz
0 1111111 CF0= 11.1937 MHz
Subaddress 04H, IF_Count_P1
MSB LSB Function 1 1000000 CF1= 22.600 MHz
D7D6D5D4D3D2D1D0 0 1000000 CF0= 10.800 MHz
1 IF_Count enabled
0 IF_Count disabled 1 0110001 CF1= 21.4125 MHz
0 not used (must be=0) 0 0110001 CF0= 10.70625 MHz
100 Window=+/-100kHz* 1 0110000 CF1= 21.400 MHz
011 Window=+/-50kHz* 0 0110000 CF0= 10.700 MHz
010 Window=+/-25kHz* 1 0101111 CF1= 21.3875 MHz
001 Window=+/-12.5kHz* 0 0101111 CF0= 10.69375 MHz
0 0 0 Window=+/-6.25kHz*
111 Gatetime= 40.96ms 1 0100000 CF1= 21.200 MHz
110 Gatetime= 20.48ms 0 0100000 CF0= 10.600 MHz
1 0 1 Gateti me= 10. 24m s
100 Gatetime= 5.12ms 1 0010000 CF1= 21.000 MHz
011 Gatetime= 2.56ms 0 0010000 CF0= 10.500 MHz
0 1 0 Gatetime= 1.2 8ms
001 Gatetime= 640us 1 0000000 CF1= 20.800 MHz
000 Gatetime= 320us 0 0000000 CF0= 10.400 MHz
* Valid for D7= 0 in subaddress 05H Centerfrequencies for
Multiply window value with 2 for D7= 1 in subaddress 05H D7=1 CF1= 20.800 MHz +n*12.5 kHz, CFStep=12.5 kHz
(e. g. D7= 0 Window =+/- 6.25 kHz D7=0 CF0= 10.400 MHz +n*6.25 kHz, CFStep=6.25 kHz
D7= 1 Window =+/- 12.5 kHz) n=0...127
Reference
5 - 12
TUA 4401K
Wireless Components
Specification, 17.02.00
*) For continuous tuning characteristic it is recommended to skip steps 8 and 9
Subaddress 06H, Specials Subaddress 07H, IF_DAC4
MSB LSB Function MSB LSB Function
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 XTAL_DIV6 enabled x x x x not used
0 XTAL_DIV6 disabled 1111 IF_DAC Gain adj.
typ. 16 dB
1 1st LO divided by 1 1110 IF_DAC Gain adj.
0 1st LO divided by 2 1101 IF_DAC Gain adj.
00 Prest. AGC threshold typ.
15 mV 1100 IF_DAC Gain adj.
01 Prest. AGC threshold typ.
30 mV 1011 IF_DAC Gain adj.
typ. 21 dB
10 Prest. AGC threshold typ.
45 mV 1010 IF_DAC Gain adj.
11 Prest. AGC threshold typ.
60 mV 1001 IF_DAC Gain adj.
1111 XTAL_adjust C
L = 15 pF 1000 IF_DAC Gain adj.
1110 XTAL_adjust C
L = 14pF 0111 IF_DAC Gain adj.
1101 XTAL_adjust C
L = 13 pF 0110 IF_DAC Gain adj.
1100 XTAL_adjust C
L = 12 pF 0101 IF_DAC Gain adj.
1011 XTAL_adjust C
L = 11 pF 0100 IF_DAC Gain adj.
typ. 24 dB
1010 XTAL_adjust C
L = 10 pF 0011 IF_DAC Gain adj.
1001 XTAL_adjust C
L = 9 pF *) 0010 IF_DAC Gain adj.
1000 XTAL_adjust C
L = 8 pF *) 0001 IF_DAC Gain adj.
0111 XTAL_adjust C
L = 7 pF 0000 IF_DAC Gain adj.
typ. 26 dB
0110 XTAL_adjust C
L = 6 pF
0101 XTAL_adjust C
L = 5 pF
0100 XTAL_adjust C
L = 4 pF
0011 XTAL_adjust C
L = 3 pF
0010 XTAL_adjust C
L = 2 pF
0001 XTAL_adjust C
L = 1pF
0000 XTAL_adjust C
L = 0pF
Subaddress 0BH, Comp preset
MSBLSBMSBLSB
Function
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X not used
FP26FP25FP24FP23FP22FP21FP20Preset value Fieldstrength
MP26MP25MP24MP23MP22MP21MP20Preset value Multipath
Reference
5 - 13
TUA 4401K
Wireless Components
Specification, 17.02.00
5.4 I2C Bus Timing
Subaddress 82H, Read results from Fiel dstren gth, Multipath and IF counter
MSB LSB MSB LSB Function
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
11IF_counter result: IF frequency is outside the
desired window. IF frequency is lower as the
desired IF frequency.
01IF_counter result: IF frequency is outside the
desired window.IF frequency is higher as the
desired IF frequency.
x0IF_counter result: IF frequency is inside the
desired window
M26M25M24M23M22M21M20Result multipath byte M6...M0
F26F25F24F23F22F21F20Result fieldstrength byte F6...F0
Subaddress 83H, Read results misc
MSB LSB Function
D7 D6 D5 D4 D3 D2 D1 D0
1 1 Res Res Res Res IF_counter result: IF frequency is outside the
desired window. IF frequency is lower as the
desired IF frequency.
0 1 Res Res Res Res IF_counter result: IF frequency is outside the
desired window.IF frequency is higher as the
desired IF frequency.
x 0 Res Res Res Res IF_counter result: IF frequency is inside the
desired window
1Fieldstrength is higher as the preseted value in
subaddress 0BH (D8...D14)
0Fieldstrength is lower as the preseted value in
subaddress 0BH (D8...D14)
1Multipathsignal is higher as the preseted value in
subaddress 0BH (D0...D6)
0Multipathsignal signal is lower as the preseted
value in subaddress 0BH (D0...D6)
SCL
SDA
tBUF
S
PtHD.DAT
tHD.STA tHIGH
tF
tLOW
tR
tSU.DAT
tHD.STA tSP
P
tSU.STO
S
tSU.STA
BUS_MODE = LOW
Reference
5 - 14
TUA 4401K
Wireless Components
Specification, 17.02.00
2)Cb= capacitance of one bus line in pF.
Note that the maximum tF for the SDA and SCL bus lines quoted at 300ns is
longer than the specified maximum tOF for the output stages (250ns).This
allows series protection resistors to be connected between the SDA / SCL pins
and the SDA /SCL bus lines without exceeding the maximum specified tF.
Table 5-4
Parameter Symbol min max Unit
LOW level input voltage (SDA, SCL) VIL -0.5 0.90 V
HIGH level input volta ge (SDA, SCL) VIH 2.10 5.50 V
Pulse width of spikes which must be suppressed by the input fil-
ter tSP 050 ns
LOW level output voltage 3mA sink current (SDA) VOL 00.40 V
Output fall time from VIHmin to VILmax with a bus capacitance
from 10pF to 400pFwith up to 3mA tOF 20+0.1Cb2) 250 ns
SCL clock frequency fSCL 0400 kHz
Bus free time between a STOP and START condition tBUF 1.3 µs
Hold ti me (repe ated ) START co nd itio n. Afte r thi s pe riod , the firs t
clock pulse is generated. tHO.STA 0.6 µs
LOW period of the SCL clock tLOW 1.3 µs
HIGH period of the SCL clock tHIGH 0.6 µs
Set-up time for a repeated START condition tSU.STA 0.6 µs
Data hold time tHD.DAT 0ns
Data set -up time tSU.DAT 100 ns
Rise, fall time of both SDA and SCL signals tR, tF20+0.1Cb2) 300 ns
Set-up time for STOP condition tSU.STO 0.6 µs
Capacitive load for each bus line Cb400 pF
