08325 March 20, 2013 Rev: A
EN5319QI
1.5A Low Profile Synchronous Buck DC-DC
Converter with Integrated Inductor
RoHS Compliant
Halogen Free
www.enpirion.com
Description
The EN5319QI is a highly integrated, low profile,
highly efficient, 1.5A synchronous buck power system
on a chip (PowerSoCTM). The device features an
advance integrated inductor, integrated MOSFETs, a
PWM voltage-mode controller, and internal
compensation providing the smallest possible solution
size.
The EN5319QI is a member of the EN53x9QI family
of pin compatible and interchangeable devices. The
pin compatibility enables an easy to use scalable
family of products covering the load range from 1.5A
up to 3A in a low profile 4mm x 6mm x 1.1mm QFN
package.
The EN5319QI operates at high switching frequency
and allows for the use of tiny MLCC capacitors. It also
enables a very wide control loop bandwidth providing
excellent transient performance and reduced output
impedance. The internal compensation is designed
for unconditional stability across all operating
conditions.
The Enpirion integrated inductor solution significantly
helps to reduce noise. The complete power converter
solution enhances productivity by offering greatly
simplified board design, layout and manufacturing
requirements. All Enpirion products are RoHS
compliant and lead-free manufacturing environment
compatible.
Features
• Integrated Inductor
• Solution Footprint as Small as 50 mm2
• Low Profile, 1.1mm
• High Reliability Solution: 42,000 Years MTBF
• High Efficiency, up to 95 %
• Low Output Ripple Voltage; <4mVP-P Typical
• 2.4 V to 5.5 V Input Voltage Range
• 1.5A Continuous Output Current Capability
• Output Enable and Power OK Signal
• Pin Compatible w/ EN5329QI 2A and EN5339QI 3A
• Under Voltage Lockout, Over Current, Short Circuit,
and Thermal Protection
• RoHS Compliant; Halogen Free; 260°C Reflow
Applications
• Applications with Low Profile Requirement such as
SSD and Embedded Computing
• SAN/NAS Accelerator Appliance
• FPGA, ASSP, PLD, ASIC, and Processors
• Noise Sensitive Applications
Figure 1. Simplified Applications Circuit Figure 2. Highest Efficiency in Smallest Solution Size
0
10
20
30
40
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 2.5V
VOUT = 1.2V
CONDITIONS
VIN = 3.3V
Actual Solution Size
50mm
2
08325 March 20, 2013 Rev: A
EN5319QI
©Enpirion 2013 all rights reserved, E&OE www.enpirion.com, Page 2
Ordering Information
Part Number Package Markings Temp Rating (°C) Package Description
EN5319QI EN5319 -40 to +85 24-pin (4mm x 6mm x 1.1mm) QFN T&R
EN5319QI-E EN5319 QFN Evaluation Board
Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm
Pin Assignments (Top View)
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically
connected to the PCB. There should be no traces on PCB top layer under these keep out areas.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN NAME FUNCTION
1, 21-24 NC(SW)
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device
damage.
2-3, 8-9 PGND
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more
details.
4-7 VOUT
Regulated converter output. Connect to the load and place output filter capacitor(s) between
these pins and PGND pins 8 and 9. See layout recommendation for details
10 TST2 Test Pin. For Enpirion internal use only. Connect to AVIN at all times.
11 TST1 Test Pin. For Enpirion internal use only. Connect to AVIN at all times.
08325 March 20, 2013 Rev: A
EN5319QI
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PIN NAME FUNCTION
12 TST0 Test Pin. For Enpirion internal use only. Connect to AVIN at all times.
13 NC
NO CONNECT: This pin must be soldered to PCB but not electrically connected to any other
pin or to any external signal, voltage, or ground. This pin may be connected internally. Failure
to follow this guideline may result in device damage.
14 VFB
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor is required
parallel to the upper feedback resistor (RA). The output voltage regulation is based on the
VFB node voltage equal to 0.600V.
15 AGND
The quiet ground for the control circuits. Connect to the ground plane with a via right next to
the pin.
16 AVIN
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Decouple with a 1uF capacitor to AGND.
17 POK
POK is an open drain output. Refer to Power OK section for details. Leave POK open if
unused.
18 ENABLE
Output Enable. A logic high level on this pin enables the output and initiates a soft-start. A
logic low signal disables the output and discharges the output to GND. This pin must not be
left floating.
19-20 PVIN
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 2 to 3.
25,26 PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes. See Layout Recommendation section.
08325 March 20, 2013 Rev: A
EN5319QI
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Absolute Maximum Rati ngs
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER SYMBOL MIN MAX UNITS
Voltages on : PVIN, AVIN, VOUT -0.3 6.5 V
Voltages on: ENABLE, POK, TST0, TST1, TST2 -0.3 VIN+0.3 V
Voltages on: VFB -0.3 2.7 V
Storage Temperature Range TSTG -65 150 °C
Maximum Operating Junction Temperature TJ-ABS Max 150 °C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C
ESD Rating (Human Body Model) 2000 V
ESD Rating (Charge Device Model) 500 V
Recommended Operating Conditions
PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range VIN 2.4 5.5 V
Output Voltage Range (Note 1) VOUT 0.6 VIN – VDO V
Output Current IOUT 0 1.5 A
Operating Ambient Temperature TA -40 +85 °C
Operating Junction Temperature TJ -40 +125 °C
Thermal Characteristics
PARAMETER SYMBOL TYP UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2) θJA 36 °C/W
Thermal Resistance: Junction to Case (0 LFM) θJC 6 °C/W
Thermal Shutdown TSD 150 °C
Thermal Shutdown Hysteresis TSDH 15 °C
Note 1: VDO (dropout voltage) is defined as (ILOAD x Dropout Resistance). Please see Electrical Characteristics Table.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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EN5319QI
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Electrical Characteristics
NOTE: VIN = 5V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input Voltage VIN 2.4 5.5 V
Feedback Node Initial
Accuracy VVFB TA = 25°C; VIN = 5V
ILOAD = 100 mA 0.588 0.600 0.612 V
Output Variation (Note 3)
(Line, Load, Temperature) VOUT 2.4V
≤
VIN
≤
5.5V
0 ≤ ILOAD ≤ 1.5A -3 +3 %
VFB, ENABLE, TST0/1/2
Pin Input Current (Note 4) +/-40 nA
Shutdown Current ENABLE Low 20
μ
A
Under Voltage Lock-out –
VIN Rising VUVLOR Voltage Above Which UVLO is
Not Asserted 2.2 V
Under Voltage Lock-out –
tVIN Falling VUVLOF Voltage Below Which UVLO is
Asserted 2.1 V
Soft-start Time Time from Enable High (Note 4) 0.91 1.40 1.89 ms
Dropout Resistance 150 300 mΩ
ENABLE Voltage
Threshold Logic Low
Logic High
0.0
1.4 0.4
VIN V
POK Threshold VOUT Rising 92 %
POK Threshold VOUT Falling 90 %
POK Low Voltage ISINK = 1 mA 0.15 0.4 V
POK Pin VOH Leakage
Current POK High 0.5 2 µA
Current Limit Threshold 2.4V
≤
VIN
≤
5.5V 3.5 5 A
Operating Frequency FOSC 3.2 MHz
Output Ripple Voltage VRIPPLE
COUT = 2 x 22
μ
F 0603 X5R
MLCC, VOUT = 3.3 V, ILOAD = 1.5A 4 mVP-P
COUT = 2 x 22
μ
F 0603 X5R
MLCC, VOUT = 1.8 V, ILOAD = 1.5A 4 mVP-P
Note 3: Output voltage variation is based on using 0.1% accuracy resistor values.
Note 4: Parameter not production tested but is guaranteed by design.
08325 March 20, 2013 Rev: A
EN5319QI
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Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
VIN = 3.3V
0
10
20
30
40
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
VIN = 5V
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4
OUTPUT VOLTAGE (V)
INPUT VOLTAGE(V)
Dropout Voltage
IOUT = 1A
IOUT=1.5A
CONDITIONS
VOUT = 3.3V
3.24
3.26
3.28
3.3
3.32
3.34
3.36
0 0.25 0.5 0.75 1 1.25 1.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 3.3V
CONDITIONS
VIN = 5V
2.44
2.46
2.48
2.5
2.52
2.54
2.56
0 0.25 0.5 0.75 1 1.25 1.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 2.5V
CONDITIONS
VIN = 5V
1.74
1.76
1.78
1.8
1.82
1.84
1.86
0 0.25 0.5 0.75 1 1.25 1.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.8V
CONDITIONS
VIN = 5V
08325 March 20, 2013 Rev: A
EN5319QI
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Typical Performance Curves (Continued)
1.14
1.16
1.18
1.2
1.22
1.24
1.26
0 0.25 0.5 0.75 1 1.25 1.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.2V
CONDITIONS
VIN = 5V
2.44
2.46
2.48
2.5
2.52
2.54
2.56
0 0.25 0.5 0.75 1 1.25 1.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 2.5V
CONDITIONS
VIN = 3.3V
1.74
1.76
1.78
1.8
1.82
1.84
1.86
0 0.25 0.5 0.75 1 1.25 1.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.8V
CONDITIONS
VIN = 3.3V
1.14
1.16
1.18
1.2
1.22
1.24
1.26
00.250.50.7511.251.5
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.2V
CONDITIONS
VIN = 3.3V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.53.13.74.34.95.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 5mA
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.53.13.74.34.95.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 500mA
08325 March 20, 2013 Rev: A
EN5319QI
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Typical Performance Curves (Continued)
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.5 3.1 3.7 4.3 4.9 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 1A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.5 3.1 3.7 4.3 4.9 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 1.5A
0.960
0.970
0.980
0.990
1.000
1.010
1.020
1.030
1.040
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 1.5A
LOAD = 100mA
CONDITIONS
V
IN
= 5V
V
OUT_NOM
= 1.0V
1.760
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1.840
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 1.5A
LOAD = 100mA
CONDITIONS
V
IN
= 5V
V
OUT_NOM
= 1.8V
CONDITIONS
V
IN
= 5V
V
OUT_NOM
= 1.8V
0
0.5
1
1.5
2
2.5
-40 -15 10 35 60 85
GUARANTEED OUTPUT CURRENT (A)
AMBIENT TEMPERATURE(°C)
No Thermal Derating
Conditions
V
IN
= 5.0V
V
OUT
= 3.3V
CONDITIONS
V
IN
= 5.0V
V
OUT
= 1.0V
0
0.5
1
1.5
2
2.5
-40 -15 10 35 60 85
GUARANTEED OUTPUT CURRENT (A)
AMBIENT TEMPERATURE(°C)
No Thermal Derating
Conditions
V
IN
= 5.0V
V
OUT
= 3.3V
CONDITIONS
V
IN
= 5.0V
V
OUT
= 3.3V
08325 March 20, 2013 Rev: A
EN5319QI
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Typical Performance Characteristics (Continued)
Output Ripple at 20MHz
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 1.5A
CIN = 1x 10µF (0805)
COUT = 2 x 22µF (0603)
VOUT
(AC Coupled)
Output Ripple at 20MHz
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 1.5A
CIN = 1x 10µF (0805)
COUT = 2 x 22µF (0603)
VOUT
(AC Coupled)
Output Ripple at 500MHz
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 1.5A
CIN = 1x 10µF (0805)
COUT = 2 x 22µF (0603)
VOUT
(AC Coupled)
Output Ripple at 500MHz
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 1.5A
CIN = 1x 10µF (0805)
COUT = 2 x 22µF (0603)
VOUT
Startup Waveforms at 0A
VIN = 5V, VOUT = 1.8V
CIN = 1 X 10µF (0805), COUT = 2 x 22µF (0603),IOUT=0A
LOAD
ENABLE
POK
VOUT
Startup Waveforms at 1.5A
VIN = 5V, VOUT = 1.8V
CIN = 1 X 10µF (0805), COUT = 2 x 22µF (0603),IOUT=1.5A
LOAD
ENABLE
POK
08325 March 20, 2013 Rev: A
EN5319QI
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Typical Performance Characteristics (Continued)
VOUT
(AC Coupled)
Load Transient from 0 to 750mA
CONDIT IONS
VIN = 3.3V
VOUT = 1.8V
CIN = 1 X 10µF (0805)
COUT = 2 x 22µF (0603)
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 1.5A
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
CIN = 1 X 10µF (0805)
COUT = 2 x 22µF (0603)
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 750mA
CONDITIONS
VIN = 5V
VOUT = 2.5V
CIN = 1 X 10µF (0805)
COUT = 2 x 22µF (0603)
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 1.5A
CONDITIONS
VIN = 5V
VOUT = 2.5V
CIN = 1 X 10µF (0805)
COUT = 2 x 22µF (0603)
LOAD
08325 March 20, 2013 Rev: A
EN5319QI
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Functional Block Diagram
DAC
VREF
(+)
(-)
Error
Amp
VFB
VOUT
Package Boundary
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)
PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC
(SW)
POK
POK
AVIN AGND
BIAS
TST
Figure 4: Functional Block Diagram
Functional Description
Overview
The EN5319QI is a highly integrated synchronous
buck converter with an internal inductor utilizing
advanced CMOS technology to provide high
switching frequency, while also maintaining high
efficiency. The EN5319QI is a high power density
device packaged in a tiny 4x6x1.1mm 24-pin QFN
package. Its high switching frequency allows for the
use of very small MLCC input and output filter
capacitors and results in a total solution size as
small as 50mm2.
The EN5319QI is a member of a family of pin
compatible devices. This offers scalability for
applications where load currents may not be known
apriori, and/or speeds time to market with a
convenient common solution footprint.
The EN5319QI buck converter uses Type III
voltage mode control to provide pin-point output
voltage accuracy, high noise immunity, low output
impedance and excellent load transient response.
The EN5319QI features include Power OK, under
voltage lockout (UVLO), over current protection,
short circuit protection, and thermal overload
protection.
Stability and Compensation
The EN5319QI utilizes an internal compensation
network that is designed to provide stable operation
over a wide range of operating conditions. The
output compensation circuit may be customized to
improve transient performance or reduce output
voltage ripple with dynamic loads.
Soft-Start
The EN5319QI has an internal soft-start circuit that
controls the ramp of the output voltage. The control
circuitry limits the VOUT ramp rate to levels that are
safe for the Power MOSFETs and the integrated
inductor.
The EN5319QI has a constant startup up time
08325 March 20, 2013 Rev: A
EN5319QI
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which is independent of the VOUT setting. The
output rising slew rate is proportional to the output
voltage. The startup time is approximately 1.4ms
from when the ENABLE is first pulled high until
VOUT reaches the regulated voltage level.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. Since the slew rate varies with the output
voltage setting, the maximum capacitance is a
function of the VOUT setting.
The maximum capacitance on the output power
rail, including the output filter capacitors and all
decoupling and bulk capacitors on the supply rail is
given by:
COUT_TOTAL_MAX [µF] = 3.41x103 / VOUT
NOTE: The above number and formula assume a
no load condition at startup.
Over Current/Short Circuit Protection
When an over current condition occurs, VOUT is
pulled low and the device disables switching
internally. This condition is maintained for a period
of 1.2 ms and then a normal soft-start cycle is
initiated. If the over current condition still persists,
this cycle will repeat.
Under Voltage Lockout
An under voltage lockout circuit will hold off
switching during initial power up until the input
voltage reaches sufficient level to ensure proper
operation. If the voltage drops below the UVLO
threshold the lockout circuitry will again disable
switching. Hysteresis is included to prevent
chattering between UVLO high and low states.
Enable
The ENABLE pin provides means to shut down the
converter or initiate normal operation. A logic high
on the ENABLE pin will initiate the converter to start
the soft-start cycle and regulate the output voltage
to the desired value. A logic low will allow the
device to discharge the output and go into
shutdown mode for minimal power consumption.
When the output is discharged, an auxiliary NFET
turns on and limits the discharge current to 300 mA
or below. The ENABLE pin should not be left
floating.
Thermal Shutdown
When excessive power is dissipated in the device,
its junction temperature rises. Once the junction
temperature exceeds the thermal shutdown
temperature of 150°C, the thermal shutdown circuit
turns off the converter, allowing the device to cool.
When the junction temperature drops 15°C, the
device will be re-enabled and go through a normal
startup process.
Power OK
The Power OK (POK) feature is an open drain
output signal used to indicate if the output voltage
is within 92% of the set value. Within this range, the
POK output is allowed to be pulled high. Outside
this range, the POK output is maintained low.
During transitions such as power up and power
down, the POK output will not change state until the
transition is complete for enhanced noise immunity.
The POK has 1mA sink capability. When POK is
pulled high, the worst case pin leakage current is
as low as 500nA over temperature. This allows a
large pull up resistor such as 100kΩ to be used for
minimal current consumption in shutdown mode.
The POK output can also be conveniently used as
an enable input of the next stage for power
sequencing of multiple converters.
08325 March 20, 2013 Rev: A
EN5319QI
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Application Information
Setting the Output Voltage
The EN5319 uses a simple and flexible resistor
divider network to program the output voltage. A
feed-forward capacitor (Ca) is used to improve
transient response. Table 3 shows the required
critical component values for the feedback network
as a function of VOUT. It is recommended to use
1% or better feedback resistors to ensure output
voltage accuracy. The Ra resistor value is fixed at
348k as shown in Table 3. Based on that value, the
bottom resistor Rb can be calculated below as:
V0.6V V0.6Ra
Rb
OUT −
×
=
The VOUT is the nominal output voltage. The Rb
and Ra resistors have the same units based on the
above equation.
Figure 5. Typical Application Circuit.
(NOTE: Enable can be separated from PVIN if the
application requires it)
AVIN Filter Capacitor
A 1.0 μF, 10V, 0402 MLCC capacitor should be
placed between AVIN and AGND as close to the
pins as possible. This will provide high frequency
bypass to ensure clean chip supply for optimal
performance.
Input Filter Capacitor Selection
A single 10μF, 0805 MLCC capacitor is needed on
PVIN for all applications. Connect the input
capacitor between PVIN and PGND as close to the
pins as possible. Placement of the input capacitor
is critical to ensure low noise and EMI Low ESR
MLCC capacitors with X5R or X7R or equivalent
dielectric should be used for the input capacitors.
Y5V or equivalent dielectrics lose too much
capacitance with frequency, DC bias, and
temperature. Therefore, they are not suitable for
switch-mode DC-DC converter filtering, and must
be avoided.
Table 1: Recommended Input Capacitors
Description MFG P/N
10µF, 10V,
X5R, 0805
Taiyo Yuden LMK212ABJ106KG
Murata GRM21BR61A106KE19
Output Filter Capacitor Selection
The EN5319QI output capacitor selection may be
determined based on two configurations. Table 3
provides the allowed output capacitor
configurations based on operating conditions. For
lower output ripple, choose 2 x 22µF 0603 for the
output capacitors. For smaller solution size, use
one 22µF 0805 output capacitor. Table 2 shows the
recommended type and brand of output capacitors
to use. For details regarding other configurations,
contact Enpirion (techsupport@enpirion.com).
In some rare applications modifications to the
compensation may be required. The EN5329QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact Enpirion
Applications Engineering support.
Table 2: Recommended Output Capacitors
Description MFG P/N
22µF, 6.3V,
X5R, 0805
Taiyo Yuden JMK212ABJ226MG
Murata GRM21BR60J226ME39
22µF, 6.3V,
X5R, 0603 Murata GRM188R60J226MEA0
Table 3. Required Critical Components
(Note: Follow Layout Recommendations)
VOUT (V) Ca (pF) Ra (kΩ) Cout (µF)
Vout ≤ 2.0V 10 348 1x22uF/0805
2.0V < Vout ≤ 3.3V 8.2
Vout ≤ 2.0V 12 348 2x22uF/0603
2.0V < Vout ≤ 3.3V 6.8
Vout ≤ 2.0V 12
348 2x22uF/0805
2.0V < Vout ≤ 3.3V 6.8
Vout > 3.3V 6.8
08325 March 20, 2013 Rev: A
EN5319QI
©Enpirion 2013 all rights reserved, E&OE www.enpirion.com, Page 14
Power Up/Down Sequencing
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. The PVIN should never be powered
when AVIN is off. During power down, the AVIN
should not be powered down before PVIN. Tying
PVIN and AVIN or all three pins (AVIN, PVIN,
ENABLE) together during power up or power down
meets these requirements.
Pre-Bias Start-up
The EN5319QI does not support startup into a pre-
biased condition. Be sure the output capacitors are
not charged or the output of the EN5319QI is not
pre-biased when the EN5319QI is first enabled.
08325 March 20, 2013 Rev: A
EN5319QI
©Enpirion 2013 all rights reserved, E&OE www.enpirion.com, Page 15
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated needs to be
accounted for. The Enpirion PowerSoCTM helps
alleviate some of those concerns.
The Enpirion EN5319QI DC-DC converter is
packaged in a 4x6x1.1mm 24-pin QFN package.
The QFN package is constructed with exposed
thermal pads on the bottom of the package. The
exposed thermal pad should be soldered directly on
to a copper ground pad on the printed circuit board
(PCB) to act as a heat sink. The recommended
maximum junction temperature for continuous
operation is 125°C. Continuous operation above
125°C may reduce long-term reliability. The device
has a thermal overload protection circuit designed
to turn off the device at an approximate junction
temperature value of 150°C.
The EN5319QI is guaranteed to support the full 2A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN5319QI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 1.5A
First calculate the output power.
POUT = 3.3V x 1.5A = 4.95W
Next, determine the input power based on the
efficiency (η) shown in Figure 6.
Figure 6: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 1.5A, η ≈ 94%
η = POUT / PIN = 94% = 0.94
PIN = POUT / η
PIN ≈ 4.95W / 0.94 ≈ 5.3W
The power dissipation (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 5.3W – 4.95W ≈ 0.35W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN5319QI has
a θJA value of 36 ºC/W without airflow.
Determine the change in die temperature (ΔT)
based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.35W x 36°C/W = 12.6°C ≈ 13°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 13°C ≈ 38°C
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (TAMAX) allowed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 13°C ≈ 112°C
The ambient temperature can actually rise by
another 87°C, bringing it to 112°C before the
device will reach TJMAX. This indicates that the
EN5319QI can support the full 1.5A output current
range up to approximately 112°C ambient
temperature given the input and output voltage
conditions. Note that the efficiency will be slightly
lower at higher temperatures and these calculations
are estimates.
0
10
20
30
40
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
EFFICIENCY (%)
OUTPUT CURRENT (A)
VOUT = 3.3V CONDITIONS
VIN = 5V
CONDITIONS
VIN = 5V
CONDITIONS
VIN = 5V
CONDITIONS
VIN = 5V
~94%
08325 March 20, 2013 Rev: A
EN5319QI
©Enpirion 2013 all rights reserved, E&OE www.enpirion.com, Page 16
Engineering Schematic
Figure 7. Engineering Schematic with Critical Components
08325 March 20, 2013 Rev: A
EN5319QI
©Enpirion 2013 all rights reserved, E&OE www.enpirion.com, Page 17
Layout Recommendations
Figure 8. Optimized Layout Recommendations
This layout only shows the critical components
and top layer traces for minimum footprint with
ENABLE as a separate signal. Alternate
ENABLE configurations & the POK pin need to
be connected and routed according to
customer application. Please see the Gerber
files at www.enpirion.com for details on all
layer.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN5319QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN5319QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 3: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 4: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 3) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops.
Recommendation 5: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 8 this connection is made at the input
capacitor. Connect a 1µF capacitor from the AVIN
pin to AGND.
Recommendation 6: The layer 1 metal under the
device must not be more than shown in Figure 8.
See the section regarding exposed metal on bottom
of package. As with any switch-mode DC/DC
converter, try not to run sensitive signal or control
lines underneath the converter package on other
layers.
Recommendation 7: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node.
Recommendation 8: Keep RA, CA, RB close to the
VFB pin (See Figures 6). The VFB pin is a high-
impedance, sensitive node. Keep the trace to this
pin as short as possible. Whenever possible,
connect RB directly to the AGND pin instead of
going through the GND plane.
Recommendation 9: Enpirion provides schematic
and layout reviews for all customer designs. Please
contact local sales representatives for references to
Enpirion Applications Engineering support
(techsupport@enpirion.com).
08325 March 20, 2013 Rev: A
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08325 March 20, 2013 Rev: A
EN5319QI
©Enpirion 2013 all rights reserved, E&OE www.enpirion.com, Page 19
Recommended PCB Footprint
Figure 10. EN5319 PCB Footprint (Top View)
The solder stencil aperture for the thermal pads (shown in blue) is based on Enpirion’s manufacturing recommendations
08325 March 20, 2013 Rev: A
©En
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