SD5000I-2
Vishay Siliconix
Document Number: 70296
S-02889—Rev. J, 21-Dec-00 www.vishay.com
1
N-Channel Lateral DMOS FETs
(Available Only In Extended Hi-Rel Flow)
PRODUCT SUMMARY
V(BR)DS Min (V) VGS(th) Max (V) rDS(on) Max (W) Crss Max (pF) tON Max (ns)
20 1.5 70 @ VGS = 5 V 0.5 2
FEATURES BENEFITS APPLICATIONS
DQuad SPST Switch with Zener Input Protection
DLow Interelectrode Capacitance and Leakage
DUltra-High Speed Switching—tON: 1 ns
DUltra-Low Reverse Capacitance: 0.2 pF
DLow Guaranteed rDS @ 5 V
DLow Turn-On Threshold Voltage
DHigh-Speed System Performance
DLow Insertion Loss at High
Frequencies
DLow Transfer Signal Loss
DSimple Driver Requirement
DSingle Supply Operation
DFast Analog Switch
DFast Sample-and-Holds
DPixel-Rate Switching
DVideo Switch
DMultiplexer
DDAC Deglitchers
DHigh-Speed Driver
DESCRIPTION
The SD5000I-2 monolithic switch features four individual
double-diffused enhancement-mode MOSFETs built on a
common substrate. This bidirectional device provides low
on-resistance and low interelectrode capacitances to
minimize insertion loss and crosstalk.
Built on Vishay Siliconix’ proprietary DMOS process, the
SD5000I-2 utilizes lateral construction to achieve low
capacitance and ultra-fast switching speeds. For manufacturing
reliability, these devices feature poly-silicon gates protected by
Zener diodes.
The SD5000I is available only in the “–2” extended hi-rel flow.
The Vishay Siliconix “–2” flow complies with the requirements
of MIL-PRF-19500 for JANTX discrete devices.
S2S1
SUBSTRATE NC
G2G1
D2D1
D3
G3
S3
D4
G4
S4
Dual-In-Line
Sidebraze
Top View
11
12
13
14
2
3
4
1
8
9
105
6
7
Applications Information—See Applications Note AN502
SD5000I-2
Vishay Siliconix
www.vishay.com
2 Document Number: 70296
S-02889—Rev. J, 21-Dec-00
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Gate-Drain, Gate-Source Voltage +30 V/–25 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-Substrate Voltage +30 V/–0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-Source Voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-Source-Substrate Voltage 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain Current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead Temperature (1/16” from case for 10 seconds) 300_C. . . . . . . . . . . . . .
Storage Temperature –65 to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Junction Temperature –55 to 150_C. . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipationa, b: (Package) 500 mW. . . . . . . . . . . . . . . . . . . . . . . . . .
(Each Device) 300 mW. . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Derate 4 mW/_C above 25_C
SPECIFICATIONSa
Limits
Parameter SymbolbTest ConditionsbMin TypcMax Unit
Static
Drain-Source Breakdown Voltage V(BR)DS VGS = VBS = –5 V, ID = 10 nA 20 30
Source-Drain Breakdown Voltage V(BR)SD VGD = VBD = –5 V, IS = 10 nA 20 22
Drain-Substrate Breakdown Voltage V(BR)DBO VGB = 0 V, ID = 10 nA, Source Open 25 35 V
Source-Substrate
Breakdown Voltage V(BR)SBO VGB = 0 V, IS = 10 mA, Drain Open 25 35
VDS = 10 V 0.4
Drain-Source Leakage IDS(off) VGS = VBS = –5 V VDS = 15 V 0.7
DS(off) GS BS VDS = 20 V 0.9 10
VSD = 10 V 0.5 nA
Source-Drain Leakage ISD(off) VGD = VBD = –5 V VSD = 15 V 0.8
SD(off) GD BD VSD = 20 V 1 10
Gate Leakage IGBS VDB = VSB = 0 V, VGB = 30V 0.01 100
Threshold Voltage VGS(th) VDS = VGS , ID = 1 mA, VSB = 0 V 0.1 0.8 1.5 V
VGS = 5 V 58 70
VGS = 10 V 38
Drain-Source On-Resistance rDS(on) VSB = 0 V
I = 1 mA VGS = 15 V 30 W
ID = 1 mA VGS = 20 V 26
Resistance Match DrDS(on) VGS = 5 V 1 5
Dynamic
Forward Transconductance gfs VDS = 10 V, VSB = 0 V, ID = 20 mA, f = 1 kHz 10 12 mS
Gate-Node Capacitance C(GS+GD+GB) 2.5 3.5
Drain-Node Capacitance C(GD+DB) V
DS
= 10 V, f = 1 MHz 2.0 3
Source-Node Capacitance C(GS+SB)
VDS = 10 V, f = 1 MHz
VGS = VBS = –15 V 3.7 5 pF
Reverse Transfer Capacitance crss 0.2 0.5
Crosstalk f= 3 kHz –107 dB
Switching
td(on) 0.5 1
Turn-On Time trV
SB
= 5 V, V
IN
0 to 5 V, R
G
= 25 W0.6 1
td(off)
VSB = 5 V, VIN 0 to 5 V, RG = 25
W
VDD = 5 V, RL = 680 W2ns
Turn-Off Time tf6
Notes:
a. TA = 25_C unless otherwise noted. DMCA
b. B is is the body (substrate) and V(BR) is breakdown.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
SD5000I-2
Vishay Siliconix
Document Number: 70296
S-02889—Rev. J, 21-Dec-00 www.vishay.com
3
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
On-Resistance vs. Temperature
On-Resistance vs. Gate-Source Voltage
Common-Source Forward Transconductance
vs. Drain Current
300
04812 20
240
180
60
016
120 5 V
10 V
1 100
20
16
12
8
4
010
25_C
VDS = 15 V
VBS = 0 V
TA = 55_C
125_C
100
–60 6020–20 100 140
80
60
40
20
0
TA – Temperature (_C) ID – Drain Current (mA)
Leakage Current vs. Applied Voltage
Applied Voltage (V)
020
10 nA
1 nA
100 pA
10 pA
1 pA
Leakage
4 8 12 16
VGS = 4 V
IGSS (Diode)
ID(off)
ISBO
IS(off)
ID (off) @ VGS = VBG = –5 V
IS(off) @ VGD = VBD = –5V
ISBO @ VGB = 0 V, Drain Open
ID = 5 mA, VBS = 0 V
VGS = 5 V
15 V 10 V
20 V
gfs – Forward Transconductance (mS)
VSB – Source-Substrate Breakdown Voltage (V)
– On-Resistance (rDS(on) W)– On-Resistance (rDS(on) W)
Threshold Voltage vs. Substrate-Source Voltage Leakage Current vs. Temperature
5
0–4–20
4
3
2
1
0
H
L
VGS = VDS = VTH
ID = 1 mA
TA = 25_C
100
10
125 50 75 100 125
IGSS
(Diode)
TA – Temperature (_C)
–8–12 –16
– Gate-Source Threshold Voltage (V)VGS(th)
ID(off) @ VGS = VBS = –5 V, VDS = 10 V
IS(off) @ VGD = VBD = –5 V, VSD = 10 V
IGSS @ VGS = 10 V
ISBO @ VSB = 10 V
Drain Open
Leakage (nA)
ISBO
ID(off)
IS(off)
VBS – Body-Source Voltage (V)
SD5000I-2
Vishay Siliconix
www.vishay.com
4 Document Number: 70296
S-02889—Rev. J, 21-Dec-00
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Body Leakage Current vs. Drain-Body Voltage
012168420
– Body Leakage
IB
VBS – Body-Source Voltage (V)
Input Admittance Forward Admittance
Capacitance vs. Gate-Source Voltage
10
04 20
8
6
4
2
0
VDS = 10 V, f = 1 MHz
VGS = VBS
Capacitance (pF)
100
10
1
0.1 100 1000
bis
gis
(mS)
VDS = 10 V
ID = 10 mA
TA = 25_C
100
10
1
0.1 100 1000
(mS)
VDS = 10 V
ID = 10 mA
TA = 25_C
VGS – Gate-Source Voltage (V)
f – Frequency (MHz) f – Frequency (MHz)
81216
200 500 200 500
ID = 13 mA
1 mA
100 mA
100 nA
1 nA
100 pA
1 pA
10 mA
1 mA
10 nA
10 pA
gfs
–bfs
C(GS+SB)
C(GS+GD+GB)
C(GD+DB)
C(DG)
Reverse Admittance Output Admittance
1
0.1
0.01
0.001100 1000
(mS)
VDS = 10 V
ID = 10 mA
TA = 25_C
100
10
1
0.1 100 1000
(mS)
VDS = 10 V
ID = 10 mA
TA = 25_C
f – Frequency (MHz) f – Frequency (MHz)
200 500 200 500
brs
+grg
–grg
bog
gog
SD5000I-2
Vishay Siliconix
Document Number: 70296
S-02889—Rev. J, 21-Dec-00 www.vishay.com
5
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Output Conductance vs. Drain Current
Switching Characteristics Output Characteristics
700
600
500
001 7
400
300
200
100
256
tf – Fall Time (ns)
RL(
50
04 20
40
30
20
10
0
VBS = 0 V
TA = 25_C
1.0
0204
0.8
0.6
0.4
0.2
0
VBS = 0 V
f = 1 kHz
VDS – Drain-Source Voltage (V)
ID – Drain Current (mA)
– Drain Current (mA)
ID
81216
81216
Threshold Voltage vs. Temperature
5
–60 60 10020–20 140
4
3
2
1
0
TA – Temperature (_C)
4 V
3 V
2 V
VGS = 5 V
gos – Output Conductance (mS)
– Gate-Source Threshold Voltage (V)VGS(th)
VDS = 5 V
10 V
15 V
VGS = VDS = VTH
ID = 1 mA
–5 V
–1 V –0.5 V
0 V
VBS = –10 V
)W
SWITCHING TIME TEST CIRCUIT
510 WRL
51 W
VIN
To
Scope +VDD
VOUT
To Scope
0 V
50%
10%
90%
td(on) td(off)
trtf
+5 V
0 V
+VDD
VIN
VOUT
Input pulse: td, tr < 1 ns
Pulse width: 100 ns
Rep rate: 1 MHz
Sampling Scope
tr < 360 ps
RIN = 1 MW
CIN = 2 pF
BW = 500 MHz
50%
