K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM Document Title 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft Jan. 18. 1999 Preliminary 0.1 1. Update ICC & ISB values. 2. Remove tCYC 117MHz ( -85 ) May. 27. 1999 Preliminary 0.2 1. Change ISB value from 150mA to 110mA at -67. 2. Change ISB value from 130mA to 90mA at -72 . 3. Change ISB value from 120mA to 80mA at -10 . Sep. 04. 1999 Preliminary 0.3 1. Changed DC condition at Icc and parameters Icc ; from 420mA to 400mA at -67, from 400mA to 380mA at -72, from 350mA to 320mA at -10, Nov. 19. 1999 Preliminary 1.0 1. Final Spec Release. Dec. 08. 1999 Final 2.0 1.Remove tCYC 100MHz . Feb. 23. 2001 Final 3.0 1. Change Access time( tCD & tOE) tCD & tOE ; from 3.8ns to 3.0ns at -15 from 4.0ns to 3.5ns at -14 May. 23. 2001 Final 4.0 1. Add tCYC 167MHz ( -16 ) May. 30. 2001 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION * Synchronous Operation. * 2 Stage Pipelined operation with 4 Burst. * On-Chip Address Counter. * Self-Timed Write Cycle. * On-Chip Address and Control Registers. * VDD= 3.3V +0.165V/-0.165V Power Supply. * I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. * 5V Tolerant Inputs Except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 2cycle Disable. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * TTL-Level Three-State Output. * 100-TQFP-1420A Package The K7A163601M and K7A161801M are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW , LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW , and each byte write is performed by the combination of WE x and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor( ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system s burst sequence and are controlled by the burst address advance(ADV ) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7A163601M and K7A161801M are fabricated using SAMSUNG s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. FAST ACCESS TIMES Symbol -16 -15 -14 Unit Cycle Time PARAMETER t CYC 6.0 6.7 7.2 ns Clock Access Time t CD 3.0 3.0 3.5 ns Output Enable Access Time t OE 3.0 3.0 3.5 ns LOGIC BLOCK DIAGRAM CLK LBO BURST CONTROL A 0~A 18 or A 0~A19 GW BW ADDRESS REGISTER A2 ~A 18 or A 2~A 19 DATA-IN REGISTER CO NTR OL RE G IS TE R CS 2 512Kx36 , 1Mx18 MEMORY ARRAY A 0~A1 A0 ~A 1 ADSP CS 1 CS 2 BURST ADDRESS COUNTER LOGIC CO NTRO L REG IS TER ADV ADSC OUTPUT REGISTER CONTROL LOGIC BUFFER WEx (x=a,b,c,d or a,b) OE ZZ DQa 0 ~ DQd 7 or DQa0 ~ DQb7 DQPa,DQPb DQPa ~ DQPd -2- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM A6 A7 CS1 CS2 WEd WEc WEb WEa CS2 VDD VSS CLK GW BW OE ADSC ADSP ADV A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 43 44 45 46 47 48 49 50 A10 A11 A12 A13 A14 A15 A16 41 VDD A17 40 V SS 42 39 N.C. A18 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7A163601M(512Kx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 L BO DQPc DQc 0 DQc 1 V DDQ VSSQ DQc 2 DQc 3 DQc 4 DQc 5 VSSQ V DDQ DQc 6 DQc 7 N.C. VDD N.C. VSS DQd0 DQd1 V DDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ V DDQ DQd6 DQd7 DQPd 10 0 PIN CONFIGURATION(TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb 7 DQb 6 VDDQ VSSQ DQb 5 DQb 4 DQb 3 DQb 2 VSSQ VDDQ DQb 1 DQb 0 VSS N.C. VDD ZZ DQa 7 DQa 6 VDDQ VSSQ DQa 5 DQa 4 DQa 3 DQa 2 VSSQ VDDQ DQa 1 DQa 0 DQPa PIN NAME SYMBOL A0 - A18 PIN NAME TQFP PIN NO. Address Inputs 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50,81,82,99,100 ADV Burst Address Advance 83 ADSP Address Status Processor 84 ADSC Address Status Controller 85 CLK Clock 89 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 WEx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 GW Global Write Enable 88 BW Byte Write Enable 87 ZZ Power Down Input 64 LBO Burst Mode Control 31 SYMBOL PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) Ground 15,41,65,91 17,40,67,90 N.C. No Connect 14,16,38,39,66 DQa0~a 7 DQb0~b 7 DQc 0~c7 DQd0~d 7 DQPa~P d Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply (3.3V or 2.5V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Note : 1. A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -3- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM ADSP ADV A8 A9 83 82 81 49 50 A16 A17 ADSC 48 OE 85 A15 BW 86 84 GW 87 47 CLK 88 A14 VSS 89 46 VDD 90 A13 CS2 91 45 WEa 92 A12 WEb 93 44 N.C. 94 A11 N.C. 95 43 CS2 96 A18 CS1 97 42 A7 98 A19 A6 99 100 Pin TQFP (20mm x 14mm) 31 32 33 34 35 36 37 38 39 40 41 A4 A3 A2 A1 A0 N.C. N.C. V SS VDD K7A161801M(1Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 L BO N.C. N.C. N.C. V DDQ VSSQ N.C. N.C. DQb 0 DQb 1 VSSQ V DDQ DQb 2 DQb 3 N.C. VDD N.C. VSS DQb 4 DQb 5 V DDQ VSSQ DQb 6 DQb 7 DQPb N.C. VSSQ V DDQ N.C. N.C. N.C. 10 0 PIN CONFIGURATION (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa 7 DQa 6 VSSQ VDDQ DQa 5 DQa 4 VSS N.C. VDD ZZ DQa 3 DQa 2 VDDQ VSSQ DQa 1 DQa 0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A0 - A19 Address Inputs ADV ADSP ADSC CLK CS1 CS2 CS2 WEx(x=a,b) OE GW BW ZZ LBO Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control TQFP PIN NO. SYMBOL 32,33,34,35,36,37,42 43,44,45,46,47,48,49 50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) Ground 15,41,65,91 17,40,67,90 N.C. No Connect 1,2,3,6,7,14,16,25,28,29 30,38,39,51,52,53,56,57 66,75,78,79,95,96 DQa0 ~ a 7 DQb0 ~ b 7 DQPa, Pb Data Inputs/Outputs 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 VDDQ Output Power Supply (3.3V or 2.5V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Note : 1. A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM FUNCTION DESCRIPTION The K7A163601M and K7A161801M are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV . When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to control signals by disabling CS1. All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WE x when GW is high. Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WE x are sampled Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the next address of burst, if both WE x and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte write enable signals( WEa, WEb, WEc or WEd) sampled low. The WE a control DQa0 ~ DQa 7 and DQPa, WEb controls DQb 0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd 7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows; ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high). Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the st ate of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is selected. BURST SEQUENCE TABLE LBO PIN (Interleaved Burst) Case 1 HIGH A1 0 0 1 1 First Address Fourth Address Case 2 A0 0 1 0 1 A1 0 0 1 1 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 1 0 0 BQ TABLE LBO PIN A0 1 0 1 0 (Linear Burst) Case 1 LOW Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 First Address Fourth Address Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. ASYNCHRONOUS TRUTH TABLE OPERATION ZZ OE I/O Status Sleep Mode H X High-Z L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Read Notes 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. -5- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS 2 CS2 ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED Operation H X X X L X X N/A Not Selected L L X L X X X N/A Not Selected L X H L X X X N/A Not Selected L L X X L X X N/A Not Selected L X H X L X X N/A Not Selected L H L L X X X External Address Begin Burst Read Cycle L H L H L X L External Address Begin Burst Write Cycle L H L H L X H External Address Begin Burst Read Cycle X X X H H L H Next Address Continue Burst Read Cycle H X X X H L H Next Address Continue Burst Read Cycle X X X H H L L Next Address Continue Burst Write Cycle H X X X H L L Next Address Continue Burst Write Cycle X X X H H H H Current Address Suspend Burst Read Cycle H X X X H H H Current Address Suspend Burst Read Cycle X X X H H H L Current Address Suspend Burst Write Cycle H X X X H H L Current Address Suspend Burst Write Cycle Notes : 1. X means "Dont Care". 2. The rising edge of clock is symbolized by . 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE (x36) GW BW WE a WE b WEc WE d OPERATION H H X X X X READ H L H H H H READ H L L H H H WRITE BYTE a H L H L H H WRITE BYTE b H L H H L L WRITE BYTE c and d H L L L L L WRITE ALL BYTEs L X X X X X WRITE ALL BYTEs Notes : 1. X means "Don t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(). WRITE TRUTH TABLE (x18) GW BW WEa WEb OPERATION H H X X READ H L H H READ H L L H WRITE BYTE a H L H L WRITE BYTE b H L L L WRITE ALL BYTEs L X X X WRITE ALL BYTEs Notes : 1. X means "Don t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ). -6- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM PASS-THROUGH TRUTH TABLE PREVIOUS CYCLE OPERATION PRESENT CYCLE WRITE OPERATION NEXT CYCLE CS1 WRITE OE Write Cycle, All bytes Address=An-1, Data=Dn-1 All L Initiate Read Cycle Address=An Data=Qn-1 for all bytes L H L Read Cycle Data=Qn Write Cycle, All bytes Address=An-1, Data=Dn-1 All L No new cycle Data=Qn-1 for all bytes H H L No carryover from previous cycle Write Cycle, All bytes Address=An-1, Data=Dn-1 All L No new cycle Data=High-Z H H H No carryover from previous cycle Write Cycle, One byte Address=An-1, Data=Dn-1 One L Initiate Read Cycle Address=An Data=Qn-1 for one byte L H L Read Cycle Data=Qn Write Cycle, One byte Address=An-1, Data=Dn-1 One L No new cycle Data=Qn-1 for one byte H H L No carryover from previous cycle Note : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle. ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT VDD -0.3 to 4.6 V V DDQ VDD V V Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to V SS Voltage on Input Pin Relative to V SS VIN -0.3 to 4.6 Voltage on I/O Pin Relative to V SS V IO -0.3 to VDDQ+0.5 V Power Dissipation PD 1.6 W Storage Temperature T STG -65 to 150 C Operating Temperature TOPR 0 to 70 C Storage Temperature Range Under Bias T BIAS -10 to 85 C *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O(0 C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. Max Unit VDD 3.135 3.3 3.465 V V DDQ 3.135 3.3 3.465 V V SS 0 0 0 V OPERATING CONDITIONS at 2.5V I/O(0 C TA 70C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. Max Unit VDD 3.135 3.3 3.465 V V DDQ 2.375 2.5 2.9 V V SS 0 0 0 V CAPACITANCE*(TA=25C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION Min Max Unit C IN VIN=0V - 7 pF C OUT VOUT=0V - 9 pF *Note : Sampled not 100% tested. -7- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM DC ELECTRICAL CHARACTERISTICS(V DD=3.3V+0.165V/-0.165V, T A =0C to +70C) PARAMETER SYMBOL Input Leakage Current(except ZZ) I IL VDD =Max ; V IN=V SS to VDD Output Leakage Current I OL Output Disabled, V OUT=V SS to V DDQ Operating Current I CC I SB Standby Current TEST CONDITIONS Device Selected, I OUT=0mA, ZZ VIL , Cycle Time t CYC Min Device deselected, I OUT=0mA, ZZ VIL, f=Max, All Inputs0.2V or VDD-0.2V MIN MAX UNIT -2 +2 A A -2 +2 -16 - 420 -15 - 400 -14 - 380 -16 - 120 -15 - 110 -14 - 90 NOTES mA 1,2 mA I SB1 Device deselected, I OUT=0mA, ZZ0.2V, f =0, All Inputs=fixed (VDD -0.2V or 0.2V) - 30 mA I SB2 Device deselected, IOUT=0mA, ZZ VDD -0.2V, f=Max, All Inputs VIL or VIH - 30 mA Output Low Voltage(3.3V I/O) V OL IOL =8.0mA - 0.4 V Output High Voltage(3.3V I/O) VOH IOH =-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) V OL IOL =1.0mA - 0.4 V Output High Voltage(2.5V I/O) VOH IOH =-1.0mA 2.0 - V Input Low Voltage(3.3V I/O) V IL -0.3* 0.8 V Input High Voltage(3.3V I/O) VIH 2.0 VDD+0.5** V Input Low Voltage(2.5V I/O) V IL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 2.0 VDD+0.5** V 3 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH =V D D Q +0.3V V IH VSS VS S - 1.0V 20% tC Y C (MIN) TEST CONDITIONS (V DD=3.3V+0.165V/-0.165V ,VDDQ=3.3V+0.165/-0.165V or VDD =3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, T A =0to70C) Parameter Value Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2 Output Load See Fig. 1 -8- May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM Output Load(A) Output Load(B), (for tLZC, t LZOE, tHZOE & t HZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50 Dout Zo=50 30pF* VL=1.5V for 3.3V I/O V DDQ/2 for 2.5V I/O 319 / 1667 Dout 353 / 1538 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(V DD=3.3V+0.165V/-0.165V, T A=0C to +70C) -16 PARAMETER Cycle Time SYMBOL Min -15 Max MIN -14 MAX MIN MAX UNIT t CYC 6.0 - 6.7 - 7.2 - ns Clock Access Time t CD - 3.0 - 3.0 - 3.5 ns Output Enable to Data Valid t OE - 3.0 - 3.0 - 3.5 ns Clock High to Output Low-Z t LZC 0 - 0 - 0 - ns Output Hold from Clock High tOH 1.5 - 1.5 - 1.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z t HZOE - 3.0 - 3.0 - 3.5 ns Clock High to Output High-Z tHZC 1.5 3.0 1.5 3.0 1.5 3.5 ns Clock High Pulse Width t CH 2.1 - 2.3 - 2.5 - ns Clock Low Pulse Width t CL 2.1 - 2.3 - 2.5 - ns Address Setup to Clock High t AS 1.5 - 1.5 - 2.0 - ns Address Status Setup to Clock High t SS 1.5 - 1.5 - 2.0 - ns Data Setup to Clock High t DS 1.5 - 1.5 - 2.0 - ns Write Setup to Clock High (GW , BW, WEX ) t WS 1.5 - 1.5 - 2.0 - ns t ADVS 1.5 - 1.5 - 2.0 - ns Chip Select Setup to Clock High tCSS 1.5 - 1.5 - 2.0 - ns Address Hold from Clock High t AH 0.5 - 0.5 - 0.5 - ns Address Status Hold from Clock High t SH 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High t DH 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (GW , BW, WEX ) t WH 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High t ADVH 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High t CSH 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - cycle Address Advance Setup to Clock High Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. 4. At any given voltage and temperature, tH Z C is less than tL Z C -9- May 2001 Rev 4.0 - 10 - Data O ut OE ADV CS WRITE ADDRES S ADSC ADSP CLOCK t CSS tAS tSS A1 t ADVS t CSH tWS t AH t SH Q1 -1 A2 t HZOE t SH Q 2-1 t CD t OH Q 2-2 A3 Q2-3 (ADV IN SERT S WAIT ST AT E) BURST CONTIN UED WIT H NEW BASE AD DRESS t CYC tCL NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L CS = L means CS 1 = L, CS 2 = H and CS2 = L CS = H means CS1 = H, or CS 1 = L and CS2 = H, or CS 1 = L, and CS 2 = L t LZOE t OE t ADVH t WH tSS tCH TIMING WAVEFORM OF READ CYCLE Q 2-4 Q3 -1 Q3- 2 Q3 -3 Undefined Dont Care Q 3-4 tH ZC K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM May 2001 Rev 4.0 - 11 - Data Out Data In OE ADV CS WRITE ADDRESS ADS C ADS P CLO CK Q0 -3 t CSS t AS t SS t CSH tH ZOE Q0 -4 A1 tAH t SH D1-1 t CL tC YC t CH A2 D2-1 D2 -2 (ADV SUSPEND S BUR ST ) D2-2 D2-3 (ADSC EXTENDED BURST ) TIMING WAVEFORM OF WRTE CYCLE D2- 4 D3-1 A3 t DS tADVS tWS t SS D3 -2 tDH t ADVH t WH t SH D3 -3 Undefined Dont Care D3-4 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM May 2001 Rev 4.0 - 12 - Data Out Data In OE ADV CS WRITE ADDRESS ADS P CLO CK t HZC tSS A1 t SH tCD tLZ C t AS Q1- 1 A2 tCL t HZOE t DS t ADVS t WS t CYC t AH tCH D2-1 t DH tADVH t WH t OE t LZOE A3 Q 2-1 Q 3-1 Q 3-2 tOH Q3 -3 TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH) Undefined Dont Care Q 3-4 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM May 2001 Rev 4.0 - 13 - Data In Data Out OE ADV CS WRITE ADDRESS ADSC CLOCK tC SS t SS A1 tC SH t SH t OE tLZ OE A2 Q 1-1 A3 Q 2-1 A4 Q 3-1 Q 4-1 tHZ OE D5-1 A5 t DS tWS D6-1 A6 t DH t WH D7-1 A7 tC L tWS t CYC t CH A8 t CD t WH Q 7-1 A9 TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH) Q 8-1 Undefined Dont Care Q9- 1 tOH K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM May 2001 Rev 4.0 - 14 - ZZ Data Out Data In OE ADV CS WRITE ADDRESS ADSC ADSP CLOCK tCSS t AS tSS A1 tCSH t AH t SH tOE t LZOE Q 1-1 Z Z Setup Cycle t PDS t HZC Sleep State t CL tPUS ZZ R ecovery Cycle t CYC tCH TIMING WAVEFORM OF POWER DOWN CYCLE t WS Normal Operation Mode t HZOE A2 D2 -1 t WH Undefined Dont Care D2-2 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic. I/O[0:71] Data Address A[0:19] A[19] A[0:18] A[19] A[0:18] Address Data CLK Address Data CS2 CS2 CS2 CLK Microprocessor Address ADSC CLK CS2 512Kx36 SPB SRAM WEx OE Cache Controller ADSC WEx (Bank 0) CS1 ADV CLK 512Kx36 SPB SRAM (Bank 1) OE CS1 ADV ADSP ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock t SS t SH ADSP t AS ADDRESS [0:n*] A1 t AH A2 tWS t WH WRITE t CSS tCSH CS 1 Bank 0 is selected by CS 2, and Bank 1 deselected by CS 2 A n+1* t ADVS Bank 0 is deselected by CS 2, and Bank 1 selected by CS 2 t ADVH ADV OE t OE Data Out (Bank 0) tLZOE tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Data Out (Bank 1) *Notes : n = 14 32K depth , 16 128K depth , 18 512K depth , 15 64K depth 17 256K depth 19 1M depth - 15 - Q2-1 Q2-2 Q2-3 Q2-4 Dont Care Undefined May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM APPLICATION INFORMATION DEPTH EXPANSION The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic. I/O[0:71] Data Address A[20] A[0:20] A[20] A[0:19] Address Data CLK Address Data CS2 CS2 CS2 Microprocessor CLK Address ADSC CLK A[0:19] CS2 1Mx18 SPB SRAM CLK 1Mx18 SPB SRAM ADSC WEx WEx (Bank 0) Cache Controller (Bank 1) OE OE CS1 CS1 ADV ADSP ADV ADSP ADS INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH) Clock t SS t SH ADSP t AS ADDRESS [0:n*] A1 t AH A2 tWS t WH WRITE t CSS tCSH CS 1 Bank 0 is selected by CS 2, and Bank 1 deselected by CS 2 A n+1* t ADVS Bank 0 is deselected by CS 2, and Bank 1 selected by CS 2 t ADVH ADV OE t OE Data Out (Bank 0) Data Out (Bank 1) tHZC tLZOE Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC *Notes : n = 14 16 18 20 32K depth , 128K depth , 512K depth , 2M depth 15 64K depth 17 256K depth 19 1M depth - 16 - Q2-1 Q2-2 Q2-3 Q2-4 Dont Care Undefined May 2001 Rev 4.0 K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8 22.00 0.30 0.10 0.127+- 0.05 20.00 0.20 16.00 0.30 14.00 0.20 0.10 MAX (0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58) 1.40 0.10 1.60 MAX 0.50 0.10 - 17 - 0.05 MIN May 2001 Rev 4.0