74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Commercial 74F112PC 74F112SC (Note 1) 74F112SJ (Note 1) Package Number Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features Y Guaranteed 4000V minimum ESD protection Package Description 16-Lead (0.300x Wide) Molded Dual-In-Line 16-Lead (0.150x Wide) Molded Small Outline, JEDEC 16-Lead (0.300x Wide) Molded Small Outline, EIAJ N16E M16A M16D Note 1: Devices also available in 13x reel. Use suffix e SCX and SJX. Logic Symbols Connection Diagram Pin Assignment for SOIC TL/F/9472-3 TL/F/9472 - 4 IEEE/IEC TL/F/9472 - 1 TL/F/9472 - 6 TRI-STATEE is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9472 RRD-B30M115/Printed in U. S. A. 74F112 Dual JK Negative Edge-Triggered Flip-Flop August 1995 Unit Loading/Fan Out 74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs 1.0/1.0 1.0/4.0 1.0/5.0 1.0/5.0 50/33.3 20 mA/b0.6 mA 20 mA/b2.4 mA 20 mA/b3.0 mA 20 mA/b3.0 mA b 1 mA/20 mA Truth Table Inputs Outputs SD CD CP J K Q Q L H L H H H H H L L H H H H X X X K K K K X X X h l h l X X X h h l l H L H Q0 L H Q0 L H H Q0 H L Q0 H(h) e HIGH Voltage Level L(l) e LOW Voltage Level X e Immaterial K e HIGH-to-LOW Clock Transition Q0(Q0) e Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram (One Half Shown) TL/F/9472 - 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions b 65 C to a 150 C Storage Temperature Ambient Temperature under Bias b 55 C to a 125 C Junction Temperature under Bias Plastic b 55 C to a 175 C b 55 C to a 150 C VCC Pin Potential to Ground Pin Free Air Ambient Temperature Commercial 0 C to a 70 C Supply Voltage Commercial a 4.5V to a 5.5V b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage Typ Units VCC Conditions Max 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min IIN e b18 mA V Min IOH e b1 mA IOH e b1 mA VCD Input Clamp Diode Voltage VOH Output HIGH Voltage 74F 10% VCC 74F 5% VCC VOL Output LOW Voltage 74F 10% VCC 0.5 V Min IOL e 20 mA IIH Input HIGH Current 74F 5.0 mA Max VIN e 2.7V IBVI Input HIGH Current Breakdown Test 74F 7.0 mA Max VIN e 7.0V ICEX Output HIGH Leakage Current 74F 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All other pins grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All other pins grounded IIL Input LOW Current b 0.6 b 2.4 b 3.0 mA Max VIN e 0.5V (Jn, Kn) VIN e 0.5V (CPn) VIN e 0.5V (CDn, SDn) 2.5 2.7 4.75 IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V ICCH Power Supply Current b 60 12 19 mA Max VO e HIGH ICCL Power Supply Current 12 19 mA Max VO e LOW 3 AC Electrical Characteristics Symbol Parameter 74F 74F TA e a 25 C VCC e a 5.0V CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Units Min Typ fmax Maximum Clock Frequency 85 105 Max tPLH tPHL Propagation Delay CPn to Qn or Qn 2.0 2.0 5.0 5.0 6.5 6.5 2.0 2.0 7.5 7.5 ns tPLH tPHL Propagation Delay CDn, SDn to Qn, Qn 2.0 2.0 4.5 4.5 6.5 6.5 2.0 2.0 7.5 7.5 ns 80 MHz AC Operating Requirements Symbol Parameter 74F 74F TA e a 25 C VCC e a 5.0V TA, VCC e Com Min Max Min Units Max ts(H) ts(L) Setup Time, HIGH or LOW Jn or Kn to CPn 4.0 3.0 5.0 3.5 th(H) th(L) Hold Time, HIGH or LOW Jn or Kn to CPn 0 0 0 0 tw(H) tw(L) CP Pulse Width HIGH or LOW 4.5 4.5 5.0 5.0 ns tw(L) Pulse Width, LOW CDn or SDn 4.5 5.0 ns trec Recovery Time SDn, CDn to CP 4.0 5.0 ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 112 S C X Temperature Range Family 74F e Commercial Special Variations X e Devices shipped in 13x reel Device Type Temperature Range C e Commercial (0 C to a 70 C) Package Code P e Plastic DIP S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ 4 Physical Dimensions inches (millimeters) 16-Lead (0.150x Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M16A 16-Lead (0.300x Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number M16D 5 74F112 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300x Wide) Molded Dual-In-Line Package (P) NS Package Number N16E LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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