TL/F/9472
74F112 Dual JK Negative Edge-Triggered Flip-Flop
August 1995
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’F112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trig-
gering occurs at a voltage level of the clock and is not di-
rectly related to the transition time. The J and K inputs can
change when the clock is in either state without affecting
the flip-flop, provided that they are in the desired state dur-
ing the recommended setup and hold times relative to the
falling edge of the clock. A LOW signal on SDor CDpre-
vents clocking and forces Q or Q HIGH, respectively. Simul-
taneous LOW signals on SDand CDforce both Q and Q
HIGH.
Asynchronous Inputs:
LOW input to SDsets Q to HIGH level
LOW input to CDsets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CDand SDmakes both Q
and Q HIGH
Features
YGuaranteed 4000V minimum ESD protection
Commercial Package Package Description
Number
74F112PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
74F112SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F112SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
Note 1: Devices also available in 13×reel. Use suffix eSCX and SJX.
Logic Symbols Connection Diagram
TL/F/9472–3 TL/F/9472–4
IEEE/IEC
TL/F/9472–6
Pin Assignment
for SOIC
TL/F/9472–1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Unit Loading/Fan Out
74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
J1,J
2
,K
1
,K
2Data Inputs 1.0/1.0 20 mA/b0.6 mA
CP1,CP
2Clock Pulse Inputs (Active Falling Edge) 1.0/4.0 20 mA/b2.4 mA
CD1,C
D2 Direct Clear Inputs (Active LOW) 1.0/5.0 20 mA/b3.0 mA
SD1,S
D2 Direct Set Inputs (Active LOW) 1.0/5.0 20 mA/b3.0 mA
Q1,Q
2
,Q
1
,Q
2Outputs 50/33.3 b1 mA/20 mA
Truth Table
Inputs Outputs
SDCDCP JK Q Q
LH XXXHL
HL XXXLH
LL XXXHH
HHKhhQ
0Q
0
HHKlh L H
HHKhl H L
HHKllQ
0Q
0
H(h) eHIGH Voltage Level
L(l) eLOW Voltage Level
XeImmaterial
KeHIGH-to-LOW Clock Transition
Q0(Q0)eBefore HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one
setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram (One Half Shown)
TL/F/9472–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
Storage Temperature b65§Ctoa
150§C
Ambient Temperature under Bias b55§Ctoa
125§C
Junction Temperature under Bias b55§Ctoa
175§C
Plastic b55§Ctoa
150§C
VCC Pin Potential to
Ground Pin b0.5V to a7.0V
Input Voltage (Note 2) b0.5V to a7.0V
Input Current (Note 2) b30 mA to a5.0 mA
Voltage Applied to Output
in HIGH State (with VCC e0V)
Standard Output b0.5V to VCC
TRI-STATEÉOutput b0.5V to a5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Commercial 0§Ctoa
70§C
Supply Voltage
Commercial a4.5V to a5.5V
DC Electrical Characteristics
Symbol Parameter 74F Units VCC Conditions
Min Typ Max
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage b1.2 V Min IIN eb
18 mA
VOH Output HIGH 74F 10% VCC 2.5 V Min IOH eb
1mA
Voltage 74F 5% VCC 2.7 IOH eb
1mA
V
OL Output LOW 74F 10% VCC 0.5 V Min IOL e20 mA
Voltage
IIH Input HIGH 74F 5.0 mA Max VIN e2.7V
Current
IBVI Input HIGH Current 74F 7.0 mA Max VIN e7.0V
Breakdown Test
ICEX Output HIGH 74F 50 mA Max VOUT eVCC
Leakage Current
VID Input Leakage 74F 4.75 V 0.0 IID e1.9 mA
Test All other pins grounded
IOD Output Leakage 74F 3.75 mA 0.0 VIOD e150 mV
Circuit Current All other pins grounded
IIL Input LOW Current b0.6 VIN e0.5V (Jn,K
n
)
b
2.4 mA Max VIN e0.5V (CPn)
b3.0 VIN e0.5V (CDn,S
Dn)
IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V
ICCH Power Supply Current 12 19 mA Max VOeHIGH
ICCL Power Supply Current 12 19 mA Max VOeLOW
3
AC Electrical Characteristics
74F 74F
TAea
25§CTA,V
CC eCom
Symbol Parameter VCC ea
5.0V CLe50 pF Units
CLe50 pF
Min Typ Max Min Max
fmax Maximum Clock Frequency 85 105 80 MHz
tPLH Propagation Delay 2.0 5.0 6.5 2.0 7.5 ns
tPHL CPnto Qnor Qn2.0 5.0 6.5 2.0 7.5
tPLH Propagation Delay 2.0 4.5 6.5 2.0 7.5 ns
tPHL CDn,S
Dn to Qn,Q
n2.0 4.5 6.5 2.0 7.5
AC Operating Requirements
74F 74F
Symbol Parameter TAea
25§CTA,V
CC eCom Units
VCC ea
5.0V
Min Max Min Max
ts(H) Setup Time, HIGH or LOW 4.0 5.0
ts(L) Jnor Knto CPn3.0 3.5 ns
th(H) Hold Time, HIGH or LOW 0 0
th(L) Jnor Knto CPn00
t
w
(H) CP Pulse Width 4.5 5.0 ns
tw(L) HIGH or LOW 4.5 5.0
tw(L) Pulse Width, LOW 4.5 5.0 ns
CDn or SDn
trec Recovery Time 4.0 5.0 ns
SDn,C
Dn to CP
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 112 S C X
Temperature Range Family Special Variations
74F eCommercial X eDevices shipped in 13×reel
Device Type Temperature Range
CeCommercial (0§Ctoa
70§C)
Package Code
PePlastic DIP
SeSmall Outline SOIC JEDEC
SJ eSmall Outline SOIC EIAJ
4
Physical Dimensions inches (millimeters)
16-Lead (0.150×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M16A
16-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M16D
5
74F112 Dual JK Negative Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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