STM32F412xE STM32F412xG ARM(R)-Cortex(R)-M4 32b MCU+FPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces Datasheet - production data Features )%*$ * Dynamic Efficiency Line with BAM (Batch Acquisition Mode) (R) (R) * Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator (ART AcceleratorTM) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions * Memories - Up to 1 Mbyte of Flash memory - 256 Kbyte of SRAM - Flexible external static memory controller with up to 16-bit data bus: SRAM, PSRAM, NOR Flash memory - Dual mode Quad-SPI interface * LCD parallel interface, 8080/6800 modes * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration * Power consumption - Run: 112 A/MHz (peripheral off) - Stop (Flash in Stop mode, fast wakeup time): 50 A Typ @ 25 C; 75 A max @25 C - Stop (Flash in Deep power down mode, slow wakeup time): down to 18 A @ 25 C; 40 A max @25 C - Standby: 2.4 A @25 C / 1.7 V without RTC; 12 A @85 C @1.7 V - VBAT supply for RTC: 1 A @25 C LQFP64 (10x10mm) WLCSP64 UFQFPN48 (3.623x3.651mm) LQFP100 (14x14mm) (7x7 mm) LQFP144 (20x20mm) UFBGA100 (7x7mm) UFBGA144 (10x10mm) * Up to 17 timers: up to twelve 16-bit timers, two 32-bit timers up to 100 MHz each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog timers (independent and window), one SysTick timer * Debug mode - Serial wire debug (SWD) & JTAG - Cortex(R)-M4 Embedded Trace MacrocellTM * Up to 114 I/O ports with interrupt capability - Up to 109 fast I/Os up to 100 MHz - Up to 114 five V-tolerant I/Os * Up to 17 communication interfaces - Up to 4x I2C interfaces (SMBus/PMBus) - Up to 4 USARTs (2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control) - Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol), out of which 2 muxed full-duplex I2S interfaces - SDIO interface (SD/MMC/eMMC) - Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with PHY - 2x CAN (2.0B Active) * True random number generator * CRC calculation unit * 96-bit unique ID * RTC: subsecond accuracy, hardware calendar (R) * All packages are ECOPACK 2 Table 1. Device summary Reference Part number * 2x digital filters for sigma delta modulator, 4x PDM interfaces, stereo microphone support STM32F412xE STM32F412CE, STM32F412RE, STM32F412VE, STM32F412ZE * General-purpose DMA: 16-stream DMA STM32F412xG STM32F412CG, STM32F412RG, STM32F412VG, STM32F412ZG * 1x12-bit, 2.4 MSPS ADC: up to 16 channels May 2016 This is information on a product in full production. DocID028087 Rev 4 1/193 www.st.com Contents STM32F412xE/G Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 ARM(R) Cortex(R)-M4 with FPU core with embedded Flash and SRAM . . . 19 3.2 Adaptive real-time memory accelerator (ART AcceleratorTM) . . . . . . . . . 19 3.3 Batch Acquisition mode (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20 3.8 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.10 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23 3.14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.19 2/193 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.18.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.19.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31 3.20 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31 3.21 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID028087 Rev 4 STM32F412xE/G Contents 3.22 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.23 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.23.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.23.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.24 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.25 Universal synchronous/asynchronous receiver transmitters (USART) . . 37 3.26 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.27 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 38 3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40 3.31 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40 3.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.35 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.38 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID028087 Rev 4 3/193 5 Contents 7 4/193 STM32F412xE/G 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.2 VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 79 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 80 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 80 6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 110 6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 115 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.24 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 159 6.3.27 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.1 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DocID028087 Rev 4 STM32F412xE/G Contents 7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.6 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.7 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.8.1 8 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Appendix A Recommendations when using the internal reset OFF . . . . . . . . 186 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 187 B.2 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 B.3 Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DocID028087 Rev 4 5/193 5 List of tables STM32F412xE/G List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. 6/193 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F412xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F412xE/G pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32F412xE/G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STM32F412xE/G register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 78 VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 79 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 84 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 85 Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 86 Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 87 Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 88 Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 89 Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 90 Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 91 Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 92 Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 92 Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . . 92 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 93 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Low-power mode wakeup timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 DocID028087 Rev 4 STM32F412xE/G Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. List of tables HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 125 FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 138 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 138 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 148 Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 150 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 152 DocID028087 Rev 4 7/193 8 List of tables Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. 8/193 STM32F412xE/G Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 157 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . 161 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 WLCSP64 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 163 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 179 UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 182 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 DocID028087 Rev 4 STM32F412xE/G List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F412xE/G block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 25 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30 Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30 STM32F412xE/G WLCSP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F412xE/G UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F412xE/G LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F412xE/G LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F412xE/G LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F412xE/G UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F412xE/G UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Typical VBAT current consumption (LSE and RTC ON/LSE oscillator "low power" mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Typical VBAT current consumption (LSE and RTC ON/LSE oscillator "high drive" mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 DocID028087 Rev 4 9/193 11 List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. 10/193 STM32F412xE/G USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 135 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 141 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 142 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 146 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 148 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 149 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 151 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 157 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 WLCSP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 168 LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 171 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 174 LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 187 USB peripheral-only Full speed mode with direct connection for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 188 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 188 USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 189 Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 DocID028087 Rev 4 STM32F412xE/G Figure 87. List of figures Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 DocID028087 Rev 4 11/193 11 Introduction 1 STM32F412xE/G Introduction This datasheet provides the description of the STM32F412xE/G microcontrollers. For information on the Cortex(R)-M4 core, refer to the Cortex(R)-M4 programming manual (PM0214) available from www.st.com. 12/193 DocID028087 Rev 4 STM32F412xE/G 2 Description Description The STM32F412XE/G devices are based on the high-performance ARM(R) Cortex(R) -M4 32bit RISC core operating at a frequency of up to 100 MHz. Their Cortex(R)-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F412XE/G belong to the STM32 Dynamic EfficiencyTM product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching. The STM32F412XE/G incorporate high-speed embedded memories (up to 1 Mbyte of Flash memory, 256 Kbyte of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer one 12-bit ADC, a low-power RTC, twelve general-purpose 16-bit timers, two PWM timer for motor control and two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces. * Up to four I2Cs, including one I2C supporting Fast-Mode Plus * Five SPIs * Five I2Ss out of which two are full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicate internal audio PLL or via an external clock to allow synchronization. * Four USARTs * An SDIO/MMC interface * An USB 2.0 OTG full-speed interface * Two CANs. In addition, the STM32F412xE/G embed advanced peripherals: * A flexible static memory control interface (FSMC) * A Quad-SPI memory interface * A digital filter for sigma modulator (DFSDM), two filters, up to four inputs, and support of microphone MEMs. The STM32F412xE/G are offered in 7 packages ranging from 48 to 144 pins. The set of available peripherals depends on the selected package. Refer to Table 2: STM32F412xE/G features and peripheral counts for the peripherals available for each part number. The STM32F412xE/G operates in the - 40 to + 105 C temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. DocID028087 Rev 4 13/193 42 Description STM32F412xE/G These features make the STM32F412xE/G microcontrollers suitable for a wide range of applications: * Motor drive and application control * Medical equipment * Industrial applications: PLC, inverters, circuit breakers * Printers, and scanners * Alarm systems, video intercom, and HVAC * Home audio appliances * Mobile phone sensor hub * Wearable devices * Connected objects * Wifi modules Figure 4 shows the general block diagram of the devices. 14/193 DocID028087 Rev 4 STM32F412xE/G Description Table 2. STM32F412xE/G features and peripheral counts Peripherals STM32F412xE STM32F412xG 512 1024 Flash memory (Kbyte) SRAM (Kbyte) System 256 FSMC memory controller Quad-SPI memory interface Timers - 1 - - 1 - Generalpurpose 10 Advancedcontrol 2 Basic 2 Random number generator SPI/ I I 5/5 (2 full duplex) 2C 3 I2CFMP 1 3 4 3 1 Yes 1 No CAN LCD parallel interface Data bus size GPIOs 12-bit ADC Number of channels 2 2 2 2 3 4 3 4 - 8 36 50 16 81 114 - 8 36 50 16 81 114 1 10 16 10 16 100 MHz Operating voltage Package 1 Yes 1 No 2 Maximum CPU frequency Operating temperatures 4 1 USB/OTG FS Dual power rail Number of digital Filters for Sigma-delta modulator Number of channels 1 1 2S USART Comm. interfaces SDIO/MMC 1 1.7 to 3.6 V Ambient temperatures: -40 to +85 C/-40 to +105 C Junction temperature: -40 to + 125 C UFQ LQFP64 FPN48 WLCSP64 UFBGA 100 LQFP100 UFBGA LQFP64 UFQ 144 WLCSP FPN48 LQFP144 64 DocID028087 Rev 4 UFBGA UFBGA 100 144 LQFP100 LQFP144 15/193 42 Description 2.1 STM32F412xE/G Compatibility with STM32F4 series The STM32F412xE/G are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F412xE/G can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1. Compatible board design for LQFP100 package 3% QRW DYDLODEOHDQ\PRUH 5HSODFHG E\ 9 &$3B 3( 3( 3( 3( 3( 3( 3% 9&$3B 966 9'' 3' 3' 3' 3' 3% 3% 3% 3% 3( 3( 3( 3( 3( 3( 3% 3% 9&$3B 9'' 670)670)OLQH 670)670)OLQH 670)670)OLQH 670)670)OLQH 670)[[ 670)[[ 670)[[ 670)[[ 3' 3' 3' 3' 3% 3% 3% 3% 966 9'' 966 9'' 06Y9 16/193 DocID028087 Rev 4 STM32F412xE/G Description Figure 2. Compatible board design for LQFP64 package 670)[[ 670)[[ 670)[[ 670)[[ 670)[[ 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3%QRWDYDLODEOHDQ\PRUH 5HSODFHGE\9&$3B 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% 3% 9&$3B 966 9'' 3% 3% 3% 9&$3B 9'' 3& 3& 3& 3$ 3$ 3& 3& 3& 3$ 3$ 670)670)OLQH 9&$3BLQFUHDVHGWRI (65RUEHORZ 966 9 6 6 9 '' 9'' 06Y9 Figure 3. Compatible board design for LQFP144 package 670)670)OLQH 670)670)OLQH 670)670)OLQH 670)670)OLQH 3' 3' 3& 3& 3& 3$ 3$ 3' 3' 3& 3& 3& 3$ 3$ 670)[[ 670)[[ 9'' 966 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9'' 966 3* 6HSDUDWH86%SRZHUUDLO &RQQHFWHGWR9''LIDGLIIHUHQW SRZHUVXSSO\IRUWKH86%LVQRW UHTXLUHG 9'' 966 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9''B86% 966 3* 06Y9 DocID028087 Rev 4 17/193 42 Description STM32F412xE/G Figure 4. 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The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked from TIMxCLK up to 50 MHz. 18/193 DocID028087 Rev 4 STM32F412xE/G Functional overview 3 Functional overview 3.1 ARM(R) Cortex(R)-M4 with FPU core with embedded Flash and SRAM The ARM(R) Cortex(R)-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM(R) Cortex(R)-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F412xE/G devices are compatible with all ARM tools and software. Figure 4 shows the general block diagram of the STM32F412xE/G. Note: Cortex(R)-M4 with FPU is binary compatible with Cortex(R)-M3. 3.2 Adaptive real-time memory accelerator (ART AcceleratorTM) The ART AcceleratorTM is a memory accelerator which is optimized for STM32 industrystandard ARM(R) Cortex(R)-M4 with FPU processors. It balances the inherent performance advantage of the ARM(R) Cortex(R)-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 125 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 100 MHz. 3.3 Batch Acquisition mode (BAM) The Batch acquisition mode allows enhanced power efficiency during data batching. It enables data acquisition through any communication peripherals directly to memory using the DMA in reduced power consumption as well as data processing while the rest of the system is in low-power mode (including the flash and ART). For example in an audio system, a smart combination of PDM audio sample acquisition and processing from the DFSDM directly to RAM (flash and ARTTM stopped) with the DMA using BAM followed by some very short processing from flash allows to drastically reduce the power consumption of the application. A dedicated application note (AN4515) describes how to implement the STM32F412xE/G BAM to allow the best power efficiency. DocID028087 Rev 4 19/193 42 Functional overview 3.4 STM32F412xE/G Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.5 Embedded Flash memory The devices embed up to 1 Mbyte of Flash memory available for storing programs and data. The Flash user area can be protected against reading by an entrusted code (Read Protection, RDP) with different protection levels. The flash user sectors can also be individually protected against write operation. Furthermore the proprietary readout protection (PCROP) can also individually protect the flash user sectors against D-bus read accesses. (Additional information can be found in the product reference manual). To optimize the power consumption the Flash memory can also be switched off in Run or in Sleep mode (see Section 3.21: Low-power modes). Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between power saving and startup time. Before disabling the Flash, the code must be executed from the internal RAM. 3.6 One-time programmable bytes A one-time programmable area is available with16 OTP blocks of 32 bytes. Each block can be individually locked (Additional information can be found in the product reference manual) 3.7 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 20/193 DocID028087 Rev 4 STM32F412xE/G 3.8 Functional overview Embedded SRAM All devices embed 256 Kbyte of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states 3.9 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 5. Multi-AHB matrix 6 6 6 '0$B3 '0$B0(0 '0$B0(0 '0$B3, 6EXV 6 *3 '0$ *3 '0$ 6 0 ,&2'( 0 '&2'( %XVPDWUL[6 $&&(/ 6 'EXV ,EXV $50 &RUWH[0 )ODVK 8SWR0% 0 65$0 .% 0 $+% SHULSK $3% 0 $+% SHULSK $3% 0 )60&H[WHUQDO 0HP&WUO 4XDG63, 06Y9 3.10 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. DocID028087 Rev 4 21/193 42 Functional overview STM32F412xE/G The DMA can be used with the main peripherals: 3.11 * SPI and I2S * I2C and I2CFMP * USART * General-purpose, basic and advanced-control timers TIMx * SD/SDIO/MMC/eMMC host interface * Quad-SPI * ADC * Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter. Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR Flash memory. The main functions are: * 8-,16-bit data bus width * Write FIFO * Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.12 Quad-SPI memory interface (QUAD-SPI) All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode through registers, external Flash status register polling mode and memory mapped mode. Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or 32-bit mode. Code execution is also supported. The opcode and the frame format are fully programmable. Communication can be performed either in single data rate or dual data rate. 22/193 DocID028087 Rev 4 STM32F412xE/G 3.13 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)-M4 with FPU. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.14 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 21 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines. 3.15 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 C. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. DocID028087 Rev 4 23/193 42 Functional overview 3.16 STM32F412xE/G Boot modes At startup, boot pins are used to select one out of three boot options: * Boot from user Flash memory * Boot from system memory * Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using one of the interface listed in the Table 3 or the USB OTG FS in device mode through DFU (device firmware upgrade). Table 3. Embedded bootloader interfaces Package USART1 USART2 USART3 I2C1 PA9/ PD6/ PB11/ PB6/ PA10 PD5 PB10 PB7 SPI3 I2C2 PF0/ PF1 I2C3 PA8/ PB4 I2C FMP1 PB14/ PB15 SPI1 PA4/ PA5/ PA6/ PA7 PA15/ PC10/ PC11/ PC12 SPI4 PE11/ CAN2 USB PE12/ PB5/ PA11 PE13/ PB13 /P12 PE14 UFQFPN48 Y - - Y - Y Y Y - - Y Y WLCSP64 Y - - Y - Y Y Y Y - Y Y LQFP64 Y - - Y - Y Y Y Y - Y Y LQFP100 Y Y - Y - Y Y Y Y Y Y Y LQFP144 Y Y Y Y Y Y Y Y Y Y Y Y UFBGA100 Y Y Y Y - Y Y Y Y Y Y Y UFBGA144 Y Y Y Y Y Y Y Y Y Y Y Y For more detailed information on the bootloader, refer to Application Note: AN2606, STM32TM microcontroller system memory boot mode. 3.17 Note: 24/193 Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor (POR/PDR) disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and NRST pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with decoupling technique. The VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF and internal power supply supervisor availability to identify the packages supporting this option. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. * VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6 V) for USB transceivers. For example, when device is powered at 1.8 V, an independent power supply 3.3V can be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, DocID028087 Rev 4 STM32F412xE/G Functional overview it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected: - During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - VDDUSB rising and falling time rate specifications must be respected. - In operating mode phase, VDDUSB could be lower or higher than VDD: - If USB is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - If USB is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 6. VDDUSB connected to an external independent power supply 9''86%B0$; 86% IXQFWLRQDODUHD 9''86% 9''86%B0,1 86%QRQ IXQFWLRQDO DUHD 9'' 9''$ 86%QRQ IXQFWLRQDO DUHD 2SHUDWLQJPRGH 3RZHUGRZQ 9''B0,1 3RZHURQ WLPH 069 DocID028087 Rev 4 25/193 42 Functional overview STM32F412xE/G 3.18 Power supply supervisor 3.18.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.18.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to low. An external power supply supervisor should monitor VDD and should set the device in reset mode when VDD is below 1.7 V. NRST should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. 26/193 DocID028087 Rev 4 STM32F412xE/G Functional overview Figure 7. Power supply supervisor interconnection with internal reset OFF(1) 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 1567 3'5B21 9'' 06Y9 1. The PRD_ON pin is available only on WLCSP64, UFBGA100, UFBGA144 and LQFP144 packages. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no longer supported: 3.19 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. * The brownout reset (BOR) circuitry must be disabled. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. Voltage regulator The regulator has three operating modes: 3.19.1 - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. DocID028087 Rev 4 27/193 42 Functional overview STM32F412xE/G There are three power modes configured by software when the regulator is ON: * MR is used in the nominal regulation mode (With different voltage scaling in Run mode) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. * LPR is used in the Stop mode The LP regulator mode is configured by software when entering Stop mode. * Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Depending on the package, one or two external ceramic capacitors should be connected on the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the 100 pins and 144 pins packages. All packages have the regulator ON feature. 3.19.2 Regulator OFF This feature is available only on UFBGA100 and UFBGA144 packages, which feature the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: 28/193 * PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. * As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. DocID028087 Rev 4 STM32F412xE/G Functional overview Figure 8. Regulator OFF 9 ([WHUQDO9&$3BSRZHU $SSOLFDWLRQUHVHW VXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYH VLJQDO RSWLRQDO ZKHQ9&$3B0LQ9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL9 The following conditions must be respected: Note: * VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. * If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). * Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). * If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application. DocID028087 Rev 4 29/193 42 Functional overview STM32F412xE/G Figure 9. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9 0LQ9 9&$3B9&$3B WLPH 1567 3$ WLPH 06Y9 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B9&$3B 9 0LQ9 1567 WLPH 3$DVVHUWHGH[WHUQDOO\ WLPH 1. This figure is valid whatever the internal reset mode (ON or OFF). 30/193 DocID028087 Rev 4 06Y9 STM32F412xE/G 3.19.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal power supply supervisor availability Package Regulator ON Regulator OFF Power supply supervisor ON Power supply supervisor OFF UFQFPN48 Yes No Yes No WLCSP64 Yes No Yes PDR_ON set to VDD Yes PDR_ON set to VSS LQFP64 Yes No Yes No LQFP100 Yes No Yes No LQFP144 Yes No Yes PDR_ON set to VDD Yes PDR_ON set to VSS UFBGA100 Yes Yes BYPASS_REG set to BYPASS_REG set to VSS VDD UFBGA144 Yes Yes BYPASS_REG set to BYPASS_REG set to VSS VDD 3.20 Real-time clock (RTC) and backup registers The backup domain includes: * The real-time clock (RTC) * 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC features a reference clock detection, a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The backup registers are 32-bit registers used to store 80 byte of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.21: Low-power modes). DocID028087 Rev 4 31/193 42 Functional overview STM32F412xE/G Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.21 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. To further reduce the power consumption, the Flash memory can be switched off before entering in Sleep mode. Note that this requires a code execution from the RAM. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/ tamper/ time stamp events). * Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp event occurs. Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 3.22 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external super-capacitor, or from VDD when no external battery and an external super-capacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC and the backup registers. Note: 32/193 When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. DocID028087 Rev 4 STM32F412xE/G 3.23 Functional overview Timers and watchdogs The devices embed two advanced-control timer, ten general-purpose timers, two basic timers, two watchdog timers and one SysTick timer. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control and general-purpose timers. DocID028087 Rev 4 33/193 42 Functional overview STM32F412xE/G Table 5. Timer feature comparison Timer type Advance d-control Counter Counter Prescaler Timer resolution type factor TIM1, TIM8 TIM2, TIM5 TIM3, TIM4 TIM9 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 100 100 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 50 100 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 50 100 16-bit Up Any integer between 1 and 65536 No 2 No 100 100 Up Any integer between 1 and 65536 No 1 No 100 100 Up Any integer between 1 and 65536 No 2 No 50 100 Up Any integer between 1 and 65536 No 1 No 50 100 Up Any integer between 1 and 65536 Yes 0 No 50 100 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic timers 34/193 TIM6, TIM7 Max. Max. DMA Capture/ Complemen- interface timer request compare tary output clock clock generation channels (MHz) (MHz) 16-bit 16-bit 16-bit 16-bit DocID028087 Rev 4 STM32F412xE/G 3.23.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator multiplexed on 4 independent channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete generalpurpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability (0-100%). The advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. 3.23.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F412xE/G (see Table 5 for differences). * TIM2, TIM3, TIM4, TIM5 The STM32F412xE/G devices include 4 full-featured general-purpose timers: TIM2. TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 15 input capture/output compare/PWMs TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in conjunction with the other general-purpose timers and TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM output. TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or onepulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 fullfeatured general-purpose timers or used as simple time bases. 3.23.3 Basic timer (TIM6, TIM7) TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request generation. DocID028087 Rev 4 35/193 42 Functional overview 3.23.4 STM32F412xE/G Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.23.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.23.6 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.24 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source. Inter-integrated circuit interface (I2C) The devices feature up to four I2C bus interfaces which can operate in multimaster and slave modes: * One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to 400 kHz) modes and Fast-mode plus (up to 1 MHz). * Three I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode (up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on the complete solution, refer to the nearest STMicroelectronics sales office. All I2C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave) and embed a hardware CRC generation/verification. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 6). Table 6. Comparison of I2C analog and digital filters Pulse width of suppressed spikes 36/193 Analog filter Digital filter 50 ns Programmable length from 1 to 15 I2C peripheral clocks DocID028087 Rev 4 STM32F412xE/G 3.25 Functional overview Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6). These four interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. USART1 and USART6 interfaces are able to communicate at speeds of up to 12.5 Mbit/s. USART2 and USART3 interfaces communicate at up to 6.25 bit/s. All USART interfaces provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 7. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X X X X X 6.25 12.5 APB2 (max. 100 MHz) USART2 X X X X X X 3.12 6.25 APB1 (max. 50 MHz) USART3 X X X X X X 3.12 6.25 APB1 (max. 50 MHz) USART6 X X X X X X 6.25 12.5 APB2 (max. 100 MHz) 3.26 Serial peripheral interface (SPI) The devices feature five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interfaces can be configured to operate in TI mode for communications in master mode and slave mode. DocID028087 Rev 4 37/193 42 Functional overview 3.27 STM32F412xE/G Inter-integrated sound (I2S) Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be operated in master or slave mode, in simplex communication mode, and full duplex mode for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx interfaces can be served by the DMA controller. 3.28 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. Different sources can be selected for the I2S master clock of the APB1 and the I2S master clock of the APB2. This gives the flexibility to work with two different audio sampling frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin (external PLL or Codec output) The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. 3.29 Digital filter for sigma-delta modulators (DFSDM) The device embeds one DFSDM with 2 digital filters modules and 4 external input serial channels (transceivers) or alternately 2 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface formats (to support various modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution. 38/193 DocID028087 Rev 4 STM32F412xE/G Functional overview The DFSDM peripheral supports: * * 4 multiplexed input digital serial channels: - configurable SPI interface to connect various SD modulator(s) - configurable Manchester coded 1 wire interface support - PDM (Pulse Density Modulation) microphone input support - maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding) - clock output for SD modulator(s): 0...20 MHz alternative inputs from 4 internal digital parallel channels (up to 16 bit input resolution): - * internal sources: device memory data streams (DMA) 2 digital filter modules with adjustable digital signal processing: - Sincx filter: filter order/type (1...5), oversampling ratio (up to 1...1024) - integrator: oversampling ratio (1...256) * up to 24-bit output data resolution, signed output data format * automatic data offset correction (offset stored in register by user) * continuous or single conversion * start-of-conversion triggered by * * - software trigger - internal timers - external events - start-of-conversion synchronously with first digital filter module (DFSDM1FLT0) analog watchdog feature: - low value and high value data threshold registers - dedicated configurable Sincx digital filter (order = 1...3, oversampling ratio = 1...32 - input from digital output data or from selected input digital serial channels - continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values (bottom and top range): - up to 8-bit counter to detect 1...256 consecutive 0's or 1's on serial data stream - monitoring continuously each input serial channel * break signal generation on analog watchdog event or on short circuit detector event * extremes detector: - storage of minimum and maximum values of final conversion data - refreshed by software * DMA capability to read the final conversion data * interrupts: end of conversion, overrun, analog watchdog, short circuit input serial channel clock absence * "regulator" or injected" conversions: - "regular" conversions can be requested at any time or even in continuous mode without having any impact on the timing of "injected" conversions - "injected" conversions for precise timing and with high conversion priority. DocID028087 Rev 4 39/193 42 Functional overview 3.30 STM32F412xE/G Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.31 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 byte of SRAM are allocated for each CAN. 3.32 Universal serial bus on-the-go full-speed (USB_OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The Battery Charging Detection (BCD) can detect and identify the type of port, it is connected to (standard USB or charger). The type of charging is also detected: Dedicated Charging Port (DCP), Charging Downstream Port (CDP) and Standard Downstream Port (SDP). Some packages provide a dedicated USB power rail allowing a different supply for the USB and for the rest of the chip. For instance the chip can be powered with the minimum specified supply and the USB running at the level defined by the standard. The major features are: 40/193 * Combined Rx and Tx FIFO size of 320 x 35 bits with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 6 bidirectional endpoints * 12 host channels with periodic OUT support * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected * Link Power Management (LPM) * Battery Charging Detection (BCD) supporting DCP, CDP and SDP DocID028087 Rev 4 STM32F412xE/G 3.33 Functional overview Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 100 MHz. 3.35 Analog-to-digital converter (ADC) One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4 or TIM5 timer. 3.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value. Refer to the reference manual for additional information. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.37 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DocID028087 Rev 4 41/193 42 Functional overview 3.38 STM32F412xE/G Embedded Trace MacrocellTM The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F412xE/G through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using any high-speed channel available. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 42/193 DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Figure 11. STM32F412xE/G WLCSP64 pinout $ 9'' 966 3% 3% 3' 3& 3$ 9'' % 3& 9%$7 3% 3% 3% 3& 3$ 966 3'5B21 3% 3% 3& 3$ 3$ & 3& 3& 26&B,1 26&B287 ' 3+ 26&B,1 1567 3& 3& %227 3$ 3$ 3$ ( 3+ 26&B287 3& 3$ 3$ 3& 3$ 3& 3& ) 3& 9''$ 95() 3$ 3$ 3% 3& 3% 3& * 966$ 95() 3$ 3$ 3& 3% 3% 3% 3% + 3$ 9'' 3$ 3% 3% 9&$3B 966 9'' 06Y9 1. The above figure shows the package bump side. 3$ 966 3&26&B,1 3$ 3&26&B287 3$ 3+26&B,1 3$ 3+26&B287 3$ 1567 3$ 966$95() 3$ 9''$95() 3% 3$ 3% 3$ 3% 3$ 3% 3$ 3$ 3$ 3% 3% 3% 3% 966 9'' 3$ 3% 3& 3% 9'' 3% 3% 3% 3$ 3% %227 966 9%$7 3% 9'' Figure 12. STM32F412xE/G UFQFPN48 pinout 3$ 8)4)31 9&$3B 4 Pinouts and pin description 069 1. The above figure shows the package top view. DocID028087 Rev 4 43/193 67 Pinouts and pin description STM32F412xE/G 9%$7 3& 3&26&B,1 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ /4)3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 9&$3B 966 9'' 3&26&B287 3+26&B,1 3+26&B287 1567 3& 3& 3& 3& 966$95() 9''$95() 3$ 3$ 3$ 966 9'' Figure 13. STM32F412xE/G LQFP64 pinout 069 1. The above figure shows the package top view. 44/193 DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 14. STM32F412xE/G LQFP100 pinout ,1&0 6$$ 633 6#!0? 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633 6$$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 6#!0? 633 6$$ 0% 0% 0% 0% 0% 6"!4 0# 0# /3#?). 0# /3#?/54 633 6$$ 0( /3#?). 0( /3#?/54 .234 0# 0# 0# 0# 6$$ 633!62%& 62%& 6$$! 0! 0! 0! -36 1. The above figure shows the package top view. DocID028087 Rev 4 45/193 67 Pinouts and pin description STM32F412xE/G 9'' 3'5B21 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 15. STM32F412xE/G LQFP144 pinout 3( 3( 3( 3( 9'' 966 9&$3B 3$ 3( 3$ 9%$7 3$ 3& 3&26&B,1 3$ 3$ 3&26&B287 3$ 3) 3& 3) 3) 3& 3& 3) 3& 3) 9''86% 3) 966 966 3* 9'' 3* 3) 3* 3) 3* 3) 3* 3) 3* 3) 3* 3+26&B,1 3' 3+26&B287 3' 1567 9'' 3& 966 3& 3' 3& 3' 3& 3' 9'' 3' 966$95() 3' 95() 3' 9''$ 3% 3$ 3% 3$ 3% 3$ 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3* 3* 3( 3( 3( 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 9&$3B 9'' /4)3 06Y9 1. The above figure shows the package top view. 46/193 DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Figure 16. STM32F412xE/G UFBGA100 pinout $ 3( 3( 3% % 3( 3( & 3& 3' 3% 3% 3$ 3$ 3$ 3$ 3' 3' 3' 3' 3& 3& 3$ 3' 3' 3& 9&$3 B 3$ 966 3$ 3$ 3& %<3$66 B5(* 3& 3& 3& 966 966 966 3+ 26&B 287 9'' 9'' 9'' + 3& 1567 3'5 B21 3' 3' 3' - 966$ 3& 3& 3' 3' 3' . 95() 3& 3$ 3$ 3& / 95() 3$ 3$ 3$ 3& 3% 0 9''$ 3$ 3$ 3$ 3% 3% ' ( ) * %227 3' 3% 3% 3% 3( 3( 9'' 3% 3& 26& B,1 3( 3& 26& B287 9%$7 3+ 26&B ,1 3' 3% 3% 3% 3% 3( 3( 3( 3% 9&$3 B 3% 3( 3( 3( 3( 3( 3( 06Y9 1. The above figure shows the package top view. DocID028087 Rev 4 47/193 67 Pinouts and pin description STM32F412xE/G Figure 17. STM32F412xE/G UFBGA144 pinout $ 3& 3( 3( 3( 3( 3% 3% 3' 3' 3$ 3$ 3$ % 3& 26&B,1 3( 3( 3( 3% 3% 3* 3* 3' 3& 3& 3$ & 3& 26&B287 9%$7 3) 3) 3% 3% 3* 3* 3' 3& 9''86% 3$ ' 3+ 26&B,1 966 9'' 3) %227 3% 3* 3* 3' 3' 3$ 3$ ( 3+ 26&B287 3) 3) 3) 3'5B21 966 966 3* 3' 3' 3& 3$ ) 1567 3) 3) 9'' 9'' 9'' 9'' 9'' 9'' 9'' 3& 3& * 3) 3) 3) 966 9'' 9'' 9'' 966 9&$3B 966 3* 3& + 3& 3& 3& 3& %<3$66B 5(* 966 9&$3B 3( 3' 3* 3* 3* - 966$ 3$ 3$ 3& 3% 3* 3( 3( 3' 3* 3* 3* . 95() 3$ 3$ 3& 3) 3* 3( 3( 3' 3' 3' 3' / 95() 3$ 3$ 3% 3) 3) 3( 3( 3' 3' 3% 3% 0 9''$ 3$ 3$ 3% 3) 3) 3( 3( 3% 3% 3% 3% 06Y9 1. The above figure shows the package top view. Table 8. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input/ output pin FT 5 V tolerant I/O TC Standard 3.3 V I/O B Dedicated BOOT0 pin NRST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers 48/193 DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name (function Pin I/O Notes after type structure (1) reset) Alternate functions Additional functions - - - - 1 B2 A3 1 PE2 I/O FT - TRACECLK, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, QUADSPI_BK1_IO2, FSMC_A23, EVENTOUT - - - 2 A1 A2 2 PE3 I/O FT - TRACED0, FSMC_A19, EVENTOUT - - TRACED1, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, DFSDM1_DATIN3, FSMC_A20, EVENTOUT - - TRACED2, TIM9_CH1, SPI4_MISO, SPI5_MISO, DFSDM1_CKIN3, FSMC_A21, EVENTOUT - - - - - - - - 3 4 B1 C2 B2 B3 3 4 PE4 I/O PE5 I/O FT FT - - - 5 D2 B4 5 PE6 I/O FT - TRACED3, TIM9_CH2, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, FSMC_A22, EVENTOUT 1 1 B7 6 E2 C2 6 VBAT S - - - VBAT 2 2 B8 7 C1 A1 7 PC13 I/O FT (2)(3) EVENTOUT TAMP_1 3 3 C8 8 D1 B1 8 PC14OSC32_IN I/O FT (4) EVENTOUT OSC32_IN 4 4 C7 9 E1 C1 9 PC15OSC32_ OUT I/O FT (2)(4) EVENTOUT OSC32_ OUT - - - - - C3 10 PF0 I/O FT - I2C2_SDA, FSMC_A0, EVENTOUT - - - - - - C4 11 PF1 I/O FT - I2C2_SCL, FSMC_A1, EVENTOUT - - - - - - D4 12 PF2 I/O FT - I2C2_SMBA, FSMC_A2, EVENTOUT - - - - - - E2 13 PF3 I/O FT - TIM5_CH1, FSMC_A3, EVENTOUT - - - - - - E3 14 PF4 I/O FT - TIM5_CH2, FSMC_A4, EVENTOUT - DocID028087 Rev 4 (2)(3) 49/193 67 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) Pin Number UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin name I/O (function Pin Notes type structure after (1) reset) - - - - - E4 15 PF5 I/O FT - TIM5_CH3, FSMC_A5, EVENTOUT - - - - 10 F2 D2 16 VSS S - - - - - - - 11 G2 D3 17 VDD S - - - - - - - - - F3 18 PF6 I/O FT - TRACED0, TIM10_CH1, QUADSPI_BK1_IO3, EVENTOUT - - - - - - F2 19 PF7 I/O FT - TRACED1, TIM11_CH1, QUADSPI_BK1_IO2, EVENTOUT - - - - - - G3 20 PF8 I/O FT - TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT - - - - - - G2 21 PF9 I/O FT - TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT - - - - - - G1 22 PF10 I/O FT - TIM1_ETR, TIM5_CH4, EVENTOUT - 5 5 D8 12 F1 D1 23 PH0 OSC_IN I/O FT (4) EVENTOUT OSC_IN 6 6 E8 13 G1 E1 24 PH1 OSC_OUT I/O FT (4) EVENTOUT OSC_OUT 7 7 D7 14 H2 F1 25 NRST I/O RST - - NRST - 8 D5 15 H1 H1 26 PC0 I/O FT - EVENTOUT ADC1_10, WKUP2 - 9 F8 16 J2 H2 27 PC1 I/O FT - EVENTOUT ADC1_11, WKUP3 - 10 E7 17 J3 H3 28 PC2 I/O FT - SPI2_MISO, I2S2ext_SD, DFSDM1_CKOUT, FSMC_NWE, EVENTOUT ADC1_12 - 11 D6 18 K2 H4 29 PC3 I/O FT - SPI2_MOSI/I2S2_SD, FSMC_A0, EVENTOUT ADC1_13 - - 19 - - 30 VDD S - - - - 12 G8 20 - - 31 VSSA/ VREF S - - - - J1 J1 - VSSA S - - - - 8 - 50/193 - - - - DocID028087 Rev 4 Alternate functions Additional functions STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) Pin Number UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin name I/O (function Pin Notes type structure after (1) reset) - - - - K1 K1 - VREF- S - - - - 9 13 F7 - - - - VDDA/ VREF+ S - - - - - - - 21 L1 L1 32 VREF+ S - - - - - - - 22 M1 M1 33 VDDA S - - - - - TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, EVENTOUT ADC1_0, WKUP1 - TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, QUADSPI_BK1_IO3, EVENTOUT ADC1_1 - TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, FSMC_D4, EVENTOUT ADC1_2 ADC1_3 10 11 12 14 E6 23 15 G7 24 16 H8 25 L2 M2 K3 J2 K2 L2 34 35 36 PA0 I/O PA1 I/O PA2 I/O FT FT FT Alternate functions Additional functions 13 17 F6 26 L3 M2 37 PA3 I/O FT - TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, FSMC_D5, EVENTOUT - 18 - 27 - G4 38 VSS S - - - - - - - - E3 H5 - BYPASS_ REG I FT - - - - F4 39 VDD S - - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, DFSDM1_DATIN1, FSMC_D6, EVENTOUT ADC1_4 - TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK/I2S1_CK, DFSDM1_CKIN1, FSMC_D7, EVENTOUT ADC1_5 - 14 15 19 H7 28 20 G6 29 21 F5 30 M3 K4 J3 K3 40 41 PA4 PA5 I/O I/O FT FT DocID028087 Rev 4 51/193 67 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) 16 22 H6 31 L4 L3 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 42 Pin name I/O (function Pin Notes type structure after (1) reset) PA6 I/O FT Alternate functions Additional functions - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, I2S2_MCK, TIM13_CH1, QUADSPI_BK2_IO0, SDIO_CMD, EVENTOUT ADC1_6 ADC1_7 17 23 E5 32 M4 M3 43 PA7 I/O FT - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, QUADSPI_BK2_IO1, EVENTOUT - 24 E4 33 K5 J4 44 PC4 I/O FT - I2S1_MCK, QUADSPI_BK2_IO2, FSMC_NE4, EVENTOUT ADC1_14 - I2CFMP1_SMBA, USART3_RX, QUADSPI_BK2_IO3, FSMC_NOE, EVENTOUT ADC1_15 - TIM1_CH2N, TIM3_CH3, TIM8_CH2N, SPI5_SCK/I2S5_CK, EVENTOUT ADC1_8 ADC1_9 - 18 25 G5 34 26 H5 35 L5 M5 K4 L4 45 46 PC5 PB0 I/O I/O FT FT 19 27 36 M6 M4 47 PB1 I/O FT - TIM1_CH3N, TIM3_CH4, TIM8_CH3N, SPI5_NSS/I2S5_WS, DFSDM1_DATIN0, QUADSPI_CLK, EVENTOUT 20 28 G4 37 L6 J5 48 PB2 I/O FT - DFSDM1_CKIN0, QUADSPI_CLK, EVENTOUT BOOT1 F4 - - - - - M5 49 PF11 I/O FT - TIM8_ETR, EVENTOUT - - - - - - L5 50 PF12 I/O FT - TIM8_BKIN, FSMC_A6, EVENTOUT - - - - - - - 51 VSS S - - - - - - - - - G5 52 VDD S - - - - - - - - - K5 53 PF13 I/O FT - I2CFMP1_SMBA, FSMC_A7, EVENTOUT - 52/193 DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) Pin Number UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin name I/O (function Pin Notes type structure after (1) reset) - - - - - M6 54 PF14 I/O FT - I2CFMP1_SCL, FSMC_A8, EVENTOUT - - - - - - L6 55 PF15 I/O FT - I2CFMP1_SDA, FSMC_A9, EVENTOUT - - - - - - K6 56 PG0 I/O FT - CAN1_RX, FSMC_A10, EVENTOUT - - - - - - J6 57 PG1 I/O FT - CAN1_TX, FSMC_A11, EVENTOUT - - TIM1_ETR, DFSDM1_DATIN2, QUADSPI_BK2_IO0, FSMC_D4/FSMC_DA4, EVENTOUT - - TIM1_CH1N, DFSDM1_CKIN2, QUADSPI_BK2_IO1, FSMC_D5/FSMC_DA5, EVENTOUT - - - - - - - - 38 39 M7 L7 M7 L7 58 59 PE7 PE8 I/O I/O FT FT Alternate functions Additional functions - - - 40 M8 K7 60 PE9 I/O FT - TIM1_CH1, DFSDM1_CKOUT, QUADSPI_BK2_IO2, FSMC_D6/FSMC_DA6, EVENTOUT - - - - - - 61 VSS S - - - - - - - - - G6 62 VDD S - - - - - TIM1_CH2N, QUADSPI_BK2_IO3, FSMC_D7/FSMC_DA7, EVENTOUT - - TIM1_CH2, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, FSMC_D8/FSMC_DA8, EVENTOUT - - TIM1_CH3N, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, FSMC_D9/FSMC_DA9, EVENTOUT - - - - - - - - - - 41 42 43 L8 M9 L9 J7 H8 J8 63 64 65 PE10 PE11 PE12 I/O I/O I/O FT FT FT DocID028087 Rev 4 53/193 67 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) - K8 LQFP144 44 M1 0 UFBGA144 UFBGA100 - LQFP100 - WLCSP64 LQFP64 UFQFPN48 Pin Number 66 Pin name I/O (function Pin Notes type structure after (1) reset) PE13 I/O FT Alternate functions Additional functions - TIM1_CH3, SPI4_MISO, SPI5_MISO, FSMC_D10/FSMC_DA10, EVENTOUT - - - - - 45 M11 L8 67 PE14 I/O FT - TIM1_CH4, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, FSMC_D11/FSMC_DA11, EVENTOUT - - - 46 M1 2 M8 68 PE15 I/O FT - TIM1_BKIN, FSMC_D12/FSMC_DA12, EVENTOUT - - 21 M9 69 PB10 I/O FT - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, USART3_TX, I2CFMP1_SCL, SDIO_D7, EVENTOUT K9 M1 0 70 PB11 I/O FT - TIM2_CH4, I2C2_SDA, I2S2_CKIN, USART3_RX, EVENTOUT - 29 H4 47 L10 - - - - 22 30 H3 48 L11 H7 71 VCAP_1 S - - - - 23 31 H2 49 F12 H6 - VSS S - - - - 24 32 H1 50 G1 2 G7 72 VDD S - - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, USART3_CK, CAN2_RX, DFSDM1_DATIN1, FSMC_D13/FSMC_DA13, EVENTOUT - - TIM1_CH1N, I2CFMP1_SMBA, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, USART3_CTS, CAN2_TX, DFSDM1_CKIN1, EVENTOUT - 25 26 33 G3 51 L12 M11 34 G2 52 K12 54/193 M1 2 73 74 PB12 PB13 I/O I/O FT FT DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) 27 UFBGA144 LQFP144 75 Pin name I/O (function Pin Notes type structure after (1) reset) PB14 I/O FT Alternate functions Additional functions - TIM1_CH2N, TIM8_CH2N, I2CFMP1_SDA, SPI2_MISO, I2S2ext_SD, USART3_RTS, DFSDM1_DATIN2, TIM12_CH1, FSMC_D0, SDIO_D6, EVENTOUT - - 54 K10 L12 76 PB15 I/O FT - RTC_50Hz, TIM1_CH3N, TIM8_CH3N, I2CFMP1_SCL, SPI2_MOSI/I2S2_SD, DFSDM1_CKIN2, TIM12_CH2, SDIO_CK, EVENTOUT - 55 - L9 77 PD8 I/O FT - USART3_TX, FSMC_D13/ FSMC_DA13, EVENTOUT - - - 56 K8 K9 78 PD9 I/O FT - USART3_RX, FSMC_D14/FSMC_DA14, EVENTOUT - - - 57 J12 J9 79 PD10 I/O FT - USART3_CK, FSMC_D15/FSMC_DA15, EVENTOUT - - I2CFMP1_SMBA, USART3_CTS, QUADSPI_BK1_IO0, FSMC_A16, EVENTOUT - - TIM4_CH1, I2CFMP1_SCL, USART3_RTS, QUADSPI_BK1_IO1, FSMC_A17, EVENTOUT - - 36 F2 - - - - - UFBGA100 35 G1 53 K11 L11 28 - LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number - - - - 58 J11 H9 59 J10 L10 - - - - - - - - - - - - - 80 81 PD11 PD12 I/O I/O FT FT 82 PD13 I/O FT - TIM4_CH2, I2CFMP1_SDA, QUADSPI_BK1_IO3, FSMC_A18, EVENTOUT G8 83 VSS S - - - - F8 84 VDD S - - - - 60 H12 K10 DocID028087 Rev 4 55/193 67 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) - - - 61 H11 K11 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 85 Pin name I/O (function Pin Notes type structure after (1) reset) PD14 I/O FT Alternate functions Additional functions - TIM4_CH3, I2CFMP1_SCL, FSMC_D0/FSMC_DA0, EVENTOUT - - 86 PD15 I/O FT - TIM4_CH4, I2CFMP1_SDA, FSMC_D1/FSMC_DA1, EVENTOUT J12 87 PG2 I/O FT - FSMC_A12, EVENTOUT - - J11 88 PG3 I/O FT - FSMC_A13, EVENTOUT - - - J10 89 PG4 I/O FT - FSMC_A14, EVENTOUT - - - - H12 90 PG5 I/O FT - FSMC_A15, EVENTOUT - - - - - H11 91 PG6 I/O FT - QUADSPI_BK1_NCS, EVENTOUT - - - - - - H10 92 PG7 I/O FT - USART6_CK, EVENTOUT - - - - - - G11 93 PG8 I/O FT - USART6_RTS, EVENTOUT - - - - - - - 94 VSS S - - - - - - - - - F10 - VDD S - - - - - - C11 95 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, I2CFMP1_SCL, I2S2_MCK, DFSDM1_CKIN3, USART6_TX, FSMC_D1, SDIO_D6, EVENTOUT - - TIM3_CH2, TIM8_CH2, I2CFMP1_SDA, SPI2_SCK/I2S2_CK, I2S3_MCK, USART6_RX, DFSDM1_DATIN3, SDIO_D7, EVENTOUT - - TIM3_CH3, TIM8_CH3, USART6_CK, QUADSPI_BK1_IO2, SDIO_D0, EVENTOUT - - - - - - - - - - - - - - - - - - - - - - 37 38 39 56/193 F1 E1 F3 62 H10 K12 63 E12 G12 64 E11 F12 65 E10 F11 96 97 98 PC6 PC7 PC8 I/O I/O I/O FT FT FT DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) - 29 30 31 32 40 41 E2 E3 66 D12 E11 LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 99 67 D11 E12 100 42 D1 68 D10 D12 101 43 D2 69 C12 D11 102 44 D3 70 B12 C12 103 Pin name I/O (function Pin Notes type structure after (1) reset) PC9 PA8 PA9 PA10 PA11 I/O I/O I/O I/O I/O FT FT FT FT FT Alternate functions Additional functions - MCO_2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S2_CKIN, QUADSPI_BK1_IO0, SDIO_D1, EVENTOUT - - MCO_1, TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1, EVENTOUT - - TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2, EVENTOUT - - TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, USB_FS_ID, EVENTOUT - - TIM1_CH4, SPI4_MISO, USART1_CTS, USART6_TX, CAN1_RX, USB_FS_DM, EVENTOUT - - 33 45 C1 71 A12 B12 104 PA12 I/O FT - TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, CAN1_TX, USB_FS_DP, EVENTOUT 34 46 C2 72 A11 A12 105 PA13 I/O FT - JTMS-SWDIO, EVENTOUT - VCAP_2 S - - - - 74 F11 G10 107 VSS S - - - - 75 G11 - - - 35 47 B1 36 48 - - - A1 37 49 B2 38 50 A2 73 C11 G9 106 - - VDD S - - - - F9 108 VDD S - - - - 76 A10 A11 109 PA14 I/O FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX, EVENTOUT - - 77 - A9 A10 110 PA15 I/O FT DocID028087 Rev 4 57/193 67 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) - LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number 51 C3 78 B11 B11 111 Pin name I/O (function Pin Notes type structure after (1) reset) PC10 I/O FT Alternate functions Additional functions - SPI3_SCK/I2S3_CK, USART3_TX, QUADSPI_BK1_IO1, SDIO_D2, EVENTOUT - - - 52 B3 79 C10 B10 112 PC11 I/O FT - I2S3ext_SD, SPI3_MISO, USART3_RX, QUADSPI_BK2_NCS, FSMC_D2, SDIO_D3, EVENTOUT - 53 A3 80 B10 C10 113 PC12 I/O FT - SPI3_MOSI/I2S3_SD, USART3_CK, FSMC_D3, SDIO_CK, EVENTOUT - - - - 81 C9 E10 114 PD0 I/O FT - CAN1_RX, FSMC_D2/FSMC_DA2, EVENTOUT - - - - 82 B9 D10 115 PD1 I/O FT - CAN1_TX, FSMC_D3/FSMC_DA3, EVENTOUT - - 54 A4 83 C8 PD2 I/O FT - TIM3_ETR, FSMC_NWE, SDIO_CMD, EVENTOUT - - E9 116 - - - 84 B8 D9 117 PD3 I/O FT - TRACED1, SPI2_SCK/I2S2_CK, DFSDM1_DATIN0, USART2_CTS, QUADSPI_CLK, FSMC_CLK, EVENTOUT - - - 85 B7 C9 118 PD4 I/O FT - DFSDM1_CKIN0, USART2_RTS, FSMC_NOE, EVENTOUT - - - - 86 A6 B9 119 PD5 I/O FT - USART2_TX, FSMC_NWE, EVENTOUT - - - - - - E7 120 VSS S - - - - - - - - - F7 121 VDD S - - - - - SPI3_MOSI/I2S3_SD, DFSDM1_DATIN1, USART2_RX, FSMC_NWAIT, EVENTOUT - - 58/193 - - 87 B6 A8 122 PD6 I/O FT DocID028087 Rev 4 STM32F412xE/G Pinouts and pin description Table 9. STM32F412xE/G pin definition (continued) Pin Number UFQFPN48 LQFP64 WLCSP64 LQFP100 UFBGA100 UFBGA144 LQFP144 Pin name I/O (function Pin Notes type structure after (1) reset) - - - 88 A5 A9 123 PD7 I/O FT - DFSDM1_CKIN1, USART2_CK, FSMC_NE1, EVENTOUT - - - - - - E8 124 PG9 I/O FT - USART6_RX, QUADSPI_BK2_IO2, FSMC_NE2, EVENTOUT - - - - - - D8 125 PG10 I/O FT - FSMC_NE3, EVENTOUT - - - - - - C8 126 PG11 I/O FT - CAN2_RX, EVENTOUT - - - - - - B8 127 PG12 I/O FT - USART6_RTS, CAN2_TX, FSMC_NE4, EVENTOUT - - - - - - D7 128 PG13 I/O FT - TRACED2, USART6_CTS, FSMC_A24, EVENTOUT - - - - - - C7 129 PG14 I/O FT - TRACED3, USART6_TX, QUADSPI_BK2_IO3, FSMC_A25, EVENTOUT - - - - - - - 130 VSS S - - - - - - - - - F6 131 VDD S - - - - - - - - - B7 132 PG15 I/O FT - USART6_CTS, EVENTOUT - - JTDO-SWO, TIM2_CH2, I2CFMP1_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, I2C2_SDA, EVENTOUT - - JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0, EVENTOUT - - TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, CAN2_RX, SDIO_D3, EVENTOUT - 39 40 41 55 56 A5 B4 89 90 57 C4 91 A8 A7 C5 A7 A6 B6 133 134 135 PB3 PB4 PB5 I/O I/O I/O FT FT FT DocID028087 Rev 4 Alternate functions Additional functions 59/193 67 Pinouts and pin description STM32F412xE/G Table 9. STM32F412xE/G pin definition (continued) LQFP144 UFBGA144 UFBGA100 LQFP100 WLCSP64 LQFP64 UFQFPN48 Pin Number Pin name I/O (function Pin Notes type structure after (1) reset) Alternate functions Additional functions - 42 58 B5 92 B5 C6 136 PB6 I/O FT - TIM4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, QUADSPI_BK1_NCS, SDIO_D0, EVENTOUT 43 59 A6 93 B4 D6 137 PB7 I/O FT - TIM4_CH2, I2C1_SDA, USART1_RX, FSMC_NL, EVENTOUT - 44 60 D4 94 A4 D5 138 BOOT0 I B - - VPP - TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, CAN1_RX, I2C3_SDA, SDIO_D4, EVENTOUT - - 45 61 C5 95 A3 C5 139 PB8 I/O FT 46 62 B6 96 B3 B5 140 PB9 I/O FT - TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, I2C2_SDA, SDIO_D5, EVENTOUT - - - 97 C3 A5 141 PE0 I/O FT - TIM4_ETR, FSMC_NBL0, EVENTOUT - - - - 98 A2 A4 142 PE1 I/O FT - FSMC_NBL1, EVENTOUT - 47 63 A7 99 - E6 - VSS S - - - - - - C6 - H3 E5 143 PDR_ON I FT - - - 48 64 A8 10 0 - F5 144 VDD S - - - - 1. Function availability depends on the chosen device. 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F412xE/Greference manual. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 60/193 DocID028087 Rev 4 AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PA0 - TIM2_CH1/ TIM2_ETR TIM5_CH1 TIM8_ETR - - - USART2_CTS - - - - EVENTOUT PA1 - TIM2_CH2 TIM5_CH2 - - SPI4_MOSI/I 2S4_SD - USART2_RTS - QUADSPI_ BK1_IO3 - - EVENTOUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - I2S2_CKIN - USART2_TX - - - FSMC_D4 EVENTOUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - I2S2_MCK - USART2_RX - - - FSMC_D5 EVENTOUT PA4 - - - - - SPI1_NSS/I2 S1_WS SPI3_NSS/ I2S3_WS USART2_CK DFSDM1_ DATIN1 - - FSMC_D6 EVENTOUT PA5 - TIM2_CH1/ TIM2_ETR - TIM8_CH1N - SPI1_SCK/ I2S1_CK - - DFSDM1_ CKIN1 - - FSMC_D7 EVENTOUT PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO I2S2_MCK - - TIM13_ CH1 QUADSPI_ BK2_IO0 SDIO_CMD EVENTOUT PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI/I 2S1_SD - - - TIM14_ CH1 QUADSPI_ BK2_IO1 - EVENTOUT PA8 MCO_1 TIM1_CH1 - - I2C3_SCL - - USART1_CK - - USB_FS_ SOF SDIO_D1 EVENTOUT PA9 - TIM1_CH2 - - I2C3_ SMBA - - USART1_TX - - USB_FS_ VBUS SDIO_D2 EVENTOUT PA10 - TIM1_CH3 - - - - SPI5_MOSI/ I2S5_SD USART1_RX - - USB_FS_ID - EVENTOUT PA11 - TIM1_CH4 - - - - SPI4_MISO USART1_CTS USART6_ TX CAN1_RX USB_FS_DM - EVENTOUT PA12 - TIM1_ETR - - - - SPI5_MISO USART1_RTS USART6_ RX CAN1_TX USB_FS_DP - EVENTOUT PA13 JTMSSWDIO - - - - - - - - - - - EVENTOUT PA14 JTCKSWCLK - - - - - - - - - - - EVENTOUT PA15 JTDI TIM2_CH1/ TIM2_ETR - - - SPI1_NSS/ I2S1_WS SPI3_NSS/ I2S3_WS USART1_TX - - - - EVENTOUT DocID028087 Rev 4 Port A Port 61/193 Pinouts and pin description AF1 STM32F412xE/G Table 10. STM32F412xE/G alternate functions AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - SPI5_SCK/ I2S5_CK - - - - - EVENTOUT PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - SPI5_NSS/ I2S5_WS - DFSDM1_ DATIN0 QUADSPI_ CLK - - EVENTOUT PB2 - - - - - - DFSDM1_ CKIN0 - - QUADSPI_ CLK - - EVENTOUT PB3 JTDOSWO TIM2_CH2 I2CFMP1_ SDA SPI1_SCK/I2 S1_CK SPI3_SCK/ I2S3_CK USART1_RX - I2C2_SDA - - EVENTOUT PB4 JTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO I2S3ext_ SD - I2C3_SDA - SDIO_D0 EVENTOUT PB5 - - TIM3_CH2 - I2C1_SMBA SPI1_MOSI/I 2S1_SD SPI3_MOSI/ I2S3_SD - - CAN2_RX - SDIO_D3 EVENTOUT PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - CAN2_TX QUADSPI_ BK1_NCS SDIO_D0 EVENTOUT PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - FSMC_NL EVENTOUT PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - SPI5_MOSI/I2S 5_SD - CAN1_RX I2C3_SDA - SDIO_D4 EVENTOUT PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/ I2S2_WS - - CAN1_TX I2C2_SDA - SDIO_D5 EVENTOUT PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK/ I2S2_CK I2S3_MCK USART3_TX - I2CFMP1_ SCL - SDIO_D7 EVENTOUT PB11 - TIM2_CH4 - - I2C2_SDA I2S2_CKIN - USART3_RX - - - - EVENTOUT PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS/ I2S2_WS SPI4_NSS/ I2S4_WS SPI3_SCK/ I2S3_CK USART3_ CK CAN2_RX DFSDM1_ DATIN1 FSMC_D13/F SMC_DA13 EVENTOUT PB13 - TIM1_CH1N - - I2CFMP1_ SMBA SPI2_SCK/ I2S2_CK SPI4_SCK/ I2S4_CK - USART3_ CTS CAN2_TX DFSDM1_ CKIN1 - EVENTOUT PB14 - TIM1_CH2N - TIM8_CH2N I2CFMP1_ SDA SPI2_MISO I2S2ext_SD USART3_ RTS DFSDM1_ DATIN2 TIM12_CH1 FSMC_D0 SDIO_D6 EVENTOUT PB15 RTC_ 50Hz TIM1_CH3N - TIM8_CH3N I2CFMP1_ SCL SPI2_MOSI/I 2S2_SD - - DFSDM1_ CKIN2 TIM12_CH2 - SDIO_CK EVENTOUT DocID028087 Rev 4 Port B Port STM32F412xE/G AF1 Pinouts and pin description 62/193 Table 10. STM32F412xE/G alternate functions (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PC0 - - - - - - - - - - - - EVENTOUT PC1 - - - - - - - - - - - - EVENTOUT PC2 - - - - - SPI2_MISO I2S2ext_SD - DFSDM1_ CKOUT - - FSMC_NWE EVENTOUT PC3 - - - - - SPI2_MOSI/I 2S2_SD - - - - - FSMC_A0 EVENTOUT PC4 - - - - - I2S1_MCK - - - - QUADSPI_ BK2_IO2 FSMC_NE4 EVENTOUT PC5 - - - - I2CFMP1_ SMBA - - USART3_RX - - QUADSPI_ BK2_IO3 FSMC_NOE EVENTOUT PC6 - - TIM3_CH1 TIM8_CH1 I2CFMP1_ SCL I2S2_MCK DFSDM1_ CKIN3 - USART6_ TX - FSMC_D1 SDIO_D6 EVENTOUT PC7 - - TIM3_CH2 TIM8_CH2 I2CFMP1_ SDA SPI2_SCK/ I2S2_CK I2S3_MCK - USART6_ RX - DFSDM1_ DATIN3 SDIO_D7 EVENTOUT PC8 - - TIM3_CH3 TIM8_CH3 - - - - USART6_ CK QUADSPI_ BK1_IO2 - SDIO_D0 EVENTOUT PC9 MCO_2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN - - - QUADSPI_ BK1_IO0 - SDIO_D1 EVENTOUT PC10 - - - - - - SPI3_SCK/ I2S3_CK USART3_TX - QUADSPI_ BK1_IO1 - SDIO_D2 EVENTOUT PC11 - - - - - I2S3ext_SD SPI3_MISO USART3_RX - QUADSPI_ BK2_NCS FSMC_D2 SDIO_D3 EVENTOUT PC12 - - - - - - SPI3_MOSI/ I2S3_SD USART3_CK - - FSMC_D3 SDIO_CK EVENTOUT PC13 - - - - - - - - - - - - EVENTOUT PC14 - - - - - - - - - - - - EVENTOUT PC15 - - - - - - - - - - - - EVENTOUT DocID028087 Rev 4 Port C Port 63/193 Pinouts and pin description AF1 STM32F412xE/G Table 10. STM32F412xE/G alternate functions (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PD0 - - - - - - - - - CAN1_RX - FSMC_D2/FS MC_DA2 EVENTOUT PD1 - - - - - - - - - CAN1_TX - FSMC_D3/FS MC_DA3 EVENTOUT PD2 - - TIM3_ETR - - - - - - - FSMC_NWE SDIO_CMD EVENTOUT DFSDM1_ DATIN0 USART2_ CTS - QUADSPI_ CLK - FSMC_CLK EVENTOUT DocID028087 Rev 4 Port D Port TRACED1 - - - - PD4 - - - - - - DFSDM1_ CKIN0 USART2_ RTS - - - FSMC_NOE EVENTOUT PD5 - - - - - - - USART2_TX - - - FSMC_NWE EVENTOUT PD6 - - - - - SPI3_MOSI/I 2S3_SD DFSDM1_ DATIN1 USART2_RX - - - FSMC_ NWAIT EVENTOUT PD7 - - - - - - DFSDM1_ CKIN1 USART2_CK - - - FSMC_NE1 EVENTOUT PD8 - - - - - - - USART3_TX - - - FSMC_D13/ FSMC_DA13 EVENTOUT PD9 - - - - - - - USART3_RX - - - FSMC_D14/ FSMC_DA14 EVENTOUT PD10 - - - - - - - USART3_CK - - - FSMC_D15/ FSMC_DA15 EVENTOUT PD11 - - - - I2CFMP1_ SMBA - - USART3_ CTS - QUADSPI_ BK1_IO0 - FSMC_A16 EVENTOUT PD12 - - TIM4_CH1 - I2CFMP1_ SCL USART3_ RTS - QUADSPI_ BK1_IO1 - FSMC_A17 EVENTOUT PD13 - - TIM4_CH2 - I2CFMP1_ SDA - - - - QUADSPI_ BK1_IO3 - FSMC_A18 EVENTOUT PD14 - - TIM4_CH3 - I2CFMP1_ SCL - - - - - - FSMC_D0/ FSMC_DA0 EVENTOUT PD15 - - TIM4_CH4 - I2CFMP1_ SDA - - - - - - FSMC_D1/ FSMC_DA1 EVENTOUT STM32F412xE/G PD3 SPI2_SCK/ I2S2_CK Pinouts and pin description 64/193 Table 10. STM32F412xE/G alternate functions (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PE0 - - TIM4_ETR - - - - - - - - FSMC_NBL0 EVENTOUT PE1 - - - - - - - - - - - FSMC_NBL1 EVENTOUT PE2 TRACECL K - - - - SPI4_SCK/ I2S4_CK SPI5_SCK/ I2S5_CK - - QUADSPI_ BK1_IO2 - FSMC_A23 EVENTOUT PE3 TRACED0 - - - - - - - - - - FSMC_A19 EVENTOUT PE4 TRACED1 - - - - SPI4_NSS/ I2S4_WS SPI5_NSS/ I2S5_WS - DFSDM1_ DATIN3 - - FSMC_A20 EVENTOUT PE5 TRACED2 - - TIM9_CH1 - SPI4_MISO SPI5_MISO - DFSDM1_ CKIN3 - - FSMC_A21 EVENTOUT PE6 TRACED3 - - TIM9_CH2 - SPI4_MOSI/I 2S4_SD SPI5_MOSI/ I2S5_SD - - - - FSMC_A22 EVENTOUT PE7 - TIM1_ETR - - - - DFSDM1_ DATIN2 - - - QUADSPI_ BK2_IO0 FSMC_D4/ FSMC_DA4 EVENTOUT PE8 - TIM1_CH1N - - - - DFSDM1_ CKIN2 - - - QUADSPI_ BK2_IO1 FSMC_D5/ FSMC_DA5 EVENTOUT PE9 - TIM1_CH1 - - - - DFSDM1_ CKOUT - - - QUADSPI_ BK2_IO2 FSMC_D6/ FSMC_DA6 EVENTOUT PE10 - TIM1_CH2N - - - - - - - - QUADSPI_ BK2_IO3 FSMC_D7/ FSMC_DA7 EVENTOUT PE11 - TIM1_CH2 - - - SPI4_NSS/ I2S4_WS SPI5_NSS/ I2S5_WS - - - FSMC_D8/ FSMC_DA8 EVENTOUT PE12 - TIM1_CH3N - - - SPI4_SCK/ I2S4_CK SPI5_SCK/ I2S5_CK - - - - FSMC_D9/ FSMC_DA9 EVENTOUT PE13 - TIM1_CH3 - - - SPI4_MISO SPI5_MISO - - - - FSMC_D10/ FSMC_DA10 EVENTOUT PE14 - TIM1_CH4 - - - SPI4_MOSI/I 2S4_SD SPI5_MOSI/ I2S5_SD - - - - FSMC_D11/ FSMC_DA11 EVENTOUT PE15 - TIM1_BKIN - - - - - - - - - FSMC_D12/ FSMC_DA12 EVENTOUT DocID028087 Rev 4 Port E Port 65/193 Pinouts and pin description AF1 STM32F412xE/G Table 10. STM32F412xE/G alternate functions (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PF0 - - - - I2C2_SDA - - - - - - FSMC_A0 EVENTOUT PF1 - - - - I2C2_SCL - - - - - - FSMC_A1 EVENTOUT PF2 - - - - I2C2_SMBA - - - - - - FSMC_A2 EVENTOUT PF3 - - TIM5_CH1 - - - - - - - - FSMC_A3 EVENTOUT PF4 - - TIM5_CH2 - - - - - - - - FSMC_A4 EVENTOUT PF5 - - TIM5_CH3 - - - - - - - - FSMC_A5 EVENTOUT - - EVENTOUT DocID028087 Rev 4 Port F Port TRACED0 - - TIM10_CH1 - - - - - PF7 TRACED1 - - TIM11_CH1 - - - - - QUADSPI_ BK1_IO2 - - EVENTOUT PF8 - - - - - - - - - TIM13_CH1 QUADSPI_ BK1_IO0 - EVENTOUT PF9 - - - - - - - - - TIM14_CH1 QUADSPI_ BK1_IO1 - EVENTOUT PF10 - TIM1_ETR TIM5_CH4 - - - - - - - - - EVENTOUT PF11 - - - TIM8_ETR - - - - - - - - EVENTOUT PF12 - - - TIM8_BKIN - - - - - - - FSMC_A6 EVENTOUT PF13 - - - - I2CFMP1_ SMBA - - - - - - FSMC_A7 EVENTOUT PF14 - - - - I2CFMP1_ SCL - - - - - - FSMC_A8 EVENTOUT PF15 - - - - I2CFMP1_ SDA - - - - - - FSMC_A9 EVENTOUT STM32F412xE/G PF6 QUADSPI_ BK1_IO3 Pinouts and pin description 66/193 Table 10. STM32F412xE/G alternate functions (continued) AF0 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15 SYS_AF TIM1/ TIM2 TIM3/ TIM4/ TIM5 TIM8/ TIM9/ TIM10/ TIM11 I2C1/ I2C2/ I2C3/ I2CFMP1 SPI1/I2S1/ SPI2/I2S2/ SPI3/I2S3/ SPI4/I2S4 SPI2/I2S2/SPI3 /I2S3/SPI4/ I2S4/SPI5/I2S5 /DFSDM1 SPI3/I2S3/ USART1/ USART2/ USART3 DFSDM1/ USART3/ USART6/ CAN1 I2C2/I2C3/ I2CFMP1/ CAN1/CAN2 /TIM12/ TIM13/TIM14 /QUADSPI DFSDM1/ QUADSPI/ FSMC /OTG1_FS FSMC /SDIO SYS_AF PG0 - - - - - - - - - CAN1_RX - FSMC_A10 EVENTOUT PG1 - - - - - - - - - CAN1_TX - FSMC_A11 EVENTOUT PG2 - - - - - - - - - - - FSMC_A12 EVENTOUT PG3 - - - - - - - - - - - FSMC_A13 EVENTOUT PG4 - - - - - - - - - - - FSMC_A14 EVENTOUT PG5 - - - - - - - - - - - FSMC_A15 EVENTOUT PG6 - - - - - - - - - - QUADSPI_ BK1_NCS - EVENTOUT PG7 - - - - - - - - USART6_ CK - - - EVENTOUT PG8 - - - - - - - - USART6_ RTS - - - EVENTOUT PG9 - - - - - - - - USART6_ RX QUADSPI_ BK2_IO2 - FSMC_NE2 EVENTOUT PG10 - - - - - - - - - - - FSMC_NE3 EVENTOUT PG11 - - - - - - - - - CAN2_RX - - EVENTOUT PG12 - - - - - - - - USART6_ RTS CAN2_TX - FSMC_NE4 EVENTOUT PG13 TRACED2 - - - - - - - USART6_ CTS - - FSMC_A24 EVENTOUT PG14 TRACED3 - - - - - - - USART6_ TX QUADSPI_ BK2_IO3 - FSMC_A25 EVENTOUT PG15 - - - - - - - - USART6_ CTS - - - EVENTOUT PH0 - - - - - - - - - - - - EVENTOUT PH1 - - - - - - - - - - - - EVENTOUT 67/193 Port H DocID028087 Rev 4 Port G Port Pinouts and pin description AF1 STM32F412xE/G Table 10. STM32F412xE/G alternate functions (continued) Memory mapping 5 STM32F412xE/G Memory mapping The memory map is shown in Figure 18. Figure 18. Memory map 5HVHUYHG &RUWH[1/20LQWHUQDO SHULSKHUDOV 5HVHUYHG [([)))))))) [([())))) [$')))))) [$))) $+% [ [))))))) $+% 5HVHUYHG [)))))))) 0E\WH EORFN LQWHUQDO 3HULSKHUDOV [ [[))))))) [)) $+% [( ['))))))) 0E\WH EORFN 1RWXVHG [& [%))))))) 5HVHUYHG 5HVHUYHG [ [[)))) [)) [$ [$))) )60& DQG 4XDG63, [ [))))))) $3% 0E\WH EORFN 3HULSKHUDOV [ [))))))) 0E\WH EORFN 3HULSKHUDOV [ [))))))) 0E\WH EORFN 3HULSKHUDOV [ 5HVHUYHG 65$0 .%DOLDVHG E\ELWEDQGLQJ 5HVHUYHG 2SWLRQE\WHV [[))))))) [[)))) 5HVHUYHG [)))&[))))))) [ [[)))) [)) [)))&[)))& [)))$[)))%))) 5HVHUYHG 273DUHDORFN 6\VWHPPHPRU\ [)))[)))$) [)))[))))) 5HVHUYHG )ODVKPHPRU\ [[))))) [[))()))) $3% [[)))))) 5HVHUYHG $OLDVHGWR)ODVKV\VWHP PHPRU\RU65$0GHSHQGLQJ [[))))) RQWKH%227SLQV [ 68/193 DocID028087 Rev 4 06Y9 STM32F412xE/G Memory mapping Table 11. STM32F412xE/G register boundary addresses Bus (R) Cortex -M4 AHB3 AHB2 AHB1 Boundary address Peripheral 0xE010 0000 - 0xFFFF FFFF Reserved 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 2000 - 0xDFFF FFFF Reserved 0xA000 1000 - 0xA000 1FFF QuadSPI control register 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF QUADSPI 0x7000 0000 - 0x08FFF FFFF Reserved 0x6000 0000 - 0x6FFF FFFF FSMC 0x5006 0C00 - 0x5FFF FFFF Reserved 0x5006 0800 0x5006 0BFF RNG 0x5004 000- 0x5006 07FF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4002 6800 - 0x4FFF FFFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2000 - 0x4002 2FFF Reserved 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA DocID028087 Rev 4 69/193 71 Memory mapping STM32F412xE/G Table 11. STM32F412xE/G register boundary addresses (continued) Bus APB2 70/193 Boundary address Peripheral 0x4001 6400- 0x4001 FFFF Reserved 0x4001 6000 - 0x4001 63FF DFSDM1 0x4001 5400 - 0x4001 5FFF Reserved 0x4001 5000 - 0x4001 53FF SPI5/I2S5 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF SPI4/I2S4 0x4001 3000 - 0x4001 33FF SPI1/I2S1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7400 - 0x4000 FFFF Reserved DocID028087 Rev 4 STM32F412xE/G Memory mapping Table 11. STM32F412xE/G register boundary addresses (continued) Bus APB1 Boundary address Peripheral 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800- 0x4000 6BFF CAN2 0x4000 6400- 0x4000 67FF CAN1 0x4000 6000- 0x4000 63FF I2CFMP1 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 4C00 - 0x4000 53FF Reserved 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 DocID028087 Rev 4 71/193 71 Electrical characteristics STM32F412xE/G 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Input voltage measurement -#5 PIN -#5 PIN # P& 6). -36 72/193 DocID028087 Rev 4 -36 STM32F412xE/G 6.1.6 Electrical characteristics Power supply scheme Figure 21. Power supply scheme 9%$7 9%$7 WR9 *3,2V i) 9''B86% 9&$3B 9&$3B 9'' 966 iQ) i) ,2 /RJLF .HUQHOORJLF &38GLJLWDO 5$0 9ROWDJH UHJXODWRU %<3$66B5(* 9''86% Q) ) 3'5B21 9'' )ODVKPHPRU\ 27* )6 3+< 5HVHW FRQWUROOHU 9''$ 95() Q) ) ,1 /HYHOVKLIWHU 287 9'' %DFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV 3RZHU VZLWFK Q) ) 95() 95() $'& $QDORJ 5&V 3// 966$ 06Y9 1. To connect PDR_ON pin, refer to Section: Power supply supervisor. 2. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 3. VCAP_2 pad is only available on 100-pin and 144-pin packages. 4. VDDA=VDD and VSSA=VSS. 5. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and associated DP/DM GPIOs. VDDUSB value does not depend on the VDD and VDDA values, but it must be the last supply to be provided and the first to disappear. Caution: Each power supply pair (for example VDD/VSS, VDDA/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. DocID028087 Rev 4 73/193 161 Electrical characteristics 6.1.7 STM32F412xE/G Current consumption measurement Figure 22. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 12: Voltage characteristics, Table 13: Current characteristics, and Table 14: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 12. Voltage characteristics Symbol VDD-VSS VIN Ratings Min Max -0.3 4.0 Input voltage on FT and TC pins(2) VSS-0.3 VDD+4.0 Input voltage on any other pin VSS-0.3 4.0 VSS 9.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 External main supply voltage (including VDDA, VDD, VDDUSB and VBAT)(1) Input voltage for BOOT0 |VDDx| |VSSX -VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit see Section 6.3.14: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 13 for the values of the maximum allowed injected current. 74/193 DocID028087 Rev 4 V mV STM32F412xE/G Electrical characteristics Table 13. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source)(1) 160 IVSS (1) -160 IVDDUSB Total current out of sum of all VSS_x ground lines (sink) Total current into VDDUSB power lines (source) 25 IVDD Maximum current into each VDD_x power line (source)(1) 100 IVSS (1) -100 IIO Maximum current out of each VSS_x ground line (sink) Output current sunk by any I/O and control pin 25 Output current sourced by any I/O and control pin -25 Total output current sunk by sum of all I/O and control pins IIO IINJ(PIN) (2) Injected current on FT and TC pins mA 120 Total output current sunk by sum of all USB I/Os Total output current sourced by sum of all I/Os and control IINJ(PIN) (3) Unit 25 pins(2) -120 (4) -5/+0 Injected current on NRST and B pins (4) Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 14. Thermal characteristics Symbol TSTG TJ TLEAD Ratings Storage temperature range Maximum junction temperature Maximum lead temperature during soldering (WLCSP64, LQFP64/100/144, UFQFPN48, UFBGA100/144) Value Unit -65 to +150 125 C see note (1) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011). DocID028087 Rev 4 75/193 161 Electrical characteristics STM32F412xE/G 6.3 Operating conditions 6.3.1 General operating conditions Table 15. General operating conditions Symbol fHCLK Parameter Internal AHB clock frequency Conditions Min Typ Max Power Scale3: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x01 0 - 64 Power Scale2: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x10 0 - 84 Power Scale1: Regulator ON, VOS[1:0] bits in PWR_CR register = 0x11 0 - 100 Unit MHz fPCLK1 Internal APB1 clock frequency - 0 - 50 MHz fPCLK2 Internal APB2 clock frequency - 0 - 100 MHz Standard operating voltage - 1.7(1) - 3.6 V 1.7(1) - 2.4 VDD VDDA(2)(3) VDDUSB VBAT Analog operating voltage (ADC limited to 1.2 M samples) Analog operating voltage (ADC limited to 2.4 M samples) Must be the same potential as VDD(4) USB supply voltage USB not used (supply voltage for PA11 and USB used(5) PA12 pins) Backup operating voltage - V 2.4 - 3.6 1.7 3.3 3.6 3.0 - 3.6 1.65 - 3.6 V V VOS[1:0] bits in PWR_CR register = 0x01 1.08(6) 1.14 1.20(6) Max frequency 64 MHz V12 V12 VIN Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins Regulator OFF: 1.2 V external voltage must be supplied on VCAP_1/VCAP_2 pins VOS[1:0] bits in PWR_CR register = 0x11 Max frequency 100 MHz 1.26 1.32 1.38 Max frequency 64 MHz 1.10 1.14 1.20 Max frequency 84 MHz 1.20 1.26 1.32 Max frequency 100 MHz 1.26 1.32 1.38 -0.3 - 5.5 -0.3 - 5.2 0 - 9 Input voltage on RST, FT and 2 V VDD 3.6 V TC pins(7) VDD 2 V Input voltage on BOOT0 pin 76/193 VOS[1:0] bits in PWR_CR register = 0x10 1.20(6) 1.26 1.32(6) Max frequency 84 MHz - DocID028087 Rev 4 V V V STM32F412xE/G Electrical characteristics Table 15. General operating conditions (continued) Symbol PD Parameter Power dissipation at TA = 85C for range 6 or TA = 105C for range 7(8) Min Typ Max UFQFPN48 - - 625 WLCSP64 - - 392 LQFP64 - - 425 LQFP100 - - 465 LQFP144 UFBGA100 - - 351 UFBGA144 - - 416 -40 - 85 Maximum power dissipation Low power dissipation -40 - 105 Ambient temperature for range 7 Maximum power dissipation -40 - 105 -40 - 125 Range 6 -40 - 105 Range 7 -40 - 125 Junction temperature range (9) Low power Unit mW 571 Ambient temperature for range 6 TA TJ Conditions dissipation(9) C 1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 2. When the ADC is used, refer to Table 71: ADC characteristics. 3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 5. Only the DM (PA11) and DP (PA12) pads are supplied through VDDUSB. For application where the VBUS (PA9) is directly connected to the chip, a minimum VDD supply of 2.7V is required. (some application examples are shown in appendix B) 6. Guaranteed by test in production 7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. DocID028087 Rev 4 77/193 161 Electrical characteristics STM32F412xE/G Table 16. Features depending on the operating power supply range Operating power supply range ADC operation VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps VDD = 2.7 to 3.6 V(6) Conversion time up to 2.4 Msps Maximum Flash memory access frequency with no wait states (fFlashmax) Maximum Flash memory access frequency with wait states (1)(2) I/O operation Clock output frequency on I/O pins(3) Possible Flash memory operations 100 MHz with 6 wait states - No I/O up to 30 MHz compensation 8-bit erase and program operations only 18 MHz 100 MHz with 5 wait states - No I/O up to 30 MHz compensation 16-bit erase and program operations 24 MHz 100 MHz with 4 wait states - I/O compensation up to 50 MHz works 16-bit erase and program operations 100 MHz with 3 wait states - up to 100 MHz when VDD = - I/O 3.0 to 3.6 V compensation - up to works 50 MHz when VDD = 2.7 to 3.0 V 32-bit erase and program operations 16 MHz (5) 30 MHz 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. Refer to Table 58: I/O AC characteristics for frequencies vs. external load. 4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 5. Prefetch available over the complete VDD supply range. 6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V. 78/193 DocID028087 Rev 4 STM32F412xE/G 6.3.2 Electrical characteristics VCAP_1/VCAP_2 external capacitors Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors are replaced by a single capacitor. CEXT is specified in Table 17. Figure 23. External capacitor CEXT & (65 5/HDN 069 1. Legend: ESR is the equivalent series resistance. Table 17. VCAP_1/VCAP_2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor with the pins VCAP_1 and VCAP_2 available 2.2 F ESR ESR of external capacitor with the pins VCAP_1 and VCAP_2 available <2 CEXT Capacitance of external capacitor with a single VCAP pin available 4.7 F ESR ESR of external capacitor with a single VCAP pin available <1 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 6.3.3 Operating conditions at power-up/power-down (regulator ON) Subject to general operating conditions for TA. Table 18. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD Parameter Min Max VDD rise time rate 20 VDD fall time rate 20 DocID028087 Rev 4 Unit s/V 79/193 161 Electrical characteristics 6.3.4 STM32F412xE/G Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 19. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 VDD fall time rate Power-down 20 VCAP_1 and VCAP_2 rise time rate Power-up 20 VCAP_1 and VCAP_2 fall time rate Power-down 20 Unit s/V 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below 1.08 V. Note: This feature is only available for UFBGA100 and UFBGA144 packages. 6.3.5 Embedded reset and power control block characteristics The parameters given in Table 20 are derived from tests performed under ambient temperature and VDD supply voltage @ 3.3V. Table 20. Embedded reset and power control block characteristics Symbol (2) VPOR/PDR 80/193 Conditions Programmable voltage detector level selection VPVD VPVDhyst Parameter Min Typ Max PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 PLS[2:0]=101 (falling edge) 2.65 2.84 3.02 PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 - 100 - Falling edge 1.60(1) 1.68 1.76 Rising edge 1.64 1.72 1.80 PVD hysteresis - Power-on/power-down reset threshold DocID028087 Rev 4 Unit V mV V STM32F412xE/G Electrical characteristics Table 20. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 40 - mV Falling edge 2.13 2.19 2.24 Rising edge 2.23 2.29 2.33 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 Rising edge 2.53 2.59 2.63 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 Rising edge 2.85 2.92 2.97 VPDRhyst(2) PDR hysteresis VBOR1 Brownout level 1 threshold VBOR2 VBOR3 VBORhyst (2) TRSTTEMPO (2)(3) IRUSH(2) ERUSH (2) V BOR hysteresis - - 100 - mV POR reset timing - 0.5 1.5 3.0 ms In-Rush current on voltage regulator poweron (POR or wakeup from Standby) - - 160 200 mA - - 5.4 C In-Rush energy on voltage regulator power- VDD = 1.7 V, TA = 105 C, on (POR or wakeup from IRUSH = 171 mA for 31 s Standby) 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. 3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is fetched by the user application code. 6.3.6 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 22: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. DocID028087 Rev 4 81/193 161 Electrical characteristics STM32F412xE/G Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in input mode with a static value at VDD or VSS (no load). * All peripherals are disabled except if it is explicitly mentioned. * The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges (refer to Table 16: Features depending on the operating power supply range). * The voltage scaling is adjusted to fHCLK frequency as follows: - Scale 3 for fHCLK 64 MHz - Scale 2 for 64 MHz < fHCLK 84 MHz - Scale 1 for 84 MHz < fHCLK 100 MHz * The system clock is HCLK, fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK. * External clock is 4 MHz and PLL is ON except if it is explicitly mentioned. * The maximum values are obtained for VDD = 3.6 V and a maximum ambient temperature (TA), and the typical values for TA= 25 C and VDD = 3.3 V unless otherwise specified. Table 21. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V Symbol Parameter Conditions External clock, PLL ON, all peripherals enabled(2)(3) IDD Supply current in Run mode HSI, PLL off, all peripherals enabled(2)(3) External clock, PLL ON, all peripherals disabled(3) HSI, PLL off, all peripherals disabled(3) fHCLK (MHz) Max(1) Typ TA= 25 C TA= 25 C Unit TA=85 C TA=105 C 100 28.1 30.24 31.27 32.21 84 22.7 24.05 24.54 25.11 64 15.7 16.99 17.47 18.03 50 12.3 13.36 13.82 14.36 25 6.5 7.44 7.82 8.30 20 5.6 6.16 6.66 7.20 16 3.9 4.70 5.31 6.08 1 0.6 0.78 1.33 1.98 100 14.0 15.48 16.08 16.83 84 11.3 12.23 12.75 13.41 64 7.9 8.84 9.31 10.01 50 6.2 7.06 7.53 8.19 25 3.4 4.18 4.61 5.13 20 2.9 3.44 3.98 4.65 16 2.0 2.51 3.13 3.89 1 0.5 0.64 1.21 1.90 1. Based on characterization, not tested in production unless otherwise specified 2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part. 82/193 DocID028087 Rev 4 mA STM32F412xE/G Electrical characteristics Table 22. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V Max(1) Typ Symbol Parameter fHCLK (MHz) Conditions External clock, PLL ON, all peripherals enabled(2) IDD Supply current in Run mode HSI, PLL OFF(4), all peripherals enabled(2) External clock, PLL ON, all peripherals disabled(2) HSI, PLL OFF, all peripherals disabled(2) TA= 25 C TA= 25 C TA= 85 C TA= 105 C 100 28.4 28.80(3) 30.84 32.39(3) 84 23.0 24.09(3) 25.20 26.57(3) 64 16.0 16.83(3) 17.77 19.12(3) 50 12.6 13.46 13.98 14.68 25 6.8 7.63 8.14 8.61 20 5.8 6.31 6.74 7.43 16 3.9 4.65 5.33 6.11 1 0.6 0.78 1.34 2.00 100 14.3 15.09(3) 16.22 17.90(3) 84 11.6 12.28(3) 13.36 14.99(3) 64 8.2 8.75(3) 9.68 11.21(3) 50 6.5 7.21 7.69 8.47 25 3.6 4.22 4.68 5.29 20 3.2 3.65 4.18 4.94 16 2.0 2.48 3.12 3.94 1 0.5 0.65 1.26 1.94 Unit mA 1. Based on characterization, not tested in production unless otherwise specified 2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part. 3. Tested in production 4. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be considered DocID028087 Rev 4 83/193 161 Electrical characteristics STM32F412xE/G Table 23. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V Symbol Parameter Conditions fHCLK (MHz) External clock, PLL ON, all peripherals enabled(2)(3) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(2) External clock, PLL ON(4) all peripherals disabled(2) HSI, PLL OFF, all peripherals disabled(2) Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 26.9 28.78 29.86 31.30 84 21.6 23.14 23.93 24.89 64 15.0 16.08 16.70 17.46 50 11.8 12.74 13.33 14.07 25 6.3 7.13 7.69 8.30 20 5.5 6.09 6.64 7.30 16 3.9 4.20 4.78 4.49 1 0.9 0.98 1.50 2.20 100 12.7 13.82 14.71 15.76 84 10.3 11.20 11.97 12.96 64 7.2 7.87 8.57 9.41 50 5.7 6.33 7.02 7.87 25 3.2 3.77 4.38 5.13 20 2.9 3.31 3.93 4.69 16 2.1 2.25 2.83 3.56 1 0.7 0.83 1.42 2.12 Unit mA 1. Based on characterization, not tested in production unless otherwise specified. 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part. 4. Refer to Table 44 and RM0383 for the possible PLL VCO setting 84/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 24. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V Symbol Parameter Conditions fHCLK (MHz) External clock, PLL ON(2), all peripherals enabled(3) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3) External clock, PLL ON(2) all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 27.2 28.70(4) 30.14 31.98 84 21.9 23.60 24.31 25.37 64 15.2 16.45 17.03 17.87 50 12.1 13.12 13.67 14.46 25 6.6 7.59 8.12 8.77 20 5.7 6.51 7.07 7.77 16 4.0 4.32 4.88 5.69 1 0.8 1.14 1.67 2.38 100 13.0 14.06(4) 15.34 17.27 84 10.5 11.21 12.16 13.47 64 7.5 8.29 9.01 9.88 50 6.0 6.73 7.32 8.27 25 3.5 4.18 4.73 5.57 20 3.1 3.72 4.25 5.10 16 2.1 2.41 2.94 3.75 1 0.7 0.99 1.51 2.30 Unit mA 1. Based on characterization, not tested in production unless otherwise specified. 2. Refer to Table 44 and RM0383 for the possible PLL VCO setting 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 4. Tested in production. DocID028087 Rev 4 85/193 161 Electrical characteristics STM32F412xE/G Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V Symbol Parameter Conditions fHCLK (MHz) External clock, PLL ON(2), all peripherals enabled(3) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(3) External clock, PLL ON(2) all peripherals disabled(3) HSI, PLL OFF, all peripherals disabled(3) Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 36.3 38.95 41.19 42.95 84 31.1 33.22 34.81 36.10 64 22.3 23.97 25.10 26.23 50 18.3 19.77 20.65 21.73 25 10.1 11.39 12.16 13.11 20 8.6 9.60 10.25 11.06 16 6.3 6.85 7.51 8.38 1 1.1 1.39 1.82 2.61 100 22.1 23.95 25.80 27.50 84 19.7 20.79 22.52 24.12 64 14.5 15.88 17.21 18.54 50 12.2 13.38 14.59 15.79 25 7.0 8.05 8.89 10.16 20 6.0 6.84 7.51 8.52 16 4.4 4.91 5.56 6.54 1 0.9 1.25 1.79 2.59 Unit mA 1. Based on characterization, not tested in production unless otherwise specified. 2. Refer to Table 44 and RM0383 for the possible PLL VCO setting 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 86/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 26. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V Symbol Parameter Conditions External clock, PLL ON, all peripherals enabled(2)(3) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled(2)(3) External clock, PLL ON(3) all peripherals disabled HSI, PLL OFF, all peripherals disabled(3) fHCLK (MHz) Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 35.9 38.55 40.77 42.52 84 29.4 31.59 33.12 34.42 64 22.4 24.02 25.15 26.28 50 18.6 20.07 21.08 22.05 25 10.3 11.62 12.39 13.34 20 8.9 9.85 10.59 11.32 16 6.7 7.26 8.04 8.80 1 1.1 1.44 1.99 2.66 100 21.7 23.55 25.48 27.07 84 18.0 19.16 20.93 22.39 64 14.6 15.93 17.32 18.59 50 12.5 13.63 14.90 16.07 25 7.2 8.25 9.26 10.26 20 6.3 7.15 7.99 8.84 16 4.9 5.37 6.20 7.03 1 1.0 1.30 1.91 2.65 Unit mA 1. Based on characterization, not tested in production unless otherwise specified. 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the analog part. DocID028087 Rev 4 87/193 161 Electrical characteristics STM32F412xE/G Table 27. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V Symbol Parameter Conditions External clock, PLL ON, all peripherals enabled(2) IDD Supply current in Run mode HSI, PLL OFF, all peripherals enabled External clock, PLL ON(2) all peripherals disabled HSI, PLL OFF, all peripherals disabled fHCLK (MHz) Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 38.9 41.10 42.85 44.28 84 32.8 34.61 35.77 36.72 64 23.6 24.96 25.84 26.64 50 18.7 19.90 20.67 21.45 25 10.1 11.11 11.70 12.40 20 8.6 9.46 10.07 10.81 16 6.3 6.77 7.42 8.21 1 1.1 1.35 1.84 2.59 100 24.7 26.11 27.59 28.84 84 21.4 22.22 23.53 24.66 64 15.8 16.80 17.90 18.99 50 12.6 13.51 14.52 15.54 25 7.0 7.85 8.57 9.39 20 6.0 6.67 7.37 8.26 16 4.5 4.80 5.47 6.33 1 0.9 1.25 1.81 2.58 Unit mA 1. Based on characterization, not tested in production unless otherwise specified. 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 88/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 28. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V Symbol Parameter Conditions All peripherals enabled(2), External clock, PLL ON, Flash deep power down enabled(2), All peripherals HSI, PLL OFF, Flash deep power down All peripherals enabled(2), External clock, PLL ON Flash ON IDD Supply current in Sleep mode All peripherals enabled(2), HSI, PLL ON, Flash ON All peripherals disabled, External clock, PLL ON(2), Flash deep power down All peripherals disabled, HSI, PLL OFF(2), Flash deep power down All peripherals disabled, External clock, PLL ON(2), Flash ON All peripherals disabled, HSI, PLL OFF(2), Flash ON fHCLK (MHz) Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 17.7 18.48(3) 19.83 21.70 84 14.3 15.39 16.31 17.48 64 10.0 10.71 11.35 12.13 50 7.9 8.53 9.13 9.89 25 4.4 4.99 5.46 6.11 20 4.0 4.42 4.95 5.64 16 2.7 2.83 3.47 4.21 1 0.5 0.68 1.25 1.92 100 18.1 19.39 20.70 22.24 84 14.7 15.80 16.71 17.92 64 10.3 11.02 11.66 12.45 50 8.2 8.88 9.53 10.26 25 4.7 5.30 5.82 6.53 20 4.2 4.67 5.18 5.90 16 2.7 3.10 3.72 4.50 1 0.8 0.93 1.50 2.18 100 3.2 3.42 4.98 6.88 84 2.6 3.09 3.63 4.44 64 2.0 2.33 2.81 3.46 50 1.7 2.02 2.54 3.12 25 1.2 1.63 2.21 2.89 20 1.3 1.62 2.09 2.78 16 0.5 0.63 1.24 1.92 1 0.4 0.53 1.14 1.82 100 3.6 4.17 4.84 5.63 84 3.0 3.49 4.13 4.88 64 2.3 2.69 3.23 3.85 50 2.0 2.33 2.83 3.45 25 1.4 1.88 2.39 3.06 20 1.5 1.88 2.43 3.06 16 0.8 0.91 1.50 2.22 1 0.7 0.78 1.37 2.09 Unit mA 1. Based on characterization, not tested in production unless otherwise specified. DocID028087 Rev 4 89/193 161 Electrical characteristics STM32F412xE/G 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). 3. Tested in production. Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V Symbol Parameter fHCLK (MHz) Conditions External clock, PLL ON, Flash deep power down, all peripherals enabled(2) OFF(2), IDD Supply current in Sleep mode HSI, PLL Flash deep power down, all peripherals enabled ON(2) External clock, PLL all peripherals enabled, Flash ON HSI, PLL OFF(2), all peripherals enabled, Flash ON 90/193 Max(1) Typ TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 17.3 18.62 19.90 21.40 84 14.0 15.08 16.04 17.16 64 9.7 10.41 11.02 11.80 50 7.6 8.27 8.89 9.62 25 4.2 4.79 5.35 6.00 20 3.7 4.11 4.67 5.31 16 2.4 2.81 3.45 4.20 1 0.5 0.67 1.27 1.91 100 17.8 19.08 20.35 21.90 84 14.4 15.49 16.42 17.59 64 10.0 10.76 11.43 12.18 50 7.9 8.58 9.19 9.94 25 4.4 4.99 5.54 6.21 20 4.0 4.42 4.95 5.64 16 2.7 3.09 3.75 4.49 1 0.8 0.93 1.52 2.18 DocID028087 Rev 4 Unit mA STM32F412xE/G Electrical characteristics Table 29. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V (continued) Symbol Parameter fHCLK (MHz) Conditions TA = 25 C TA = 25 C TA = 85 C TA = 105 C 100 2.9 3.51 4.14 4.90 84 2.4 2.83 3.46 4.16 64 1.7 2.08 2.59 3.18 50 1.4 1.77 2.23 2.84 25 1.0 1.37 1.88 2.50 20 1.3 1.37 1.88 2.50 16 0.5 0.63 1.23 1.91 1 0.4 0.52 1.13 1.81 100 3.3 3.22 3.98 4.90 84 2.8 2.62 3.30 4.16 64 2.1 1.89 2.50 3.18 50 1.7 1.58 2.16 2.84 25 1.2 1.28 1.82 2.50 20 1.3 1.28 1.82 2.50 16 0.8 0.88 1.36 1.91 1 0.7 0.77 1.26 1.81 All peripherals disabled, External clock, PLL ON(2), Flash deep power down IDD Supply current in Sleep mode Max(1) Typ All peripherals disabled, HSI, PLL OFF(2), Flash deep power down All peripherals disabled, External clock, PLL ON(2), Flash ON All peripherals disabled, HSI, PLL OFF(2), Flash ON Unit mA 1. Based on characterization, not tested in production unless otherwise specified. 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). Table 30. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V Typ(1) Symbol Conditions Flash in Stop mode, all oscillators OFF, no independent watchdog IDD_STOP Flash in Deep power Parameter Max(1) TA = 25 C TA = 25 C TA = 85 C TA = 105 C Main regulator usage 121.1 168.0 648.7 1213.0 Low power regulator usage 50.8 104.7 667.4 1328.0 Main regulator usage 79.1 122.0 609.1 1181.0 22.4 74.7 631.9 1286.0 18.5 58.5 558.3 1145.0 down mode, all oscillators Low power regulator usage OFF, no independent Low power low voltage regulator watchdog usage Unit A 1. Based on characterization, not tested in production. DocID028087 Rev 4 91/193 161 Electrical characteristics STM32F412xE/G Table 31. Typical and maximum current consumption in Stop mode - VDD=3.6 V Max(1) Typ Symbol Conditions Parameter Flash in Stop mode, all oscillators OFF, no independent watchdog TA = 25 C TA = 25 C TA = 85 C TA = 105 C Main regulator usage 124.0 179.0(2) 907.2 1762.0(2) Low power regulator usage 52.8 104.9(2) 773.8 IDD_STOP Flash in Deep power Main regulator usage 87.6 down mode, all oscillators Low power regulator usage 26.2 OFF, no independent Low power low voltage regulator usage 20.1 watchdog 1559.0 123.0 698.5 1374.0 74.7 737.2 1515.0 (2) 58.5 Unit A 629.1 1299.0(2) 1. Based on characterization, not tested in production. 2. Tested in production. Table 32. Typical and maximum current consumption in Standby mode - VDD= 1.7 V Typ(1) Symbol Parameter Conditions Low-speed oscillator (LSE in low drive mode) and RTC ON IDD_STBY TA = 25 C Max(2) TA = TA = 25 C 85 C TA = 105 C 1.8 3.7 12.9 23.7 Supply current in Low-speed oscillator (LSE in high drive Standby mode mode) and RTC ON 2.6 4.5 13.7 24.5 RTC and LSE OFF 1.1 3.0 13.1 25.0 Unit A 1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 A. 2. Based on characterization, not tested in production unless otherwise specified. Table 33. Typical and maximum current consumption in Standby mode - VDD= 3.6 V Typ(1) Symbol Parameter Conditions Low-speed oscillator (LSE in low drive mode) and RTC ON IDD_STBY TA = 25 C Max(2) TA = TA = 25 C 85 C 3.7 5.4 16.0 28.4 Supply current in Low-speed oscillator (LSE in high drive Standby mode mode) and RTC ON 4.5 6.2 16.8 29.2 RTC and LSE OFF 2.6 4.0 16.0 30.0(3) 1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 A. 2. Guaranteed by characterization, not tested in production unless otherwise specified. 3. Tested in production. 92/193 TA = 105 C DocID028087 Rev 4 Unit A STM32F412xE/G Electrical characteristics Table 34. Typical and maximum current consumptions in VBAT mode Max(2) Typ Symbol TA = TA = 85 C 105 C Unit TA = 25 C Conditions(1) Parameter VBAT = VBAT= VBAT = VBAT = VBAT = 3.6 V 1.7 V 2.4 V 3.3 V 3.6 V Low-speed oscillator (LSE in lowdrive mode) and RTC ON Backup IDD_VBAT domain supply Low-speed oscillator (LSE in highcurrent drive mode) and RTC ON RTC and LSE OFF 0.74 0.87 1.04 1.11 3.0 5.0 1.52 1.70 1.97 2.09 3.8 5.8 0.04 0.04 0.05 0.05 2.0 4.0 A 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization, not tested in production. Figure 24. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator "low power" mode selection) 9 9 ,''B9%$7 $ 9 9 9 9 9 7HPSHUDWXUH & 069 DocID028087 Rev 4 93/193 161 Electrical characteristics STM32F412xE/G Figure 25. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator "high drive" mode selection) 9 ,''B9%$7 $ 9 9 9 9 9 9 9 9 7HPSHUDWXUH & 069 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 56: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 36: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O 94/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. DocID028087 Rev 4 95/193 161 Electrical characteristics STM32F412xE/G Table 35. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling Typ frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 90 MHz 1.67 2 MHz 0.10 8 MHz 0.35 25 MHz 1.05 50 MHz 2.20 60 MHz 2.40 84 MHz 3.55 90 MHz 4.23 2 MHz 0.20 8 MHz 0.65 25 MHz 1.85 50 MHz 2.45 60 MHz 4.70 84 MHz 8.80 90 MHz 10.47 2 MHz 0.25 8 MHz 1.00 25 MHz 3.45 50 MHz 7.15 60 MHz 11.55 2 MHz 0.32 8 MHz 1.27 25 MHz 3.88 50 MHz 12.34 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 96/193 DocID028087 Rev 4 Unit mA STM32F412xE/G Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: * At startup, all I/O pins are in analog input configuration. * All peripherals are disabled unless otherwise mentioned. * The ART accelerator is ON. * Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. * HCLK is the system clock at 100 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK. The given value is calculated by measuring the difference of current consumption * - with all peripherals clocked off, - with only one peripheral clocked on, - scale 1 with fHCLK = 100 MHz, - scale 2 with fHCLK = 84 MHz, - scale 3 with fHCLK = 64 MHz. Ambient operating temperature is 25 C and VDD=3.3 V. Table 36. Peripheral current consumption IDD (Typ) Peripheral AHB1 Scale 2 Scale 3 GPIOA 1.84 1.75 1.55 GPIOB 1.90 1.80 1.61 GPIOC 1.77 1.67 1.50 GPIOD 1.67 1.58 1.42 GPIOE 1.75 1.67 1.48 GPIOF 1.65 1.56 1.39 GPIOG 1.65 1.56 1.39 GPIOH 0.62 0.57 0.53 CRC 0.26 0.25 0.22 (1) 1,71N+2,98 1,62N+2,87 1,45N+2,58 (1) 1,78N+2,62 1,70N+2.53 1,52N+2.26 DMA1 DMA2 AHB2 AHB3 Unit Scale 1 RNG 0.77 0.74 0.66 USB_OTG_FS 19.68 18.73 16.78 FSMC 5.36 5.11 4.56 QSPI 9.99 9.51 8.53 DocID028087 Rev 4 A/MHz 97/193 161 Electrical characteristics STM32F412xE/G Table 36. Peripheral current consumption (continued) IDD (Typ) Peripheral APB1 98/193 Unit Scale 1 Scale 2 Scale 3 AHB-APB1 bridge 1.10 1.00 0.94 TIM2 13.62 12.95 11.59 TIM3 10.56 10.05 8.97 TIM4 10.72 10.21 9.12 TIM5 13.46 12.83 11.47 TIM6 2.92 2.79 2.47 TIM7 2.72 2.60 2.31 TIM12 6.22 5.93 5.28 TIM13 4.70 4.48 3.97 TIM14 4.60 4.38 3.91 WWDG 1.76 1.67 1.47 SPI2/I2S2 4.04 3.83 3.41 SPI3/I2S3 4.26 4.05 3.62 USART2 4.42 4.19 3.75 USART3 4.44 4.21 3.75 I2C1 4.32 4.10 3.66 I2C2 4.36 4.17 3.69 I2C3 4.36 4.14 3.69 I2CFMP1 5.96 5.69 5.06 CAN1 6.18 5.90 5.25 CAN2 5.86 5.52 4.97 PWR 1.82 1.69 1.56 DocID028087 Rev 4 A/MHz STM32F412xE/G Electrical characteristics Table 36. Peripheral current consumption (continued) IDD (Typ) Peripheral APB2 Unit Scale 1 Scale 2 Scale 3 AHB-APB2 bridge 0.09 0.07 0.08 TIM1 6.83 6.46 5.81 TIM8 6.63 6.29 5.63 USART1 3.31 3.11 2.80 USART6 3.21 3.02 2.73 ADC1 3.51 3.31 2.98 SDIO 3.74 3.51 3.17 SPI1 1.47 1.36 1.23 SPI4 1.56 1.45 1.31 SYSCFG 0.54 0.49 0.45 TIM9 3.09 2.92 2.63 TIM10 1.91 1.79 1.61 TIM11 1.93 1.81 1.64 SPI5 1.54 1.44 1.30 DFSDM1 4.25 4.02 3.61 3.23 3.06 2.73 Bus Matrix A/MHz 1. N is the number of stream enable (1...8). 6.3.7 Wakeup time from low-power modes The wakeup times given in Table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PA0/PC0/PC1) pins are used to wakeup from Standby, Stop and Sleep modes. DocID028087 Rev 4 99/193 161 Electrical characteristics STM32F412xE/G Figure 26. Low-power mode wakeup :DNHXSIURP6WRSPRGH PDLQUHJXODWRU 2SWLRQE\WHVDUHQRWUHORDGHG &38UHVWDUW 5HJXODWRU +6,UHVWDUW )ODVKVWRSH[LW UDPSXS :DNHXSIURP6WRSPRGH PDLQUHJXODWRU IODVKLQ'HHSSRZHUGRZQPRGH 2SWLRQE\WHVDUHQRWUHORDGHG &38UHVWDUW 5HJXODWRU +6,UHVWDUW )ODVK'HHS3GUHFRYHU\ UDPSXS :DNHXSIURP6WRS UHJXODWRULQORZSRZHUPRGH 2SWLRQE\WHVDUHQRWUHORDGHG 5HJXODWRU UDPSXS &38UHVWDUW +6,UHVWDUW )ODVKVWRSH[LW :DNHXSIURP6WRS UHJXODWRULQORZSRZHUPRGH IODVKLQ'HHSSRZHUGRZQPRGH 2SWLRQE\WHVDUHQRWUHORDGHG 5HJXODWRU UDPSXS :DNHXSIURP6WDQGE\PRGH &38UHVWDUW )ODVK'HHS3GUHFRYHU\ 5HJXODWRU 2)) 5HJXODWRU UHVWDUW :DNHXSIURP6OHHSDQG )ODVKLQ'HHSSRZHUGRZQ +6,UHVWDUW &38UHVWDUW +6,UHVWDUW 5HJXODWRU 21 &38UHVWDUW )ODVK'HHS3GUHFRYHU\ 2SWLRQE\WHVORDGLQJ 2SWLRQE\WHVDUHQRWUHORDGHG )ODVK'HHS3GUHFRYHU\ 069 All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 37. Low-power mode wakeup timings(1) Symbol Parameter tWUSLEEP Wakeup from Sleep mode tWUSLEEPFDSM 100/193 Conditions Min(1) Typ(1) Max(1) Unit - - 4 6 clk cycles Flash memory in Deep power down mode - - 50.0 s DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 37. Low-power mode wakeup timings(1) (continued) Symbol Conditions Min(1) Typ(1) Max(1) Main regulator - 12.9 15.0 Main regulator, Flash memory in Deep power down mode - 104.9 120.0 Wakeup from Stop mode, regulator in low power mode(2) - 20.8 28.0 Regulator in low power mode, Flash memory in Deep power down mode(2) - 112.9 130.0 Main regulator with Flash in Stop mode or Deep power down - 4.9 7.0 Wakeup from Stop mode, regulator in low power mode and Flash in Stop mode or Deep power down(2) - 12.8 20.0 - - 316.8 400.0 From Flash_Stop mode - 11.0 From Flash Deep power down mode - 50.0 Parameter Wakeup from STOP mode Code execution on Flash tWUSTOP Wakeup from STOP mode code execution on RAM(3) tWUSTOP tWUSTDBY Wakeup from Standby mode tWUFLASH Wakeup of Flash Unit s 1. Guaranteed by characterization, not tested in production. 2. The specification is valid for wakeup from regulator in low power mode or low power low voltage mode, since the timing difference is negligible. 3. For the faster wakeup time for code execution on RAM, the Flash must be in STOP or DeepPower Down mode (see reference manual RM0402). 6.3.8 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56. However, the recommended clock input waveform is shown in Figure 27. The characteristics given in Table 38 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 15. DocID028087 Rev 4 101/193 161 Electrical characteristics STM32F412xE/G Table 38. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 - 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - V ns tr(HSE) tf(HSE) OSC_IN rise or fall time Cin(HSE) (1) OSC_IN input capacitance(1) DuCy(HSE) Duty cycle VSS VIN VDD OSC_IN Input leakage current IL - - 10 - 5 - pF 45 - 55 % - - 1 A 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 56. However, the recommended clock input waveform is shown in Figure 28. The characteristics given in Table 39 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 15. Table 39. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 OSC32_IN input capacitance(1) - 5 - pF 30 - 70 % - - 1 A Cin(LSE) DuCy(LSE) IL ns Duty cycle OSC32_IN Input leakage current VSS VIN VDD 1. Guaranteed by design, not tested in production. 102/193 V DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Figure 27. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR(3% TF(3% T7(3% /3#?). ), T7(3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34-& AI Figure 28. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W: /6( W: /6( W 7/6( ([WHUQDO FORFNVRXUFH I/6(BH[W 26&B,1 ,/ 670) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). DocID028087 Rev 4 103/193 161 Electrical characteristics STM32F412xE/G Table 40. HSE 4-26 MHz oscillator characteristics(1) Symbol fOSC_IN RF IDD Parameter Conditions Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - k VDD=3.3 V, ESR= 30 , CL=5 pF @25 MHz - 450 - VDD=3.3 V, ESR= 30 , CL=10 pF @25 MHz - 530 - - -500 - 500 ppm Startup - - 1 mA/V VDD is stabilized - 2 - ms HSE current consumption ACCHSE(2) HSE accuracy Gm_crit_max Maximum critical crystal gm tSU(HSE) (3) Startup time A 1. Guaranteed by design, not tested in production. 2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 29. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) 26&B28 7 %LDV FRQWUROOHG JDLQ 670) DL 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 41. In the application, the resonator and the load capacitors have to be placed as close as 104/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol RF IDD ACCLSE(2) Parameter Min Typ Max Unit - - 18.4 - M Low-power mode (default) - - 1 High-drive mode - - 3 - -500 - 500 Startup, low-power mode - - 0.56 Startup, high-drive mode - - 1.50 VDD is stabilized - 2 - Feedback resistor LSE current consumption LSE accuracy Gm_crit_max Maximum critical crystal gm tSU(LSE)(3) Conditions startup time A ppm A/V s 1. Guaranteed by design, not tested in production. 2. This parameter depends on the crystal used in the application. Refer to the application note AN2867. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. For information about the LSE high-power mode, refer to the reference manual RM0383. Figure 30. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV & / I /6( 26&B ,1 N+] UHVRQDWRU & / 5) 26&B 28 7 %LDV FRQWUROOHG JDLQ 670) DLD DocID028087 Rev 4 105/193 161 Electrical characteristics 6.3.9 STM32F412xE/G Internal clock source characteristics The parameters given in Table 42 and Table 43 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. High-speed internal (HSI) RC oscillator Table 42. HSI oscillator characteristics (1) L Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % -8 - 4.5 % -4 - 4 % -1 - 1 % (3) ACCHSI TA = -40 to 105 C Accuracy of the HSI oscillator TA = -10 to 85 TA = 25 C(3) C(4) tsu(HSI)(2) HSI oscillator startup time - - 2.2 4 s IDD(HSI)(2) HSI oscillator power consumption - - 60 80 A 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design, not tested in production 3. Based on characterization, not tested in production 4. Factory calibrated, parts not soldered. Figure 31. ACCHSI versus temperature !##(3) 4! # -IN -AX 4YPICAL -36 1. Guaranteed by characterization, not tested in production. 106/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 s LSI oscillator power consumption - 0.4 0.6 A Frequency (3) IDD(LSI)(3) 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by characterization, not tested in production. 3. Guaranteed by design, not tested in production. Figure 32. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -36 DocID028087 Rev 4 107/193 161 Electrical characteristics 6.3.10 STM32F412xE/G PLL characteristics The parameters given in Table 44 and Table 45 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 15. Table 44. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10 MHz fPLL_OUT PLL multiplier output clock - 24 - 100 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75 MHz fVCO_OUT PLL VCO output - 100 - 432 MHz VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 - 25 - - 150 - - 15 - peak to peak - 200 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples. - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 tLOCK PLL lock time Cycle-to-cycle jitter Jitter(3) RMS System clock 100 MHz Period Jitter peak to peak RMS s ps mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of two PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization, not tested in production. 108/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 45. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10 fPLLI2S_OUT PLLI2S multiplier output clock - - - 216 fVCO_OUT PLLI2S VCO output - 100 - 432 tLOCK PLLI2S lock time VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - peak to peak - 280 - Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 Cycle to cycle at 12.288 MHz on 48 kHz period, N=432, R=5 Master I2S clock jitter Jitter(3) Unit MHz s ps mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Guaranteed by characterization, not tested in production. DocID028087 Rev 4 109/193 161 Electrical characteristics 6.3.11 STM32F412xE/G PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 52: EMI characteristics for LQFP144). It is available only on the main PLL. Table 46. SSCG parameter constraints Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 kHz md Peak modulation depth 0.25 - 2 % - 215 MODEPER * INCSTEP (Modulation period) * (Increment Step) - -1 - 1. Guaranteed by design, not tested in production. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x PLLN ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 250 ) ] = 126md(quantitazed)% An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x PLLN ) As a result: md quantized % = ( 250 x 126 x 100 x 5 ) ( ( 2 110/193 DocID028087 Rev 4 15 - 1 ) x 240 ) = 2.002%(peak) STM32F412xE/G Electrical characteristics Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 34. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DLE 6.3.12 Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 47. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - Write / Erase 32-bit mode, VDD = 3.3 V - 12 - DocID028087 Rev 4 Unit mA 111/193 161 Electrical characteristics STM32F412xE/G Table 48. Flash memory programming Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Vprog Mass erase time Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V 1. Guaranteed by characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 112/193 DocID028087 Rev 4 s ms ms s s STM32F412xE/G Electrical characteristics Table 49. Flash memory programming with VPP voltage Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) s - 230 - - 490 - - 875 - - 6.9 - s TA = 0 to +40 C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.6 V VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 1. Guaranteed by design, not tested in production. 2. The maximum programming time is measured after 100K erase operations. 3. VPP should only be connected during programming/erasing. Table 50. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 1 kcycle (2) 10 kcycle at TA = 105 C (2) at TA = 55 C 10 Unit kcycles Years 20 1. Guaranteed by characterization, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. DocID028087 Rev 4 113/193 161 Electrical characteristics STM32F412xE/G The test results are given in Table 52. They are based on the EMS levels and classes defined in application note AN1709. Table 51. EMS characteristics for LQFP144 package Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP144 Voltage limits to be applied on any I/O pin TA = +25 C, fHCLK = 100 MHz, to induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP144 TA = +25 C, fHCLK = 100 MHz, conforms to IEC 61000-4-4 4B When the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1, PA2, on LQFP144 packages and PDR_ON on WLCSP49. As a consequence, it is recommended to add a serial resistor (1 k maximum) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). 114/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading. Table 52. EMI characteristics for LQFP144 Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 8/100 MHz SEMI 6.3.14 Peak level VDD = 3.6 V, TA = 25 C, LQFP144 package, conforming to IEC 61967-2, EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled. 0.1 to 30 MHz 20 30 to 130 MHz 28 130 MHz to 1 GHz 21 EMI Level 3.5 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 53. ESD absolute maximum ratings Symbol VESD(HBM) VESD(CDM) Class Maximum value(1) TA = +25 C conforming to JESD22-A114 2 2000 TA = +25 C conforming to ANSI/ESD STM5.3.1, UFBGA144, UFBGA100, LQFP100, LQFP64, UFQFPN48 4 500 3 400 3 250 Ratings Electrostatic discharge voltage (human body model) Conditions Electrostatic TA = +25 C conforming to ANSI/ESD STM5.3.1, discharge voltage (charge device model) WLCSP64 TA = +25 C conforming to ANSI/ESD STM5.3.1, LQFP144 Unit V 1. Guaranteed by characterization, not tested in production. DocID028087 Rev 4 115/193 161 Electrical characteristics STM32F412xE/G Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 54. Electrical sensitivities Symbol LU 6.3.15 Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 55. 116/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 55. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 pin -0 NA Injected current on NRST pin -0 NA Injected current on PB3, PB4, PB5, PB6, PB7, PB8, PB9, PC13, PC14, PC15, PH1, PDR_ON, PC0, PC1,PC2, PC3, PD1, PD5, PD6, PD7, PE0, PE2, PE3, PE4, PE5, PE6 -0 NA Injected current on any other FT pin -5 NA Injected current on any other pins -5 +5 Unit mA 1. NA = not applicable. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the conditions summarized in Table 15. All I/Os are CMOS and TTL compliant. Table 56. I/O static characteristics Symbol Parameter FT, TC and NRST I/O input low level voltage VIL BOOT0 I/O input low level voltage FT, TC and NRST I/O input high level voltage(5) VIH BOOT0 I/O input high level voltage Conditions Min Typ Max 1.7 VVDD3.6 V - - 0.3VDD(1) 1.75 VVDD 3.6 V, -40 CTA 105 C - - 1.7 VVDD 3.6 V, 0 CTA 105 C - - 1.7 VVDD3.6 V 0.7VDD(1) - 1.75 VVDD 3.6 V, -40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C DocID028087 Rev 4 Unit V 0.1VDD+0.1(2) V 0.17VDD+0.7(2) - - 117/193 161 Electrical characteristics STM32F412xE/G Table 56. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max 1.7 VVDD3.6 V 10% VDD(2)(3) - - 0.1 - - VSS VIN VDD - - 1 VIN = 5 V - - 3 All pins except for PA10 (OTG_FS_ID) VIN = VSS 30 40 50 PA10 (OTG_FS_ID) - 7 10 14 All pins except for PA10 (OTG_FS_ID) VIN = VDD 30 40 50 PA10 (OTG_FS_ID) - 7 10 14 - - 5 - FT, TC and NRST I/O input hysteresis VHYS BOOT0 I/O input hysteresis I/O input leakage current (4) Ilkg I/O FT/TC input leakage current (5) RPU RPD CIO(8) Weak pull-up equivalent resistor(6) Weak pull-down equivalent resistor(7) I/O pin capacitance 1.75 VVDD 3.6 V, -40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C Unit V A k pF 1. Guaranteed by test in production. 2. Guaranteed by design, not tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT and TC I/Os is shown in Figure 35. 118/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Figure 35. FT/TC I/O input characteristics 9,/9,+ 9 ' 9' L P ,+ Q 9 QW H P LUH 77/UHTXLUHPHQW U 9,+PLQ 9 26 0 & ' 9' Q R WL XF LQ RG +P , SU 9 LQ QV WLR HG VW XOD P L 7H V LJQ HV $UHDQRW Q' R G VH GHWHUPLQHG '' D % 9 D[ ,/P QV9 ODWLR X LP V VLJQ Q'H HGR 77/UHTXLUHPHQW9,/PD[ %DV 9 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9'' X HT 9'' 9 069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to 3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 13). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 13). Output voltage levels Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. All I/Os are CMOS and TTL compliant. DocID028087 Rev 4 119/193 161 Electrical characteristics STM32F412xE/G Table 57. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL (1) Output low level voltage for an I/O pin VOH (3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V VDD 3.6 V - 0.4 VDD-0.4 - - 0.4 2.4 - - 1.3(4) VDD-1.3(4) - - 0.4(4) VDD-0.4(4) - - 0.4(5) VDD-0.4(5) - TTL port(2) IIO =+8 mA 2.7 V VDD 3.6 V IIO = +20 mA 2.7 V VDD 3.6 V IIO = +6 mA 1.8 V VDD 3.6 V IIO = +4 mA 1.7 V VDD 3.6 V Unit V V V V V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 13. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 13 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results, not tested in production. 5. Guaranteed by design, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 58, respectively. Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 15. Table 58. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 00 tf(IO)out/ tr(IO)out 120/193 Output high to low level fall time and output low to high level rise time Min Typ Max CL = 50 pF, VDD 2.70 V - - 4 CL = 50 pF, VDD 1.7 V - - 2 CL = 10 pF, VDD 2.70 V - - 8 CL = 10 pF, VDD 1.7 V - - 4 CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 DocID028087 Rev 4 Unit MHz ns STM32F412xE/G Electrical characteristics Table 58. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions fmax(IO)out Maximum frequency(3) 01 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(3) 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Fmax(IO)out Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 50 pF, VDD 2.70 V - - 25 CL = 50 pF, VDD 1.7 V - - 12.5 CL = 10 pF, VDD 2.70 V - - 50 CL = 10 pF, VDD 1.7 V - - 20 CL = 50 pF, VDD 2.7 V - - 10 CL = 50 pF, VDD 1.7 V - - 20 CL = 10 pF, VDD 2.70 V - - 6 CL = 10 pF, VDD 1.7 V - - 10 CL = 40 pF, VDD 2.70 V - - 50(4) CL = 40 pF, VDD 1.7 V - - 25 CL = 10 pF, VDD 2.70 V - - 100(4) CL = 10 pF, VDD 1.7 V - - 50(4) CL = 40 pF, VDD 2.70 V - - 6 CL = 40 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 2.70 V - - 4 CL = 10 pF, VDD 1.7 V - - 6 CL = 30 pF, VDD 2.70 V - - 100(4) CL = 30 pF, VDD 1.7 V - - 50(4) CL = 30 pF, VDD 2.70 V - - 4 CL = 30 pF, VDD 1.7 V - - 6 CL = 10 pF, VDD 2.70 V - - 2.5 CL = 10 pF, VDD 1.7 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller - Unit MHz ns MHz ns MHz ns ns 1. Guaranteed by characterization, not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 36. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. DocID028087 Rev 4 121/193 161 Electrical characteristics STM32F412xE/G Figure 36. I/O AC characteristics definition (;7(51$/ 287387 21&/ WU ,2 RXW WI ,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH,2$&FKDUDFWHULVWLFV 6.3.17 DLG NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56). Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 15. Refer to Table 56: I/O static characteristics for the values of VIH and VIL for NRST pin. Table 59. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 k VF(NRST)(2) NRST Input filtered pulse - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - s VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design, not tested in production. 122/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Figure 37. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW 1567 538 ,QWHUQDO5HVHW )LOWHU ) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 59. Otherwise the reset is not taken into account by the device. 6.3.18 TIM timer characteristics The parameters given in Table 60 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 60. TIMx characteristics(1)(2) Symbol tres(TIM) Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 100 MHz 1 - tTIMxCLK 11.9 - ns 1 - tTIMxCLK 11.9 - ns Parameter Timer resolution time AHB/APBx prescaler>4, fTIMxCLK = 100 MHz fEXT ResTIM tCOUNTER Timer external clock frequency on CH1 to CH4 f TIMxCLK = 100 MHz 0 fTIMxCLK/2 MHz 0 50 MHz Timer resolution - 16/32 bit 0.0119 780 s - 65536 x 65536 tTIMxCLK - 51.1 S 16-bit counter clock period when internal clock fTIMxCLK = 100 MHz is selected Maximum possible count tMAX_COUNT with 32-bit counter fTIMxCLK = 100 MHz 1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers. 2. Guaranteed by design, not tested in production. 3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK >= 4x PCLKx. DocID028087 Rev 4 123/193 161 Electrical characteristics 6.3.19 STM32F412xE/G Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 61. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400 kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the complete solution, contact your local ST sales representative. Table 61. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - 0 900(4) s th(SDA) SDA data hold time 0 3450(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s tSP Pulse width of the spikes that are suppressed by the analog filter for standard fast mode - - 50 120(5) ns Cb Capacitive load for each bus line - 400 - 400 pF ns s 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 124/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 5. The minimum width of the spikes filtered by the analog filter is above tSP (max) Figure 38. I2C bus AC waveforms and measurement circuit 9''B,& 9''B,& 53 53 670)[[ 56 6'$ ,&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 67267$ 6723 WK 6'$ WZ 6&/+ 6&/ WU 6&/ WZ 6&// WI 6&/ WVX 672 06Y9 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 62. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE 2 1. RP = External pull-up resistance, fSCL = I C speed 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. DocID028087 Rev 4 125/193 161 Electrical characteristics STM32F412xE/G FMPI2C characteristics The following table presents FMPI2C characteristics. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output function characteristics (SDA and SCL). Table 63. FMPI2C characteristics(1) Standard mode Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 18 - fFMPI2CC FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 - tw(SCLH) SCL clock high time 4.0 - 0.6 - 0.26 - tsu(SDA) SDA setup time 0.25 - 0.10 - 0.05 - tH(SDA) SDA data hold time 0 - 0 - 0 - - 3.45 - 0.9 - 0.45 tv(SDA,ACK) Data, ACK valid time tr(SDA) tr(SCL) SDA and SCL rise time - 1.0 - 0.30 - 0.12 tf(SDA) tf(SCL) SDA and SCL fall time - 0.30 - 0.30 - 0.12 th(STA) Start condition hold time 4 - 0.6 - 0.26 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - 0.26 - tsu(STO) Stop condition setup time 4 - 0.6 - 0.26 - 4.7 - 1.3 - 0.5 - tSP Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode - - 0.05 0.1 0.05 0.1 Cb Capacitive load for each bus Line - 400 - 400 - 550(2) tw(STO:STA) Stop to Start condition time (bus free) 1. Based on characterization results, not tested in production. 2. Can be limited. Maximum supported value can be retrieved by referring to the following formulas: tr(SDA/SCL) = 0.8473 x Rp x Cload Rp(min) = (VDD -VOL(max)) / IOL(max) 126/193 DocID028087 Rev 4 s pF STM32F412xE/G Electrical characteristics Figure 39. FMPI2C timing diagram and measurement circuit 9''B,& 9''B,& 53 53 670)[[ 56 6'$ ,&EXV 56 6&/ 67$575(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 67267$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 06Y9 DocID028087 Rev 4 127/193 161 Electrical characteristics STM32F412xE/G SPI interface characteristics Unless otherwise specified, the parameters given in Table 64 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 64. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Duty(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master full duplex/receiver mode, 2.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Master transmitter mode 1.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Master mode 1.7 V < VDD < 3.6 V SPI1/2/3/4/5 - - 25 Slave transmitter/full duplex mode 2.7 V < VDD < 3.6 V SPI1//4/5 - - 50 Slave transmitter/full duplex mode 1.7 V < VDD < 3.6 V SPI1/4/5 - - 35(2) Slave receiver mode, 1.7 V < VDD < 3.6 V SPI1/4/5 - - 50 Slave mode, 1.7 V < VDD < 3.6 V SPI2/3 - - 25 30 50 70 % Duty cycle of SPI clock Slave mode frequency Unit MHz tw(SCKH) tw(SCKL) SCK high and low time Master mode, SPI presc = 2 TPCLK-1.5 TPCLK TPCLK +1.5 ns tsu(NSS) NSS setup time Slave mode, SPI presc = 2 3TPCLK - - ns th(NSS) NSS hold time Slave mode, SPI presc = 2 2TPCLK - - ns Master mode 4.5 - - ns Slave mode 1.5 - - ns Master mode 5 - - ns Slave mode 0.5 - - ns tsu(MI) tsu(SI) th(MI) th(SI) 128/193 Data input setup time Data input hold time DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 64. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 7.5 9 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V - 7.5 14 ns tv(SO) Data output valid time th(SO) Data output hold time Slave mode (after enable edge), 1.7 V < VDD < 3.6 V 5.5 - - ns tv(MO) Data output valid time Master mode (after enable edge) - 3 8 ns Master mode (after enable edge) 2 - - ns th(MO) Data output hold time 1. Guaranteed by characterization, not tested in production. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50% Figure 40. SPI timing diagram - slave mode and CPHA = 0 166LQSXW 6&.,QSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ W9 62 WD 62 0,62 287387 WK 62 06%287 %,7287 06%,1 %,7,1 WU 6&. WI 6&. WGLV 62 /6%287 WVX 6, 026, ,1387 /6%,1 WK 6, DLF DocID028087 Rev 4 129/193 161 Electrical characteristics STM32F412xE/G Figure 41. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW 6&.LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ 0,62 287387 06%287 WU 6&. WI 6&. %,7287 WGLV 62 /6%287 WK 6, WVX 6, 026, ,1387 WK 62 WY 62 WD 62 06%,1 %,7,1 /6%,1 DLE Figure 42. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ 06%,1 WU 6&. WI 6&. %,7,1 /6%,1 WK 0, 026, 287387 06%287 WY 02 % , 7287 /6%287 WK 02 DLF 130/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 65 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 65. I2S dynamic characteristics(1) Symbol Parameter fMCK I2S Main clock output fCK I2S clock frequency DCK Conditions Min Max Unit 256x8K 256xFs(2) MHz Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 - I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 5 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 2 - th(WS) WS hold time Slave mode 0.5 - Master receiver 0 - Slave receiver 2 - Master receiver 0 - Slave receiver 2.5 - Slave transmitter (after enable edge) - 15 Master transmitter (after enable edge) - 2.5 Slave transmitter (after enable edge) 6 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization, not tested in production. 2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency). Note: Refer to the I2S section of RM0383 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DocID028087 Rev 4 131/193 161 Electrical characteristics STM32F412xE/G Figure 43. I2S slave timing diagram (Philips protocol)(1) tc(CK) CK Input CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit SDreceive LSB LSB transmit th(SD_MR) tsu(SD_MR) receive(2) Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 132/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics QSPI interface characteristics Unless otherwise specified, the parameters given in the following tables for QSPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C=20pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics. Table 66. QSPI dynamic characteristics in SDR mode(1) Symbol fSCK 1/tc(SCK) tw(CKH) Parameter QSPI clock frequency Conditions Min Typ Max Write mode 1.71 VVDD3.6 V Cload = 15 pF - - 80 Read mode 2.7 V<VDD<3.6 V Cload = 15 pF - - 100 1.71 VVDD3.6 V - - 50 (T(CK) / 2)-1 - T(CK) / 2 T(CK) / 2) - (T(CK) / 2)+1 MHz QSPI clock high and low - ts(IN) Data input setup time - 0.5 - - th(IN) Data input hold time - 3.5 - - tv(OUT) Data output valid time - - 1 1.5 th(OUT) Data output hold time - 0.5 - - tw(CKL) Unit ns 1. Guaranteed by characterization results, not tested in production. Table 67. QSPI dynamic characteristics in DDR mode(1) Symbol fSCK 1/tc(SCK) Parameter QSPI clock frequency Conditions Min Typ Max Write mode 1.71 VVDD3.6 V Cload = 15 pF - - 80 Read mode 2.7 V<VDD<3.6 V Cload = 15 pF - - 80 1.71 VVDD3.6 V - - 50 DocID028087 Rev 4 Unit MHz 133/193 161 Electrical characteristics STM32F412xE/G Table 67. QSPI dynamic characteristics in DDR mode(1) (continued) Symbol Parameter Conditions QSPI clock high and low - ts(IN) Data input setup time th(IN) Data input hold time tv(OUT) Data output valid time th(OUT) Data output hold time tw(CKH) tw(CKL) Min Typ Max Unit (T(CK) / 2)-1 - T(CK) / 2 T(CK) / 2) - (T(CK) / 2)+1 - 0 - - - 4 - - 2.7 V<VDD<3.6 V - 8 10.5 1.71 V<VDD<3.6 V - 8 13 - 7.5 - - ns 1. Guaranteed by characterization results, not tested in production. USB OTG full speed (FS) characteristics This interface is present in USB OTG FS controller. Table 68. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 s 1. Guaranteed by design, not tested in production. Table 69. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage 3.0(2) - 3.6 VDI(3) Differential input sensitivity I(USB_FS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold 1.3 - 2.0 VOL Static output level low - - 0.3 2.8 - 3.6 17 21 24 0.65 1.1 2.0 Output levels RPD VOH Static output level high RL of 1.5 k to 3.6 V(4) RL of 15 k to PA11, PA12 (USB_FS_DM/DP) VSS(4) VIN = VDD PA9 (OTG_FS_VBUS) RPU PA11, PA12 (USB_FS_DM/DP) VIN = VSS 1.5 1.8 2.1 PA9 (OTG_FS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 134/193 Min.(1) Typ. Max.(1) Unit DocID028087 Rev 4 V V V k STM32F412xE/G Electrical characteristics 2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers. Note: When VBUS sensing feature is enabled, PA9 should be left at their default state (floating input), not as alternate function. A typical 200 A current consumption of the embedded sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 when the feature is enabled. Figure 45. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S tr tf ai14137 Table 70. USB OTG FS electrical characteristics(1) Driver characteristics Symbol Parameter time(2) tr Rise tf Fall time(2) trfm VCRS Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification Chapter 7 (version 2.0). CAN (controller area network) interface Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). DocID028087 Rev 4 135/193 161 Electrical characteristics 6.3.20 STM32F412xE/G 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 71 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 15. Table 71. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage fADC fTRIG(2) VAIN RAIN(2) ADC clock frequency External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Typ Max Unit (1) 1.7 - 3.6 V 1.7(1) - VDDA V VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 k - - - 6 k - - 4 7 pF - - 0.100 s 1/fADC VDDA -VREF+ < 1.2 V Min tlat(2) Injection trigger conversion latency fADC = 30 MHz - - - 3(5) tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 s 1/fADC tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) - - - 2(5) fADC = 30 MHz 0.100 - 16 s - 3 - 480 1/fADC - - 2 3 s fADC = 30 MHz 12-bit resolution 0.50 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.30 - 16.20 s 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 136/193 DocID028087 Rev 4 1/fADC STM32F412xE/G Electrical characteristics Table 71. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps Sampling rate fS(2) (fADC = 30 MHz, and tS = 3 ADC cycles) IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 A IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.18.2: Internal reset OFF). 2. Guaranteed by characterization, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 71. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 72. ADC accuracy at fADC = 18 MHz(1) Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Typ Max(2) 3 4 2 3 1 3 1 2 2 3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization, not tested in production. DocID028087 Rev 4 137/193 161 Electrical characteristics STM32F412xE/G Table 73. ADC accuracy at fADC = 30 MHz(1) Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 k, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA -VREF < 1.2 V Typ Max(2) 2 5 1.5 2.5 1.5 4 1 2 1.5 3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization, not tested in production. Table 74. ADC accuracy at fADC = 36 MHz(1) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(2) 4 7 2 3 3 6 2 3 3 6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Guaranteed by characterization, not tested in production. Table 75. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 kHz Temperature = 25 C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - -72 -67 dB 1. Guaranteed by characterization, not tested in production. Table 76. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC = 36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 kHz Temperature = 25 C 1. Guaranteed by characterization, not tested in production. 138/193 DocID028087 Rev 4 Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - - -72 -70 dB STM32F412xE/G Note: Electrical characteristics ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.16 does not affect the ADC accuracy. Figure 46. ADC accuracy characteristics ;,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AIC 1. See also Table 73. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. DocID028087 Rev 4 139/193 161 Electrical characteristics STM32F412xE/G Figure 47. Typical connection diagram using the ADC 9'' 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$,1 9$,1 5$'& $,1[ &SDUDVLWLF 97 9 ELW FRQYHUWHU ,/$ &$'& 069 1. Refer to Table 71 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 140/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 48 or Figure 49, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA) 670) 95() )Q) 9''$ )Q) 966$95() DLE 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. DocID028087 Rev 4 141/193 161 Electrical characteristics STM32F412xE/G Figure 49. Power supply and reference decoupling (VREF+ connected to VDDA) 670) 95()9''$ )Q) 95()966$ DLF 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 6.3.21 Temperature sensor characteristics Table 77. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 - mV/C Voltage at 25 C - 0.76 - V tSTART(2) Startup time - 6 10 s TS_temp(2) ADC sampling time when reading the temperature (1 C accuracy) 10 - - s TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. Table 78. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F 142/193 DocID028087 Rev 4 STM32F412xE/G 6.3.22 Electrical characteristics VBAT monitoring characteristics Table 79. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit K R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s (1) Er TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.23 Embedded reference voltage The parameters given in Table 80 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 15. Table 80. Embedded internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V - 10 - - s VDD = 3V 10mV - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range TCoeff(2) Temperature coefficient - - 30 50 ppm/C tSTART(2) Startup time - - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production Table 81. Internal reference voltage calibration values Symbol Parameter Memory address VREFIN_CAL Raw data acquired at temperature of 30 C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B DocID028087 Rev 4 143/193 161 Electrical characteristics 6.3.24 STM32F412xE/G DFSDM characteristics Unless otherwise specified, the parameters given in Table 82 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 15: General operating conditions. * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM). Table 82. DFSDM characteristics(1) Symbol Parameter Conditions Min Typ Max fDFSDMCLK DFSDM clock - - - fSYSCLK - - 20 (fDFSDMCLK/4) MHz fCKIN (1/TCKIN) Input clock frequency SPI mode (SITP[1:0] = 01) Unit Output clock frequency - - - 20 MHz Output clock DuCyCKOUT frequency duty cycle - 30 50 75 % fCKOUT Input clock high and low time SPI mode (SITP[1:0] = 01), External clock mode (SPICKSEL[1:0] = 0) TCKIN/2-0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=01), External clock mode (SPICKSEL[1:0] = 0) 1 - - th Data input hold time SPI mode (SITP[1:0]=01), External clock mode (SPICKSEL[1:0] = 0) Manchester data period (recovered clock period) Manchester mode (SITP[1:0] = 10 or 11), Internal clock mode (SPICKSEL[1:0] 0) twh(CKIN) twl(CKIN) TManchester ns 1 - - (CKOUT DIV+1) TDFSDMCLK - (2 CKOUTDIV) TDFSDMCLK 1. Data based on characterization results, not tested in production. 144/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics ')6'0B &.,1\ ')6'0B'$7,1\ 63,WLPLQJ63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7,1\ WVX ')6'0B'$7,1\ 0DQFKHVWHUWLPLQJ 63,WLPLQJ63,&.6(/ 63,&.6(/ WK 6,73 WVX WK 6,73 6,73 6,73 5HFRYHUHGFORFN 5HFRYHUHGGDWD 06Y9 6.3.25 FSMC characteristics Unless otherwise specified, the parameters given in Table 83 to Table 90 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitance load C = 30 pF * Measurement points are done at CMOS levels: 0.5.VDD DocID028087 Rev 4 145/193 161 Electrical characteristics STM32F412xE/G Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 50 through Figure 53 represent asynchronous waveforms and Table 83 through Table 90 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms WZ 1( )60&B1( WY 12(B1( WZ 12( WK 1(B12( )60&B12( )60&B1:( WK $B12( WY $B1( )60&B$>@ $GGUHVV WY %/B1( WK %/B12( )60&B1%/>@ WK 'DWDB1( WVX 'DWDB12( WK 'DWDB12( WVX 'DWDB1( 'DWD )60&B'>@ WY 1$'9B1( WZ 1$'9 )60&B1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06Y9 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. 146/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 83. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK - 1 2 THCLK + 0.5 0 1 2THCLK - 1.5 2THCLK FSMC_NOE high to FSMC_NE high hold time 0 - FSMC_NEx low to FSMC_A valid - 1.5 th(A_NOE) Address hold time after FSMC_NOE high 0 - tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - tsu(Data_NE) Data to FSMC_NEx high setup time THCLK - 1 - tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK - 1 - th(Data_NOE) Data hold time after FSMC_NOE high 0 - th(Data_NE) Data hold time after FSMC_NEx high 0 - tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 0 FSMC_NADV low time - THCLK + 0.5 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 84. Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings(1)(2) Symbol tw(NE) tw(NOE) tw(NWAIT) Parameter Min Max 7THCLK - 1 7THCLK + 0.5 FSMC_NWE low time 5THCLK - 1.5 5THCLK FSMC_NWAIT low time THCLK - 0.5 - FSMC_NE low time tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 5THCLK -1 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid 4THCLK + 1 - Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. DocID028087 Rev 4 147/193 161 Electrical characteristics STM32F412xE/G Figure 51. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( WK 1(B1:( WZ 1:( )60&B1:( WK $B1:( WY $B1( )60&B$>@ $GGUHVV WY %/B1( )60&B1%/>@ WK %/B1:( 1%/ WY 'DWDB1( WK 'DWDB1:( 'DWD )60&B'>@ WY 1$'9B1( )60&B1$'9 WZ 1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06Y9 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 85. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Min Max FSMC_NE low time 3 THCLK - 1 3 THCLK +0.5 FSMC_NEx low to FSMC_NWE low THCLK + 0.5 THCLK + 0.5 FSMC_NWE low time THCLK - 1.5 THCLK+ 1 THCLK - 1 - - 0.5 THCLK - 0.5 - - 1 THCLK - 1 - FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FSMC_NWE high THCLK + 0.5 - tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 1 FSMC_NADV low time - THCLK+ 0.5 tw(NADV) 148/193 Parameter DocID028087 Rev 4 Unit ns STM32F412xE/G Electrical characteristics 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max 8THCLK - 1 8THCLK + 0.5 6THCLK + 0.5 6THCLK + 1 FSMC_NE low time tw(NE) tw(NWE) FSMC_NWE low time tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6THCLK + 0.5 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid - 4THCLK + 1 Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 52. Asynchronous multiplexed PSRAM/NOR read waveforms WZ 1( )60&B1( WK 1(B12( WY 12(B1( )60&B12( WZ 12( )60&B1:( WK $B12( WY $B1( )60&B$>@ $GGUHVV WK %/B12( WY %/B1( )60&B1%/>@ 1%/ WK 'DWDB1( WVX 'DWDB1( WVX 'DWDB12( WY $B1( )60&B$'>@ WY 1$'9B1( WK 'DWDB12( 'DWD $GGUHVV WK $'B1$'9 WZ 1$'9 )60&B1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06Y9 DocID028087 Rev 4 149/193 161 Electrical characteristics STM32F412xE/G Table 87. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max 3THCLK - 1 3THCLK + 0.5 2THCLK 2THCLK + 1 THCLK - 1.5 THCLK FSMC_NOE high to FSMC_NE high hold time 0 - FSMC_NEx low to FSMC_A valid - 0.5 FSMC_NEx low to FSMC_NADV low 0 1 THCLK - 0.5 THCLK + 0.5 FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NADV low time th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) 0 - th(A_NOE) Address hold time after FSMC_NOE high THCLK - 0.5 - th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 tsu(Data_NE) Data to FSMC_NEx high setup time THCLK - 2 - tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK - 2 - th(Data_NE) Data hold time after FSMC_NEx high 0 - th(Data_NOE) Data hold time after FSMC_NOE high 0 - Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 88. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) Symbol Min Max 8THCLK - 1 8THCLK + 0.5 5THCLK 5THCLK + 0.5 tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 5THCLK - 1 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid 4THCLK + 1 - tw(NE) tw(NOE) Parameter FSMC_NE low time FSMC_NWE low time 1. CL = 30 pF. 2. Based on characterization, not tested in production. 150/193 DocID028087 Rev 4 Unit ns STM32F412xE/G Electrical characteristics Figure 53. Asynchronous multiplexed PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WK 1(B1:( WZ 1:( WY 1:(B1( )60&B1:( WK $B1:( WY $B1( )60&B$>@ $GGUHVV WY %/B1( WK %/B1:( )60&B1%/>@ 1%/ WY $B1( )60&B$'>@ WY 'DWDB1$'9 $GGUHVV W Y 1$'9B1( WK 'DWDB1:( 'DWD WK $'B1$'9 WZ 1$'9 )60&B1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( DocID028087 Rev 4 06Y9 151/193 161 Electrical characteristics STM32F412xE/G Table 89. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Min Max 4THCLK - 1 4THCLK+0.5 THCLK THCLK + 1 2THCLK - 1 2THCLK + 0.5 THCLK - 1.5 - FSMC_NEx low to FSMC_A valid - 2 FSMC_NEx low to FSMC_NADV low 0 1 THCLK - 0.5 THCLK+ 0.5 THCLK - THCLK- 1.5 - THCLK - FSMC_NEx low to FSMC_BL valid - 1.5 tv(Data_NADV) FSMC_NADV high to Data valid - THCLK + 2 th(Data_NWE) Data hold time after FSMC_NWE high THCLK + 0.5 - tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NADV low time FSMC_AD(adress) valid hold time after FSMC_NADV high) th(A_NWE) Address hold time after FSMC_NWE high th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(BL_NE) Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 90. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Min Max FSMC_NE low time 9THCLK - 1 9THCLK + 0.5 FSMC_NWE low time 7THCLK - 1 7THCLK + 0.5 tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6THCLK -1 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid 4THCLK + 1 - tw(NE) tw(NWE) Parameter Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Synchronous waveforms and timings Figure 54 through Figure 57 represent synchronous waveforms and Table 91 through Table 94 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: 152/193 * BurstAccessMode = FSMC_BurstAccessMode_Enable; * MemoryType = FSMC_MemoryType_CRAM; * WriteBurst = FSMC_WriteBurst_Enable; * CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390) * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM DocID028087 Rev 4 STM32F412xE/G Electrical characteristics In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 90 MHz). Figure 54. Synchronous multiplexed NOR/PSRAM read timings WZ &/. %867851 WZ &/. )60&B&/. 'DWDODWHQF\ WG &/./1([/ )60&B1([ WG &/./1$'9/ WG &/.+1([+ WG &/./1$'9+ )60&B1$'9 WG &/.+$,9 WG &/./$9 )60&B$>@ WG &/./12(/ WG &/.+12(+ )60&B12( WG &/./$',9 WG &/./$'9 )60&B$'>@ WK &/.+$'9 WVX $'9&/.+ WVX $'9&/.+ $'>@ ' WVX 1:$,79&/.+ WK &/.+$'9 ' WK &/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX 1:$,79&/.+ WK &/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX 1:$,79&/.+ WK &/.+1:$,79 06Y9 DocID028087 Rev 4 153/193 161 Electrical characteristics STM32F412xE/G Table 91. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Max 2THCLK - 0.5 - - 1 THCLK + 0.5 - td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKH_NExH) FSMC_CLK high to FSMC_NEx high (x= 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) - 2 td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16...25) THCLK - - 1.5 THCLK - td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 2.5 td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 1 - th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 2 - tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2 - th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 2 - 1. CL = 30 pF. 2. Based on characterization, not tested in production. 154/193 Min DocID028087 Rev 4 Unit ns STM32F412xE/G Electrical characteristics Figure 55. Synchronous multiplexed PSRAM write timings WZ &/. %867851 WZ &/. )60&B&/. 'DWDODWHQF\ WG &/./1([/ WG &/.+1([+ )60&B1([ WG &/./1$'9/ WG &/./1$'9+ )60&B1$'9 WG &/.+$,9 WG &/./$9 )60&B$>@ WG &/.+1:(+ WG &/./1:(/ )60&B1:( WG &/./$',9 WG &/./$'9 )60&B$'>@ WG &/./'DWD WG &/./'DWD $'>@ ' ' )60&B1:$,7 :$,7&)* E:$,732/E WVX 1:$,79&/.+ WK &/.+1:$,79 WG &/.+1%/+ )60&B1%/ 06Y9 DocID028087 Rev 4 155/193 161 Electrical characteristics STM32F412xE/G Table 92. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max tw(CLK) FSMC_CLK period, VDD range= 2.7 to 3.6 V 2THCLK - 0.5 - td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x= 0...2) - 1 td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0...2) THCLK + 0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - - 2 THCLK - - 1.5 THCLK + 0.5 - td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low t(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 2.5 td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 4 td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low - 3 td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high THCLK - tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2 - th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 2 - 1. CL = 30 pF. 2. Based on characterization, not tested in production. 156/193 Min DocID028087 Rev 4 Unit ns STM32F412xE/G Electrical characteristics Figure 56. Synchronous non-multiplexed NOR/PSRAM read timings WZ &/. WZ &/. )60&B&/. WG &/./1([/ WG &/.+1([+ 'DWDODWHQF\ )60&B1([ WG &/./1$'9/ WG &/./1$'9+ )60&B1$'9 WG &/./$9 WG &/.+$,9 )60&B$>@ WG &/.+12(+ WG &/./12(/ )60&B12( WVX '9&/.+ WK &/.+'9 WVX '9&/.+ ' )60&B'>@ WVX 1:$,79&/.+ )60&B1:$,7 :$,7&)* E :$,732/E ' WK &/.+1:$,79 WVX 1:$,79&/.+ )60&B1:$,7 :$,7&)* E :$,732/E WVX 1:$,79&/.+ WK &/.+'9 WK &/.+1:$,79 WK &/.+1:$,79 06Y9 Table 93. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Min Max 2THCLK - 0.5 - - 1 THCLK +0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - - 2 THCLK - - 1.5 THCLK - tw(CLK) t(CLKL-NExL) td(CLKH-NExH) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x=0..2) FSMC_CLK high to FSMC_NEx high (x= 0...2) td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16...25) td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 1 - th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 2 - tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2 - th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 2 - DocID028087 Rev 4 Unit ns 157/193 161 Electrical characteristics STM32F412xE/G 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 57. Synchronous non-multiplexed PSRAM write timings WZ &/. WZ &/. )60&B&/. WG &/./1([/ WG &/.+1([+ 'DWDODWHQF\ )60&B1([ WG &/./1$'9/ WG &/./1$'9+ )60&B1$'9 WG &/./$9 WG &/.+$,9 )60&B$>@ WG &/./1:(/ WG &/.+1:(+ )60&B1:( WG &/./'DWD )60&B'>@ )60&B1:$,7 :$,7&)* E :$,732/E WG &/./'DWD ' WVX 1:$,79&/.+ ' WG &/.+1%/+ WK &/.+1:$,79 )60&B1%/ 06Y9 158/193 DocID028087 Rev 4 STM32F412xE/G Electrical characteristics Table 94. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Min Max 2THCLK - 0.5 - - 1 THCLK + 0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - - 2 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) td(CLKL-NExL) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0...2) td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16...25) td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16...25) td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 4 td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low - 3 THCLK - 2 - 2 - td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high tsu(NWAITCLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high Unit ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. 6.3.26 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 95 for the SDIO are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 15, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. DocID028087 Rev 4 159/193 161 Electrical characteristics STM32F412xE/G Figure 58. SDIO high-speed mode TF TR T# T7#+( T7#+, #+ T/6 T/( $ #-$ OUTPUT T)35 T)( $ #-$ INPUT AI Figure 59. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI Table 95. Dynamic characteristics: SD / MMC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =50MHz 4 - - tIH Input hold time HS fpp =50MHz 2.5 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =50MHz - 13 13.5 tOH Output hold time HS fpp =50MHz 11 - - 160/193 DocID028087 Rev 4 ns STM32F412xE/G Electrical characteristics Table 95. Dynamic characteristics: SD / MMC characteristics(1)(2) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =25MHz 2.5 - - tIHD Input hold time SD fpp =25MHz 2.5 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =25 MHz - 1.5 2 tOHD Output hold default time SD fpp =25 MHz 0.5 - - ns 1. Guaranteed by characterization results, not tested in production. 2. VDD = 2.7 to 3.6 V. Table 96. Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS fpp =50MHz 3.5 - - tIH Input hold time HS fpp =50MHz 4 - - ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS fpp =50MHz - 13.5 15 tOH Output hold time HS fpp =50MHz 12 - - ns 1. Guaranteed by characterization results, not tested in production. 2. CLOAD = 20 pF. 6.3.27 RTC characteristics Table 97. RTC characteristics Symbol Parameter - fPCLK1/RTCCLK frequency ratio Conditions Any read/write operation from/to an RTC register DocID028087 Rev 4 Min Max 4 - 161/193 161 Package information 7 STM32F412xE/G Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 WLCSP64 package information Figure 60. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package outline H EEE = ) * $ 'HWDLO$ H H + * H $ $ $ ) %XPSVLGH 6LGHYLHZ ' %XPS $ HHH = ( $ 2ULHQWDWLRQ UHIHUHQFH E FFF = ; < GGG = = 6HDWLQJSODQH DDD [ :DIHUEDFNVLGH 'HWDLO$ URWDWHG $)B0(B9 1. Drawing is not to scale. 162/193 DocID028087 Rev 4 STM32F412xE/G Package information Table 98. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.170 - - 0.0067 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.588 3.623 3.658 0.1413 0.1426 0.1440 E 3.616 3.651 3.686 0.1424 0.1437 0.1451 e - 0.400 - - 0.0157 - e1 - 2.800 - - 0.1102 - e2 - 2.800 - - 0.1102 - F - 0.4115 - - 0.0162 - G - 0.4255 - - 0.0168 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 A3 (2) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 61. WLCSP64 - 64-pin, 3.658 x 3.686 mm, 0.4 mm pitch wafer level chip scale recommended footprint 'SDG 'VP $)B)3B9 Table 99. WLCSP64 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm DocID028087 Rev 4 163/193 190 Package information STM32F412xE/G Table 99. WLCSP64 recommended PCB design rules (0.4 mm pitch) (continued) Dimension Recommended values Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for WLCSP64 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 62. WLCSP64 marking example (package top view) W WZZ )5*< 'DWHFRGH \HDUZHHN < :: = ZZZ 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 164/193 DocID028087 Rev 4 STM32F412xE/G 7.2 Package information UFQFPN48 package information Figure 63. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < ' / &[ SLQFRUQHU 5W\S 'HWDLO= ( = $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 DocID028087 Rev 4 165/193 190 Package information STM32F412xE/G Table 100. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 64. UFQFPN48 recommended footprint 1. Dimensions are in millimeters. 166/193 DocID028087 Rev 4 !"?&0?6 STM32F412xE/G Package information Device marking for UFQFPN48 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 65. UFQFPN48 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 670) &*8 'DWHFRGH < :: 3LQ LQGHQWLILHU 5HYLVLRQFRGH 5 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID028087 Rev 4 167/193 190 Package information 7.3 STM32F412xE/G LQFP64 package information Figure 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. 168/193 DocID028087 Rev 4 STM32F412xE/G Package information Table 101. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID028087 Rev 4 169/193 190 Package information STM32F412xE/G Figure 67. LQFP64 recommended footprint AIC 1. Dimensions are in millimeters. Device marking for LQFP64 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 68. LQFP64 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670) 5*7 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 170/193 DocID028087 Rev 4 STM32F412xE/G LQFP100 package information Figure 69. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! 3%!4).' 0,!.% # ! '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B 7.4 Package information E ,?-%?6 1. Drawing is not to scale. Dimensions are in millimeters. Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 DocID028087 Rev 4 171/193 190 Package information STM32F412xE/G Table 102. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 70. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint AIC 1. Dimensions are in millimeters. 172/193 DocID028087 Rev 4 STM32F412xE/G Package information Device marking for LQFP100 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 71. LQFP100 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ (6) 9*75 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID028087 Rev 4 173/193 190 Package information 7.5 STM32F412xE/G LQFP144 package information Figure 72. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. 174/193 DocID028087 Rev 4 STM32F412xE/G Package information Table 103. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID028087 Rev 4 175/193 190 Package information STM32F412xE/G Figure 73. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DLH 1. Dimensions are expressed in millimeters. 176/193 DocID028087 Rev 4 STM32F412xE/G Package information Device marking for LQFP144 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 74. LQFP144 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 (6)=*7 'DWHFRGH < :: 3LQ LGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID028087 Rev 4 177/193 190 Package information 7.6 STM32F412xE/G UFBGA100 package information Figure 75. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < 0 %277209,(: E EDOOV HHH 0 = < ; III 0 = 7239,(: $&B0(B9 1. Drawing is not to scale. Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol 178/193 Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DocID028087 Rev 4 STM32F412xE/G Package information Table 104. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint 'SDG 'VP $&B)3B9 Table 105. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.280 mm Dsm 0.370 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.280 mm Stencil thickness Between 0.100 mm and 0.125 mm DocID028087 Rev 4 179/193 190 Package information STM32F412xE/G Device marking for UFBGA100 The following figure gives an example of topside marking and ball 1 position identifier location. Figure 77. UFBGA100 marking example (package top view) WZZ 670) 9*+ Z < :: Z ZZZ = 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. 180/193 DocID028087 Rev 4 STM32F412xE/G 7.7 Package information UFBGA144 package information Figure 78. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline & 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) $ ( $ ) ' ' H % 0 %277209,(: E EDOOV HHH 0 & $ % III 0 & 7239,(: $<B0(B9 1. Drawing is not to scale. Table 106. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 0.050 0.080 0.110 - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.360 0.400 0.440 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.2736 0.2756 0.2776 D1 8.750 8.800 8.850 0.2343 0.2362 0.2382 E 9.950 10.000 10.050 0.2736 0.2756 0.2776 E1 8.750 8.800 8.850 0.2343 0.2362 0.2382 e 0.750 0.800 0.850 - 0.0197 - DocID028087 Rev 4 181/193 190 Package information STM32F412xE/G Table 106. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.550 0.600 0.650 0.0177 0.0197 0.0217 ddd - - 0.080 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 79. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array recommended footprint 'SDG 'VP z&Ws Table 107. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) Dimension Note: Recommended values Pitch 0.80 mm Dpad 0.400 mm Dsm 0.550 mm typ. (depends on the soldermask registration tolerance) Non solder mask defined (NSMD) pads are recommended. 4 to 6 mils solder paste screen printing process. Stencil opening is 0.400 mm. Stencil thickness is between 0.100 mm and 0.125 mm. Pad trace width is 0.120 mm. 182/193 DocID028087 Rev 4 STM32F412xE/G Package information Device marking for UFBGA144 The following figure gives an example of topside marking and ball A1 position identifier location. Figure 80. UFBGA144 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670) =*- $GGLWLRQDO LQIRUPDWLRQ = 'DWHFRGH < :: %DOO$ LQGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. DocID028087 Rev 4 183/193 190 Package information 7.8 STM32F412xE/G Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 15: General operating conditions on page 76. The maximum chip-junction temperature, TJ max., in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 108. Package thermal characteristics Symbol JA 7.8.1 Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm 35 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm 43 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm 47 Thermal resistance junction-ambient UFBGA144 - 10 x 10 mm / 0.8 mm pitch 48 Thermal resistance junction-ambient UFBGA100 - 7 x 7 mm 57 Thermal resistance junction-ambient WLCSP64 - 3.623 x 3.651 mm 51 Thermal resistance junction-ambient UFQFPN48 - 7 x 7 mm 32 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 184/193 DocID028087 Rev 4 STM32F412xE/G 8 Part numbering Part numbering Table 109. Ordering information scheme Example: STM32 F 412 C E T 6 TR Device family STM32 = ARM(R)-based 32-bit microcontroller Product type F = General-purpose Device subfamily 412 = 412 line Pin count C = 48 pins R = 64 pins V = 100 pins Z = 144 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package H = UFBGA 7 x 7 mm J = UFBGA 10 x 10 mm T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = Industrial temperature range, -40 to 85 C Packing TR = tape and reel No character = tray or tube DocID028087 Rev 4 185/193 190 Recommendations when using the internal reset OFF Appendix A STM32F412xE/G Recommendations when using the internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: 186/193 * The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled. * The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. DocID028087 Rev 4 STM32F412xE/G Appendix B Application block diagrams USB OTG full speed (FS) interface solutions Figure 81. USB controller configured as peripheral-only and used in Full speed mode 9''86% 9'' 9WR9''86% 9ROWDJHUHJXODWRU 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86%6WG%FRQQHFWRU 670)[[ SLQVSDFNDJHV 06Y9 1. External voltage regulator only needed when building a VBUS powered device. Figure 82. USB peripheral-only Full speed mode with direct connection for VBUS sense 9''!9 9''86% 670)[[ SLQVSDFNDJHV 3$ 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86%6WG%FRQQHFWRU B.1 Application block diagrams 06Y9 1. External voltage regulator only needed when building a VBUS powered device. DocID028087 Rev 4 187/193 190 Application block diagrams STM32F412xE/G Figure 83. USB peripheral-only Full speed mode, VBUS detection using GPIO 99''9 9''86% *3,2 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86%6WG%FRQQHFWRU 670)[[ SLQVSDFNDJHV 06Y9 1. External voltage regulator only needed when building a VBUS powered device. Figure 84. USB controller configured as host-only and used in full speed mode 9'' *3,2,54 (1 2YHUFXUUHQW &XUUHQWOLPLWHU SRZHUVZLWFK 9 9%86 26&B,1 3$ 3$ 26&B287 '0 '3 966 86%6WG$FRQQHFWRU 670)[[ *3,2 06Y9 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 188/193 DocID028087 Rev 4 STM32F412xE/G Application block diagrams Figure 85. USB controller configured in dual mode and used in full speed mode 9'' 9WR9'' 9ROWDJH UHJXODWRU 9'' (1 2YHUFXUUHQW *3,2,54 &XUUHQWOLPLWHU SRZHUVZLWFK 9 9%86 3$ '0 3$ 26&B,1 26&B287 '3 3$ ,' 3$ 966 86%PLFUR$%FRQQHFWRU 670)[[ *3,2 06Y9 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. B.2 Sensor Hub application example Figure 86. Sensor Hub application example $FFHOHURPHWHU *\URVFRSH 0DJQHWRPHWHU 670) SLQSDFNDJH 3% 3% 3$ 6&/ ,& 3UHVVXUH 3% 3% 3% 6'$ [ *3,2 3% *3,2 . 6/. $PELHQWOLJKW ,6 3% '$7$ 3UR[LPLW\ %22 7 3$ 7; 8$57 0LFUR 3$ 5; 6:',2 -7$* 6:&/. 6:2 3$ 3$ 166 3$ 3% 3$ 6&. 15 67 26& N 63, 3$ 0,62 3$ 3& 3$ 3$ +267 026, $'& 7HPSHUDWXUH +X PLGLW\ 3& 8S WR $'& LQSX WV 06Y9 DocID028087 Rev 4 189/193 190 Application block diagrams B.3 STM32F412xE/G Display application example Figure 87. Display application example 670) SLQSDFNDJH 7,0BFK N %227 1:( $ 1( 12( )60& -7$* 6:',2 6:&/. 6:2 3$ 3$ 3% ' ' ' ' ' ' ' ' *3,2 %DFNOLJKW FRQWURO 7( 7HDULQJ 3& 3& 3& 3& :5 '& &6 5' 3& 3% 3& 3& 3& 3$ 3$ 3$ 3$ 'LVSOD\0RGXOH >''@ *3,2 ,QWHUUXSW 3% 3% 6&/ ,& 6'$ 7RXFK6FUHHQ &RQWUROOHU 06Y9 Note: 190/193 16 bit displays interfaces can be addressed with 100 and 144 pins packages. DocID028087 Rev 4 STM32F412xE/G Revision history Revision history Table 110. Document revision history Date Revision 10-Nov-2015 1 Initial release. 2 Added - Table 3: Embedded bootloader interfaces - Figure 3: Compatible board design for LQFP144 package - Figure 62: WLCSP64 marking example (package top view) - Figure 77: UFBGA100 marking example (package top view) Updated - Section 3.17: Power supply schemes - Section 3.23: Timers and watchdogs - Section 3.32: Universal serial bus on-the-go full-speed (USB_OTG_FS) - Figure 1: Compatible board design for LQFP100 package - Figure 2: Compatible board design for LQFP64 package - Figure 14: STM32F412xE/G LQFP100 pinout - Figure 16: STM32F412xE/G UFBGA100 pinout - Figure 17: STM32F412xE/G UFBGA144 pinout - Figure 20: Input voltage measurement - Figure 80: UFBGA144 marking example (package top view) - Table 2: STM32F412xE/G features and peripheral counts - Table 9: STM32F412xE/G pin definition - Table 12: Voltage characteristics - Table 13: Current characteristics - Table 15: General operating conditions - Table 36: Peripheral current consumption - Table 51: EMS characteristics for LQFP144 package - Table 63: FMPI2C characteristics 01-Feb-2016 Changes DocID028087 Rev 4 191/193 192 Revision history STM32F412xE/G Table 110. Document revision history Date 25-Mar-2016 27-May-2016 192/193 Revision Changes 3 Added: - Figure 82: USB peripheral-only Full speed mode with direct connection for VBUS sense - Figure 83: USB peripheral-only Full speed mode, VBUS detection using GPIO Updated: - Figure 15: STM32F412xE/G LQFP144 pinout - Section 6.3.6: Supply current characteristics - Table 9: STM32F412xE/G pin definition - Table 10: STM32F412xE/G alternate functions - Table 11: STM32F412xE/G register boundary addresses - Table 15: General operating conditions - Table 36: Peripheral current consumption - Table 96: Dynamic characteristics: eMMC characteristics VDD = 1.7 V to 1.9 V 4 Updated: - Section 3.23.2: General-purpose timers (TIMx) - Table 21: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 1.7 V - Table 22: Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.6 V - Table 23: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V - Table 24: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V - Table 25: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.6 V - Table 26: Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.7 V - Table 27: Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory VDD = 3.6 V - Table 28: Typical and maximum current consumption in Sleep mode - VDD = 3.6 V - Table 29: Typical and maximum current consumption in Sleep mode - VDD = 1.7 V - Table 37: Low-power mode wakeup timings(1) - Figure 38: I2C bus AC waveforms and measurement circuit - Figure 39: FMPI2C timing diagram and measurement circuit DocID028087 Rev 4 STM32F412xE/G IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved DocID028087 Rev 4 193/193 193