Features _äìÉ`çêÉ
∆
RJjìäíáãÉÇá~=mäìÖJåJdç
∆
^ìíçãçíáîÉ
■
Fully ualified Bluetooth v2.1 + EDR specification
system
■
64MIPS Kalimba DSP co-processor
■
16-bit internal stereo codec, 95dB SNR for DAC
■
Low-power 1.5V operation, 1.8V to 3.6V I/O
■
Integrated 1.5V and 1.8V linear regulators
■
Integrated switched-mode regulator
■
Integrated battery charger
■
USB, I
2
C, and UART with dual-port bypass mode
to 4Mbps
■
16Mb of internal Flash memory
■
Multi-configurable I
2
S, PCM or SPDIF interface
■
Enhanced audibility and noise cancellation
■
10 x 10 x 1.6mm, 105-ball, 0.8mm pitch LFBGA
■
Support for IEEE 802.11 coexistence
■
RoHS compliant
■
RF Plug-n-Go package
Single-chip Bluetooth
®
v2.1 + EDR
System
Production Information
BC57G687C-ANN-E4
Issue 3
General Description
_äìÉ`çêÉ
∆
RJjìäíáãÉÇá~=mäìÖJåJdç
∆
=^ìíçãçíáîÉ is a
single-chip radio and baseband IC for Bluetooth
v2.1 + EDR specification systems.
BlueCore5-Multimedia Plug-n-Go Automotive
contains 16Mb, 70ns internal Flash memory, which
makes it one of the most powerful and flexible
Bluetooth audio solutions on the market today. When
used with CSR Bluetooth stack, it provides a fully
compliant system to Bluetooth v2.1 + EDR
specification for data and voice.
2.4
GHz
Radio
I
/
O
XTAL
RF IN
RF OUT
FLASH
RAM
Baseband
DSP
MCU
Kalimba DSP
SPI
UART/USB
PIO
Audio In/Out
PCM / I
2
S / SPDIF
Figure: System Architecture
Applications
■
Bluetooth-enabled automotive wireless gateways
■
High-quality stereo wireless headsets
■
High-quality mono headsets
■
Hands-free car kits
■
Wireless speakers
■
VoIP handsets
■
Analogue and USB multimedia dongles
BlueCore5-Multimedia Plug-n-Go Automotive
contains the Kalimba DSP co-processor with double
the MIPS and double the memory of BlueCore3-
Multimedia, supporting enhanced audio applications.
BlueCore5-Multimedia Plug-n-Go Automotive is
designed to reduce the number of external
components required which ensures production costs
are minimised.
The device incorporates auto-calibration and BIST
routines to simplify development, type approval and
production test.
To improve the performance of both Bluetooth and
IEEE 802.11b/g co-located systems a wide range of
coexistence features are available including a variety
of hardware signalling: basic activity signalling, Intel
WCS activity and channel signalling.
CS-121449-DSP3
Production Information
This material is subject to CSR's Non-Disclosure Agreement
© Cambridge Silicon Radio Limited 2008
Page 1 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
Document History
Revision Date Change Reason
Issue 1 06 JUN 08 Original Publication of document.
Issue 2 05 NOV 08 Update to USB section, Pin-out table, Schematic and Device Diagram.
Issue 3 17 NOV 08 Update to recommended temperature specification and some editorial changes.
If you have any comments about this document, email Comments@csr.com giving the
number, title and section with your feedback.
Document History
CS-121449-DSP3
Production Information
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© Cambridge Silicon Radio Limited 2008
Page 2 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
Status Information
The status of this Data Sheet is Production Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-Production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
ESD Precautions
BlueCore5-Multimedia Plug-n-Go Automotive is classified as a JESD22-A114 class 2 product. Apply ESD static
handling precautions during manufacturing.
Life Support Policy and Use in Safety-Critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
RoHS Compliance
BlueCore5-Multimedia Plug-n-Go Automotive devices meet the requirements of Directive 2002/95/EC of the
European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Patents and Licenses
Unless otherwise stated, words and logos marked with
™
or
®
are trademarks registered or owned by CSR plc or its
affiliates. Bluetooth
®
and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR.
Other products, services and names used in this document may have been trademarked by their respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned
by CSR plc.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
CSR’s products are not authorised for use in life-support or safety-critical applications.
Refer to www.csrsupport.com for compliance and conformance to standards information.
Status Information
CS-121449-DSP3
Production Information
This material is subject to CSR's Non-Disclosure Agreement
© Cambridge Silicon Radio Limited 2008
Page 3 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
Contents
1 Device Details ................................................................................................................................................. 9
2 Device Diagram ............................................................................................................................................ 10
3 Package Information ..................................................................................................................................... 11
3.1 Pinout Diagram .................................................................................................................................... 11
3.2 BlueCore5-Multimedia Plug-n-Go Automotive Device Terminal Functions ......................................... 12
3.3 Package Dimensions ........................................................................................................................... 18
3.4 PCB Design and Assembly Considerations ......................................................................................... 19
3.4.1 Thermal Resistance ............................................................................................................... 19
3.5 Typical Solder Reflow Profile ............................................................................................................... 19
4 Bluetooth Modem .......................................................................................................................................... 20
4.1 RF Plug-n-Go ....................................................................................................................................... 20
4.2 RF Receiver ......................................................................................................................................... 20
4.2.1 Low Noise Amplifier ............................................................................................................... 20
4.2.2 RSSI Analogue to Digital Converter ....................................................................................... 20
4.3 RF Transmitter ..................................................................................................................................... 20
4.3.1 IQ Modulator .......................................................................................................................... 20
4.3.2 Power Amplifier ...................................................................................................................... 20
4.4 Bluetooth Radio Synthesiser ............................................................................................................... 21
4.5 Baseband ............................................................................................................................................. 21
4.5.1 Burst Mode Controller ............................................................................................................ 21
4.5.2 Physical Layer Hardware Engine ........................................................................................... 21
4.6 Basic Rate Modem .............................................................................................................................. 21
4.7 Enhanced Data Rate Modem .............................................................................................................. 21
4.7.1 Enhanced Data Rate π/4 DQPSK .......................................................................................... 22
4.7.2 Enhanced Data Rate 8DPSK ................................................................................................. 23
5 Clock Generation .......................................................................................................................................... 25
5.1 Clock Architecture ................................................................................................................................ 25
5.2 Input Frequencies and PS Key Settings .............................................................................................. 25
5.3 External Reference Clock .................................................................................................................... 26
5.3.1 Input (XTAL_IN) ..................................................................................................................... 26
5.3.2 XTAL_IN Impedance in External Mode .................................................................................. 26
5.3.3 Clock Start-up Delay .............................................................................................................. 26
5.3.4 Clock Timing Accuracy ........................................................................................................... 26
5.4 Crystal Oscillator (XTAL_IN, XTAL_OUT) ........................................................................................... 27
5.4.1 Load Capacitance .................................................................................................................. 28
5.4.2 Frequency Trim ...................................................................................................................... 28
5.4.3 Transconductance Driver Model ............................................................................................ 29
5.4.4 Negative Resistance Model ................................................................................................... 29
5.4.5 Crystal PS Key Settings ......................................................................................................... 30
6 Bluetooth Stack Microcontroller .................................................................................................................... 31
6.1 TCXO Enable OR Function ................................................................................................................. 31
6.2 Programmable I/O (PIO) Parallel Ports ............................................................................................... 31
6.3 WLAN Coexistence Interface ............................................................................................................... 32
7 Kalimba DSP ................................................................................................................................................ 33
8 Memory Interface and Management ............................................................................................................. 34
8.1 Memory Management Unit .................................................................................................................. 34
8.2 System RAM ........................................................................................................................................ 34
8.3 Kalimba DSP RAM .............................................................................................................................. 34
8.4 Internal Flash Memory (16Mb) ............................................................................................................. 34
8.4.1 Flash Specification ................................................................................................................. 34
Contents
CS-121449-DSP3
Production Information
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© Cambridge Silicon Radio Limited 2008
Page 4 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
9 Serial Interfaces ............................................................................................................................................ 35
9.1 UART Interface .................................................................................................................................... 35
9.1.1 UART Configuration While Reset is Active ............................................................................ 37
9.1.2 UART Bypass Mode ............................................................................................................... 37
9.1.3 Current Consumption in UART Bypass Mode ........................................................................ 37
9.2 USB Interface ...................................................................................................................................... 37
9.3 Serial Peripheral Interface ................................................................................................................... 38
9.3.1 Instruction Cycle ..................................................................................................................... 38
9.3.2 Writing to the Device .............................................................................................................. 38
9.3.3 Reading from the Device ........................................................................................................ 39
9.3.4 Multi-slave Operation ............................................................................................................. 39
9.4 I
2
C Interface ......................................................................................................................................... 39
9.4.1 Software I
2
C Interface ............................................................................................................ 39
9.4.2 Bit-serialiser Interface ............................................................................................................ 40
10 Audio Interface .............................................................................................................................................. 41
10.1 Audio Input and Output ........................................................................................................................ 41
10.2 Stereo Audio Codec Interface .............................................................................................................. 42
10.2.1 Mono Audio Codec Block Diagram ........................................................................................ 42
10.2.2 Stereo Codec Set-up .............................................................................................................. 42
10.2.3 ADC ........................................................................................................................................ 43
10.2.4 ADC Sample Rate Selection .................................................................................................. 43
10.2.5 ADC Digital Gain .................................................................................................................... 43
10.2.6 ADC Analogue Gain ............................................................................................................... 44
10.2.7 DAC ........................................................................................................................................ 44
10.2.8 DAC Sample Rate Selection .................................................................................................. 44
10.2.9 DAC Digital Gain .................................................................................................................... 44
10.2.10 DAC Analogue Gain ............................................................................................................... 46
10.2.11 Microphone Input ................................................................................................................... 47
10.2.12 Line Input ............................................................................................................................... 49
10.2.13 Output Stage .......................................................................................................................... 50
10.2.14 Mono Operation ..................................................................................................................... 50
10.2.15 Side Tone ............................................................................................................................... 51
10.2.16 Integrated Digital Filter ........................................................................................................... 51
10.3 PCM Interface ...................................................................................................................................... 52
10.4 Digital Audio Interface (I²S) .................................................................................................................. 52
11 Power Control and Regulation ...................................................................................................................... 57
11.1 Power Control and Regulation ............................................................................................................. 57
11.2 Power Sequencing ............................................................................................................................... 57
11.3 External Voltage Source ...................................................................................................................... 58
11.4 Switch-mode Regulator ....................................................................................................................... 58
11.5 High-voltage Linear Regulator ............................................................................................................. 58
11.6 Low-voltage Linear Regulator .............................................................................................................. 58
11.7 Low-voltage Audio Linear Regulator .................................................................................................... 59
11.8 Voltage Regulator Enable Pins ............................................................................................................ 59
11.9 Battery Charger ................................................................................................................................... 59
11.10LED Drivers ......................................................................................................................................... 61
11.11Reset (RST#) ....................................................................................................................................... 62
11.11.1 Digital Pin States on Reset .................................................................................................... 62
11.11.2 Status after Reset .................................................................................................................. 63
12 Product Reliability Tests for BlueCore5-Multimedia Plug-n-Go Automotive ................................................. 64
12.1 AEC-Q100 ........................................................................................................................................... 64
12.2 Automotive Die Test for BC57G687C .................................................................................................. 64
12.3 Automotive Package Test for BC57G687C ......................................................................................... 64
Contents
CS-121449-DSP3
Production Information
This material is subject to CSR's Non-Disclosure Agreement
© Cambridge Silicon Radio Limited 2008
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_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
13 Example Application Schematic ................................................................................................................... 65
14 Electrical Characteristics .............................................................................................................................. 66
14.1 Absolute Maximum Ratings ................................................................................................................. 66
14.2 Recommended Operating Conditions .................................................................................................. 66
14.3 Input/Output Terminal Characteristics ................................................................................................. 67
14.3.1 High-voltage Linear Regulator ............................................................................................... 67
14.3.2 Low-voltage Linear Regulator ................................................................................................ 68
14.3.3 Low-voltage Linear Audio Regulator ...................................................................................... 69
14.3.4 Switch-mode Regulator .......................................................................................................... 70
14.3.5 Reset ...................................................................................................................................... 71
14.3.6 Regulator Enable ................................................................................................................... 71
14.3.7 Battery Charger ...................................................................................................................... 72
14.3.8 Digital Terminals .................................................................................................................... 74
14.3.9 LED Driver Pads .................................................................................................................... 75
14.3.10 USB ........................................................................................................................................ 75
14.3.11 Auxiliary ADC ......................................................................................................................... 76
14.3.12 Clocks .................................................................................................................................... 76
14.3.13 Stereo Codec: Analogue to Digital Converter ........................................................................ 77
14.3.14 Stereo Codec: Digital to Analogue Converter ........................................................................ 79
15 Power Consumption ..................................................................................................................................... 80
15.1 Kalimba DSP and CODEC Typical Average Current Consumption .................................................... 82
15.2 Typical Peak Current at 20°C .............................................................................................................. 82
15.3 Conditions ............................................................................................................................................ 82
16 RoHS Statement with a List of Banned Materials ......................................................................................... 83
16.1 RoHS Statement .................................................................................................................................. 83
16.1.1 List of Banned Materials ......................................................................................................... 83
17 CSR Bluetooth Software Stack ..................................................................................................................... 84
17.1 BlueCore HCI Stack ............................................................................................................................ 84
17.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality ......................................... 84
17.1.2 Key Features of the HCI Stack: Extra Functionality ............................................................... 86
17.2 Host-Side Software .............................................................................................................................. 86
17.3 CSR Development Systems ................................................................................................................ 86
17.4 eXtension ............................................................................................................................................. 86
18 Ordering Information ..................................................................................................................................... 87
18.1 Tape and Reel Information .................................................................................................................. 87
18.1.1 Tape Orientation .................................................................................................................... 87
18.1.2 Reel Information ..................................................................................................................... 88
18.2 Moisture Sensitivity Level .................................................................................................................... 88
19 Document References .................................................................................................................................. 89
Terms and Definitions ............................................................................................................................................ 90
List of Figures
Figure 2.1 BlueCore5-Multimedia Plug-n-Go Automotive Device diagram ...................................................... 10
Figure 3.1 BlueCore5-Multimedia Plug-n-Go Automotive Device Pinout ......................................................... 11
Figure 3.2 BlueCore5-Multimedia Plug-n-Go Automotive 105-ball LFBGA Package Dimensions ................... 18
Figure 4.1 Circuit for RF_CONNECT ............................................................................................................... 20
Figure 4.2 BDR and EDR Packet Structure ..................................................................................................... 22
Figure 4.3 π/4 DQPSK Constellation Pattern ................................................................................................... 22
Figure 4.4 8DPSK Constellation Pattern .......................................................................................................... 23
Figure 5.1 Clock Architecture ........................................................................................................................... 25
Figure 5.2 TCXO Clock Accuracy .................................................................................................................... 27
Figure 5.3 Crystal Driver Circuit ....................................................................................................................... 27
Contents
CS-121449-DSP3
Production Information
This material is subject to CSR's Non-Disclosure Agreement
© Cambridge Silicon Radio Limited 2008
Page 6 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
Figure 5.4 Crystal Equivalent Circuit ................................................................................................................ 27
Figure 6.1 Example TCXO Enable OR Function .............................................................................................. 31
Figure 7.1 Kalimba DSP Interface to Internal Functions .................................................................................. 33
Figure 9.1 Universal Asynchronous Receiver .................................................................................................. 35
Figure 9.2 Break Signal .................................................................................................................................... 36
Figure 9.3 UART Bypass Architecture ............................................................................................................. 37
Figure 9.4 SPI Write Operation ........................................................................................................................ 39
Figure 9.5 SPI Read Operation ........................................................................................................................ 39
Figure 9.6 Example EEPROM Connection ...................................................................................................... 40
Figure 10.1 Audio Interface ................................................................................................................................ 41
Figure 10.2 Mono Codec Audio Input and Output Stages .................................................................................. 42
Figure 10.3 ADC Analogue Amplifier Block Diagram ......................................................................................... 44
Figure 10.4 Microphone Biasing (Single Channel Shown) ................................................................................. 47
Figure 10.5 Differential Input (Single Channel Shown) ...................................................................................... 50
Figure 10.6 Single-Ended Input (Single Channel Shown) .................................................................................. 50
Figure 10.7 Speaker Output (Single Channel Shown) ....................................................................................... 50
Figure 10.8 Digital Audio Interface Modes ......................................................................................................... 54
Figure 10.9 Digital Audio Interface Slave Timing ............................................................................................... 55
Figure 10.10 Digital Audio Interface Master Timing ............................................................................................. 56
Figure 11.1 Voltage Regulator Configuration ..................................................................................................... 57
Figure 11.2 LED Equivalent Circuit .................................................................................................................... 61
Figure 13.1 BlueCore5-Multimedia Plug-n-Go Automotive Automotive Example Application Schematic .......... 65
Figure 17.1 BlueCore HCI Stack ........................................................................................................................ 84
Figure 18.1 Tape and Reel Orientation .............................................................................................................. 87
Figure 18.2 Reel Dimensions ............................................................................................................................. 88
List of Tables
Table 4.1 Data Rate Schemes ......................................................................................................................... 22
Table 4.2 2-bits Determine Phase Shift Between Consecutive Symbols ......................................................... 23
Table 4.3 3-bits Determine Phase Shift Between Consecutive Symbols ......................................................... 24
Table 5.1 PS Key Values for CDMA/3G Phone TCXO .................................................................................... 25
Table 5.2 External Clock Specifications ........................................................................................................... 26
Table 5.3 Crystal Specification ......................................................................................................................... 28
Table 8.1 Internal Flash Device Specifications ................................................................................................ 34
Table 9.1 Possible UART Settings ................................................................................................................... 35
Table 9.2 Standard Baud Rates ....................................................................................................................... 36
Table 9.3 Instruction Cycle for an SPI Transaction .......................................................................................... 38
Table 10.1 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 41
Table 10.2 ADC Digital Gain Rate Selection ...................................................................................................... 43
Table 10.3 DAC Digital Gain Rate Selection ...................................................................................................... 45
Table 10.4 DAC Analogue Gain Rate Selection ................................................................................................. 46
Table 10.5 Voltage Output Steps ....................................................................................................................... 48
Table 10.6 Current Output Steps ....................................................................................................................... 49
Table 10.7 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 53
Table 10.8 PSKEY_DIGITAL_AUDIO_CONFIG ................................................................................................. 53
Table 10.9 Digital Audio Interface Slave Timing ................................................................................................ 55
Table 10.10 Digital Audio Interface Master Timing .............................................................................................. 56
Table 11.1 BlueCore5-Multimedia Plug-n-Go Automotive Voltage Regulator Enable Pins ............................... 59
Table 11.2 Pin States on Reset .......................................................................................................................... 62
Contents
CS-121449-DSP3
Production Information
This material is subject to CSR's Non-Disclosure Agreement
© Cambridge Silicon Radio Limited 2008
Page 7 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
List of Equations
Equation 5.1 Load Capacitance ........................................................................................................................... 28
Equation 5.2 Trim Capacitance ............................................................................................................................ 28
Equation 5.3 Frequency Trim ............................................................................................................................... 28
Equation 5.4 Pullability ......................................................................................................................................... 29
Equation 5.5 Transconductance Required for Oscillation .................................................................................... 29
Equation 5.6 Equivalent Negative Resistance ..................................................................................................... 29
Equation 9.1 Baud Rate ....................................................................................................................................... 36
Equation 10.1IIR Filter Transfer Function, H(z) ..................................................................................................... 52
Equation 10.2 IIR Filter plus DC Blocking Transfer Function, H
DC
(z) .................................................................... 52
Equation 11.1LED Current .................................................................................................................................... 61
Equation 11.2LED PAD Voltage ............................................................................................................................ 61
Contents
CS-121449-DSP3
Production Information
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© Cambridge Silicon Radio Limited 2008
Page 8 of 92
_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
1 Device Details
Radio
■
Common Tx/Rx terminal simplifies external
matching; eliminates external antenna switch
■
BIST minimises production test time
■
Antenna matching and filtering within the IC
■
Bluetooth v2.1 + EDR specification compliant
Transmitter
■
5dBm RF transmit power with level control from on-
chip 6-bit DAC over a dynamic range >30dB
■
Class 2 and Class 3 support without the need for an
external power amplifier or TX/RX switch
Receiver
■
Receiver sensitivity of -90dBm
■
Integrated channel filters
■
Digital demodulator for improved sensitivity and co-
channel rejection
■
Real-time digitised RSSI available on HCI interface
■
Fast AGC for enhanced dynamic range
Synthesiser
■
Fully integrated synthesiser requires no external
VCO, varactor diode, resonator or loop filter
■
Compatible with crystals between 16MHz to 26MHz
or an external clock between 12MHz to 52MHz
■
Accepts 14.40, 15.36, 16.2, 16.8, 19.2, 19.44,
19.68, 19.8 and 38.4MHz TCXO frequencies for
GSM and CDMA devices with sinusoidal or logic
level signals
Baseband and Software
■
16Mb of internal Flash
■
48KB of internal RAM, allows full-speed data
transfer, mixed voice/data and full piconet support
■
Logic for forward error correction, header error
control, access code correlation, CRC,
demodulation, encryption bit stream generation,
whitening and transmit pulse shaping
■
Transcoders for A-law, μ-law and linear voice from
host and A-law, μ-law and CVSD voice over air
Physical Interfaces
■
Serial peripheral interface
(SPI) with clock speeds
up to 64MHz in Master mode
1
and 32MHz in Slave
mode
■
I
2
C master compatible interface
■
UART interface with programmable data rate up to
4Mbits/s with an optional bypass mode
■
Full-speed USB v1.1 interface
■
Bi-directional serial programmable audio interface
supporting PCM, I
2
S and SPDIF formats
■
Two LED drivers with faders
Kalimba DSP
■
Very low power Kalimba DSP co-processor,
64MIPS, 24-bit fixed point core
■
Sub-band coding
(SBC) decode takes
approximately 4mW power consumption while
streaming music
■
Single-cycle MAC; 24 x 24-bit multiply and 56-bit
accumulator
■
32-bit instruction word, dual 24-bit data memory
■
24-Kbyte (6-Kword) program RAM, 36-Kbyte + 48-
Kbyte (16-Kword + 12-Kword) data RAM
■
64-word x 32-bit program memory cache when
executing from Flash
Stereo Audio CODEC
■
16-bit internal stereo CODEC
■
Dual ADC and DAC for stereo audio
■
Integrated amplifiers for driving 16Ω speakers; no
need for external components
■
Support for single-ended speaker termination and
line output
■
Integrated low-noise microphone bias
■
ADC sample are 8, 11.025, 16, 22.05, 32 and
44.1kHz
■
DAC sample are 8, 11.025, 12, 16, 22.05, 24, 32,
44.1 and 48kHz
Auxiliary Features
■
User space on processor for customer applications
■
Crystal oscillator with built-in digital trimming
■
Power management includes digital shutdown and
wake-up commands with an integrated low-power
oscillator for ultra-low power Park/Sniff/Hold mode
■
Clock request output to control external clock
■
On-chip regulators: 1.5V output from 1.8V to 2.7V
input and 1.8V output from 2.7V to 4.5V input
■
On-chip high-efficiency switched-mode regulator;
1.8V output from 2.7V to 4.4V input
■
Power-on-reset cell detects low supply voltage
■
10-bit ADC available to applications
■
On-chip charger for lithium ion/polymer batteries
Bluetooth Stack
CSR's Bluetooth Protocol Stack runs on the on-chip
MCU in a variety of configurations:
■
Standard HCI (UART or USB)
■
Complete stack and application running on chip
■
Audio CODEC and echo-noise suppression or
customer-specific algorithms running on the DSP
Package Option
■
LFBGA 105-ball, 10 x 10 x 1.6mm, 0.8mm pitch
1
Requires firmware support
Device Details
CS-121449-DSP3
Production Information
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© Cambridge Silicon Radio Limited 2008
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_äìÉ`çêÉRJjìäíáãÉÇá~=mäìÖJåJdç=^ìíçãçíáîÉ Data Sheet
2 Device Diagram
Switch Mode
Regulator
Clock
Generation
Power Control and Regulation
SENSE
Audio Low
Voltage Regulator
OUT
IN EN
VREGIN_AUDIO
VDD_AUDIO
VREGENABLE_L
VREGIN_L
VREGIN_H
VREGOUT_H
EN
VREGENABLE_H
BAT_N
Battery Charger
OUT
IN
BAT_P
VDD_CHG
VSS_AUDIO
RF_NEG
RF_CONNECT
XTAL_OUT
XTAL_IN
LO_REF
VDD_RADIO
VDD_LO
LED[0]
VDD_PADS
VSS_DIG
VSS_ANA
SUBS
VDD_MEM
BlueCore5-Multimedia Plug-n-Go
RST#
TEST_EN
High Voltage
Linear Regulator
OUT
IN EN
SENSE
VDD_SMP_CORE
Low Voltage
Linear Regulator
OUT SENSE
SENSE
VDD_CORE
IN EN
VDD_ANA
LX
I
2
C Bus available on any PIO
pins, default configuration shown
VSS_LO
VSS_RADIO
Memory Management Unit
Microcontroller
MCU
Interrupt
Controller
Timers
System RAM
Kalimba DSP
Interrupt
Controller
Timers
Data Memory
DM2
Program
Memory PM
Data Memory
DM1
PCM /I
2
S
Interface SPDIF Stereo Audio
Interface
Audio Interfaces
SPKR_A_P
SPKR_A_N
SPKR_B_N
SPKR_B_P
MIC_BIAS
MIC_A_P
MIC_A_N
MIC_B_N
MIC_B_P
AU_REF
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
Serial Interfaces
USB v1.1 UART
UART_TX
UART_RX
UART_CTS
UART_RTS
USB_DP
USB_DN
VDD_USB
I
2
CInterface
PIO[7]
PIO[8]
PIO[6]
SPI
Interface
SPI_CS#
SPI_MISO
SPI_MOSI
SPI_CLK
SCL
SDA
Internal Flash Memory Interface
16Mbit Flash
Programmable I/O
LED Driver AIO GPIO
LED[1]
AIO[0]
AIO[1]
PIO[5:0]
VSS_PIO
VDD_PIO
PIO[11:9]
RF_BIAS
RF_DCPL
BAL_MATCH
Bluetooth v2.1 Radio
Baseband
Radio Control
Basic Rate
Modem
Enhanced
Rate Modem
Plug-n-Go
Figure 2.1: BlueCore5-Multimedia Plug-n-Go Automotive Device diagram
Device Diagram
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3 Package Information
3.1 Pinout Diagram
A
B
C
D
E
F
G
H
J
K
L
1234567891011
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
D1 D2 D3 D9 D10 D11
E1 E2 E3 E9 E10 E11
F1 F2 F3 F9 F10 F11
G1 G2 G3 G9 G10 G11
H1 H2 H3 H9 H10 H11
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Orientation from top of device
E7
F7
F5 F6
G5 G6 G7
E5 E6
Figure 3.1: BlueCore5-Multimedia Plug-n-Go Automotive Device Pinout
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3.2 BlueCore5-Multimedia Plug-n-Go Automotive Device Terminal
Functions
Radio Ball Pad Type Supply Domain Description
BAL_MATCH C1 RF RF Tie to VSS_RADIO
RF_CONNECT D1 RF RF 50Ω RF matched I/O
RF_BIAS G1 RF RF Bias for internal Balun
RF_DCPL H1 RF RF Decoupling for RF_BIAS. Tie to
VSS.
RF_NEG K1 RF RF Cold end of Balun Ouput. Tie to
VSS.
Synthesiser and
Oscillator Ball Pad Type Supply Domain Description
XTAL_IN L3 Analogue VDD_ANA For crystal or external clock input
XTAL_OUT L4 Analogue VDD_ANA Drive for crystal
LO_REF J5 Analogue VDD_LO Reference voltage to decouple the
synthesiser
UART and USB Ball Pad Type Supply Domain Description
UART_TX H9
Bi-directional CMOS
output, tri-state, with
weak internal pull-up
VDD_USB UART data output
UART_RX J9
CMOS input with
weak internal pull-
down
VDD_USB UART data input
UART_RTS K9
Bi-directional CMOS
output, tri-state, with
weak internal pull-up
VDD_USB UART request to send, active low
UART_CTS K8
CMOS input with
weak internal pull-
down
VDD_USB UART clear to send, active low
USB_DP K11 Bi-directional VDD_USB USB data plus with selectable
internal 1.5kΩ pull-up resistor
USB_DN K10 Bi-directional VDD_USB USB data minus
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PCM Interface Ball Pad Type Supply Domain Description
PCM_OUT F11
CMOS output, tri-
state, with weak
internal pull-down
VDD_PADS Synchronous data output
PCM_IN G11
CMOS input, with
weak internal pull-
down
VDD_PADS Synchronous data input
PCM_SYNC F10
Bi-directional with
weak internal pull-
down
VDD_PADS Synchronous data sync
PCM_CLK F9
Bi-directional with
weak internal pull-
down
VDD_PADS Synchronous data clock
SPI Interface Ball Pad Type Supply Domain Description
SPI_MISO D11
CMOS output, tri-
state, with weak
internal pull-down
VDD_PADS SPI data output
SPI_MOSI E9
CMOS input, with
weak internal pull-
down
VDD_PADS SPI data input
SPI_CS# E11 Input with weak
internal pull-up VDD_PADS Chip select for (SPI), active low
SPI_CLK E10 Input with weak
internal pull-down VDD_PADS SPI clock
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PIO Port Ball Pad Type Supply Domain Description
PIO[0] B1
Bi-directional with
programmable
strength internal pull-
up/down
VDD_PIO Programmable input/output line
PIO[1] B7
PIO[2] B6
PIO[3] A6
PIO[4] B8
Bi-directional with
programmable
strength internal pull-
up/down
VDD_PADS Programmable input/output line
PIO[5] C8
PIO[6] K6
PIO[7] L6
PIO[8] K7
PIO[9] J8
PIO[10] L7
PIO[11] J7
AIO[0] J6
Bi-directional VDD_ANA Analogue programmable input/
output line
AIO[1] K5
Test and Debug Ball Pad Type Supply Domain Description
RST# G9 CMOS input with
weak internal pull-up VDD_PADS
Reset if low. Input debounced so
must be low for >5ms to cause a
reset
TEST_EN G10
CMOS input with
strong internal pull-
down
VDD_PADS For test purposes only (leave
unconnected)
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CODEC Ball Pad Type Supply Domain Description
MIC_A_P A2 Analogue VDD_AUDIO Microphone input positive, left
MIC_A_N A1 Analogue VDD_AUDIO Microphone input negative, left
MIC_B_P B4 Analogue VDD_AUDIO Microphone input positve, right
MIC_B_N A3 Analogue VDD_AUDIO Microphone input negative, right
SPKR_A_P C2 Analogue VDD_AUDIO Speaker output positive, left
SPKR_A_N C3 Analogue VDD_AUDIO Speaker output negative, left
SPKR_B_P B2 Analogue VDD_AUDIO Speaker output positive, right
SPKR_B_N B3 Analogue VDD_AUDIO Speaker output negative, right
MIC_BIAS B5 Analogue VDD_AUDIO Microphone bias
AU_REF_DCPL C5 Analogue VDD_AUDIO Decoupling of audio reference (for
high-quality audio)
LED Drivers Ball Pad Type Supply Domain Description
LED[1] D10 Open drain output See Section 11.10 LED driver
LED[0] C10 Open drain output See Section 11.10 LED driver
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Power Supplies and
Control Ball Pad Type Description
VREGENABLE_L K2 Analogue
Take high to enable both low-
voltage regulator and audio low-
voltage regulator
VREGENABLE_H A8 Analogue
Take high to enable high-voltage
linear regulator and switch-mode
regulator
VREGIN_L K3 Regulator input Low-voltage linear regulator input
for non-audio core circuitry
VREGIN_AUDIO A5 Regulator input Audio low-voltage linear regulator
input
VREGIN_H A11 Regulator input High-voltage linear regulator input
VREGOUT_H B11 Supply High-voltage linear regulator output
LX A10
Switched-mode
power regulator
output
Switched-mode power regulator
output
VDD_USB L11 VDD Positive supply for UART and USB
ports
VDD_PIO E3 VDD Positive supply for PIO
VDD_PADS J11 VDD Positive supply for all other digital
input/output ports
VDD_CORE H11, C11 VDD Positive supply for internal digital
circuitry, 1.5V
VDD_RADIO H3 VDD/Low-voltage
regulator sense Positive supply for RF circuitry, 1.5V
VDD_LO J3 VDD Positive supply for local oscillator
circuitry, 1.5V
VDD_ANA L2 VDD/Low-voltage
regulator output
Positive supply output for analogue
circuitry and 1.5V regulated output
(from low-voltage regulator)
VDD_AUDIO A4 VDD Positive supply for audio, 1.5V
BAT_P B10 Battery positive
terminal
Lithium ion/polymer battery positive
terminal. Battery charger output and
input to switch-mode regulator
VDD_CHG B9 Charger input Lithium ion/polymer battery charger
input
VDD_SMP_CORE A9 VDD Positive supply for switch mode
control circuitry
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Power Supplies and
Control Ball Pad Type Description
VDD_MEM A7, L8, L10 VDD Positive supply for internal Flash
memory
VSS_DIG C6, D9, F3, H10, J10, L5, L9 VSS Ground connection for internal
digital circuitry
VSS_RADIO F2, H2 VSS Ground connections for RF circuitry
VSS_LO J2 VSS Ground connections for local
oscillator
VSS_ANA K4 VSS Ground connections for analogue
circuitry
VSS_AUDIO C4 VSS Ground connection for audio
BAT_N C9 Battery negative
terminal
Lithium ion/polymer battery
negative terminal. Ground
connection for switch-mode
regulator.
SUBS C7, E5, E6, E7, F5, F6, F7,
G5, G6, G7, J4 VSS
Connection to internal die substrate.
Connect to lowest possible
potential.
Unconnected
Terminals Ball Description
N/C D2, D3, E1, E2, F1, G2, G3,
J1, L1 Leave unconnected
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3.3 Package Dimensions
DD1
e
A
B
C
D
E
F
G
H
J
K
L
X
Y
78
9
1011
11 654321
78
9
106
5
4
3
21
A
A1 A2
SE
SD
A3
SEATING PLANE
Z2
0.12 Z
3
0.2 Z
Øb
1
Top View Bottom View
Description 105-Ball Low-Profile Fine-Pitch Ball Grid Array (LFBGA)
Size 10 x 10 x 1.6mm
Pitch 0.8mm
Package Ball Land Solder mask defined. Solder mask aperture 300mmØ
Dimension Minimum Typical Maximum Notes
A1.6
A1 0.27 - 0.37
A2 0.26
A3 1.00
b0.37-0.47
D 9.90 10.00 10.10
E 9.90 10.00 10.10
e0.80
D1 8.00
E1 8.00
F 0.950 1.000 1.050
G 0.950 1.000 1.050
H 0.950 1.000 1.050
J 0.950 1.000 1.050
PX 0.625
PY 0.625
SD 0
SE 0
X1.10
Y0.70
1
2
3
4
5
Dimension b is measur ed at the maxim um
solder ball diameter parallel to datum
plane Z
Datum Z is defined by the spherical crowns
of the solder balls
Parallelism measurement shall exclude any
effect of mark on top surface of package
Top-side polarity mark. The dimensions of
the square polarity mark are 0.5 x 0.5mm.
Bottom-side polarity mark. The dimensions of
the triangular polarity mark are 0.30 x 0.30 x
0.42mm.
JEDEC MO-210
Unit mm
4
PX
PY
Scale = 1mm
A
B
C
D
E
F
G
H
J
K
L
EE1
F
G
JH
5
Figure 3.2: BlueCore5-Multimedia Plug-n-Go Automotive 105-ball LFBGA Package Dimensions
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3.4 PCB Design and Assembly Considerations
This section lists recommendations to achieve maximum board-level reliability of the 10 x 10 x 1.6mm LFBGA 105-
ball package:
■
NSMD lands (that is, lands smaller than the solder mask aperture) are preferred because of the greater
accuracy of the metal definition process compared to the solder mask process. With solder mask defined
pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which
can cause stress concentration and act as a point for crack initiation.
■
Via-in-pad technology should be used to achieve truly NSMD lands. Where this is not possible, a maximum
of one trace connected to each land is preferred and this trace should be as thin as possible, taking into
consideration its current carrying and the RF requirements.
■
35µm thick (1oz) copper lands are recommended rather than 17µm thick (0.5oz). This results in a greater
standoff which has been proven to provide greater reliability during thermal cycling.
■
Land diameter should be the same as that on the package to achieve optimum reliability.
■
Solder paste is preferred to flux during the assembly process because this adds to the final volume of solder
in the joint, increasing its reliability.
■
Where a nickel gold plating finish is used, the gold thickness should be kept below 0.5µm to prevent brittle
gold/tin intermetallics forming in the solder.
3.4.1 Thermal Resistance
By simulation to JEDEC JESD-51 the Theta Ja of the BlueCore5-Multimedia Plug-n-Go Automotive 10 x 10 x 1.6mm
LFBGA 105-ball package is 38ºC/W, on a 4-layer PCB with zero air flow.
3.5 Typical Solder Reflow Profile
See
Typical Solder Reflow Profile for Lead-free Devices
for information.
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4 Bluetooth Modem
4.1 RF Plug-n-Go
The package used on the BlueCore5-Multimedia Plug-n-Go Automotive device is an RF Plug-n-Go package, where
the terminal RF_CONNECT forms an unbalanced output with a nominal 50Ω impedance. This terminal can be
connected to an antenna requiring no impedance matching network as Figure 4.1 indicates, however a filter is
needed.
Filter
RF_CONNECT
R1
50Ω
BlueCore
Figure 4.1: Circuit for RF_CONNECT
4.2 RF Receiver
The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and W-
CDMA cellular phone transmitters without being desensitised. The use of a digital FSK discriminator means that no
discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore5-Multimedia
Plug-n-Go Automotive to exceed the Bluetooth requirements for co-channel and adjacent channel rejection.
For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed
to the EDR modem.
4.2.1 Low Noise Amplifier
The LNA operates in differential mode and takes its input from the shared RF port.
4.2.2 RSSI Analogue to Digital Converter
The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference limited environments.
4.3 RF Transmitter
4.3.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
4.3.2 Power Amplifier
The internal PA has a maximum output power that allows BlueCore5-Multimedia Plug-n-Go Automotive to be used
in Class 2 and Class 3 radios without an external RF PA.
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4.4 Bluetooth Radio Synthesiser
The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening
can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time
across the guaranteed temperature range to meet the Bluetooth v2.1 + EDR specification.
4.5 Baseband
4.5.1 Burst Mode Controller
During transmission the BMC constructs a packet from header information previously loaded into memory-mapped
registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception,
the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer
in RAM. This architecture minimises the intervention required by the processor during transmission and reception.
4.5.2 Physical Layer Hardware Engine
Dedicated logic performs the following:
■
Forward error correction
■
Header error control
■
Cyclic redundancy check
■
Encryption
■
Data whitening
■
Access code correlation
■
Audio transcoding
Firmware performs the following voice data translations and operations:
■
A-law/µ-law/linear voice data (from host)
■
A-law/µ-law/CVSD (over the air)
■
Voice interpolation for lost packets
■
Rate mismatch correction
The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR specification including AFH
and eSCO.
4.6 Basic Rate Modem
The basic rate modem satisfies the basic data rate requirements of the Bluetooth v2.1 + EDR specification. The
basic rate was the standard data rate available on the Bluetooth v1.2 specification and below, it is based on GFSK
modulation scheme.
The inclusion of the basic rate modem allows BlueCore5-Multimedia Plug-n-Go Automotive compatibility with earlier
Bluetooth products.
The basic rate modem uses the RF ports, receiver, transmitter and synthesiser, alongside the baseband components
described in Section 4.5.
4.7 Enhanced Data Rate Modem
The EDR modem satisfies the requirements of the Bluetooth v2.1 + EDR specification. EDR has been introduced
to provide 2x and 3x data rates with minimal disruption to higher layers of the Bluetooth stack. BlueCore5-Multimedia
Plug-n-Go Automotive supports both the basic and enhanced data rates and is compliant with the Bluetooth
v2.1 + EDR specification.
At the baseband level, EDR utilises both the same 1.6kHz slot rate and the 1MHz symbol rate as defined for the
basic data rate. EDR differs in that each symbol in the payload portion of a packet represents 2 or 3-bits. This is
achieved using two new distinct modulation schemes. Table 4.1 and Figure 4.2 summarise these. Link Establishment
and management are unchanged and still use GFSK for both the header and payload portions of these packets.
The enhanced data rate modems uses the RF Ports, Receiver, Transmitter and Synthesiser, with the baseband
components described in Section 4.5.
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Data Rate Scheme Bits Per Symbol Modulation
BDR 1GFSK
EDR 2π/4 DQPSK
EDR 38DPSK (optional)
Table 4.1: Data Rate Schemes
Access Code
Access Code
Header
Header
Payload
Guard Sync Payload Trailer
Basic Rate
Enhanced Data Rate
/
4 DQPSK or 8DPSK
Figure 4.2: BDR and EDR Packet Structure
4.7.1 Enhanced Data Rate π/4 DQPSK
The 2x data rate for EDR uses a π/4-DQPSK. Each symbol represents 2-bits of information. Figure 4.3 shows the
constellation. It has two planes, each having four points. Although it seems there are eight possible phase states,
the encoding ensures that the trajectory of the modulation between symbols is restricted to the four states in the
other plane.
For a given starting point, each phase change between symbols is restricted to 3π/4, π/4, -π/4 or -3π/4 radians
(135°, 45°, -45° or -135°). For example, the arrows shown in Figure 4.3 represent trajectory to the four possible
states in the other plane. Table 4.2 shows the phase shift encoding of symbols.
There are two main advantages in using π/4 DQPSK modulation:
■
The scheme avoids the crossing of the origin (a π or -π phase shift) and therefore minimises amplitude
variations in the envelope of the transmitted signal. This in turn allows the RF power amplifiers of the
transmitter to be operated closer to their compression point without introducing spectral distortions.
Consequently, the DC to RF efficiency is maximised.
■
The differential encoding also allows for the demodulation without the knowledge of an absolute value for
the phase of the RF carrier.
0001
11 10
Figure 4.3: π/4 DQPSK Constellation Pattern
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Bit Pattern Phase Shift
00 π/4
01 3π/4
11 -3π/4
10 -π/4
Table 4.2: 2-bits Determine Phase Shift Between Consecutive Symbols
4.7.2 Enhanced Data Rate 8DPSK
The 3x data rate modulation uses 8DPSK. Each symbol in the payload portion of the packet represents 3 baseband
bits. Although it seems the 8DPSK is similar to π/4 DQPSK, the differential phase shifts between symbols are now
permissible between any of the eight possible phase states. This reduces the separation between adjacent symbols
on the constellation to π/4 (45°) and thereby reduces the noise and interference immunity of the modulation scheme.
Nevertheless, because each symbol now represents 3 baseband bits, the actual throughput of the data is 3x when
compared with the basic rate packet.
Figure 4.4 shows the 8DPSK constellation and Table 4.3 shows the phase encoding.
001010
111 100
000
011
110
101
Figure 4.4: 8DPSK Constellation Pattern
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Bit Pattern Phase Shift
000 0
001 π/4
011 π/2
010 3π/4
110 π
111 -3π/4
101 -π/2
100 -π/4
Table 4.3: 3-bits Determine Phase Shift Between Consecutive Symbols
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5 Clock Generation
BlueCore5-Multimedia Plug-n-Go Automotive requires a Bluetooth reference clock frequency of 12MHz to 52MHz
from either an externally connected crystal or from an external TCXO source.
All BlueCore5-Multimedia Plug-n-Go Automotive internal digital clocks are generated using a phase locked loop,
which is locked to the frequency of either the external 12MHz to 52MHz reference clock source or an internally
generated watchdog clock frequency of 1kHz.
The Bluetooth operation determines the use of the watchdog clock in low-power modes.
5.1 Clock Architecture
Bluetooth
Radio
Auxiliary
PLL
Digital
Circuitry
Reference Clock
Figure 5.1: Clock Architecture
5.2 Input Frequencies and PS Key Settings
BlueCore5-Multimedia Plug-n-Go Automotive should be configured to operate with the chosen reference frequency.
Do this by setting the PS Key PSKEY_ANA_FREQ (
0x01FE
) for all frequencies with an integer multiple of 250kHz.
The input frequency default setting in BlueCore5-Multimedia Plug-n-Go Automotive is 26MHz depending on the
software build. Full details are in the software release note for the specific build from www.csrsupport.com.
The following CDMA/3G phone TCXO frequencies are also catered for: 14.40, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68,
19.8 and 38.4MHz. The value of the PS Key is a multiple of 1kHz, so 38.4MHz is selected by using a PS Key value
of 38400.
Reference Crystal Frequency (MHz) PSKEY_ANA_FREQ (
0x1fe
) (kHz)
14.40 14400
15.36 15360
16.20 16200
16.80 16800
19.20 19200
19.44 19440
19.68 19680
19.80 19800
38.40 38400
n x 0.25 n x 250
26.00 (default) 26000
Table 5.1: PS Key Values for CDMA/3G Phone TCXO
Clock Generation
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5.3 External Reference Clock
5.3.1 Input (XTAL_IN)
The external reference clock is applied to the BlueCore5-Multimedia Plug-n-Go Automotive XTAL_IN input.
BlueCore5-Multimedia Plug-n-Go Automotive is configured to accept the external reference clock at XTAL_IN by
connecting XTAL_OUT to ground. The external clock can be either a digital level square wave or sinusoidal, and
this may be directly coupled to XTAL_IN without the need for additional components. A digital level reference clock
gives superior noise immunity, as the high slew rate clock edges have lower voltage to phase conversion. If peaks
of the reference clock are either below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking
capacitor (approximately 33pF) connected to XTAL_IN.
The external reference clock signal should meet the specifications outlined in Table 5.2.
Min Typ Max Unit
Frequency
(a)
12 26 52 MHz
Duty cycle 20:80 50:50 80:20
Edge jitter (at zero crossing) - - 15 ps rms
Signal level
AC coupled sinusoid 0.4 -VDD_ANA
(b)
V pk-pk
DC coupled
digital
V
IL
-VSS_ANA
(c)
- V
V
IH
-VDD_ANA
(b)
(c)
- V
Table 5.2: External Clock Specifications
(a)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
(b)
VDD_ANA is 1.5V nominal
(c)
If driven via a DC blocking capacitor max amplitude is reduced to 750mV pk-pk for non 50:50 duty cycle
5.3.2 XTAL_IN Impedance in External Mode
The impedance of XTAL_IN does not change significantly between operating modes, typically 10fF. When
transitioning from Deep Sleep to an active state a spike of up to 1pC may be measured. For this reason CSR
recommends that a buffered clock input is used.
5.3.3 Clock Start-up Delay
BlueCore5-Multimedia Plug-n-Go Automotive hardware incorporates an automatic 5ms delay after the assertion of
the system clock request signal before running firmware. This is suitable for most applications using an external
clock source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable
after this period. Under these conditions, BlueCore5-Multimedia Plug-n-Go Automotive firmware provides a software
function that extends the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY.
This value is set in milliseconds from 1-31ms. Zero is the default entry for 5ms delay.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still
keeping the current consumption of BlueCore5-Multimedia Plug-n-Go Automotive as low as possible. BlueCore5-
Multimedia Plug-n-Go Automotive consumes about 2mA of current for the duration of
PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
5.3.4 Clock Timing Accuracy
As Figure 5.2 shows, the 250ppm timing accuracy on the external clock is required 2ms after the firmware begins
to run. This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth
v2.1 + EDR specification. Radio activity may occur after 6ms after the firmware starts. Therefore, at this point the
timing accuracy of the external clock source must be within ±20ppm.
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Clock Accuracy
0
20 ppm
6
250 ppm
2
1000 ppm
ms After Firmware
CLK_REQ
Firmware Activity
PSKEY_CLOCK_STARTUP_DELAY
Firmware Activity
Radio Activity
Figure 5.2: TCXO Clock Accuracy
5.4 Crystal Oscillator (XTAL_IN, XTAL_OUT)
BlueCore5-Multimedia Plug-n-Go Automotive contains a crystal driver circuit. This operates with an external crystal
and capacitors to form a Pierce oscillator. The external crystal is connected to pins XTAL_IN, XTAL_OUT.
-
g
m
C
tri
m
C
int
C
t2
C
t1
X
TAL_OUT
XTAL_IN
Figure 5.3: Crystal Driver Circuit
Figure 5.4 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.
L
m
R
m
C
m
C
o
Figure 5.4: Crystal Equivalent Circuit
The resonant frequency may be trimmed with the crystal load capacitance. BlueCore5-Multimedia Plug-n-Go
Automotive contains variable internal capacitors to provide a fine trim.
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Parameter Min Typ Max Unit
Frequency 16 26 26 MHz
Initial Tolerance -±25 -ppm
Pullability -±20 -ppm/pF
Transconductance 2.0 - - mS
Table 5.3: Crystal Specification
The BlueCore5-Multimedia Plug-n-Go Automotive driver circuit is a transconductance amplifier. A voltage at
XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum
performance.
5.4.1 Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore5-
Multimedia Plug-n-Go Automotive provides some of this load with the capacitors C
trim
and C
int
. The remainder should
be from the external capacitors labelled C
t1
and C
t2
. C
t1
should be three times the value of C
t2
for best noise
performance. This maximises the signal swing, hence slew rate at XTAL_IN (to which all on-chip clocks are referred).
Crystal load capacitance, C
l
is calculated with Equation 5.1:
C
l
=C
int
+
(Ct2 +C
trim )Ct1
Ct2 +C
trim +C
t1
Equation 5.1: Load Capacitance
Note:
C
trim
= 3.4pF nominal (mid-range setting)
C
int
= 1.5pF
C
int
does not include the crystal internal self capacitance; it is the driver self capacitance.
5.4.2 Frequency Trim
BlueCore5-Multimedia Plug-n-Go Automotive enables frequency adjustments to be made. This feature is typically
used to remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting
the crystal load capacitance with an on-chip trim capacitor, C
trim
. The value of C
trim
is set by a 6-bit word in the PS
Key PSKEY_ANA_FTRIM (
0x1f6
). Its value is calculated as follows:
C
trim
= 125fF × PSKEY_ANA_FTRIM
Equation 5.2: Trim Capacitance
The C
trim
capacitor is connected between XTAL_IN and ground. When viewed from the crystal terminals, the
combination of the tank capacitors and the trim capacitor presents a load across the terminals of the crystal which
varies in steps of typically 125fF for each least significant bit increment of PSKEY_ANA_FTRIM.
Equation 5.3 describes the frequency trim.
Δ(Fx)
Fx
= pullability × 0.110 ×
(
Ct1
Ct1 +C
t2 +C
trim
)
(ppm / LSB)
Equation 5.3: Frequency Trim
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Note:
F
x
= crystal frequency
Pullability is a crystal parameter with units of ppm/pF.
Total trim range is 0 to 63.
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 5.4.
()
() ()
2
0I
I
m
X
X
CC
C2
C
F
F
+
=
∂
∂
•
Equation 5.4: Pullability
Note:
C
0
= Crystal self capacitance (shunt capacitance)
C
m
= Crystal motional capacitance (series branch capacitance in crystal model). See Figure 5.4.
It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to
pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with
ageing and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is
required.
5.4.3 Transconductance Driver Model
The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to
one terminal generates a voltage at the other. The transconductance amplifier in BlueCore5-Multimedia Plug-n-Go
Automotive uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the
circuit will oscillate if the transconductance, transimpedance product is greater than unity. For sufficient oscillation
amplitude, the product should be greater than three. The transconductance required for oscillation is defined by the
relationship shown in Equation 5.5.
gm>3
(2πF
x)2Rm
((
C0+C
int
)(
Ct1 +C
t2 +C
trim
)
+C
t1
(
Ct2 +C
trim
))
Ct1 (Ct2 +C
trim )
Equation 5.5: Transconductance Required for Oscillation
BlueCore5-Multimedia Plug-n-Go Automotive guarantees a transconductance value of at least 2mA/V at maximum
drive level.
Note:
More drive strength is required for higher frequency crystals, higher loss crystals (larger R
m
) or higher
capacitance loading.
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is
determined by the crystal driver transconductance.
5.4.4 Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The
driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the
negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the BlueCore5-
Multimedia Plug-n-Go Automotive crystal driver circuit is based on a transimpedance amplifier, an equivalent
negative resistance can be calculated for it using Equation 5.6.
R
neg
>
Ct1 (Ct2 +C
trim )
gm(2πF
x)2
(
C0+C
int
)((
Ct1 +C
t2 +C
trim
)
+C
t1
(
Ct2 +C
trim
))
2
Equation 5.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore5-Multimedia Plug-n-Go Automotive driver as a function
of its drive strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series
with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the
oscillator.
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5.4.5 Crystal PS Key Settings
The BlueCore5-Multimedia Plug-n-Go Automotive firmware automatically controls the drive level on the crystal circuit
to achieve optimum input swing. The PS Key PSKEY_XTAL_TARGET_AMPLITUDE (
0x24b
) is used by the
firmware to servo the required amplitude of crystal oscillation. Refer to the software build release note for a detailed
description.
BlueCore5-Multimedia Plug-n-Go Automotive should be configured to operate with the chosen reference frequency.
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6 Bluetooth Stack Microcontroller
A 16-bit RISC MCU is used for low power consumption and efficient use of memory.
The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and
host interfaces.
6.1 TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore5-Multimedia Plug-n-Go
Automotive where either device can turn on the clock without having to wake up the other device, see Figure 6.1.
PIO[3] can be used as the host clock enable input and PIO[2] can be used as the OR output with the TCXO enable
signal from BlueCore5-Multimedia Plug-n-Go Automotive.
Note:
To turn on the clock, the clock enable signal on PIO[3] must be high.
BlueCore System
GSM System
TCXO
VDD
Enable
CLK IN
CLK IN
CLK REQ IN/
PIO[3]
CLK REQ OUT/
PIO[2]
CLK REQ OUT
Figure 6.1: Example TCXO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] is tri-state. Therefore, the developer must ensure
that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This ensures that
the TCXO is oscillating at start up.
6.2 Programmable I/O (PIO) Parallel Ports
12 lines of programmable bi-directional I/O are provided.
Note:
PIO[11:4] are powered from VDD_PADS and PIO[3:0] are powered from VDD_PIO. AIO[0:1] are powered from
VDD_ANA.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO[2] can be configured as a request line for an external clock source. Using PSKEY_CLOCK_REQUEST_ENABLE
(
0x246
), this terminal can be configured to be low when BlueCore5-Multimedia Plug-n-Go Automotive is in Deep
Sleep and high when a clock is required.
Note:
CSR cannot guarantee that the PIO assignments remain as described. Refer to the relevant software release
note for the implementation of these PIO lines, as they are firmware build-specific.
Bluetooth Stack Microcontroller
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BlueCore5-Multimedia Plug-n-Go Automotive has two general-purpose analogue interface pins, AIO[0:1], used to
access internal circuitry and control signals. Auxiliary functions available on the analogue interface include a 10-bit
ADC. Signals selectable on this interface include the band gap reference voltage and a variety of clock signals: 64,
48, 32, 24, 16, 12, 8, 6 and 2MHz (outputted from AIO[0] only) and the XTAL and XTAL/2 clock frequency (outputted
from AIO[0] and AIO[1]). When used with analogue signals the voltage range is constrained by the analogue supply
voltage. When configured to drive out digital level signals (clocks) generated from within the analogue part of the
device, the output voltage level is determined by VDD_ANA.
6.3 WLAN Coexistence Interface
Dedicated hardware is provided to implement a variety of coexistence schemes. Channel skipping AFH, priority
signalling, channel signalling and host passing of channel instructions are all supported. The features are configured
in firmware.
For more information see
Bluetooth and IEEE 802.11 b/g Coexistence Solutions Overview
from .
Bluetooth Stack Microcontroller
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7 Kalimba DSP
The Kalimba DSP is an open platform Kalimba DSP allowing signal processing functions to be performed on over
air data or codec data in order to enhance audio applications. The Kalimba DSP interfaces to other functional blocks
within BlueCore5-Multimedia Plug-n-Go Automotive as shown in Figure 7.1.
DSP RAMs
Memory
Management Unit
MCU Register Interface (including Debug)
Kalimba DSP Core
DM2
(12K x 24-bit)
DM1
(16K x 24-bit)
PM
(6K x 32-bit)
Instruction Decode
Program Flow DEBUG
Data Memory
Interface
Address
Generators
ALU
Clock Select PIO
Internal Control Registers
MMU Interface
Interrupt Controller
Timer
MCU Window
Flash Window
DSP MMU Port
DSP Data Memory 2 Interface (DM2)
DSP Data Memory 1 Interface (DM1)
DSP Program Memory Interface (PM)
Registers
Programmable Clock = 64MHz
PIO In/Out
IRQ to Subsystem
IRQ from Subsystem
1µs Timer Clock
DSP Program Control
DSP, MCU and Flash Window Control
Figure 7.1: Kalimba DSP Interface to Internal Functions
The key features of the DSP include:
■
64MIPS performance, 24-bit fixed point DSP Core
■
Single cycle MAC of 24 x 24-bit multiply and 56-bit accumulate
■
32-bit instruction word
■
Separate program memory and dual data memory, allowing an ALU operation and up to two memory
accesses in a single cycle
■
Zero overhead looping
■
Zero overhead circular buffer indexing
■
Single cycle barrel shifter with up to 56-bit input and 24-bit output
■
Multiple cycle divide (performed in the background)
■
Bit reversed addressing
■
Orthogonal instruction set
■
Low overhead interrupt
Kalimba DSP
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8 Memory Interface and Management
8.1 Memory Management Unit
The MMU provides a number of dynamically allocated ring buffers that hold the data that is in transit between the
host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and
is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers.
8.2 System RAM
48KB of on-chip RAM supports the RISC MCU and is shared between the ring buffers used to hold voice/data for
each active connection and the general-purpose memory required by the Bluetooth stack.
8.3 Kalimba DSP RAM
Additional on-chip RAM is provided to support the Kalimba DSP:
■
16K x 24-bit for data memory 1 (DM1)
■
12K x 24-bit for data memory 2 (DM2)
■
6K x 32-bit for program memory (PM)
Note:
The DSP can also execute directly from internal Flash, using a 64-instruction on-chip cache.
8.4 Internal Flash Memory (16Mb)
16Mb of internal Flash memory is available on the BlueCore5-Multimedia Plug-n-Go Automotive. The internal Flash
memory is provided for system firmware and the Kalimba DSP co-processor code implementation.
The internal Flash memory provides 16Mb of internal code and data storage. This storage is used to store BlueCore5-
Multimedia Plug-n-Go Automotive settings and program code, and Kalimba DSP co-processor code and data.
8.4.1 Flash Specification
The flash device used with BlueCore5-Multimedia Plug-n-Go Automotive meets the following criteria:
Parameter Value
Data width 16-bit
Capacity 16Mb
Access time 70ns
Table 8.1: Internal Flash Device Specifications
Memory Interface and Management
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9 Serial Interfaces
9.1 UART Interface
This is a standard UART interface for communicating with other serial devices.
BlueCore5-Multimedia Plug-n-Go Automotive UART interface provides a simple mechanism for communicating with
other serial devices using the RS232 protocol.
UART_TX
UART_RX
UART_RTS
UART_CTS
Figure 9.1: Universal Asynchronous Receiver
Four signals implement the UART function, as shown in Figure 9.1. When BlueCore5-Multimedia Plug-n-Go
Automotive is connected to another digital device, UART_RX and UART_TX transfer data between the two devices.
The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control
where both are active low indicators.
UART configuration parameters, such as baud rate and packet format, are set using BlueCore5-Multimedia Plug-n-
Go Automotive firmware.
Note:
To communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter
card is required for the PC.
Parameter Possible Values
Baud rate Minimum
1200 baud (≤2%Error)
9600 baud (≤1%Error)
Maximum 4Mbaud (≤1%Error)
Flow control RTS/CTS or None
Parity None, Odd or Even
Number of stop bits 1 or 2
Bits per byte 8
Table 9.1: Possible UART Settings
The UART interface can reset BlueCore5-Multimedia Plug-n-Go Automotive on reception of a break signal. A break
is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 9.2. If t
BRK
is longer than
the value, defined by the PS Key PSKEY_HOSTIO_UART_RESET_TIMEOUT, (
0x1a4
), a reset occurs. This
feature allows a host to initialise the system to a known state. Also, BlueCore5-Multimedia Plug-n-Go Automotive
can emit a break character that may be used to wake the host.
Serial Interfaces
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UART R
X
t
BR
K
Figure 9.2: Break Signal
Note:
The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used.
This initial flash programming can be done via the SPI.
Table 9.2 shows a list of commonly used baud rates and their associated values for the PS Key
PSKEY_UART_BAUDRATE (
0x1be
). There is no requirement to use these standard values. Any baud rate within
the supported range can be set in the PS Key according to the formula in Equation 9.1.
Baud Rate = PSKEY_UART_BAUDRATE
0.004096
Equation 9.1: Baud Rate
Baud Rate
Persistent Store Value
Error
Hex Dec
1200 0x0005 51.73%
2400 0x000a 10 1.73%
4800 0x0014 20 1.73%
9600 0x0027 39 -0.82%
19200 0x004f 79 0.45%
38400 0x009d 157 -0.18%
57600 0x00ec 236 0.03%
76800 0x013b 315 0.14%
115200 0x01d8 472 0.03%
230400 0x03b0 944 0.03%
460800 0x075f 1887 -0.02%
921600 0x0ebf 3775 0.00%
1382400 0x161e 5662 -0.01%
1843200 0x1d7e 7550 0.00%
2764800 0x2c3d 11325 0.00%
3686400 0x3afb 15099 0.00%
Table 9.2: Standard Baud Rates
Serial Interfaces
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9.1.1 UART Configuration While Reset is Active
The UART interface for BlueCore5-Multimedia Plug-n-Go Automotive is tri-state while the chip is being held in reset.
This allows the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any
devices connected to this bus must tri-state when BlueCore5-Multimedia Plug-n-Go Automotive reset is de-asserted
and the firmware begins to run.
9.1.2 UART Bypass Mode
Host Processo
r
UART Bypas
s
Another Devic
e
RS
T
#
UAR
T
RX
D
CT
S
Test Interfac
e
RT
S
UART
_
R
X
UART_CT
S
UART
_
RT
S
UART
_
T
X
PIO4
PIO
5
PIO
6
PIO
7
TX
D
T
X
RT
S
CT
S
R
X
Figure 9.3: UART Bypass Architecture
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore5-Multimedia Plug-
n-Go Automotive can be used. The default state of BlueCore5-Multimedia Plug-n-Go Automotive after reset is de-
asserted; this is for the host UART bus to be connected to the BlueCore5-Multimedia Plug-n-Go Automotive UART,
thereby allowing communication to BlueCore5-Multimedia Plug-n-Go Automotive via the UART. All UART bypass
mode connections are implemented using CMOS technology and have signalling levels of 0V and VDD_PADS.
To apply the UART bypass mode, a BCCMD command is issued to BlueCore5-Multimedia Plug-n-Go Automotive.
Upon this issue, it switches the bypass to PIO[7:4] as Figure 9.3 shows. When the bypass mode has been invoked,
BlueCore5-Multimedia Plug-n-Go Automotive enters the Deep Sleep state indefinitely.
To re-establish communication with BlueCore5-Multimedia Plug-n-Go Automotive, the chip must be reset so that
the default configuration takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is
invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
Note:
When in bypass mode, the UART signal levels on the PIO are at VDD_PADS level and when not bypassed (i.e.
when using the normal UART pins) the levels are at VDD_USB levels.
9.1.3 Current Consumption in UART Bypass Mode
The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby
mode.
9.2 USB Interface
BlueCore5-Multimedia Plug-n-Go Automotive has a full-speed (12Mbps) USB interface for communicating with other
compatible digital devices. The USB interface on the BlueCore5-Multimedia Plug-n-Go Automotive acts as a USB
peripheral, responding to requests from a master host controller.
BlueCore5-Multimedia Plug-n-Go Automotive supports the
Universal Serial Bus Specification, Revision v2.0 (USB
v2.0 Specification)
, available from http://www.usb.org. For more information on how to integrate the USB interface
on BlueCore5-Multimedia Plug-n-Go Automotive see the
Bluetooth and USB Design Considerations Application
Note
.
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As well as describing USB basics and architecture the application note describes:
■
Power distribution for high and low bus-powered configurations
■
Power distribution for self-powered configuration, which includes USB VBUS monitoring
■
USB enumeration
■
Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of
ferrite beads
■
USB suspend modes and Bluetooth low-power modes:
■
Global suspend
■
Selective suspend, includes remote wake
■
Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
■
Suspend mode current draw
■
PIO status in suspend mode
■
Resume, detach and wake PIOs
■
Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend
modes and USB VBUS voltage consideration
■
USB termination when interface is not in use
■
Internal modules, certification and non-specification compliant operation
9.3 Serial Peripheral Interface
The primary function of the SPI is for debug. BlueCore5-Multimedia Plug-n-Go Automotive uses a 16-bit data and
16-bit address SPI, where transactions may occur when the internal processor is running or is stopped. This section
details the interface considerations for connection to BlueCore5-Multimedia Plug-n-Go Automotive.
Data may be written or read one word at a time, or the auto-increment feature is available for block access.
9.3.1 Instruction Cycle
The BlueCore5-Multimedia Plug-n-Go Automotive is the slave and receives commands on SPI_MOSI and outputs
data on SPI_MISO. Table 9.3 shows the instruction cycle for an SPI transaction.
1Reset the SPI interface Hold SPI_CS# high for two SPI_CLK cycles
2Write the command word Take SPI_CS# low and clock in the 8-bit command
3Write the address Clock in the 16-bit address word
4Write or read data words Clock in or out 16-bit data word(s)
5Termination Take SPI_CS# high
Table 9.3: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into
the BlueCore5-Multimedia Plug-n-Go Automotive on the rising edge of the clock line SPI_CLK. When reading,
BlueCore5-Multimedia Plug-n-Go Automotive replies to the master on SPI_MISO with the data changing on the
falling edge of the SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking
SPI_CS# high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore5-Multimedia
Plug-n-Go Automotive offers increased data transfer efficiency via an auto increment operation. To invoke auto
increment, SPI_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for
each extra word to be written or read.
9.3.2 Writing to the Device
To write to BlueCore5-Multimedia Plug-n-Go Automotive, the 8-bit write command (00000010) is sent first (C[7:0])
followed by a 16-bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location
set by the address (A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the
data written to consecutive locations until the transaction terminates when SPI_CS# is taken high.
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SPI_CS#
SPI_CLK
SPI_MOSI
SPI_MISO
C7 C6 C1 C0 A15 A14 A1 A0 D15 D14 D1 D0 D15 D14 D1 D0 D15 D14 D1 D0 Don't Care
Processor
State
Address(A) Data(A) Data(A+1) etcWri te_Command
Reset
Processor
State MISO Not Defined During Write
End of Cycl e
Figure 9.4: SPI Write Operation
9.3.3 Reading from the Device
Reading from BlueCore5-Multimedia Plug-n-Go Automotive is similar to writing to it. An 8-bit read command
(00000011) is sent first (C[7:0]), followed by the address of the location to be read (A[15:0]). BlueCore5-Multimedia
Plug-n-Go Automotive then outputs on SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the
addressed location during bits D[15:0].
The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation
to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves,
whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the
slave device not responding.
If SPI_CS# is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks,
until the transaction terminates when SPI_CS# is taken high.
SPI_CS#
SPI_CLK
SPI_MOSI
SPI_MISO
C7 C6 C1 C0 A15 A14 A1 A0 Don't Care
T15 T14 T1 T0 D15 D14 D1 D0 D15 D14 D1 D0 D15 D14 D1 D0
Address(A) Check_Word Data(A) Data(A+1) etc
Reset
Read_Command
End of Cycl e
Processor
State
Processor
State
MISO Not Defined During Address
Figure 9.5: SPI Read Operation
9.3.4 Multi-slave Operation
BlueCore5-Multimedia Plug-n-Go Automotive should not be connected in a multi-slave arrangement by simple
parallel connection of slave MISO lines. When BlueCore5-Multimedia Plug-n-Go Automotive is deselected (SPI_CS#
= 1), the SPI_MISO line does not float. Instead, BlueCore5-Multimedia Plug-n-Go Automotive outputs 0 if the
processor is running or 1 if it is stopped.
9.4 I2C Interface
9.4.1 Software I
2
C Interface
PIO[8:6] can be used to form a Master I
2
C interface. The interface is formed using software to drive these lines.
Therefore it is suited only to relatively slow functions such as driving a dot matrix LCD, keyboard scanner or
EEPROM.
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Serial EEPRO
M
(2
4
AA
3
2
)
4
3
2
1
5
6
7
8
PI
O
[
8
]
PI
O
[
7
]
PI
O
[
6
]
VC
C
W
P
SC
L
SD
A
A
0
A
1
A
2
GN
D
+
1.
8
V
Decouplin
g
Capacito
r
Figure 9.6: Example EEPROM Connection
9.4.2 Bit-serialiser Interface
In addition to the software I
2
C interface outlined in the Software I
2
C Interface section, the BlueCore5-Multimedia
Plug-n-Go Automotive includes a configurable hardware bit-serialiser interface. Any three PIOs can be used as a
serial master interface by configuring the hardware bit-serialiser. In the I
2
C master mode, the hardware bit-serialiser
supports address, direction and ACK handling, but does not support multi-master I
2
C bus systems. I
2
C slave mode
is also not supported.
Note:
The I
2
C interface can be directly controlled by the MCU or the Kalimba DSP.
Suitable firmware is required to support the hardware bit-serialiser interface.
I
2
C and SPI are supported.
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10 Audio Interface
The audio interface circuit consists of:
■
Stereo audio codec
■
Dual audio inputs and outputs
■
A configurable PCM, I
2
S or SPDIF interface
Figure 10.1 shows the functional blocks of the interface. The codec supports stereo playback and recording of audio
signals at multiple sample rates with a resolution of 16-bit. The ADC and the DAC of the codec each contain two
independent channels. Any ADC or DAC channel can be run at its own independent sample rate.
Stereo Codec
Memor y
Management
Unit
MMU Voice Port
MCU Register Interface
Voice Port
Registers
PCM
Digi tal
Audio
Stereo
Audio
Codec
Driver
PCM Interface
Left DAC
Right DAC
Right ADC
Left ADC
Figure 10.1: Audio Interface
The interface for the digital audio bus shares the same pins as the PCM codec interface described in Section 10.3
which means each of the audio buses are mutually exclusive in their usage. Table 10.1 lists these alternative
functions.
PCM Interface SPDIF Interface I
2
S Interface
PCM_OUT SPDIF_OUT SD_OUT
PCM_IN SPDIF_IN SD_IN
PCM_SYNC -WS
PCM_CLK -SCK
Table 10.1: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
10.1 Audio Input and Output
The audio input circuitry consists of a dual audio input that can be configured to be either single-ended or fully
differential and programmed for either microphone or line input. It has an analogue and digital programmable gain
stage for optimisation of different microphones.
The audio output circuitry consists of a dual differential class A-B output stage.
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10.2 Stereo Audio Codec Interface
The main features of the interface are:
■
Stereo and mono analogue input for voice band and audio band
■
Stereo and mono analogue output for voice band and audio band
■
Support for stereo digital audio bus standards such as I
2
S
■
Support for IEC-60958 standard stereo digital audio bus standards, e.g. S/PDIF and AES3/EBU
■
Support for PCM interfaces including PCM master codecs that require an external system clock
Important Note:
To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right
channel for audio input and output. With respect to software and any registers, channel 0 or channel A represents
the left channel and channel 1 or channel B represents the right channel for both input and output.
10.2.1 Mono Audio Codec Block Diagram
Digital
Circuitry
Output
Amplifier
Input
Amplifier
LP Filter
MIC_A_P
SPKR_A_P
Output
Amplifier
Input
Amplifier
LP Filter
MIC_A_N
SPKR_A_N
MIC_B_P
SPKR_B_P
MIC_B_N
SPKR_B_N
-ADCΣΔ
- DACΣΔ
- DACΣΔ
-ADCΣΔ
Figure 10.2: Mono Codec Audio Input and Output Stages
The Mono audio codec uses a fully differential architecture in the analogue signal path, which results in low noise
sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a single
power-supply of 1.5V and uses a minimum of external components.
10.2.2 Stereo Codec Set-up
The configuration and control of the ADC is through VM functions described in appropriate BlueLab Multimedia
documentation. This section is an overview of the parameters that can be set up using the VM functions.
The Kalimba DSP can communicate its codec requirements to the MCU, and therefore also to the VM, by exchange
of messages. The messages used between the Kalimba DSP and the embedded MCU are based on interrupts:
■
1 interrupt between the MCU and Kalimba DSP
■
1 interrupt between the Kalimba DSP and the MCU
Message content is transmitted using shared memory. There are VM and DSP library functions to send and receive
messages; refer to BlueLab Multimedia documentation for further details.
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10.2.3 ADC
The ADC consists of:
■
Two second-order Sigma Delta converters allowing two separate channels that are identical in functionality,
as shown in Figure 10.2.
■
Two gain stages for each channel, one of which is an analogue gain stage and the other is a digital gain
stage.
10.2.4 ADC Sample Rate Selection
Each ADC supports the following sample rates:
■
8kHz
■
11.025kHz
■
16kHz
■
22.05kHz
■
24kHz
■
32kHz
■
44.1kHz
10.2.5 ADC Digital Gain
The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain
settings summarised in Table 10.2. There is also a high resolution digital gain mode that allows the gain to be
changed in 1/32dB steps. Contact CSR for more information.
Gain Selection Value ADC Digital Gain Setting (dB)
0 0
13.5
2 6
39.5
412
515.5
618
721.5
8-24
9-20.5
10 -18
11 -14.5
12 -12
13 -8.5
14 -6
15 -2.5
Table 10.2: ADC Digital Gain Rate Selection
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10.2.6 ADC Analogue Gain
Figure 10.3 shows the equivalent block diagram for the ADC analogue amplifier. It is a two-stage amplifier:
■
The first stage amplifier has a selectable gain of either bypass for line input mode or gain of 24dB gain for
the microphone mode.
■
The second stage has a programmable gain with seven individual 3dB steps. By combining the 24dB gain
selection of the microphone input with the seven individual 3dB gain steps, the overall range of the analogue
amplifier is approximately -3dB to 42dB in 3dB st eps. All gain control of the ADC is controlled by the BlueVox
DSP.
Bypass or 24dB gain -3dB to 18dB gain
Gain 0:7
Line Mode / Mic Mode
P
N
P
N
Switches shown for Line Mod
e
Microphone Mode input impedance = 6k Ω
Line mode in
p
ut im
p
edance = 6k to 30kΩΩ
Figure 10.3: ADC Analogue Amplifier Block Diagram
10.2.7 DAC
The DAC consists of:
■
Two second-order Sigma Delta converters allowing two separate channels that are identical in functionality,
as shown in Figure 10.2.
■
Two gain stages for each channel, one of which is an analogue gain stage and the other is a digital gain
stage.
10.2.8 DAC Sample Rate Selection
Each DAC supports the following samples rates:
■
8kHz
■
11.025kHz
■
12kHz
■
16kHz
■
22.050kHz
■
24kHz
■
32kHz
■
44.1kHz
■
48kHz
10.2.9 DAC Digital Gain
The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain settings,
summarised in Table 10.3. There is also a high resolution digital gain mode that allows the gain to be changed in
1/32dB steps. Contact CSR for more information.
The overall gain control of the DAC is controlled by the BlueVox DSP. Its setting is a combined function of the digital
and analogue amplifier settings.
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Digital Gain Selection Value DAC Digital Gain Setting (dB)
0 0
13.5
2 6
39.5
412
515.5
618
721.5
8-24
9 -20.5
10 -18
11 -14.5
12 -12
13 -8.5
14 -6
15 -2.5
Table 10.3: DAC Digital Gain Rate Selection
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10.2.10 DAC Analogue Gain
The DAC analogue gain stage consists of eight gain selection values that represent seven 3dB steps, as shown in
Table 10.4.
The overall gain control of the DAC is controlled by the BlueVox DSP. Its setting is a combined function of the digital
and analogue amplifier settings.
Analogue Gain Selection Value DAC Analogue Gain Setting (dB)
7 3
6 0
5-3
4-6
3-9
2-12
1-15
0-18
Table 10.4: DAC Analogue Gain Rate Selection
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10.2.11 Microphone Input
The microphone for each channel should be biased as shown in Figure 10.4. The microphone bias, MIC_BIAS,
derives its power from the BAT_P and requires a 1µF capacitor on its output.
R2
C2
R1
C1
Microphone Bias
C3
C4
MIC_A_P
MIC_A_N
MIC1
+
Input
Amplifier
Figure 10.4: Microphone Biasing (Single Channel Shown)
The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS
maintains regulation within the limits 0.200 - 1.230mA. If the microphone sits below these limits, then the microphone
output must be pre-loaded with a large value resistor to ground.
The audio input is intended for use in the range from 1μA @ 94dB SPL to about 10μA @ 94dB SPL. With biasing
resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV.
The input impedance at MIC_A_N, MIC_A_P, MIC_B_N and MIC_B_P is typically 6.0kΩ.
C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone.
R1 sets the microphone load impedance and is normally in a range of 1 - 2kΩ.
R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Values should be
selected as required. R2 may be connected to a convenient supply, in which case the bias network is permanently
enabled, or to the MIC_BIAS output (which is ground referenced and provides good rejection of the supply), which
may be configured to provide bias only when the microphone is required.
The microphone bias provides a 4-bit programmable output voltage, shown in Table 10.5, with a 4-bit programmable
output current, shown in Table 10.6.
The characteristics of the microphone bias include:
■
Power supply:
■
BlueCore5-Multimedia Plug-n-Go Automotive microphone supply is BAT_P
■
Minimum input voltage = Output voltage + drop-out voltage
■
Maximum input voltage is 4.4V
■
Typically the microphone bias is at the same level as VDD_AUDIO (1.5V)
■
Drop-out voltage:
■
300mV minimum
■
Guaranteed for configuration of voltage or current output shown in Table 10.5 and Table 10.6
■
Output voltage:
■
4-bit programmable between 1.7 - 3.6V
■
Tolerance 90 - 110%
■
Output current:
■
4-bit programmable between 200µA – 1.230mA
■
Maximum current guaranteed to be >1mA
■
Load capacitance:
■
Unconditionally stable for 1µF ±20% and 2.2µF ±20% pure C
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Output Step VOL_SET[3:0] Min Typ Max Units
0
0000
-1.71 - V
1
0001
-1.76 - V
2
0010
-1.82 - V
3
0011
-1.87 - V
4
0100
-1.95 - V
5
0101
-2.02 - V
6
0110
-2.10 - V
7
0111
-2.18 - V
8
1000
-2.32 - V
9
1001
-2.43 - V
10
1010
-2.56 - V
11
1011
-2.69 - V
12
1100
-2.90 - V
13
1101
-3.08 - V
14
1110
-3.33 - V
15
1111
-3.57 - V
Table 10.5: Voltage Output Steps
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Output Step CUR_SET[3:0] Typ Units
0
0000
0.200 mA
1
0001
0.280 mA
2
0010
0.340 mA
3
0011
0.420 mA
4
0100
0.480 mA
5
0101
0.530 mA
6
0110
0.610 mA
7
0111
0.670 mA
8
1000
0.750 mA
9
1001
0.810 mA
10
1010
0.860 mA
11
1011
0.950 mA
12
1100
1.000 mA
13
1101
1.090 mA
14
1110
1.140 mA
15
1111
1.230 mA
Table 10.6: Current Output Steps
Note:
For BAT_P, the PSRR at 100Hz - 22kHz, with >300mV supply headroom, decoupling capacitor of 1.1μF, is
typically 58.9dB and worst case 53.4dB.
For VDD_AUDIO, the PSRR at 100Hz - 22kHz, decoupling capacitor of 1.1μF, is typically 88dB and worst case
60dB.
10.2.12 Line Input
If the input analogue gain is set to less than 24dB, BlueCore5-Multimedia Plug-n-Go Automotive automatically
selects line input mode. In line input mode the first stage of the amplifier is automatically disabled, providing additional
power saving. In line input mode the input impedance varies from 6kΩ - 30kΩ, depending on the volume setting.
Figure 10.5 and Figure 10.6 show two circuits for line input operation and show connections for either differential or
single-ended inputs.
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C1
C2
MIC_A_P
MIC_A_N
Figure 10.5: Differential Input (Single Channel Shown)
C1
C2
MIC_A_P
MIC_A_N
Figure 10.6: Single-Ended Input (Single Channel Shown)
10.2.13 Output Stage
The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling
frequency to bit stream, which is fed into the analogue output circuitry.
The output stage circuit comprises a DAC with gain setting and class AB output stage amplifier. The output is
available as a differential signal between SPKR_A_N and SPKR_A_P for the left channel, as shown in Figure
10.7, and between SPKR_B_N and SPKR_B_P for the right channel.
The output stage is capable of driving a speaker directly when its impedance is at least 8Ω and an external regulator
is used, but this will be at a reduced output swing.
SPKR_A_P
SPKR_A_N
Figure 10.7: Speaker Output (Single Channel Shown)
The analogue gain of the output stage is controlled by a 3-bit programmable resistive divider, which sets the gain in
steps of approximately 3dB.
10.2.14 Mono Operation
Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono
channel for audio in and audio out. In mono operation the right channel is auxilliary mono channel that may be used
in dual mono channel operation.
With single mono, the power consumption can be reduced by disabling the other channel.
Important Note:
For mono operation this data sheet uses the left channel for standard mono operation for audio input and output
and with respect to software and any registers, channel 0 or channel A represents the standard mono channel
for audio input and output. In mono operation the second channel which is the right channel, channel 1 or channel
B could be used as a second mono channel if required and this channel is referred to as the auxilliary mono
channel for audio input and output.
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10.2.15 Side Tone
In some applications it is necessary to implement side tone. This involves feeding an attenuated version of the
microphone signal to the earpiece. The BlueCore5-Multimedia Plug-n-Go Automotive codec contains side tone
circuitry to do this. The side tone hardware is configured through the the following PS Keys:
■
PSKEY_SIDE_TONE_ENABLE
■
PSKEY_SIDE_TONE_GAIN
■
PSKEY_SIDE_TONE_AFTER_ADC
■
PSKEY_SIDE_TONE_AFTER_DAC
10.2.16 Integrated Digital Filter
BlueCore5-Multimedia Plug-n-Go Automotive has a programmable digital filter integrated into the ADC channel of
the codec. The filter is a two stage, second order IIR and can be used for functions such as custom wind noise
rejection. The filter also has optional DC blocking.
The filter has 10 configuration words used as follows:
■
1 for gain value
■
8 for coefficient values
■
1 for enabling and disabling the DC blocking
The gain and coefficients are all 12-bit 2's complement signed integer with the format
XX.XXXXXXXXXX
Note:
The position of the binary point is between bit 10 and bit 9, where bit 11 is the most significant bit.
For example:
01.1111111111
=most positive number, close to
+2
01.0000000000
=
1
00.0000000000
=
0
11.0000000000
=
-1
10.0000000000
=
-2
, most negative number
The equation for the IIR filter is shown in Equation 10.1. When the DC blocking is enabled the equation is shown in
Equation 10.2.
The filter can be configured, enabled and disabled from the VM via the
CodecSetIIRFilterA
and
CodecSetIIRFilterB
traps
2
. The configuration function takes 10 variables in the order shown below:
0
:Gain
1
:b
01
2
:b
02
3
:a
01
2
Requires firmware support
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4
:a
02
5
:b
11
6
:b
12
7
:a
11
8
:a
12
9
: DC Block (1 = enable, 0 = disable)
Filter, H(z) = Gain ×
(1+b
01 z−1 +b
02 z−2 )
(1+a
01 z−1 +a
02 z−2 )
×
(1+b
11 z−1 +b
12 z−2 )
(1+a
11 z−1 +a
12 z−2 )
Equation 10.1: IIR Filter Transfer Function, H(z)
Filter with DC Blocking, H
DC
(z) = H(z) × (1−z
−1
)
Equation 10.2: IIR Filter plus DC Blocking Transfer Function, H
DC
(z)
10.3 PCM Interface
The audio PCM interface supports continuous transmission and reception of PCM encoded audio data over
Bluetooth.
PCM is a standard method used to digitise audio (particularly voice) for transmission over digital communication
channels. Through its PCM interface, BlueCore5-Multimedia Plug-n-Go Automotive has hardware support for
continual transmission and reception of PCM data, so reducing processor overhead. BlueCore5-Multimedia Plug-
n-Go Automotive offers a bi-directional digital audio interface that routes directly into the baseband layer of the on-
chip firmware. It does not pass through the HCI protocol layer.
Hardware on BlueCore5-Multimedia Plug-n-Go Automotive allows the data to be sent to and received from a SCO
connection.
Up to three SCO connections can be supported by the PCM interface at any one time.
BlueCore5-Multimedia Plug-n-Go Automotive can operate as the PCM interface master generating PCM_SYNC and
PCM_CLK or as a PCM interface slave accepting externally generated PCM_SYNC and PCM_CLK. BlueCore5-
Multimedia Plug-n-Go Automotive is compatible with various clock formats, including Long Frame Sync, Short Frame
Sync and GCI timing environments.
It supports 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats, and can receive and transmit on
any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are enabled by
setting the PS Key PS KEY_PCM_CONFIG32 (0x1b3).
10.4 Digital Audio Interface (I²S)
The digital audio interface supports the industry standard formats for I
2
S, left-justified or right-justified. The interface
shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table
10.7 lists these alternative functions. Figure 10.8 shows the timing diagram.
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PCM Interface I
2
S Interface
PCM_OUT SD_OUT
PCM_IN SD_IN
PCM_SYNC WS
PCM_CLK SCK
Table 10.7: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
Table 10.8 describes the values for the PS Key (PSKEY_DIGITAL_AUDIO_CONFIG) that is used to set-up the digital
audio interface. For example, to configure an I
2
S interface with 16-bit SD data set PSKEY_DIGITAL_CONFIG to
0x0406.
Bit Mask Name Description
D[0] 0x0001 CONFIG_JUSTIFY_FORMAT 0 for left justified, 1 for right justified.
D[1] 0x0002 CONFIG_LEFT_JUSTIFY_DELAY
For left justified formats: 0 is MSB of SD data
occurs in the first SCLK period following WS
transition. 1 is MSB of SD data occurs in the
second SCLK period.
D[2] 0x0004 CONFIG_CHANNEL_POLARITY For 0, SD data is left channel when WS is
high. For 1 SD data is right channel.
D[3] 0x0008 CONFIG_AUDIO_ATTEN_EN
For 0, 17-bit SD data is rounded down to
16bits. For 1, the audio attenuation defined
in CONFIG_AUDIO_ATTEN is applied over
24bits with saturated rounding. Requires
CONFIG_16_BIT_CROP_EN to be 0.
D[7:4] 0x00F0 CONFIG_AUDIO_ATTEN Attenuation in 6dB steps.
D[9:8] 0x0300 CONFIG_JUSTIFY_RESOLUTION
Resolution of data on SD_IN, 00=16bit,
01=20bit, 10=24bit, 11=Reserved. This is
required for right justified format and with left
justified LSB first.
D[10] 0x0400 CONFIG_16_BIT_CROP_EN
For 0, 17-bit SD_IN data is rounded down to
16bits. For 1 only the most significant 16bits
of data are received.
Table 10.8: PSKEY_DIGITAL_AUDIO_CONFIG
Audio Interface
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WS
SCK
SD_IN/OUT
WS
SCK
SD_IN/OUT
WS
SCK
SD_IN/OUT
LSB
MSB LSB MSB LSB
MSB LSB MSB LSB
Left-Justified Mode
Right-Justified Mode
Left Channel Right Channel
Right ChannelLeft Channel
Left Channel Right Channel
MSB LSB MSB
I
2
S Mode
Figure 10.8: Digital Audio Interface Modes
The internal representation of audio samples within BlueCore5-Multimedia Plug-n-Go Automotive is 16-bit and data
on SD_OUT is limited to 16-bit per channel.
Audio Interface
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Symbol Parameter Min Typ Max Unit
-SCK Frequency - - 6.2 MHz
-WS Frequency - - 96 kHz
t
ch
SCK high time 80 - - ns
t
cl
SCK low time 80 - - ns
t
opd
SCK to SD_OUT delay - - 20 ns
t
ssu
WS to SCK set-up time 20 - - ns
t
sh
WS to SCK hold time 20 - - ns
t
isu
SD_IN to SCK set-up time 20 - - ns
t
ih
SD_IN to SCK hold time 20 - - ns
Table 10.9: Digital Audio Interface Slave Timing
SD_OUT
SD_IN
t
t
t
t
t
t
WS(Input)
SCK(Input)
ch
opd
ih
shssu
cl
isu
t
Figure 10.9: Digital Audio Interface Slave Timing
Audio Interface
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Symbol Parameter Min Typ Max Unit
-SCK Frequency - - 6.2 MHz
-WS Frequency - - 96 kHz
t
opd
SCK to SD_OUT delay - - 20 ns
t
spd
SCK to WS delay - - 20 ns
t
isu
SD_IN to SCK set-up time 20 - - ns
t
ih
SD_IN to SCK hold time 10 - - ns
Table 10.10: Digital Audio Interface Master Timing
WS(Output)
SCK(Output)
SD_OUT
SD_IN
t
isu
t
ih
t
opd
t
spd
Figure 10.10: Digital Audio Interface Master Timing
Audio Interface
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11 Power Control and Regulation
11.1 Power Control and Regulation
BlueCore5-Multimedia Plug-n-Go Automotive contains four regulators:
■
Two high-voltage regulators, either of which can generate a 1.8V supply rail.
■
Two low-voltage regulators, running in parallel to supply the 1.5V core supplies from a 1.8V supply rail.
Various configurations for power control and regulation with the BlueCore5-Multimedia Plug-n-Go Automotive are
available:
■
A high-voltage rail running a high-voltage regulator and the low-voltage regulators in series, as shown in
Figure 11.1.
■
BlueCore5-Multimedia Plug-n-Go Automotive powered directly from an external 1.8V supply rail, by-
passing the high-voltage regulator
■
An external 1.5V rail omitting all regulators
VDD_SMP_CORE
LX
Switch Mode
Regulator
SENSEEN
LX
Battery Charger
OUT
IN
L1
C1
Audio Low
Voltage Regulator
OUT
IN
EN
VREGIN_AUDIO
VDD_AUDIO
VREGENABLE_L
VREGIN_L
VREGIN_H
VREGOUT_H
VREGENABLE_H
VDD_RADIO
Low Voltage
Linear Regulator
OUT
SENSE
SENSE
IN
EN
VDD_ANA
High Voltage
Linear Regulator
OUT
IN
EN
SENSE
1.8V Supply Rail
BAT_P
BAT_N
VDD_CHG
1.8V Supply Rail
Figure 11.1: Voltage Regulator Configuration
11.2 Power Sequencing
The 1.5V supply rails are VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO. CSR recommends
that these supply rails are all powered at the same time.
The digital I/O supply rails are VDD_PADS, VDD_PIO and VDD_USB.
Power Control and Regulation
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The sequence of powering the 1.5V supply rails relative to the digital I/O supply rails is not important. If the digital I/
O supply rails are powered before the 1.5V supply rails, all digital I/Os will have a weak pull-down irrespective of the
reset state.
VDD_ANA, VDD_AUDIO, VDD_LO and VDD_RADIO can connect directly to a 1.5V supply.
A simple RC filter is recommended for VDD_CORE to reduce transients fed back onto the power supply rails.
The digital I/O supply rails are connected together or independently to an appropriate voltage rail. Decoupling of the
digital I/O supply rails is recommended.
11.3 External Voltage Source
If any of the supply rails for BlueCore5-Multimedia Plug-n-Go Automotive are supplied from an external voltage
source, rather than one of the internal voltage regulators, then it is recommended that VDD_AUDIO, VDD_LO and
VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. Also avoid single tone frequencies.
The transient response of any external regulator used should match or be better than the internal regulator available
on BlueCore5-Multimedia Plug-n-Go Automotive. (Refer to regulator characteristics in Section 14.) It is essential
that the power rail recovers quickly at the start of a packet, where the power consumption jumps to high levels.
11.4 Switch-mode Regulator
The on-chip switch-mode regulator is available to power a 1.8V supply rail.
An external LC filter circuit of a low-resistance series inductor, L1 (22µH), followed by a low ESR shunt capacitor,
C1 (4.7µF), is required between the LX terminal and the 1.8V supply rail. A connection between the 1.8V supply rail
and the VDD_SMP_CORE pin is required.
A decoupling capacitor (2.2µF) is required between BAT_P and BAT_N.
To maintain high-efficiency power conversion and low supply ripple, it is essential that the series resistance of tracks
between the BAT_P and BAT_N terminals, the filter and decoupling components, and the external voltage source
are minimised.
The switch-mode regulator is enabled by either:
■
VREGENABLE_H pin
■
BlueCore5-Multimedia Plug-n-Go Automotive device firmware
■
BlueCore5-Multimedia Plug-n-Go Automotive battery charger
The switch-mode regulator is switched into a low-power pulse skipping mode when the device is sent into deep-
sleep mode, or in reset.
When the switch-mode regulator is not required the terminals BAT_P and LX must be grounded or left unconnected.
11.5 High-voltage Linear Regulator
The high-voltage linear regulator is available to power a 1.8V supply rail.
A smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω resistor to ground, should be connected to the
output of the high-voltage linear regulator, VREGOUT_H. Alternatively use a 2.2µF capacitor with an ESR of at least
2Ω.
The high-voltage linear regulator is enabled by either:
■
VREGENABLE_H pin
■
BlueCore5-Multimedia Plug-n-Go Automotive device firmware
■
BlueCore5-Multimedia Plug-n-Go Automotive battery charger
The regulator is switched into a low-power mode when the device is in deep-sleep mode, or in reset.
When the high-voltage linear regulator is not used the terminals VREGIN_H and VREGOUT_H must be left
unconnected, or tied to ground.
11.6 Low-voltage Linear Regulator
The low-voltage linear regulator is available to power a 1.5V supply rail. Its output is connected internally to
VDD_ANA, and can be connected externally to the other 1.5V power inputs.
Power Control and Regulation
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If the low-voltage linear regulator is used a smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω resistor
to ground, should be connected to the output of the low-voltage linear regulator, VDD_ANA. Alternatively use a 2.2µF
capacitor with an ESR of at least 2Ω.
The low-voltage linear regulator is enabled by either:
■
VREGENABLE_L pin
■
BlueCore5-Multimedia Plug-n-Go Automotive device firmware
■
BlueCore5-Multimedia Plug-n-Go Automotive battery charger
The low-voltage linear regulator is switched into a low power mode when the device is in deep-sleep mode, or in
reset.
When the low-voltage linear regulator is not used the terminal VREGIN_L must be left unconnected, or tied to
VDD_ANA.
11.7 Low-voltage Audio Linear Regulator
The low-voltage audio linear regulator is available to power a 1.5V audio supply rail. Its output is connected internally
to VDD_AUDIO, and can be connected externally to the other 1.5V audio power inputs.
If the low-voltage audio linear regulator is used a smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω
resistor to ground, should be connected to the output of the low-voltage linear regulator, VDD_AUDIO. Alternatively
use a 2.2µF capacitor with an ESR of at least 2Ω.
The low-voltage audio linear regulator is enabled by either:
■
VREGENABLE_L pin
■
BlueCore5-Multimedia Plug-n-Go Automotive device firmware
■
BlueCore5-Multimedia Plug-n-Go Automotive battery charger
The low-voltage audio linear regulator is switched into a low-power mode when no audio cells are enabled, or when
the chip is in reset.
When this regulator is not used the terminal VREGIN_AUDIO must be left unconnected or tied to VDD_AUDIO.
11.8 Voltage Regulator Enable Pins
The voltage regulator enable pins, VREGENABLE_H and VREGENABLE_L, are used to enable the BlueCore5-
Multimedia Plug-n-Go Automotive device if the on-chip regulators are being used. Table 11.1 shows the enable pin
responsible for each voltage regulator.
Enable Pin Regulator
VREGENABLE_H High-voltage Linear Regulator and Switch-mode Regulator
VREGENABLE_L Low-voltage Linear Regulator and Low-voltage Audio Linear Regulator
Table 11.1: BlueCore5-Multimedia Plug-n-Go Automotive Voltage Regulator Enable Pins
The voltage regulator enable pins are active high, with weak pull-downs.
BlueCore5-Multimedia Plug-n-Go Automotive boots-up when the voltage regulator enable pins are pulled high,
enabling the appropriate regulators. The firmware then latches the regulators on and the voltage regulator enable
pins may then be released.
The status of the VREGENABLE_H pin is available to firmware through an internal connection. VREGENABLE_H
also works as an input line.
11.9 Battery Charger
The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer
batteries only. It shares a connection to the battery terminal, BAT_P, with the switch-mode regulator. However it may
be used in conjunction with either of the high-voltage regulators on the device.
The constant current level can be varied to allow charging of different capacity batteries.
The charger enters various states of operation as it charges a battery, as listed below. A full operational description
is in
BlueCore5 Charger Description and Calibration Application Note
:
Power Control and Regulation
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■
Off : entered when charger disconnected.
■
Trickle charge: entered when battery is below 2.9V. The battery is charged at a nominal 4.5mA. This mode
is for the safe charge of deeply discharged cells.
■
Fast charge constant current: entered when battery is above 2.9V. The charger enters the main fast charge
mode. This mode charges the battery at the selected constant current, I
chgset
.
■
Fast charge constant voltage: entered when battery has reached a selected voltage, V
float
. The charger
switches mode to maintain the cell voltage at the V
float
voltage by adjusting the charge current.
■
Standby: this is the state when the battery is fully charged and no charging takes place. The battery voltage
is continuously monitored and if it drops by more than 150mV below the V
float
voltage the charger will re-
enter the fast charge constant current mode to keep the battery fully charged.
When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger
operates and an LED connected to the terminal LED[0] illuminates. By default, until the firmware is running, the LED
pulses at a low-duty cycle to minimise current consumption.
The battery charger circuitry auto-detects the presence of a power source, allowing the firmware to detect, using an
internal status bit, when the charger is powered. Therefore when the charger supply is not connected to VDD_CHG,
the terminal must be left open-circuit. The VDD_CHG pin when not connected must be allowed to float and not pulled
to a power rail. When the battery charger is not enabled this pin may float to a low undefined voltage. Any DC
connection increases current consumption of the device. Capacitive components may be connected such as diodes,
FETs and ESD protection.
The battery charger is designed to operate with a permanently connected battery. If the application enables the
charger input to be connected while the battery is disconnected, then the BAT_P pin voltage may become unstable.
This in turn may cause damage to the internal switch-mode regulator. Connecting a 470µF capacitor to BAT_P limits
these oscillations so preventing damage.
Power Control and Regulation
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11.10 LED Drivers
BlueCore5-Multimedia Plug-n-Go Automotive includes two pads dedicated to driving LED indicators. Both terminals
may be controlled by firmware, while LED[0] can also be set by the battery charger.
The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series
with a current limiting resistor.
It is recommended that the LED pad (LED[0] or LED[1] pins) are operated with a pad voltage below 0.5V. In this
case the pad can be thought of as a resistor, R
ON
. The resistance together with the external series resistor sets the
current, I
LED
, in the LED. The current is also dependent on the external voltage, VDD, shown in Figure 11.2.
LED Forward Voltage, V
F
Pad Voltage, V
PAD
; R
ON
= 20Ω
R
LED
LED0 or LED1
Resistor Voltage Drop, V
R
VDD
I
LED
Figure 11.2: LED Equivalent Circuit
From Figure 11.2 it is possible to derive Equation 11.1 to calculate I
LED
or if a known value of current is required
through the LED, to give a specific luminous intensity, then the value of R
LED
could be calculated.
I
LED
=
VDD − VF
RLED +R
ON
Equation 11.1: LED Current
For LED[0] or LED[1] pad to act as resistance, the external series resistor, R
LED
, needs to be such that the voltage
drop across it, V
R
, keeps V
PAD
below 0.5V. Therefore Equation 11.2 also applies.
VDD = V
F
+V
R
+V
PAD
Equation 11.2: LED PAD Voltage
Note:
The LED current will add to the overall application current, so conservative selection of the LEDs will preserve
power consumption.
Power Control and Regulation
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11.11 Reset (RST#)
BlueCore5-Multimedia Plug-n-Go Automotive can be reset from several sources:
■
RST# pin
■
Power-on reset
■
UART break character
■
Software configured watchdog timer
The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset
is performed between 1.5 and 4.0ms following RST# being active. CSR recommends that RST# be applied for a
period greater than 5ms.
The power-on reset typically occurs when the VDD_CORE supply falls below 1.26V and is released when
VDD_CORE rises above typically 1.31V. At reset the digital I/O pins are set to inputs for bi-directional pins and
outputs are tri-state. Following a reset, BlueCore5-Multimedia Plug-n-Go Automotive assumes the maximum
XTAL_IN frequency, which ensures that the internal clocks run at a safe (low) frequency until BlueCore5-Multimedia
Plug-n-Go Automotive is configured for the actual XTAL_IN frequency. If no clock is present a t X TAL_IN , t he osci l l a tor
in BlueCore5-Multimedia Plug-n-Go Automotive free runs, again at a safe frequency.
11.11.1 Digital Pin States on Reset
Table 11.2 shows the pin states of BlueCore5-Multimedia Plug-n-Go Automotive on reset. Pull-up (PU) and pull-
down (PD) default to weak values unless specified otherwise.
Pin Name / Group I/O Type No Core Voltage
Reset Full Chip Reset
USB_DP Digital bi-directional N/a N/a
USB_DN Digital bi-directional N/a N/a
UART_RX Digital input with PD PD PD
UART_CTS Digital input with PD PD PD
UART_TX Digital bi-directional with PU PU PU
UART_RTS Digital bi-directional with PU PU PU
SPI_MOSI Digital input with PD PD PD
SPI_CLK Digital input with PD PD PD
SPI_CS# Digital input with PU PU PU
SPI_MISO Digital tri-state output with PD PD PD
PCM_IN Digital input with PD PD PD
Power Control and Regulation
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Pin Name / Group I/O Type No Core Voltage
Reset Full Chip Reset
PCM_CLK Digital bi-directional with PD PD PD
PCM_SYNC Digital bi-directional with PD PD PD
PCM_OUT Digital tri-state output with PD PD PD
RST# Digital input with PU PU PU
TEST_EN Digital input with PD PD PD
PIO[15:0] Digital bi-directional with PU/
PD PD PD
Table 11.2: Pin States on Reset
11.11.2 Status after Reset
The chip status after a reset is as follows:
■
Warm reset: data rate and RAM data remain available
■
Cold reset: data rate and RAM data not available
Power Control and Regulation
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12 Product Reliability Tests for BlueCore5-Multimedia Plug-n-
Go Automotive
12.1 AEC-Q100
The reliability tests in this section follow the tests outlined in the AEC-Q100 and were performed on BlueCore5-
Multimedia Plug-n-Go Automotive in LFBGA 105-ball 10 x 10 x 1.6mm 0.8mm pitch I/O (lead-free solder balls).
Samples are electrically tested at ambient temperature.
This package qualification will (where moisture sensitivity preconditioning is required) use IPC/Jedec MSL3, i.e., the
finished product is allowed a maximum exposure to a 30°C/60% RH environment for 168 hours before mounting.
As part of CSR's automotive test program, customers will have access to the initial device reliability test report. They
will also have access to a quarterly reliability test report update for automotive parts.
12.2 Automotive Die Test for BC57G687C
Test Test Conditions Specification Sample Size
ESD Human Body Model JEDEC 21
Latch-up Ambient and T
max
JEDEC 12
Early Life 125°C VDD
max
48 hours 3 x 800
Hot Life Test 125°C VDD
max
1000 hours 3 x 800
12.3 Automotive Package Test for BC57G687C
Test Test Conditions Specification Sample Size
Moisture Sensitivity
Preconditioning
(125°C 24 hours)
30°C / 60% RH
192 hours
3 x reflow 799
Temperature Cycling -65ºC to 150ºC 500 cycles 3 x 77
Highly Accelerated
Stress Test (unbiased) 130ºC / 85% RH (unbiased) 96 hours 3 x 77
Highly Accelerated
Stress Test (biased)
130ºC / 85% RH
VDD
MAX
96 hours 3 x 77
Hot Storage 150ºC 1000 hours 77
Package Drop Test 1500G 0.5 meters per second 30 drops 60
Mounted Part
Temperature Cycling -40ºC to 125ºC 1000 cycles 30
Product Reliability Tests for BlueCore5-Multimedia Plug-n-Go Automotive
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13 Example Application Schematic
Figure 13.1: BlueCore5-Multimedia Plug-n-Go Automotive Automotive Example Application Schematic
Example Application Schematic
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14 Electrical Characteristics
14.1 Absolute Maximum Ratings
Rating Min Max Unit
Storage Temperature -40 105 °C
Core Supply
Voltage
VDD_ANA, VDD_AUDIO, VDD_CORE,
VDD_LO and VDD_RADIO -0.4 1.65 V
I/O Voltage
VDD_PADS, VDD_PIO and VDD_USB -0.4 3.6 V
VDD_MEM -0.4 1.95 V
Supply Voltage
VREGIN_L and VREGIN_AUDIO -0.4 2.7 V
VREGIN_H, VREGENABLE_H and
VREGENABLE_L -0.4 4.9 V
BAT_P, LED[0] and LED[1] -0.4 4.4 V
VDD_CHG -0.4 6.5 V
RF_BIAS -0.4 1.65 V
Other Terminal Voltages VSS-0.4 VDD+0.4 V
14.2 Recommended Operating Conditions
Operating Condition Min Typ Max Unit
Operating Temperature Range
(a)
-40 20 85 °C
Core Supply
Voltage
VDD_ANA,
VDD_AUDIO,
VDD_CORE, VDD_LO
and VDD_RADIO
1.42 -1.57 V
I/O Supply
Voltage
VDD_PADS, VDD_PIO
and VDD_USB 1.7 3.3 3.6 V
VDD_MEM 1.70 1.8 1.95 V
RF_BIAS 1.42 -1.57 V
(a)
For radio performance over temperature refer to BlueCore5 Multimedia Plug-n-Go Automotive Performance Specification.
Electrical Characteristics
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14.3 Input/Output Terminal Characteristics
Note:
For all I/O Terminal Characteristics:
■
VDD_ANA, VDD_AUDIO, VDD_CORE, VDD_LO and VDD_RADIO at 1.5V unless shown otherwise.
■
VDD_PADS, VDD_PIO and VDD_USB at 3.3V unless shown otherwise.
■
Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
14.3.1 High-voltage Linear Regulator
Normal Operation Min Typ Max Unit
Input voltage 2.7 -5.5
(a)
V
Output voltage (I
load
= 100mA / VREGIN_H = 3.0V) 1.70 1.80 1.95 V
Temperature coefficient -300 0300 ppm/°C
Output Noise
(b)
(c)
- - 1 mV rms
Load regulation (100µA < I
load
< 200mA ), ΔV
out
- - 5 mV
Settling time
(b)
(d)
- - 50 μs
Maximum output current 200 - - mA
Minimum load current 5 - - µA
Drop-out voltage ( I
load
= 200mA) - - 900 mV
Quiescent current (excluding load, I
load
< 1mA) 30 50 60 μA
Low-power Mode
(e)
Quiescent current (excluding load, I
load
< 100μA) 11 15 21 μA
(a)
Short-term operation up to 5.5V is permissible without damage and without the output voltage rising sufficiently to damage the rest of the
device, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.9V. 5.5V can only be tolerated
for short periods.
(b)
Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(c)
Frequency range 100Hz - 100kHz.
(d)
10mA - 200mA pulsed load.
(e)
The regulator is in low power mode when the chip is in deep sleep mode, or in reset.
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14.3.2 Low-voltage Linear Regulator
Normal Operation Min Typ Max Unit
Input voltage 1.70 1.80 1.95 V
Output voltage (I
load
= 70mA / VREGIN_L = 1.7V) 1.42 1.50 1.57 V
Temperature coefficient -300 0300 ppm/°C
Output noise
(a)
(b)
- - 1 mV rms
Load regulation (100µA < I
load
< 90mA ), ΔV
out
- - 5 mV
Load regulation (100µA < I
load
< 115mA ), ΔV
out
- - 25 mV
Settling time
(a)
(c)
- - 50 μs
Maximum output current 115 - - mA
Minimum load current 5 - 100 µA
Drop-out voltage ( I
load
= 115mA) - - 300 mV
Quiescent current (excluding load, I
load
< 1mA) 50 90 150 μA
Low-power Mode
(d)
Quiescent current (excluding load, I
load
< 100μA) 5 8 15 μA
(a)
Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(b)
Frequency range 100Hz to 100kHz.
(c)
1mA to 115mA pulsed load.
(d)
The regulator is in low power mode when the chip is in deep sleep mode, or in reset.
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14.3.3 Low-voltage Linear Audio Regulator
Normal Operation Min Typ Max Unit
Input voltage 1.70 1.80 1.95 V
Output voltage (I
load
= 70mA / VREGIN_AUDIO = 1.7V) 1.42 1.50 1.57 V
Temperature coefficient -300 0300 ppm/°C
Output noise
(a)
(b)
- - 1 mV rms
Load regulation (100µA < I
load
< 70mA ), ΔV
out
- - 5 mV
Settling time
(a)
(c)
- - 50 μs
Maximum output current 70 - - mA
Minimum load current 5 - 100 µA
Dropout voltage ( I
load
= 70mA) - - 300 mV
Quiescent current (excluding load, I
load
< 1mA) 25 30 50 μA
Low-power Mode
(d)
Quiescent current (excluding load, I
load
< 100μA) 5 8 15 μA
(a)
Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(b)
Frequency range 100Hz to 100kHz.
(c)
1mA to 70mA pulsed load.
(d)
The regulator is in low power mode when the chip is in deep sleep mode, or in reset.
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14.3.4 Switch-mode Regulator
Switch-mode Regulator Min Typ Max Unit
Input voltage 2.5 -4.4 V
Output voltage (I
load
= 70mA) 1.70 1.80 1.90 V
Temperature coefficient -250 -250 ppm/°C
Normal Operation
Output ripple - - 10 mV rms
Transient settling time
(a)
- - 50 μs
Maximum load current 200 - - mA
Conversion efficiency (I
load
= 70mA) -90 - %
Switching frequency
(b)
-1.333 -MHz
Start-up current limit
(c)
30 50 80 mA
Low-power Mode
(d)
Output ripple - - 1 mV rms
Transient settling time
(e)
- - 700 μs
Maximum load current 5 - - mA
Minimum load current 1 - - µA
Conversion efficiency (I
load
= 1mA ) -80 - %
Switching frequency
(f)
50 -150 kHz
(a)
For step changes in load of 30 to 80mA and 80 to 30mA.
(b)
Locked to crystal frequency.
(c)
Current is limited on start-up to prevent excessive stored energy in the filter inductor.
(d)
The regulator is in low power mode when the chip is in deep sleep mode, or in reset.
(e)
100μA to 1mA pulsed load.
(f)
Defines minimum period between pulses. Pulses are skipped at low current loads.
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14.3.5 Reset
Power-on Reset Min Typ Max Unit
VDD_CORE falling threshold 1.13 1.25 1.30 V
VDD_CORE rising threshold 1.20 1.30 1.35 V
Hysteresis 0.05 0.10 0.15 V
14.3.6 Regulator Enable
Switching Threshold Min Typ Max Unit
VREGENABLE_H
Rising threshold 0.50 -0.95 V
Falling threshold 0.35 -0.80 V
Hysteresis 0.14 -0.28 V
VREGENABLE_L
Rising threshold 0.50 -0.95 V
Falling threshold 0.35 -0.80 V
Hysteresis 0.14 -0.28 V
Electrical Characteristics
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14.3.7 Battery Charger
Battery Charger Min Typ Max Unit
Input voltage 4.5 -6.5 V
Charging Mode (BAT_P rising to 4.2V)
Supply current
(a)
-4.5 6mA
Battery trickle charge current
(b)
(c)
Maximum setting (I-CTRL = 15) -14 -mA
Minimum setting (I-CTRL = 0) - 4 - mA
Maximum battery fast charge
current (I-CTRL = 15)
(c)
(d)
Headroom
(e)
> 0.7V 140- - mA
mAHeadroom = 0.3V -120 -
Minimum battery fast charge
current (I-CTRL = 0)
(c)
(d)
mAHeadroom > 0.7V -40 -
mAHeadroom = 0.3V -35 -
Fast charge step size
(I-CTRL = 0 to 15) Spread ±17% -6.3 -mA
Trickle charge voltage threshold -2.9 - V
Float voltage (with correct trim value set), V
FLOAT
(f)
4.17 4.2 4.23 V
Float voltage trim step size
(f)
-50 -mV
Battery charge termination current, % of fast charge current 510 20 %
Standby Mode (BAT_P falling from 4.2V)
Supply current
(a)
-1.5 2mA
Battery current --5 -μA
Battery recharge hysteresis
(g)
100 -200 mV
Shutdown Mode (VDD_CHG too low or disabled by firmware)
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Battery Charger Min Typ Max Unit
VDD_CHG under-voltage
threshold
VVDD_CHG rising -3.90 -
VVDD_CHG falling -3.70 -
VDD_CHG - BAT_P lockout
threshold
VVDD_CHG rising -0.22 -
VVDD_CHG falling -0.17 -
Supply current -1.5 2mA
Battery current -1 - 0 μA
(a)
Current into VDD_CHG - does not include current delivered to battery (I
VDD_CHG
- I
BAT_P
)
(b)
BAT_P < Float voltage
(c)
Charge current can be set in 16 equally spaced steps.
(d)
Trickle charge threshold < BAT_P < Float voltage
(e)
Where headroom = VDD_CHG - BAT_P
(f)
Float voltage can be adjusted in 15 steps. Trim setting is determined in production test and must be loaded into the battery charger by
firmware during boot-up sequence
(g)
Hysteresis of (V
FLOAT
- BAT_P) for charging to restart
Electrical Characteristics
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14.3.8 Digital Terminals
Supply Voltage Levels Min Typ Max Unit
VDD
PRE
1.4Pre-driver supply voltage 1.5 1.6 V
VDD I/O supply
voltage (post-driver)
3.0Full spec. 3.3 3.6 V
1.7Reduced spec. -3.0 V
Input Voltage Levels Min Typ Max Unit
V
IL
input logic level low -0.3 -0.25 x VDD V
V
IH
input logic level high 0.625 x VDD -VDD + 0.3 V
V
SCHMITT
Schmitt voltage 0.25 x VDD -0.625 x VDD V
Output Voltage Levels Min Typ Max Unit
V
OL
output logic level low, l
OL
= 4.0mA 0 - 0.125 V
V
OH
output logic level high, l
OH
= -4.0mA 0.75 x VDD -VDD V
Input and Tri-state Currents Min Typ Max Unit
I
i
input leakage current at V
in
= VDD or 0V -100 0100 nA
I
oz
tri-state output leakage current at V
o
= VDD or 0V -100 0100 nA
With strong pull-up -100 -40 -10 μA
With strong pull-down 10 40 100 μA
With weak pull-up -5 -1.0 -0.2 μA
With weak pull-down -0.2 1.0 5.0 μA
C
I
Input Capacitance 1.0 -5.0 pF
Resistive Strength Min Typ Max Unit
R
puw
weak pull-up strength at VDD - 0.2V 0.5 - 2 MΩ
R
pdw
weak pull-down strength at 0.2V 0.5 - 2 MΩ
R
pus
strong pull-up strength at VDD - 0.2V 10 -50 kΩ
R
pds
strong pull-down strength at 0.2V 10 -50 kΩ
Electrical Characteristics
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14.3.9 LED Driver Pads
LED Driver Pads Min Typ Max Unit
Off current - 1 2 µA
On resistance V
PAD
< 0.5V -20 33 Ω
On resistance, pad enabled
by battery charger V
PAD
< 0.5V -20 50 Ω
14.3.10 USB
Min Typ Max Unit
VDD_USB for correct USB operation 3.1 -3.6 V
Input Threshold
V
IL
input logic level low - - 0.3 x
VDD_USB V
V
IH
input logic level high 0.7 x
VDD_USB - - V
Input Leakage Current
VSS_DIG < V
IN
< VDD_USB
(a)
-1 1 5 µA
C
I
Input capacitance 2.5 -10.0 pF
Output Voltage Levels to Correctly Terminated USB Cable
V
OL
output logic level low 0.0 -0.2 V
V
OH
output logic level high 2.8 -VDD_USB V
(a)
Internal USB pull-up disabled
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14.3.11 Auxiliary ADC
Auxiliary ADC Min Typ Max Unit
Resolution - - 10 Bits
Input voltage range
(a)
0 - VDD_ANA V
Accuracy
(Guaranteed monotonic)
INL -1 - 1 LSB
DNL 0 - 1 LSB
Offset -1 - 1 LSB
Gain Error -0.8 -0.8 %
Input Bandwidth -100 -kHz
Conversion time -2.5 -µs
Sample rate
(b)
- - 700 Samples/
s
(a)
LSB size = VDD_ANA/1023
(b)
The auxilliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.
14.3.12 Clocks
Clock Source Min Typ Max Unit
Crystal Oscillator
Crystal frequency
(a)
16 26 26 MHz
Digital trim range
(b)
5.0 6.2 8.0 pF
Trim step size
(b)
-0.1 -pF
Transconductance 2.0 - - mS
Negative resistance
(c)
870 1500 2400 Ω
Electrical Characteristics
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Clock Source Min Typ Max Unit
External Clock
Input frequency
(d)
12 26 52 MHz
Clock input level
(e)
0.4 -VDD_ANA V pk-pk
Edge jitter (allowable jitter), at zero crossing - - 15 ps rms
XTAL_IN input impedance -≥10 -kΩ
XTAL_IN input capacitance -≤4 -pF
(a)
Integer multiple of 250kHz
(b)
The difference between the internal capacitance at minimum and maximum settings of the internal digital trim.
(c)
XTAL frequency = 16MHz; XTAL C
0
= 0.75pF; XTAL load capacitance = 8.5pF.
(d)
Clock input can be any frequency between 12MHz to 52MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of 14.40, 15.36, 16.2,
16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
(e)
Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA. A DC blocking
capacitor is required between the signal and XTAL_IN.
14.3.13 Stereo Codec: Analogue to Digital Converter
Analogue to Digital Converter
Parameter Conditions Min Typ Max Unit
Resolution - - - 16 Bits
Input Sample
Rate, F
sample
- 8 - 32 kHz
Signal to Noise
Ratio, SNR
(a)
f
in
= 1kHz
B/W = 20Hz→20kHz
A-Weighted
THD+N < 1%
150mV
pk-pk
input
F
sample
-8kHz 79 -dB
dB11.025kHz -77 -
dB16kHz -76 -
dB22.050kHz -76 -
dB32kHz -75 -
dB44.1kHz -75 -
Digital Gain Digital Gain Resolution = 1/32dB dB-24 -21.5
Electrical Characteristics
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Analogue to Digital Converter
Parameter Conditions Min Typ Max Unit
Analogue Gain Analogue Gain Resolution = 3dB dB- - 42
Input full scale at maximum gain (differential) - 4 - mV rms
Input full scale at minimum gain (differential) mV rms-800 -
3dB Bandwidth kHz-20 -
Microphone mode input impedance kΩ-6.0 -
THD+N (microphone input) @ 30mV rms input %- 0.04 -
(a)
Improved SNR performance can be achieved at the expense of current consumption. See Optimising BlueCore5-Multimedia ADC
Performance Application Note for details.
Electrical Characteristics
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14.3.14 Stereo Codec: Digital to Analogue Converter
Digital to Analogue Converter
Parameter Conditions Min Typ Max Unit
Resolution - - - 16 Bits
Output Sample
Rate, F
sample
- 8 - 32 kHz
Signal to Noise
Ratio, SNR
f
in
= 1kHz
B/W = 20Hz→20kHz
A-Weighted
THD+N < 0.01%
0dBFS signal
Load = 100kΩ
F
sample
8kHz -95 -dB
11.025kHz -95 -dB
16kHz -95 -dB
22.050kHz -95 -dB
32kHz -95 -dB
44.1kHz -95 -dB
48kHz -95 -dB
Digital Gain Digital Gain Resolution = 1/32dB -24 -21.5 dB
Analogue Gain Analogue Gain Resolution = 3dB 0 - -21 dB
Output voltage full-scale swing (differential)
(a)
-750 -mV rms
Allowed Load
Resistive 16(8) -OC Ω
Capacitive - - 500 pF
THD+N 100kΩ load - - 0.01 %
THD+N 16Ω load - - 0.1 %
SNR (Load = 16Ω, 0dBFS input relative to digital silence) -95 -dB
(a)
Any combination of gain (digital and / or analogue) and input signal which results in the output signal level exceeding the minimum or maximum
signal level (analogue or digital) could result in distortion.
Electrical Characteristics
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15 Power Consumption
Role Connection Audio Packet Type Description
Current
UnitVREGIN_L = 1.8V VREGIN_H = 3.2V VDD_CHG = 3.6V
16MHz 32MHz 16MHz 32MHz 16MHz 32MHz
Stand-by Host connection 0.07 0.08 0.08 0.09 0.06 0.07 mA
Page Scan Interval = 1280ms 0.46 0.47 0.51 0.51 0.31 0.32 mA
Inquiry and Page Scan Inquiry scan = 1280ms
Page scan = 1280ms 0.92 0.88 0.92 0.91 0.51 0.54 mA
Master ACL No traffic 4.2 4.2 4.2 4.3 2.6 2.7 mA
Master ACL File transfer TX 8.9 9.1 8.9 9.1 5.1 5.2 mA
Master ACL Sniff = 40ms 1.8 1.8 1.8 1.8 1.1 1.1 mA
Master ACL Sniff = 1280ms 0.21 0.20 0.23 0.21 0.15 0.14 mA
Master eSCO EV3 21 22 22 23 12 12 mA
Master eSCO EV3 Setting S1 23 23 24 24 13 13 mA
Master eSCO 2 EV3 Setting S2 22 22 22 22 12 12 mA
Master eSCO 2 EV3 Setting S3 16 17 17 17 9.0 9.1 mA
Master eSCO EV5 16 16 16 16 8.8 8.9 mA
Master SCO HV1 39 41 39 42 22 23 mA
Master SCO HV3 21 22 21 23 12 12 mA
Power Consumption
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Role Connection Audio Packet Type Description
Current
UnitVREGIN_L = 1.8V VREGIN_H = 3.2V VDD_CHG = 3.6V
16MHz 32MHz 16MHz 32MHz 16MHz 32MHz
Master SCO HV3 Sniff = 30ms 21 22 21 22 12 12 mA
Slave ACL No Traffic 15 15 15 16 8.2 8.2 mA
Slave ACL File transfer RX 20 18 20 18 10 9.44 mA
Slave ACL Sniff = 40ms 1.5 1.6 1.5 1.7 0.96 1.0 mA
Slave ACL Sniff = 1280ms 0.27 0.27 0.28 0.28 0.18 0.18 mA
Slave eSCO EV3 25 25 25 25 13 14 mA
Slave eSCO EV3 Setting S1 27 28 27 27 14 15 mA
Slave eSCO 2 EV3 Setting S2 26 26 26 26 14 15 mA
Slave eSCO 2 EV3 Setting S3 23 24 23 24 13 13 mA
Slave eSCO EV5 21 22 22 22 12 12 mA
Slave SCO HV1 39 41 40 42 22 23 mA
Slave SCO HV3 27 28 27 28 14 15 mA
Slave SCO HV3 Sniff = 30ms 21 21 22 22 11 12 mA
Power Consumption
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15.1 Kalimba DSP and CODEC Typical Average Current Consumption
DSP Average Unit
DSP core (including PM memory access)
Minimum (NOP) 0.11 mA/MIPS
Maximum (MAC) 0.32 mA/MIPS
DSP memory access (DM1 or DM2) 0.08 mA/MIPS
15.2 Typical Peak Current at 20°C
Device Activity / State Typ Unit
Peak current during cold boot 45 mA
Master TX peak current 45 mA
Master RX peak current 45 mA
Slave TX peak current 45 mA
Slave RX peak current 45 mA
15.3 Conditions
Note:
Due to Production Information status of Data Sheet results are based on BlueCore5-Multimedia Flash
■
Host interface = UART
■
Baud rate = 115200
■
Supply = 1.8V in to VREGIN_L and VREGIN_AUDIO
■
AFH switched OFF
■
No audio load
■
RF Output power = 0dBm
■
VM OFF
■
eSCO settings:
■
EV3 and EV5 = no retry
■
Setting S1 = optimised for power consumption
■
Firmware build ID = 4508
Power Consumption
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16 RoHS Statement with a List of Banned Materials
16.1 RoHS Statement
BlueCore5-Multimedia Plug-n-Go Automotive where explicitly stated in this Data Sheet meets the requirements of
Directive 2002/95/EC of the European Parliament and of the Council on the
Restriction of Hazardous Substance
(RoHS).
16.1.1 List of Banned Materials
The following banned substances are not present in BlueCore5-Multimedia Plug-n-Go Automotive which is compliant
with RoHS:
■
Cadmium
■
Lead
■
Mercury
■
Hexavalent chromium
■
PBB (Polybrominated Bi-Phenyl)
■
PBDE (Polybrominated Diphenyl Ether)
In addition, BlueCore5-Multimedia Plug-n-Go Automotive is free from the following substances:
■
PVC (Poly Vinyl Chloride)
RoHS Statement with a List of Banned Materials
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17 CSR Bluetooth Software Stack
BlueCore5-Multimedia Plug-n-Go Automotive is supplied with Bluetooth v2.1 + EDR specification compliant stack
firmware, which runs on the internal RISC MCU.
The BlueCore5-Multimedia Plug-n-Go Automotive software architecture allows Bluetooth processing and the
application program to be shared in different ways between the internal RISC MCU and an external host processor
(if any). The upper layers of the Bluetooth stack, above the HCI, can be run either on-chip or on the host processor.
17.1 BlueCore HCI Stack
HCI
LM
LC
Program Memory
48KBytes RAM Bluetooth Stack
MCU
Host I/O
Radio
Digital Audio
Host
Analogue Audio
2
Microphone or Speaker
USB
UART
PCM / SPDIF / I
2
S
Figure 17.1: BlueCore HCI Stack
Note:
Program Memory in Figure 17.1 is internal Flash.
In the implementation shown in Section 17.1 the internal MCU runs the Bluetooth stack up to the HCI. The Host
processor must provide all upper layers including the application.
17.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality
CSR supports the following Bluetooth v2.1 + EDR specification functionality:
■
Secure simple pairing
■
Sniff subrating
■
Encryption pause resume
■
Packet boundary flags
■
Encryption
■
Extended inquiry response
As well as the following mandatory functions of Bluetooth v2.0 + EDR specification:
■
AFH), including classifier
■
Faster connection: enhanced inquiry scan (immediate FHS response)
■
LMP improvements
■
Parameter ranges
And optional Bluetooth v2.0 + EDR specification functionality:
CSR Bluetooth Software Stack
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■
AFH as Master and Automatic Channel Classification
■
Fast Connect - Interlaced Inquiry and Page Scan plus RSSI during Inquiry
■
eSCO), eV3 +CRC, eV4, eV5
■
SCO handle
■
Synchronisation
The firmware was written against the Bluetooth v2.1 + EDR specification:
■
Bluetooth components:
■
Baseband (including LC)
■
LM
■
HCI
■
Standard UART HCI Transport Layers
■
All standard Bluetooth radio packet types
■
Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps
■
Operation with up to seven active slaves
3
■
Scatternet v2.5 operation
■
Maximum number of simultaneous active ACL connections: 7
■
Maximum number of simultaneous active SCO connections: 3
4
■
Operation with up to three SCO links, routed to one or more slaves
■
All standard SCO voice coding, plus transparent SCO
■
Standard operating modes: Page, Inquiry, Page-Scan and Inquiry-Scan
■
All standard pairing, authentication, link key and encryption operations
■
Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including Forced Hold
■
Dynamic control of peers' transmit power via LMP
■
Master/Slave switch
■
Broadcast
■
Channel quality driven data rate
■
All standard Bluetooth test modes
3
This is the maximum allowed by Bluetooth v2.1 + EDR specification.
4
BlueCore5-Multimedia Plug-n-Go Automotive supports all combinations of active ACL and SCO
channels for both master and slave operation, as specified by the Bluetooth v2.1 + EDR specification.
CSR Bluetooth Software Stack
CS-121449-DSP3
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17.1.2 Key Features of the HCI Stack: Extra Functionality
The firmware extends the standard Bluetooth functionality with the following features:
■
Supports BCSP, a proprietary, reliable alternative to the standard Bluetooth UART Host Transport
■
Supports H4DS, a proprietary alternative to the standard Bluetooth UART Host Transport, supporting Deep
Sleep for low-power applications
■
Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,
called BCCMD, provides:
■
Access to BlueCore5-Multimedia Plug-n-Go Automotive general-purpose PIO port
■
The negotiated effective encryption key length on established Bluetooth links
■
Access to the firmware random number generator
■
Controls to set the default and maximum transmit powers; these can help minimise interference
between overlapping, fixed-location piconets
■
Dynamic UART configuration
■
Bluetooth radio transmitter enable/disable. A simple command connects to a dedicated hardware
switch that determines whether the radio can transmit.
■
The firmware can read the voltage on a pair of BlueCore5-Multimedia Plug-n-Go Automotive external pins.
This is normally used to build a battery monitor
■
A block of BCCMD commands provides access to the BlueCore5-Multimedia Plug-n-Go Automotive
persistent store configuration database . The database sets the BlueCore5-Multimedia Plug-n-Go
Automotive Bluetooth address, Class of Device, Bluetooth radio (transmit class) configuration, SCO routing,
LM, etc.
■
A UART break condition can be used in three ways:
■
Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
■
Presenting a break condition at boot time can hold the chip in a low power state, preventing normal
initialisation while the condition exists
■
With BCSP, the firmware can be configured to send a break to the host before sending data. (This is
normally used to wake the host from a Deep Sleep state.)
■
A block of Bluetooth radio test or BIST commands allows direct control of the BlueCore5-Multimedia Plug-
n-Go Automotive radio. This aids the development of modules' radio designs, and can be used to support
Bluetooth qualification.
■
Hardware low power modes: Shallow Sleep and Deep Sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
■
SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be routed
over the PCM interface (at the same time as routing any remaining SCO channels over HCI).
Note:
Always refer to the Firmware Release Note for the specific functionality of a particular build.
17.2 Host-Side Software
BlueCore5-Multimedia Plug-n-Go Automotive can be ordered with companion host-side software:
■
BlueCore5-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth host-
side stack together with IC hardware described in this document.
■
BlueCore5-Mobile includes software for a full host-side stack designed for modern ARM chip-based mobile
handsets together with IC hardware described in this document.
17.3 CSR Development Systems
CSR’s BlueLab Multimedia and BlueTunes (BTN-002-2A) development kits are available to allow the evaluation of
the BlueCore5-Multimedia Plug-n-Go Automotive hardware and software, and as toolkits for developing on-chip and
host software.
17.4 eXtension
A wide range of software options is available from 3rd parties through the CSR eXtension partner program, see
http://www.csr.com/eXtension.
CSR Bluetooth Software Stack
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18 Ordering Information
Interface Version
Package
Order Number
Type Size Shipment
Method
UART and USB LFBGA 105-ball
(Pb free)
10 x 10 x 1.6mm,
0.8mm pitch Tape and reel BC57G687C-ANN-E4
(a)
(a)
Until BC57G687C reaches Production status, engineering samples order number applies. This is BC57G687C-ES-ANN-E4, with no minimum
order quantity.
Note:
At Production status Minimum Order Quantity is 2kpcs taped and reeled.
18.1 Tape and Reel Information
For tape and reel packing and labelling see
IC Packing and Labelling Specification
.
18.1.1 Tape Orientation
The general orientation of the LFBGA in the tape is as shown in Figure 18.1.
User Direction of Feed
Circular Holes
Pin A1 marker
Figure 18.1: Tape and Reel Orientation
Ordering Information
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18.1.2 Reel Information
Figure 18.2: Reel Dimensions
Package
Type
Tape
Width
A
Max B C D Min N Min W1 W2
Max
W3
Units
Min Max
10 x 10 x
1.6mm
LFBGA
16 332 1.5 13.0
(0.5/-0.2) 20.2 50 16.4
(2.0/-0.0) 22.4 16.4 19.1 mm
18.2 Moisture Sensitivity Level
BlueCore5-Multimedia Plug-n-Go Automotive is qualified to moisture sensitivity level MSL3 in accordance with
JEDEC J-STD-020.
Ordering Information
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19 Document References
Document Reference, Date
BlueCore5 Charger Description and Calibration
Procedure Application Note
CS-113282-ANP
BlueCore5-Multimedia External Recommendations for
ESD Protection
CS-114058-ANP
BlueCore5 Multimedia Plug-n-Go Automotive
Performance Specification
CS-118838-SP
Bluetooth and IEEE 802.11 b/g Co-existence Solutions
Overview
bcore-an-066P
Bluetooth and USB Design Considerations
CS-101412-AN
Core Specification of the Bluetooth System
v2.1 + EDR, 26 July 2007
Electrostatic Discharge (ESD) Sensitivity Testing
Human Body Model (HBM)
JESD22-A114
IC Packing and Labelling Specification
CS-112584-SPP
Moisture / Reflow Sensitivity Classification for
Nonhermitic Solid State Surface Mount Devices
IPC / JEDEC J-STD-020
Optimising BlueCore5-Multimedia ADC Performance
Application Note
CS-120059-AN
Selection of I
2
C EEPROMS for Use with BlueCore
bcore-an-008P
Test Suite Structure (TSS) and Test Purposes (TP)
System Specification 1.2/2.0/2.0 + EDR/ 2.1/2.1 + EDR
RF.TS/2.1.E.0, 27 December 2006
Typical Solder Reflow Profile for Lead-free Device
CS-116434-ANP
Universal Serial Bus Specification
v2.0, 27 April 2000
Document References
CS-121449-DSP3
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Terms and Definitions
Term Definition
802.11
™
WLAN specification defined by a working group within the IEEE
8DPSK 8 phase Differential Phase Shift Keying
π/4 DQPSK π/4 rotated Differential Quaternary Phase Shift Keying
ACK ACKnowledge
ACL Asynchronous ConnectionLess
ADC Analogue to Digital Converter
AFC Automatic Frequency Control
AFH Adaptive Frequency Hopping
AGC Automatic Gain Control
ALU Arithmetic logic unit
BCCMD BlueCore Command
BCSP BlueCore Serial Protocol
BGA Ball Grid Array
BIST Built-In Self Test
BlueCore
®
Group term for CSR’s range of Bluetooth wireless technology ICs
Bluetooth
®
Set of technologies providing audio and data transfer over short-range radio connections
BMC Burst Mode Controller
CDMA Code Division Multiple Access
codec Coder decoder
CRC Cyclic Redundancy Check
CSR Cambridge Silicon Radio
CVSD Continuous Variable Slope Delta Modulation
DAC Digital to Analogue Converter
DC Direct Current
DSP Digital Signal Processor
EDR Enhanced Data Rate
EEPROM Electrically Erasable Programmable Read Only Memory
eSCO Extended SCO
ESD Electro-Static Discharge
ESR Equivalent Series Resistance
etc
et cetera
, and the rest, and so forth
FHS Frequency Hop Synchronisation
FSK Frequency Shift Keying
GFSK Gaussian Frequency Shift Keying
GSM Global System for Mobile communications
H4DS H4 Deep Sleep
HBM Human Body Model
HCI Host Controller Interface
IIR Infinite Impulse Response (filter)
IQ In-Phase and Quadrature
I/O Input/Output
Terms and Definitions
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Term Definition
I
2
CInter-Integrated Circuit
I
2
SInter-Integrated Circuit Sound
IC Integrated Circuit
IEEE Institute of Electronic and Electrical Engineers
IF Intermediate Frequency
JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology
Association)
LC Link Controller
LC An inductor (L) and capacitor (C) network
LCD Liquid-Crystal Display
LED Light-Emitting Diode
LM Link Manager
LMP Link Manager Protocol
LNA Low Noise Amplifier
MAC Medium Access Control
MCU Micro Controller Unit
MIPS Million Instructions Per Second
MMU Memory Management Unit
NSMD Non Solder Mask Defined
PA Power Amplifier
PBB (Polybrominated Bi-Phenyl)
PBDE Polybrominated Diphenyl Ether
PCM Pulse Code Modulation
PIO Programmable Input Output
Plug-n-Go
®
CSR IC with RF matching components (including balun) within the package
PVC Poly Vinyl Chloride
RAM Random Access Memory
RF Radio Frequency
RH Relative Humidity
RISC Reduced Instruction Set Computer
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive
(2002/95/EC)
RSSI Received Signal Strength Indication
RX Receive or Receiver
SBC Sub-band Coding
SCO Synchronous Connection-Oriented
SNR Signal-to-Noise Ratio
SPI Serial Peripheral Interface
SPDIF Sony/Philips Digital InterFace (also IEC 958 type II, part of IEC-60958). An interface designed
to transfer stereo digital audio signals between various devices and stereo components with
minimal loss.
TCXO Temperature Compensated crystal Oscillator
TP Test Purposes
TSS Test Suite Structure
TX Transmit or Transmitter
Terms and Definitions
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Term Definition
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
VCO Voltage Controlled Oscillator
VM Virtual Machine
VoIP Voice over Internet Protocol
W-CDMA Wideband Code Division Multiple Access
WCS Wireless Co-existence System
Terms and Definitions
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