Data Sheet 16-Bit VOUT, nanoDAC, SPI Interface, 2.7 V to 5.5 V in an SOT-23 AD5061 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 16-bit digital-to-analog converter (DAC), 4 LSB INL Power-on reset to midscale or zero-scale Guaranteed monotonic by design 3 power-down functions Low power serial interface with Schmitt triggered inputs Small 8-lead SOT-23 package, low power Fast settling time of 4 s typically 2.7 V to 5.5 V power supply Low glitch on power-up SYNC interrupt facility VREF POWER-ON RESET AD5061 BUF OUTPUT BUFFER DAC REGISTER REF(+) VOUT DAC AGND INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC RESISTOR NETWORK 04762-001 APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators SYNC SCLK DACGND DIN Figure 1. GENERAL DESCRIPTION The AD5061, a member of the Analog Devices, Inc., nanoDACTM family, is a low power, single 16-bit buffered voltage-out DAC that operates from a single 2.7 V to 5.5 V supply. The device offers a relative accuracy specification of 4 LSB and operation is guaranteed monotonic with a 1 LSB DNL specification. The device uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard SPI, QSPITM, MICROWIRE, and DSP interface standards. The reference for the AD5061 is supplied from an external VREF pin. A reference buffer is also provided on-chip. The device incorporates a power-on reset circuit that ensures the DAC output powers up to mid-scale or zero scale and remains there until a valid write takes place to the device. The device contains a power-down feature that reduces the current consumption of the device to typically 330 nA at 5 V and provides software-selectable output loads while in power-down mode. The device is put into powerdown mode over the serial interface. Total unadjusted error for the device is <3 mV. This device exhibits very low glitch on power-up. Rev. E VDD Table 1. Related Devices Part No. AD5062 AD5063 AD5040/AD5060 Description 2.7 V to 5.5 V, 16-bit nanoDAC converter, 1 LSB INL, SOT-23 2.7 V to 5.5 V, 16-bit nanoDAC converter, 1 LSB INL, MSOP 2.7 V to 5.5 V, 14-bit/16-bit nanoDAC converter, 1 LSB INL, SOT-23 PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Available in a small 8-lead SOT-23 package. 16-bit resolution, 4 LSB INL. Low glitch on power-up. High speed serial interface with clock speeds up to 30 MHz. Three power-down modes available to the user. Reset to known output voltage (midscale or zero scale). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2005-2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5061 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 15 Applications ....................................................................................... 1 Input Shift Register .................................................................... 15 Functional Block Diagram .............................................................. 1 SYNC Interrupt .......................................................................... 15 General Description ......................................................................... 1 Power-On to Zero-Scale or Midscale ...................................... 16 Product Highlights ........................................................................... 1 Software Reset ............................................................................. 16 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 16 Specifications..................................................................................... 3 Microprocessor Interfacing ....................................................... 17 Timing Characteristics ..................................................................... 5 Applications Information .............................................................. 18 Absolute Maximum Ratings ............................................................ 6 Choosing a Reference ................................................................ 18 ESD Caution .................................................................................. 6 Bipolar Operation....................................................................... 18 Pin Configuration and Function Descriptions ............................. 7 Using a Galvanically Isolated Interface Chip.......................... 19 Typical Performance Characteristics ............................................. 8 Power Supply Bypassing and Grounding ................................ 19 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 20 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 20 DAC Architecture ....................................................................... 15 Reference Buffer ......................................................................... 15 REVISION HISTORY 3/2019--Rev. D to Rev. E Reorganized Applications Information Section ......................... 18 10/2018--Rev. C to Rev. D Changes to Table 2 ............................................................................ 3 Changes to Terminology Section.................................................. 14 Changes to Ordering Guide .......................................................... 20 8/2015--Rev. B to Rev. C Changed ADSP-BF53x to ADSP-BF527, ADR43x to ADR435, and ADuM130x to ADuM1300 ...................Throughout Deleted AD5061-to-ADSP-2101/ADSP-2103 Interface Section and Figure 40; Renumbered Sequentially............................................. 16 Changes to Figure 42 ................................................................................. 17 Changes to Figure 46 ................................................................................. 18 Changes to Figure 47 ................................................................................. 19 5/2011--Rev. A to Rev. B Changes to Data Sheet Title and Product Highlights Section .....1 Changes to Ordering Guide .......................................................... 20 1/2006--Rev. 0 to Rev. A Changes to General Description .....................................................1 Changes to Table 2.............................................................................3 Changes to Figure 19 Caption ...................................................... 10 Added Figure 28 to Figure 36 ....................................................... 12 Changes to Serial Interface Section.............................................. 15 Changes to Power-Down Modes Section .................................... 16 Changes to Ordering Guide .......................................................... 20 7/2005--Revision 0: Initial Version Rev. E | Page 2 of 20 Data Sheet AD5061 SPECIFICATIONS VDD = 5.5 V, VREF = 4.096 V, RL = unloaded, CL = unloaded, and TMIN to TMAX, unless otherwise specified. Table 2. B Grade 1 Typ Max Unit 0.5 0.5 0.5 0.5 0.5 0.5 4 4 3.0 3.0 1 1 Bits LSB LSB mV mV LSB LSB 0.01 0.01 1 0.02 0.02 0.5 0.05 0.05 0.05 3.0 % of FSR % of FSR ppm of FSR/C mV mV V/C mV 0.05 3.0 mV VREF 4 V s Output Noise Spectral Density Output Voltage Noise Digital to Analog Glitch Impulse Digital Feedthrough DC Output Impedance (Normal) DC Output Impedance (Power-Down) (Output Connected to 1 k Network) (Output Connected to 100 k Network) Capacitive Load Stability Output Slew Rate 64 6 2 0.003 0.015 nV/Hz V p-p nV-s nV-s 1 100 1.2 k k nF V/s Short-Circuit Current 60 mA 45 mA 4.5 s -92 -67 dB dB Parameter STATIC PERFORMANCE Resolution Relative Accuracy (INL) 2 Min 16 Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Gain Error Gain Error Temperature Coefficient Offset Error Offset Error Temperature Coefficient Full-Scale Error OUTPUT CHARACTERISTICS 3 Output Voltage Range Output Voltage Settling Time 0 1 DAC Power-Up Time DC Power Supply Rejection Ratio Wideband Spurious-Free Dynamic Range REFERENCE INPUT/OUTPUT VREF Input Range 4 Input Current (Power-Down) Input Current (Normal) DC Input Impedance 3.0 3.0 2 VDD - 50 0.1 0.5 1 mV A A M Rev. E | Page 3 of 20 Test Conditions/Comments -40C to +85C, B grade -40C to +125C, Y grade -40C to +85C, B grade -40C to +125C, Y grade Guaranteed monotonic, -40C to +85C, B grade Guaranteed monotonic, -40C to +125C, Y grade TA = -40C to +85C, B grade TA = -40C to +125C , Y grade TA = -40C to + 85C, B grade TA = -40C to + 125C, Y grade All 1s loaded to DAC register, TA = -40C to +85C, B grade All 1s loaded to DAC register, TA = -40C to +125C , Y grade 1/4 scale to 3/4 scale code transition to 1 LSB, RL = 5 k DAC code = midscale, 1 kHz DAC code = midscale , 0.1 Hz to 10 Hz bandwidth 1 LSB change around major carry, RL = 5 K DAC code = full-scale Output impedance tolerance 10% Output impedance tolerance 400 Output impedance tolerance 20 k Loads used: RL = 5 k, RL = 100 k, RL = 1/4 scale to 3/4 scale code transition to 1 LSB, RL = 5 k, CL = 200 pF DAC code = full-scale, output shorted to GND, TA = 25C DAC code = zero-scale, output shorted to VDD, TA = 25C Time to exit power-down mode to normal mode of AD5061, 24th clock edge to 90% of DAC final value, output unloaded VDD 10%, DAC code = full-scale Output frequency = 10 kHz Zero-scale loaded AD5061 Parameter LOGIC INPUTS Input Current 5 Input Low Voltage (VIL) Input High Voltage (VIH) Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 2.7 V to 5.5 V Data Sheet Min B Grade 1 Typ Max 1 Unit Test Conditions/Comments 5 0.8 0.8 A V V V V pF VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V VDD = 2.7 V to 5.5 V VDD = 2.7 V to 3.6 V 5.5 V 1.2 mA 2.0 1.8 4 2.7 1.0 0.89 IDD (All Power-Down Modes) VDD = 2.5 V to 5.5 V mA 1 0.265 A A All digital inputs at 0 V or VDD DAC active and excluding load current VIN = VDD and VIL = GND, VDD = 5.5 V, VREF = 4.096 V, code = midscale VIN = VDD and VIL = GND, VDD = 3.0 V, VREF = 4.096 V, code = midscale VIH = VDD and VIL = GND, VDD = 5.5 V, VREF = 4.096 V, code = midscale VIH = VDD and VIL = GND, VDD = 3.0 V, VREF = 4.096 V, code = midscale Temperature range for B grade: -40C to +85C, typical at 25C; temperature range for Y grade: -40C to +125C. Linearity calculated using a reduced code range (160 to 65535). 3 Guaranteed by design and characterization, not production tested. 4 The typical output supply headroom performance for various reference voltages at -40C can be seen in Figure 27. 5 Total current flowing into all pins. 1 2 Rev. E | Page 4 of 20 Data Sheet AD5061 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise specified. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Table 3. Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge set-up time Data set-up time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignore Maximum SCLK frequency is 30 MHz. t2 t4 t1 t9 SCLK t7 t3 t8 SYNC t6 t5 DIN D23 D22 D2 D1 Figure 2. Timing Diagram Rev. E | Page 5 of 20 D0 D23 D22 04762-002 1 Limit 33 5 3 10 3 2 0 12 9 AD5061 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND VREF to GND Operating Temperature Range Industrial (B Grade) Extended Automotive Temperature Range (Y Grade) Storage Temperature Range Maximum Junction Temperature Power Dissipation Thermal Impedance JA JC Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Electrostatic Discharge (ESD) Rating -0.3 V to +7.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V This device is a high performance integrated circuit with an ESD rating of <2 kV, and is ESD sensitive. Take proper precautions for handling and assembly. ESD CAUTION -40C to + 85C -40C to +125C -65C to +150C 150C (TJ max - TA)/JA 206C/W 44C/W 260C 10 sec to 40 sec 1.5 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 6 of 20 Data Sheet AD5061 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DIN 1 8 SCLK 7 SYNC VREF 3 6 DACGND VOUT 4 5 AGND VDD 2 TOP VIEW (Not to Scale) 04762-003 AD5061 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic DIN 2 3 4 5 6 7 VDD VREF VOUT AGND DACGND SYNC 8 SCLK Description Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Power Supply Input. These devices can operate from 2.7 V to 5.5 V and VDD must be decoupled to GND. Reference Voltage Input. Analog Output Voltage from DAC. Ground Reference Point for Analog Circuitry. Ground Input to the DAC. Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Rev. E | Page 7 of 20 AD5061 Data Sheet 1.2 1.0 VDD = 5.5V, VREF = 4.096V VDD = 2.7V, VREF = 2.0V 0.8 0.6 DNL ERROR (LSB) MAX DNL ERROR @ VDD = 2.7V 0.4 0.2 0 MAX DNL ERROR @ VDD = 5.5V -0.2 -0.4 -0.6 40160 50160 -1.0 MIN DNL ERROR @ VDD = 2.7V MIN DNL ERROR @ VDD = 5.5V -1.2 -40 60160 -20 0 DAC CODE 1.0 100 120 140 VDD = 5.5V, VREF = 4.096V VDD = 2.7V, VREF = 2.0V 0.8 MAX TUE ERROR @ VDD = 2.7V TUE ERROR (mV) 0.6 0.4 0.2 0 MAX TUE ERROR @ VDD = 5.5V MIN TUE ERROR @ VDD = 5.5V -0.2 -0.4 MIN TUE ERROR @ VDD = 2.7V -0.6 40160 50160 -1.0 -1.2 -40 60160 -20 0 20 40 60 80 100 120 140 1.6 VDD = 5.5V, VREF = 4.096V 1.4 VDD = 2.7V, VREF = 2.0V 1.2 1.0 MAX INL ERROR @ VDD = 2.7V 0.8 0.6 0.4 0.2 MAX INL ERROR @ VDD = 5.5V 0 MIN INL ERROR @ VDD = 5.5V -0.2 -0.4 -0.6 MIN INL ERROR @ VDD = 2.7V -0.8 -1.0 -1.2 -1.4 -1.6 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) INL ERROR (LSB) Figure 8. TUE vs. Temperature 04762-006 40160 04762-008 -0.8 04762-005 TUE ERROR (mV) 80 1.2 Figure 5. Typical TUE Plot DNL ERROR (LSB) 60 Figure 7. DNL vs. Temperature DAC CODE 1.6 1.4 TA = 25C VDD = 5V, VREF = 4.096V 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 160 10160 20160 30160 40 TEMPERATURE (C) Figure 4. Typical INL Plot 0.16 0.14 TA = 25C VDD = 5V, VREF = 4.096V 0.12 0.10 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 160 30160 10160 20160 20 04762-007 -0.8 50160 60160 DAC CODE TEMPERATURE (C) Figure 6. Typical DNL Plot Figure 9. INL vs. Temperature Rev. E | Page 8 of 20 04762-090 1.6 1.4 TA = 25C VDD = 5V, VREF = 4.096V 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 160 30160 20160 10160 04762-004 INL ERROR (LSB) TYPICAL PERFORMANCE CHARACTERISTICS 1.5 VDD = 5.5V, VREF = 4.096V VDD = 2.7V, VREF = 2.0V CODE = FULL-SCALE 1.4 1.3 SUPPLY CURRENT (mA) 1.2 MAX DNL ERROR @ VDD = 5.5V MIN DNL ERROR @ VDD = 5.5V VDD = 5.5V 1.1 1.0 0.9 0.8 VDD = 2.7V 0.7 0.6 0.5 0.4 0.3 3.0 3.5 4.0 4.5 5.0 04762-013 0.2 04762-010 DNL ERROR (LSB) 1.6 1.4 TA = 25C 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 2.0 2.5 0.1 0 -40 5.5 -20 0 20 REFERENCE VOLTAGE (V) 1.2 3.00 TA = 25C 0.8 2.50 0.6 2.25 0.4 MAX TUE ERROR @ V DD = 5.5V 0.2 0 MIN TUE ERROR @ VDD = 5.5V -0.2 -0.4 -0.6 -0.8 100 120 140 2.00 1.75 1.50 VDD = 5.5V, VREF = 4.096V 1.25 1.00 0.75 VDD = 3.0V, VREF = 2.5V 3.0 3.5 4.0 4.5 5.0 04762-014 04762-011 2.5 0.25 0 5.5 0 10000 20000 REFERENCE VOLTAGE (V) 40000 50000 60000 70000 5.0 5.5 6.0 2.0 VREF = 2.5V 1.8 TA = 25C CODE = MIDSCALE 1.6 SUPPLY CURRENT (mA) MAX INL ERROR @ VDD = 5.5V MIN INL ERROR @ VDD = 5.5V 1.4 1.2 1.0 0.8 0.6 0.4 3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V) 5.0 5.5 04762-015 1.6 1.4 TA = 25C 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 2.0 2.5 30000 DAC CODE 04762-009 INL ERROR (LSB) 80 0.50 -1.0 -1.2 2.0 60 TA = 25C 2.75 SUPPLY CURRENT (mA) TUE ERROR (mV) 1.0 40 TEMPERATURE (C) 0.2 0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 1.8 VDD = 5.5V, VREF = 4.096V VDD = 2.7V, VREF = 2.0V 1.6 CH3 = SCLK 1.4 1.0 0.8 OFFSET ERROR @ VDD = 5.5V 0.6 0.4 CH2 = VOUT 0.2 OFFSET ERROR @ VDD = 2.7V 0 -0.2 -0.6 -40 CH1 = TRIGGER 04762-012 -0.4 -20 0 20 40 60 80 100 120 CH1 2V/DIV CH2 2V/DIV 140 04762-019 OFFSET ERROR (mV) 1.2 CH3 2V TIME BASE = 5.00s TEMPERATURE (C) VDD = 3V DAC = FULL-SCALE VREF = 2.7V TA = 25C 24TH CLOCK FALLING CH1 = SCLK CH2 50mV/DIV TIME BASE 400ns/DIV VDD = 5V VREF = 4.096V TA = 25C 10ns/SAMPLE VDD = 5V TA = 25C VREF = 4.096V AMPLITUDE (200V/DIV) 200 150 FULL-SCALE 100 MIDSCALE ZERO-SCALE 50 0 100 1000 10000 FREQUENCY (Hz) 100000 1000000 04762-021 250 Y AXIS = 2V/DIV X AXIS = 4s/DIV 04762-018 NOISE SPECTRAL DENSITY (nV/ Hz) 300 CH1 2V/DIV 04762-020 04762-017 CH2 = VOUT 0 50 100 150 200 250 300 SAMPLES 350 400 450 500 0.10 VDD = 5.5V, VREF = 4.096V 0.08 VDD = 2.7V, VREF = 2.0V 0.04 CH1 = VDD GAIN ERROR @ VDD = 2.7V 0.02 0 GAIN ERROR @ VDD = 5.5V -0.02 CH2 = VOUT -0.04 -0.06 -0.10 -40 VDD = 5V VREF = 4.096V DD RAMP RATE = 200s TA = 25C 04762-022 -0.08 -20 0 20 40 60 80 100 120 04762-025 GAIN ERROR (%FSR) 0.06 CH1 2V/DIV CH2 1V/DIV TIME BASE = 100s 140 TEMPERATURE (C) 16 CH1 = SCLK 14 12 FREQUENCY CH2 = SYNC 10 8 6 CH3 = VOUT VDD = 5V VREF = 4.096VDD TA = 25C CH4 = TRIGGER 04762-023 2 0 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 04762-026 4 CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV TIME BASE 1s/DIV 0.91 MORE BIN 0.50 14 0.45 12 0.40 HEADROOM (V) 0.35 8 6 0.30 0.25 0.20 0.15 4 0.05 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 MORE 0 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 BIN REFERENCE VOLTAGE (V) 0 04762-091 0.10 2 04762-024 FREQUENCY 10 5.05 5.00 VDD = 5.0V TA = 25C DAC = FULL-SCALE 1k TO GND ZERO-SCALE C4 = 50mV p-p 4.95 DAC OUTPUT (V) 4.90 4.85 4.80 4.75 4.70 4.60 4.55 04762-048 04762-042 4.65 4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00 CH4 20.0mV M1.00s CH1 1.64V VREF (V) 5.005 VREF = 5V TA = 25C C2 25mV p-p 4.995 C3 4.96V p-p T 2 4.990 C3 FALL 935.0s 4.985 C3 RISE s NO VALID EDGE T 3 5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00 04762-049 4.975 04762-065 4.980 CH3 2.00V CH2 50mV M1.00ms CH3 1.36V VDD (V) C4 = 143mV p-p ZERO-SCALE C2 30mV p-p 1k TO GND C3 4.96V p-p T 2 C3 FALL s NO VALID EDGE T CH4 50.0mV M4.00s CH1 1.64V C3 RISE 946.2s 3 04762-050 04762-047 DAC OUTPUT (V) 5.000 CH3 2.00V CH2 50mV M1.00ms CH3 1.36V 0.0010 0.0008 2.1 CODE = MIDSCALE VDD = 5V, VREF = 4.096V VDD = 3V, VREF = 2.5V 2.0 1.9 0.0006 VDD = 5.5V VREF = 4.096V 10% TO 90% RISE TIME = 0.688s SLEW RATE = 1.16V/s 2.04V VOLTAGE (V) 1.8 0.0004 1.7 0.0002 1.6 0 1.5 1.4 -0.0002 VDD = 5.5V DAC OUTPUT 1.3 -0.0004 1.2 VDD = 3V -20 -15 -10 -5 0 5 10 15 20 25 30 CURRENT (mA) 0.10 0.08 CODE = MIDSCALE VDD = 5V, VREF = 4.096V VDD = 3V, VREF = 2.5V 0.06 VDD = 3V, VREF = 2.5V 0.02 0 -0.02 -0.04 -0.06 VDD = 5V, VREF = 4.096V 04762-063 VOUT (V) 0.04 -0.08 -0.10 -25 -20 -15 -10 -5 0 5 IOUT (mA) 10 15 20 25 30 1.04V 04762-052 -0.0008 -25 04762-051 -0.0006 1.1 1.0 -10s -8s -6s -4s -2s 0 2s 4s 6s 8s 9.96s AD5061 Data Sheet TERMINOLOGY Relative Accuracy (INL) For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical AD5061 DNL vs. code plot is shown in Figure 6. Offset Error Offset error is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output is 0 V. Offset error is expressed in mV. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output is VDD - 1 LSB. Full-scale error is expressed in percent of fullscale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot is shown in Figure 5. Offset Error Temperature Coefficient This is a measure of the change in offset error with a change in temperature. It is expressed in V/C. Gain Error Temperature Coefficient This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Digital to Analog Glitch Impulse Digital to analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition; see Figure 17 and Figure 21. The expanded view in Figure 17 shows the glitch generated following completion of the calibration routine; Figure 21 zooms in on this glitch. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus; that is, from all 0s to all 1s, and vice versa. Rev. E | Page 14 of 20 VOUT 2R 2R 2R 2R 2R 2R 2R S0 S1 S11 E1 E2 E15 FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS DB15 (MSB) 0 0 0 0 0 0 PD1 PD0 D15 D14 DB0 (LSB) D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 0 1 NORMAL OPERATION 1 0 100k TO GND 1 1 1k TO GND 3-STATE POWER-DOWN MODES 04762-028 12-BIT R-2R LADDER 047762-027 VREF OUTPUT BUFFER AD5061 POWER-DOWN CIRCUITRY RESISTOR NETWORK 04762-029 VOUT DAC SCLK DIN DB23 DB0 INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE DB23 DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE 04762-031 SYNC 80C51/80L511 AD50611 PC7 SYNC SCK SCLK P3.3 SYNC TxD SCLK RxD DIN 04762-034 68HC11/ 68L111 AD50611 MOSI 04762-032 1ADDITIONAL PINS OMITTED FOR CLARITY DIN 1ADDITIONAL PINS OMITTED FOR CLARITY CS SYNC SK SCLK SO DIN 1ADDITIONAL PINS OMITTED FOR CLARITY 1 AD5061 ADSP-B5271 DIN SCLK TFS0 SYNC 1ADDITIONAL PINS OMITTED FOR CLARITY 04762-033 DT0PRI TSCLK0 04762-035 AD50611 MICROWIRE1 7V SYNC SCLK DIN AD5061 VOUT = 0V TO 5V R2 = 10k AD5061 VDD 10F +5V R1 = 10k +5V - AD820/ OP295 + VOUT 5V OUT -5V 0.1F 3-WIRE SERIAL INTERFACE 04762-037 3-WIRE SERIAL INTERFACE 5V 04762-036 ADR395 5V REGULATOR 10F POWER 0.1F VDD V1A V0A SCLK AD5061 ADuM1300 SDI V1B V0B SYNC DATA V1C V0C DIN VOUT GND 04762-038 SCLK AD5061 Data Sheet OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 3.00 2.80 2.60 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8 4 0 0.60 BSC 0.60 0.45 0.30 12-16-2008-A 1.30 1.15 0.90 COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 48. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD5061BRJZ-1500RL7 AD5061BRJZ-2REEL7 AD5061BRJZ-2500RL7 AD5061YRJZ-1500RL7 AD5061YRJZ-1REEL7 EVAL-AD5061SDZ EVAL-SDP-CB1Z 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C INL 4 LSB 4 LSB 4 LSB 4 LSB 4 LSB Description 2.7 V to 5.5 V, Reset to 0 V 2.7 V to 5.5 V, Reset to Midscale 2.7 V to 5.5 V, Reset to Midscale 2.7 V to 5.5 V, Reset to 0 V 2.7 V to 5.5 V, Reset to 0 V Z = RoHS Compliant Part. The EVAL-AD5061SDZ and the EVAL-SDP-CB1Z must be used and ordered together. (c)2005-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04762-0-3/19(E) Rev. E | Page 20 of 20 Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 Evaluation Board Evaluation Controller Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 Marking Code D43 D44 D44 D6G D6G