KSZ8001L/S 1.8V, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver Data Sheet Rev. 1.04 General Description Features The KSZ8001 is a 10BASE-T/100BASE-TX/100BASE-FX Physical Layer Transceiver, operating the core at 1.8 volts to meet low voltage and low power requirements. The solution provides MII/RMII/SMII interfaces to transmit and receive data. A unique mixed-signal design extends signaling distance while reducing power consumption. * * * * * HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables. * * * * * Featuring LinkMD cable diagnostics, which allows detection of common cabling plant problems such as open and short circuits, the KSZ8001 represents a new level of features and performance and is an ideal choice of physical layer transceiver for 100BASE-TX/10BASET/100BASE-FX applications. Single chip 100BASE-TX/100BASE-FX/10BASE-T physical layer solution 1.8V CMOS design, power consumption 250 mW Robust (130m+) operation over standard cables Supports Media Independent Interface (MII), Reduced MII (RMII), and Serial MII (SMII) LinkMD feature to determine cable length and diagnose faulty cables up 200 m with +/- 2 m accuracy Supports HP MDI/MDI-X auto crossover Supports power down mode and power saving mode MDC/MDIO to 12.5 MHz for rapid configuration Fully compliant to IEEE 802.3u standard Supports auto-negotiation and manual selection for 10/100Mbps speed and full / half-duplex mode Functional Diagram Micrel, Inc. * 1849 Fortune Drive * San Jose, CA 95131 * USA * tel + 1 (408) 944-0800 * fax + 1 (408) 944-0970 * http://www.micrel.com June 2009 Revision 1.04 1 Micrel KSZ8001 Features (continued) * * * * * * Configurable through MII serial management port or via external control pins Programmable LED outputs for link, activity, full/half duplex, collision and speed On-chip built-in analog front end filtering for both 100BASE-TX and 10BASE-T Supports back-to-back, 100BASE-FX to 100BASE-TX for media converter applications Single 3.3V power supply with built-in 1.8V regulator (`L' parts) 48 Pin LQFP, 48 Pin SSOP Ordering Information Part Number KS8001L Integrated LDO Yes Temperature Range 0-70C KS8001S KSZ8001L KSZ8001LI No Yes Yes 0 -70 C o o 0 -70 C o o -40 -85 C KSZ8001S KSZ8001SI No No 0 -70 C o o -40 -85 C Package 48-LQFP Lead Finish Standard o o 48-SSOP 48-LQFP 48-LQFP Standard Lead-free Lead-free o o 48-SSOP 48-SSOP Lead-free Lead-free June 2009 Revision 1.04 2 Micrel KSZ8001 Revision History Revision Date Summary of Changes PRELIMINARY 25 Mar 2004 * Preliminary data 0.8 9 Aug 2004 * Updated pin 38 (VDDRCV) definition to 3.3V * Corrected pin configuration diagrams to reflect NC on pins 42 and 43 * Updated crystal tolerance to +/- 50 ppm 0.81 17 Sep 2004 * Updated series resistance for crystal specification to 40 0.82 25 Jan 2005 * LinkMD distance coefficient changed to 0.39 * Interrupt register status bits set to RO/SC * Recommended reset circuit added * RMII timing added 1.00 31 Mar 2005 * Added lead-free part numbers 1.01 16 May 2005 * Changed REXT value to 6.65 K * Removed preliminary status * Added KSZ8001S to ordering information * Updated part ordering information * Corrected recommended reset circuits to match corresponding description * Added Micrel disclaimer to last page * Corrected crystal/oscillator PPM in Reference Clock Connection Diagrams * Added current consumption for KSZ8001L * Correct RXC clock pulse width timing in 100BASE-TX MII Receive Timing Diagram * Added description for Auto MDI/MDI-X mode in register 1f.15 * Updated description for MDI/MDI-X select in register 1f.14 * Corrected Auto-Negotiation Complete bit, register 1f.7, to read only 1.02 1.03 1.04 30 Jan 2006 7 March 2006 25 June 2009 * Added "Circuit Design Reference for Power Supply" section * Updated Pin Description for the following pins: MDIO, VDDIO, VDDC, RX+, RX-, TX+, TX-, XI, XO * Removed 48 Pin QFN (targeted) package option * Renamed KS8001 to KSZ8001 throughout datasheet * Added mechanical info for SSOP package * Updated package thermal resistance * Update ordering information. June 2009 Revision 1.04 3 Micrel KSZ8001 Table of Contents Pin Description .................................................................................................................................................................................... 6 Strapping Options ............................................................................................................................................................................. 10 Pin Configuration .............................................................................................................................................................................. 11 Functional Description...................................................................................................................................................................... 12 100BASE-TX Transmit .................................................................................................................................................................... 12 100BASE-TX Receive ..................................................................................................................................................................... 12 PLL Clock Synthesizer .................................................................................................................................................................... 12 Scrambler/De-scrambler (100BASE-TX only).................................................................................................................................. 12 10BASE-T Transmit......................................................................................................................................................................... 12 10BASE-T Receive.......................................................................................................................................................................... 12 SQE and Jabber Function (10BASE-T only).................................................................................................................................... 13 Auto-Negotiation.............................................................................................................................................................................. 13 MII Management Interface................................................................................................................................................................. 13 MII Data Interface ............................................................................................................................................................................ 13 RMII (Reduced MII) Data Interface.................................................................................................................................................... 14 RMII Signal Definition ...................................................................................................................................................................... 14 Reference Clock (REF_CLK)........................................................................................................................................................... 15 Carrier Sense/Receive Data Valid (CRS_DV) ................................................................................................................................. 15 Receive Data [1:0] (RXD[1:0]) ......................................................................................................................................................... 15 Transmit Enable (TX_EN) ............................................................................................................................................................... 15 Transmit Data [1:0] (TXD[1:0])......................................................................................................................................................... 15 Collision Detection........................................................................................................................................................................... 15 RX_ER ............................................................................................................................................................................................ 15 RMII AC Characteristics .................................................................................................................................................................. 16 RMII Transmit Timing ...................................................................................................................................................................... 16 RMII Receive Timing ....................................................................................................................................................................... 16 SMII Signal Definition........................................................................................................................................................................ 17 SMII Signals .................................................................................................................................................................................... 17 Receive Path ................................................................................................................................................................................... 17 Receive Sequence Diagram ............................................................................................................................................................ 17 Transmit Path .................................................................................................................................................................................. 18 Transmit Sequence Diagram ........................................................................................................................................................... 18 Collision Detection........................................................................................................................................................................... 19 DC Specification .............................................................................................................................................................................. 19 Timing Specification ........................................................................................................................................................................ 20 HP Auto Crossover (Auto MDI/MDI-X) ............................................................................................................................................. 21 Auto MDI/MDI-X Cross-Over Transformer Connection.................................................................................................................... 22 Power Management........................................................................................................................................................................... 22 100BASE-FX Mode ............................................................................................................................................................................ 22 Media Converter Operation............................................................................................................................................................... 22 LinkMD Cable Diagnostics................................................................................................................................................................ 23 Reference Clock Connection Options ............................................................................................................................................. 24 Circuit Design Reference for Power Supply.................................................................................................................................... 25 Register Map ...................................................................................................................................................................................... 26 Register 0h - Basic Control............................................................................................................................................................. 26 Register 1h - Basic Status .............................................................................................................................................................. 27 Register 2h - PHY Identifier 1 ......................................................................................................................................................... 27 Register 3h - PHY Identifier 2 ......................................................................................................................................................... 27 Register 4h - Auto-Negotiation Advertisement................................................................................................................................ 27 June 2009 Revision 1.04 4 Micrel KSZ8001 Register 5h - Auto-Negotiation Link Partner Ability......................................................................................................................... 28 Register 6h - Auto-Negotiation Expansion...................................................................................................................................... 28 Register 7h - Auto-Negotiation Next Page...................................................................................................................................... 29 Register 8h - Link Partner Next Page Ability................................................................................................................................... 29 Register 15h - RXER Counter......................................................................................................................................................... 29 Register 1bh - Interrupt Control/Status Register ............................................................................................................................. 30 Register 1dh - LinkMD Control/Status Register .............................................................................................................................. 30 Register 1eh - PHY Control ............................................................................................................................................................ 31 Register 1fh - 100BASE-TX PHY Controller ................................................................................................................................... 31 (Note 1) Absolute Maximum Rating ...................................................................................................................................................... 33 (Note 2) Operating Range ...................................................................................................................................................................... 33 (Note 3) Package Thermal Resistance (JA) .......................................................................................................................................... 34 (Note4) Electrical Characteristics ......................................................................................................................................................... 34 Timing Diagrams ............................................................................................................................................................................... 36 Reset Timing Diagram....................................................................................................................................................................... 41 Reset Timing Parameters ................................................................................................................................................................ 41 Reset Circuit Diagram ....................................................................................................................................................................... 41 Reference Circuit for Strapping Option Configuration .................................................................................................................. 43 Selection of Isolation Transformer .................................................................................................................................................. 44 Selection of Reference Crystal......................................................................................................................................................... 44 Package Information ......................................................................................................................................................................... 45 June 2009 Revision 1.04 5 Micrel KSZ8001 Pin Description Pin Number Pin Name Type 1 MDIO I/O 2 MDC I 3 RXD3/ PHYAD1 Ipd/O 4 RXD2/ PHYAD2 Ipd/O 5 RXD1/ RXD[1]/ PHYAD3 Ipd/O 6 RXD0/ RXD[0]/ RX PHYAD4 Ipd/O 7 8 9 VDDIO GND RXDV/ CRSDV/ Pwr Gnd Ipd/O PCS_LPBK 10 RXC/ SMII_SELE CT Ipd/O 11 RXER/ RX_ER/ ISO Ipd/O 12 13 GND VDDC Gnd Pwr 14 15 TXER TXC/ REFCLK/ CLOCK Ipd I/O 16 TXEN Ipd (Note 1) Pin Function MII Management (MIIM) Interface: Data I/O This pin requires an external 4.7K pull-up resistor. MII Management (MIIM) Interface: Clock Input This pin is synchronous to the MDIO data line. 2 MII Mode: Receive Data Output[3] / Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[1] during reset. See "Strapping Options" section for details. 2 MII Mode: MII Receive Data Output[2] / Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[2] during reset. See "Strapping Options" section for details. 2 MII Mode: Receive Data Output[1] / 3 RMII Mode: Receive Data Output[1] / Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[3] during reset. See "Strapping Options" section for details. 2 MII Mode: Receive Data Output[0] / 3 RMII Mode: Receive Data Output[0] / 4 SMII Mode: Receive Data and Control / Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[4] during reset. See "Strapping Options" section for details. 3.3V digital VDD Ground MII Mode: Receive Data Valid Output / RMII Mode: Carrier Sense/Receive Data Valid / Configuration Mode: The pull-up/pull-down value is latched as pcs_lpbk during reset. See "Strapping Options" section for details. MII Receive Clock Output Operating at: 25 MHz = 100 Mbps 2.5 MHz = 10 Mbps Configuration Mode: The pull-up/pull-down value is latched as SMII during reset. See "Strapping Options" section for details. MII Mode: Receive Error Output / RMII Mode: Receive Error / Configuration Mode: The pull-up/pull-down value is latched as ISOLATE during reset. See "Strapping Options" section for details. Ground 1.8V digital core VDD VDD output : KSZ8001L / KSZ8001SL VDD input : KSZ8001S (See "Circuit Design Reference for Power Supply" section for details) MII Transmit Error Input MII Mode: MII Transmit Clock Output / RMII Mode: 50 MHz Reference Clock Input / SMII Mode: 125 MHz Synchronization Clock Input MII Transmit Enable Input June 2009 Revision 1.04 6 Micrel KSZ8001 Pin Number Pin Name Type 17 TXD0/ TXD[0]/ TX TXD1/ TXD[1]/ SYNC TXD2 TXD3 COL / RMII_SELE CT Ipd 18 19 20 21 Ipd Ipd Ipd Ipd/O 22 CRS/ RMII_BTB Ipd/O 23 24 25 GND VDDIO INT#/ PHYAD0 Gnd Pwr Ipu/O 26 LED0/ TEST Ipu/O (Note 1) Pin Function MII Mode: Transmit Data Input[0] / RMII Mode: Transmit Data Input[0] / SMII Mode: Transmit Data and Control MII Mode: Transmit Data Input[1] / RMII Mode: Transmit Data Input[1] / SMII Mode: SYNC MII Transmit Data Input[2] MII Transmit Data Input[3] MII Collision Detect Output Configuration Mode: The pull-up/pull-down value is latched as RMII select during reset. See "Strapping Options" section for details. MII Carrier Sense Output Configuration Mode: The pull-up/pull-down value is latched as RMII Loopback during reset when RMII mode is selected. See "Strapping Options section" for details. Ground 3.3V digital VDD Management Interface (MII) Interrupt Out. Configuration Mode: Latched as PHYAD[0] during power up / reset. See "Strapping Options" section for details. Programmable LED Output 0 Configuration Mode: The external pull down enable test mode and only used for tfactory test. Active Low. The LED0 pin is also programmable via register 1eh. LED mode = 00 Link/Act Pin State LED Definition No Link H Off Link L On Activity - Toggle Link Pin State LED Definition No Link H Off Link L On 10Mbps Link Pin State LED Definition No Link H Off LED mode = 01 LED mode = 10 27 LED1 / SPD100/ noFEF Ipu/O Link L On Programmable LED Output 1 Configuration Mode: Latched as SPEED (Register 0, bit 13) during power up / reset. See "Strapping Options" Section for details. Active Low. The LED1 pin is also programmable via register 1eh. LED mode = 00 Speed Pin State LED Definition 10BT H Off 100BT L On June 2009 Revision 1.04 7 Micrel Pin Number KSZ8001 Pin Name Type (Note 1) Pin Function LED mode = 01 Speed Pin State LED Definition 10BT H Off 100BT L On 100Mbps Link Pin State LED Definition No Link H Off LED mode = 10 28 LED2/ DUPLEX Ipu/O Link L On Programmable LED Output 2 Configuration Mode: Latched as DUPLEX (register 0h, bit 8) during power up / reset. See "Strapping Options" Section for details. Active Low. The LED2 pin is also programmable via register 1eh. LED mode = 00 Duplex Pin State LED Definition Half H Off Full L On Full Duplex/Col Pin State LED Definition Half H Off Full L On Collision - Toggle Duplex Pin State LED Definition Half H Off LED mode = 01 LED mode = 10 29 LED3/ NWAYEN Ipu/O Full L On Programmable LED Output 3 Configuration Mode: Latched as ANEG_EN (register 0h, bit 12) during power up / reset. See "Strapping Options" Section for details. Active Low. The LED3 pin is also programmable via register 1eh. LED mode = 00 Collision Pin State LED Definition No Collision H Off Collision L On Activity Pin State LED Definition Activity - Toggle Pin State LED Definition LED mode = 01 LED mode = 10 Activity 30 PD# Ipu Activity Chip power down input (active low) Toggle 1 (high) = Normal operation 0 (low) = Power down June 2009 Revision 1.04 8 Micrel KSZ8001 (Note 1) Pin Number Pin Name Type 31 VDDRX Pwr 1.8V analog VDD (See "Circuit Design Reference for Power Supply" section for details) 32 33 34 RXRX+ FXSD/ FXEN I/O I/O Ipd/O 35 36 37 38 GND GND REXT VDDRCV Gnd Gnd I Pwr Physical receive or transmit `-' differential signal Physical receive or transmit `+' differential signal Fiber Mode Enable / Signal Detect in Fiber Mode If FXEN=0, FX mode is disable. The default is "0". (See "100BASE-FX Mode" section for details) Ground Ground Connect a 6.65K external resistor from this pin to ground 39 40 41 42 43 44 45 46 GND TXTX+ NC NC GND XO XI Gnd I/O I/O Gnd O I 47 VDDPLL Pwr 48 RST# Ipu Note 1: Pwr = power supply; Gnd = ground; I = input; O = output; I/O = bi-directional Ipu = input w/ internal pull up; Ipd = input w/ internal pull down; Pin Function 3.3V analog VDD (See "Circuit Design Reference for Power Supply" section for details) Ground Physical transmit or receive `-' differential signal Physical transmit or receive `+' differential signal No Connect No Connect Ground 25MHz crystal/oscillator clock connections Pins (XI, XO) connect to a crystal. If an oscillator is used, XI connects to a 3.3V tolerant oscillator and XO is a no connect. Clock is +/- 50ppm for both crystal and oscillator. 1.8V analog PLL VDD (See "Circuit Design Reference for Power Supply" section for details) Chip Reset Active low, minimum of 50 us pulse is required Ipu/O = input w/ internal pull up during reset, output pin otherwise; Ipd/O = input w/ internal pull down during reset, output pin otherwise; PD = strap pull down; PU = strap pull up; Note 2: MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. Note 3: RMII Rx Mode: The RXD[1..0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY. Note 4: SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represents a new byte of data. The MAC can sample any one of every 10 segments in 10MBit mode. June 2009 Revision 1.04 9 Micrel KSZ8001 Note 5: MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD [3..0] presents valid data from the MAC through the MII. TXD [3..0] has no effect when TXEN is de-asserted. Note 6: RMII Tx Mode: The TXD[1..0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of recovered data are recovered by the PHY. Note 7: SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode, each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore, every ten segments represents a new byte of data. The PHY can sample any one of every 10 segments in 10MBit mode. Strapping Options Pin Number 6, 5, 4, 3 Pin Name PHYAD[4:1] / RXD[0:3] Type Ipd/O 25 PHYAD0 / INT# Ipu/O 9 PCS_LPBK / RXDV Ipd/O 10 SMII_SELECT / RXC Ipd/O (Note 2) Description PHY Address latched at power-up / reset. The default PHY address is 00001. Enables PCS_LPBK mode at power-up / reset. PD (default) = Disable, PU = Enable Enables SMII mode at power-up / reset. PD (default) = Disable, PU = Enable 11 ISO / RXER Ipd/O Enables ISOLATE mode at power-up /reset. PD (default) = Disable, PU = Enable 21 RMII_SELECT Ipd/O Enables RMII mode at power-up / reset. / COL PD (default) = Disable, PU = Enable 22 RMII_BTB/ Ipd/O Enable RMII_BTB mode at power-up / reset. CRS PD (default) = Disable, PU = Enable Ipu/O Latched into Register 0h bit 13 during power-up / reset. 27 SPD100 / PD = 10Mb/s, PU (default) = 100Mb/s. No FEF / If SPD100 is asserted during power-up / reset, this pin also LED1 latched as the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0 means no Far _End _Fault.) 28 DUPLEX/ Ipu/O Latched into Register 0h bit 8 during power-up / reset. LED2 PD = Half Duplex, PU (default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as the Duplex support in register 4h. 29 NWAYEN/ Ipu/O Nway (auto-=Negotiation) Enable LED3 Latched into Register 0h bit 12 during power-up / reset. PD = Disable Auto-Negotiation, PU (default) = Enable AutoNegotiation 30 PD# Ipu Power Down Enable PU (default) = Normal operation, PD = Power down mode Note: Strap-in is latched during power up or reset. In some systems, the MAC RXD pins may drive high at all times causing the PHY strap-in to be latched high during power up or system reset. In this case, it is recommended to use a strong pull down to GND via 1kohm resistor on RXDV, RXC, and RXER pins. Otherwise, the PHY may stay in Isolate or loop back modes. June 2009 Revision 1.04 10 Micrel KSZ8001 37 VDDC GND 36 TXER GND 35 FXSD/FXEN 34 GND 13 14 15 TXC/REF_CLK KSZ8001S 16 TXEN RX+ 33 17 TXD0 RX- 32 18 TXD1 VDDRX 31 19 TXD2 PD# 30 20 TXD3 LED3/NWAYEN 29 21 COL/RMII LED2/DUPLEX 28 22 CRS/RMII_BTB 23 GND 24 VDDIO LED1/SPD100 27 LED0/TEST 26 INT#/PHYAD0 25 REXT 37 VDDRCV 38 GND 39 TX- 40 TX+ 41 RX+ 33 5 RXD1/PHYAD3 RX- 32 6 RXD0/PHYAD4 7 VDDIO 8 GND 9 RXDV/PCS_LPBK LED2/DUPLEX 28 10 RXC LED1/SPD100 27 11 RXER/ISO 12 GND June 2009 FXSD/FXEN 34 KSZ8001L VDDRX 31 PD# 30 LED3/NWAYEN 29 LED0/TEST 26 INT#/PHYAD0 25 VDDIO REXT 12 RXD2/PHYAD2 24 38 RXER/ISO 4 GND VDDRCV 11 3 23 39 CRS/RMII_BTB 40 GND 35 22 TXGND RXD3/PHYAD1 COL/RMII RXDV/PCS_LPBK RXC MDC 21 9 10 GND 36 2 TXD3 41 Top View LQFP 48 20 TX+ NC 42 GND MDIO TXD2 8 1 NC 43 42 TXD1 NC 19 VDDIO 18 43 7 GND 44 NC TXD0 RXD0/PHYAD4 17 44 6 XO 45 GND TXEN RXD1/PHYAD3 16 45 5 XI 46 XO TXC/REF_CLK RXD2/PHYAD2 15 46 4 VDDPLL 47 XI 3 TXER 47 RXD3/PHYAD1 MDC 14 48 2 VDDC RST# MDIO 13 Top View SSOP 48 VDDPLL 1 RST# 48 Pin Configuration Revision 1.04 11 Micrel KSZ8001 Functional Description 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, NRZ to NRZI conversion, MLT-3 encoding and transmission. The circuitry starts with a parallel-to-serial conversion, which converts the 25 MHz, 4-bit nibbles into a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.65 K resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX driver. 100BASE-TX Receive The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock recovery, NRZI to NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. In this design, the variable equalizer will make an initial estimation based upon comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effects of base line wander and to improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized 25 MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25 Mz reference clock and both TXC and RXC clocks continue to run. PLL Clock Synthesizer The KSZ8001 generates 125 Mz, 25 Mz and 20 Mz clocks for system timing. An internal crystal oscillator circuit provides the reference clock for the synthesizer. Scrambler/De-scrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. 10BASE-T Transmit When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KSZ8001 will continue to encode and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into the 100BASE- driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.5 V amplitude. The harmonic contents are at least 27 dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent noises at the RX+ or RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8001 decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in between data reception. June 2009 Revision 1.04 12 Micrel KSZ8001 SQE and Jabber Function (10BASE-T only) In 10BASE-T operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test of the 10BASE-T transmit/receive path and is called SQE test. The 10BASE-T transmitter will be disabled and COL will go high if TXEN is High for more than 20 ms (Jabbering). If TXEN then goes low for more than 250 ms, the 10BASE-T transmitter will be re-enabled and COL will go Low. Auto-Negotiation The KSZ8001 performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever autonegotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in either full- or half-duplex mode. Autonegotiation is disabled in FX mode. During auto-negotiation, the contents of Register 4, coded in Fast Link Pulse (FLP), will be sent to its link partner under the conditions of power-on, link-loss or re-start. At the same time, the KSZ8001 will monitor incoming data to determine its mode of operation. Parallel detection circuit will be enabled as soon as either 10BASE-T NLP (Normal Link Pulse) or 100BASE-TX idle is detected. The operation mode is configured based on the following priority: * Priority 1: 100BASE-TX, full-duplex * Priority 2: 100BASE-TX, half-duplex * Priority 3: 10BASE-T, full-duplex * Priority 4: 10BASE-T, half-duplex When the KSZ8001 receives a burst of FLP from its link partner with 3 identical link code words (ignoring acknowledge bit), it will store these code words in Register 5 and wait for the next 3 identical code words. Once the KSZ8001 detects the second code words, it then configures itself according to the above-mentioned priority. In addition, the KSZ8001 also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the KSZ8001 automatically configures to match the detected operating speed. MII Management Interface The KSZ8001 supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input / Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ8001. The MDIO interface consists of the following: * * * A physical connection including a data line (MDIO), a clock line (MDC) and an optional interrupt line (INTRPT) A specific protocol that runs across the above-mentioned physical connection and it also allows one controller to communicate with multiple KSZ8001 devices. Each KSZ8001 is assigned an MII address between 0 and 31 by the PHYAD inputs. An internal addressable set of fourteen 16-bit MDIO registers. Register [0:6] are required and their functions are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality. The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a status change on the KSZ8001 based upon 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh. MII Data Interface The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access Controller (MAC) to the KSZ8001, and for receiving data from the line. Normal data transmission is implemented in 4B Nibble Mode (4-bit wide nibbles). Transmit Clock (TXC): The transmit clock is normally generated by the KSZ8001 from an external 25MHz reference source at the X1 input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KSZ8001 normally samples these signals on the rising edge of the TXC. June 2009 Revision 1.04 13 Micrel KSZ8001 Receive Clock (RXC): For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-negotiation is disabled, the receive clock then operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KSZ8001 synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the clock with 10ns setup and hold times. Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the last bit of the packet. Receive Data Valid: The KSZ8001 asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way: * * For 100BASE-TX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the data packet. For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD " 5D" and remains asserted until the end of the packet. Error Signals: Whenever the KSZ8001 receives an error symbol from the network, it asserts RXER and drives "1110" (4B) on the RXD pins. When the MAC asserts TXER, the KSZ8001 will drive "H" symbols (a Transmit Error define in the IEEE 802.3 4B/5B code group) out on the line to force signaling errors. Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, then the KSZ8001 asserts its collision signal, which is asynchronous to any clock. RMII (Reduced MII) Data Interface RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2]. This interface has the following characteristics: * * * * It is capable of supporting 10Mb/s and 100Mb/s data rates A single clock reference is sourced from the MAC to PHY (or from an external source) It provides independent 2 bit wide (di-bit) transmit and receive data paths It uses TTL signal levels, compatible with common digital CMOS ASIC processes RMII Signal Definition Signal Name Direction (with respect to the PHY) Direction (with respect to the MAC) REF_CLK Input Input or Output CRS_DV RXD[1:0] TX_EN TXD[1:0] Output Output Input Input Use Synchronous clock reference for receive, transmit and control interface Carrier Sense/Receive Data Valid Receive Data Transit Enable Transit Data Input Input Output Output Input RX_ER Output Receive Error (Not Required) Note: Unused MII signals, TXD[3:2], TXER need to be tied to GND when RMII is used June 2009 Revision 1.04 14 Micrel KSZ8001 Reference Clock (REF_CLK) REF_CLK is a continuous 50 MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_ER. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device. Each PHY device shall have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single IC. Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 non-contiguous zeroes in 10 bits are detected carrier is said to be detected. Loss of carrier shall result in the de-assertion of CRS_DV synchronous to REF_CLK. So long as carrier criteria are being met, CRS_DV shall remain asserted continuously from the first recovered di-bit of the frame through the final recovered di-bit and shall be negated prior to the first REF_CLK that follows the final di-bit. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be "00" until proper receive signal decoding takes place (see definition of RXD[1:0] behavior). Receive Data [1:0] (RXD[1:0]) RXD[1:0] shall transition synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. In some cases (e.g. before data recovery or during error conditions) a pre-determined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] shall be "00" to indicate idle when CRS_DV is de-asserted. Values of RXD[1:0] other than "00" when CRS_DV is de-asserted are reserved for out-of-band signaling (to be defined). Values other than "00" on RXD[1:0] while CRS_DV is de-asserted shall be ignored by the MAC/repeater. Upon assertion of CRS_DV, the PHY shall ensure that RXD[1:0]=00 until proper receive decoding takes place. Transmit Enable (TX_EN) Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for trans-mission. TX_EN shall be asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are presented to the RMII. TX_EN shall be negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN shall transition synchronously with respect to REF_CLK. Transmit Data [1:0] (TXD[1:0]) Transmit Data TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the PHY. TXD[1:0] shall be "00" to indicate idle when TX_EN is de-asserted. Values of TXD[1:0] other than "00" when TX_EN is de-asserted are reserved for out-of-band signaling (to be defined). Values other than "00" on TXD[1:0] while TX_EN is disserted shall be ignored by the PHY. Collision Detection Since the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC can reliably regenerate the COL signal of the MII by Ending TX_EN and CRS_DV. During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers as a self-test. The Signal Quality Error (SQE) function will not be supported by the reduced MII due to the lack of the COL signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required. RX_ER The PHY shall provide RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-11 Receive State Diagram). RX_ER shall be asserted for one or more REF_CLK periods to indicate that an error (e.g. a coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sublayer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER shall transition synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER shall have no effect on the MAC. June 2009 Revision 1.04 15 Micrel KSZ8001 RMII AC Characteristics RMII Transmit Timing 20ns REF_CLK t1 t2 TXD[1:0] TXEN Parameter REF_CLK Frequency TXD[1:0], TX_EN, Data Setup to REF_CLK rising edge TXD[1:0], TX_EN, Data hold from REF_CLK rising edge Min Typ 50 Max Unit MHz 4 ns 2 ns RMII Receive Timing 20ns REF_CLK RXD[1:0] RXDV RXER tod Parameter REF_CLK Frequency RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge Min Typ 50 2.8 June 2009 Max Unit MHz 10 ns Revision 1.04 16 Micrel KSZ8001 SMII Signal Definition SMII is composed of two signals per port, a global synchronization signal, and a global 125MHz reference clock. All signals are synchronous to the clock. All SMII I/F uses a common 125MHz reference clock and SYNC signals that are synchronous to the reference clock. There are two signals in SMII from MAC-to-PHY for each port (TXD and TxSYNC), and one signal per port from PHY-to-MAC (RXD). The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements: * Convey complete MII information between a 10/100 PHY and MAC with two pins per port. * Allow a multi-port MAC/PHY communication with one system clock. * Operate in both half and full duplex. * Per packet switching between 10Mbit and 100Mbit data rates. * Allow direct MAC-to-MAC communication. SMII Signals Signal Name RX TX SYNC Clock From PHY MAC MAC System To MAC PHY PHY MAC&PHY Use Receive Data and Control Transmit Data and Control Synchronization Synchronization Receive Path Receive data and control information are signaled in ten bit segments. In 100Mbit mode, each segment represents a new byte of data. In 10Mbit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC can simply any one of every 10 segment ion 10Mbit mode. Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks. Receive Sequence Diagram R X _C LK R X _SYN C RX CRS R X_D V RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RX contains all of the information found on the receive path of the standard MII. Bits Purpose CRS Carrier Sense - identical to MII, except that it is not an asynchronous signal RX_DV Receive Data Valid - identical to MII RXD7-0 Encoded Data, see the RXD0-7 Encoding table RX - Bit Description RXD7-0 are used to convey packet data, RX_ER, and PHY status. The MAC can infer the meaning of RXD on a segment-by-basis by encoding the two control bits. June 2009 Revision 1.04 17 Micrel KSZ8001 CRS RX_DV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 X 0 RX_ER from previous frame Speed 0=10Mbit 1=100Mbit Duplex 0=Half 1=Full Link 0=Down 1=Up Jabber 0=OK 1=Error Upper Nibble 0=invalid 1=valid False Carrier Detected 1 X 1 One Data Byte (Two MII Data Nibble) TXD7 - 0 Encoding Inter-frame status bit RXD5 conveys the validity of the upper nibble of the byte of the previous frame. Inter-frame status bit RXD0 indicates whether or not the PHY detected an error somewhere on the previous frame. Both of these bits should be valid in the segment immediately following a frame, and should stay valid until the first data segment of the next frame begins. When asserted, inter-frame status bit RXD6 indicates that the PHY has detected a false carrier event. In order to send receive data to the MAC synchronous to the reference clock, the PHY must pass the data through an elasticity FIFO to handle any difference between the reference clock rate and the clock at the packet source. The Ethernet specification calls for packet data to be referenced to a clock with a frequency tolerance of 100ppm (0.01%); however, it is not uncommon to encounter Ethernet stations with clocks that have frequency errors up to 0.1%. Therefore, the elasticity FIFO should be at least 27 bits * long, filling to the halfway point before beginning valid data transfer via RX. RX_ER should be asserted if, during the reception of a frame, this FIFO overflows or underflows. Only RXD and RX_DV should be passed through the elasticity FIFO. CRS should not be passed through the elasticity FIFO. Instead, CRS should be asserted for the time the `wire' is busy receiving a frame. Transmit Path Transmit data and control information are signaled in ten bit segments, just like the receive path. In 100Mbit mode, each segment represents anew byte of data. In 10Mbit mode each segment is repeated ten times; therefore, every ten segments represents a new byte of data. The PHY can sample any one of every 10 segments in 10Mbit mode. Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks. Transmit Sequence Diagram T X _C L K T X _S Y N C TX T X _E R Bits TX_EN TX_ER TXD7-0 TX- Bit Description T X _E N TXD 0 TXD 1 TXD 2 TXD 3 TXD 4 TXD 5 TXD 6 TXD 7 Purpose Transmit Enable - identical to MII Transmit Error - identical to MII Encoded Data - see TXD7-0 Encoding Table June 2009 Revision 1.04 18 Micrel KSZ8001 As far as the PHY is concerned, TXD7-0 are used to convey only packet data. To allow for a direct MAC-to-MAC connection, the MAC uses TXD7-0 to signal `status' in between frames. TX_ER x TX_EN 0 x TXD7 - 0 Encoding TXD0 Use to force an error in a direct MAC to MAC connection 1 TXD1 1 100MBit TXD2 1 Full Duplex TXD3 1 Link Up TXD4 0 No Jabber TXD7-5 1 One Data Byte (Two MII Data Nibbles) Collision Detection Collisions occur when CRS and TX_EN are simultaneously asserted. For this to work, the PHY must ensure that CRS is not affected by its transmit path. DC Specification Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Symbol Vih Vil Iih Iil Min 2.0 -10 -10 June 2009 Max 0.8 10 10 Units Volts Volts uA uA Revision 1.04 19 Micrel KSZ8001 Timing Specification Parameter Input Setup Input Hold Output Delay Min 1.5 1 1.5 Max 5 June 2009 Units ns ns ns Revision 1.04 20 Micrel KSZ8001 HP Auto Crossover (Auto MDI/MDI-X) Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The assignment of pin-outs for a 10/100 BASE-T crossover function cable is shown below. This feature can eliminate the confusion in real applications by allowing both straight cable and crossover cables. This feature is controlled by register 1f:13, see "Register 1fh" section for details. S tr a ig h t T h r o u g h C a b le 1 0 /1 0 0 B a s e -T M e d ia D e p e n d e n t I n t e r f a c e 1 0 /1 0 0 B a s e -T M e d ia D e p e n d e n t I n t e r f a c e 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 T r a n s m it P a ir R e c e iv e P a ir R e c e iv e P a ir T r a n s m it P a ir M o d u la r C o n n e c t o r (R J 4 5 ) M o d u la r C o n n e c t o r (R J 4 5 ) N IC HUB ( R e p e a t e r o r S w it c h ) C r o s s o v e r C a b le 1 0 /1 0 0 B A S E - T M e d ia D e p e n d e n t In te r f a c e 1 0 /1 0 0 B a s e -T M e d ia D e p e n d e n t I n te r f a c e 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 R e c e iv e P a ir R e c e iv e P a ir T r a n s m it P a ir T r a n s m it P a ir M o d u la r C o n n e c t o r ( R J 4 5 ) M o d u la r C o n n e c t o r ( R J 4 5 ) HUB ( R e p e a t e r o r S w it c h ) HUB ( R e p e a t e r o r S w it c h ) June 2009 Revision 1.04 21 Micrel KSZ8001 Auto MDI/MDI-X Cross-Over Transformer Connection KSZ8001 features HP Auto MDI/MDI-X crossover and requires symmetric transformers that support Auto MDI/MDI-X. "Selection of Isolation Transformer" for a list of transformers that support Auto MDI/MDI-X. See Power Management The KSZ8001 offers the following modes for power management: * * Power Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# Low. In the power down state, the KS8061 disables all internal functions and drives output pins to logic zero, except for the MII serial management interface. Power Saving Mode: writing to register 1fh.10 can disable this mode. The KSZ8001 will then turn off everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the KSZ8001 will shutdown most of the internal circuits to save power if there is no link. Power Saving mode will be in this most effective state when AutoNegotiation Mode is enabled. 100BASE-FX Mode 100BASE-FX mode is activated when FXSD/FXEN is higher than 0.6V (This pin has a default pull down). Under this mode, the autonegotiation and auto-MDIX features are disabled. In fiber operation FXSD pin should connect to the SD (signal detect) output of the fiber module. The internal threshold of FXSD is around Vdd +/- 50 mV (2.2V +/- 0.05V at 3.3V). Above this level, it is considered Fiber signal detected, and the operation is summarized in the following table: FXSD/FXEN Less than 0.6V Less than 2.15V, but greater than 0.6V Greater than 2.25V Condition 100TX mode FX mode No signal detected FEF generated FX mode Signal detected To ensure proper operation, the swing of fiber module SD should cover the threshold variation. A resistive voltage divider is recommended to adjust the SD voltage range. FEF (Far End Fault), repetition of a special pattern, which consists of 84-ones and 1-zero, is generated under "FX mode with no signal detected". The purpose of FEF is to notify the sender of a faulty link. When receiving a FEF, the LINK will go down to indicate a fault, even with fiber signal detected. The transmitter is not affected by receiving a FEF and still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin27 low, please refer to "Strapping Options" section. Media Converter Operation The KSZ8001 is capable of performing media conversion with 2 parts in a back-to-back RMII mode as indicated in the diagram. Both parts are in RMII mode and with RMII_BTB asserted (pin21 & 22 strapped high). One part is operating at TX mode and the other in FX mode. Both parts can share a common 50MHz oscillator. Under this operation, auto-Negotiation on the TX side will prohibit 10BASE-T link up. Additional options can be implemented under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order to do this, RXD2 and TXD2 pins need to be connected via an inverter. When TXD2 pin is high in both the copper and fiber operation, it disables transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can indicate if a line signal is detected. TXD3 should be tied low and RXD3 let float. Please contact your local Micrel FAE for a Media Converter reference design. June 2009 Revision 1.04 22 Micrel KSZ8001 Vcc 21 22 Pin Rx +/- KSZ8001 RxD TxD Tx +/TxC/ Ref_CLK OSC FTx KSZ8001 FRx 50 MHz TxC/ Ref_CLK (Fiber Mode) Pin 34 TxD RxD Pin 21 22 Vcc To the SD pin of the Fiber Module LinkMD Cable Diagnostics The KSZ8001 utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDIX pairs and analyzing the shape of the reflected signal. Timing the duration gives an indication of the distance to the cabling fault with maximum distance of 200 m and accuracy of +/- 2 m. Cable diagnostics are only valid for copper connections and do not support fiber optic operation. LinkMD is used by accessing register 1dh, the LinkMD Control/Status register in conjunction with register 1fh, the 100BASE-TX PHY Controller register. To use LinkMD, HP Auto-MDIX is disabled by writing a `1' to 1f:13 to enable manual control over which pair is used to transmit the LinkMD pulse. The self-clearing Cable diagnostic test enable bit, 1d.15 is set to `1' to start the test on this pair. When 1d.15 returns to `0', the test is complete. The test result is returned in 1d.14:13 and the distance is returned in 1d.8:0. The cable diagnostic test results are as follows: * * * * 00 = Valid test, normal condition 01 = Valid test, open circuit in cable 10 = Valid test, short circuit in cable 11 = Invalid test, LinkMD failed The `11' case, Invalid test, occurs when it is not possible for the KSZ8001 to shut down the link partner. In this case, the test is not run, since it would not be possible for the KSZ8001 to determine if the detected signal is a reflection of the signal generated or a signal from another source. Cable length can be determined by multiplying the contents of 1d.8:0 by 0.39. This constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. June 2009 Revision 1.04 23 Micrel KSZ8001 Reference Clock Connection Options KSZ8001 is capable of performing three different kinds of clock speed options for connecting the external reference clock depends upon the different interface of using MII/RMII/SMII. The figures below illustrate the recommended connection for using the different interface options. Please see the selection of reference crystal table for specifications. XI 25MHz Osc +/-50ppm XO NC NC 25MHz Oscillator Reference Clock Connection Diagram 27pF 27pF XI 27pF 27pF XO 25MHz Xtal +/-50ppm 25MHz Crystal Reference Clock Connection Diagram VCC XI 10K 50/125MHz Osc +/-50ppm NC NC XO REF_CLK 50/125 MHz Oscillator Reference Clock Connection for RMII/SMII Mode Diagram June 2009 Revision 1.04 24 Micrel KSZ8001 Circuit Design Reference for Power Supply The following diagram shows the power connections for the single 3.3V supply KSZ8001L and KSZ8001SL devices. 3.3A Ferrite Bead 1.8PLL 1uF 0.1uF 0.1uF 3.3V 7 VDDIO VDDRX VDDPLL VDDRCV Ferrite Bead 1.8V 1uF 0.1uF 31 47 38 1.8A 0.1uF 13 VDDC Ferrite Bead VIN VOUT 1.8V LDO Regulator 24 VDDIO GND KSZ8001L KSZ8001SL 8 12 23 35 36 39 44 June 2009 Revision 1.04 25 Micrel KSZ8001 Register Map Register No. 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h-14h 15h 16h - 1ah 1bh 1ch 1dh 1eh 1fh Address Name Description Basic Control Register Basic Status Register PHY Identifier I PHY Identifier II Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability Reserved RXER Counter Register Reserved Interrupt Control/Status Register Reserved LinkMD Control/Status Register PHY Control Register 100BASE-TX PHY Control Register Description Mode Default RW/ SC RW 0 RW Set by SPD100 RW Set by NWAYEN RW 0 RW Set by ISO RW/ SC RW 0 RW 0 RO RW 0 0 Register 0h - Basic Control 0.15 Reset 1 = software reset. Bit is self-clearing 0.14 Loop-back 0.13 Speed Select (LSB) 0.12 AutoNegotiation Enable 0.11 Power Down 1 = loop-back mode 0 = normal operation 1 = 100Mb/s 0 = 10Mb/s Ignored if Auto-Negotiation is enabled (0.12 = 1) 1 = enable auto-negotiation process (override 0.13 and 0.8) 0 = disable auto-negotiation process 1 = power down mode 0 = normal operation 0.10 Isolate 0.9 Restart AutoNegotiation 0.8 Duplex Mode 0.7 Collision Test 0.6:1 0.0 Reserved Disable Transmitter 1 = electrical isolation of PHY from MII and TX+/TX0 = normal operation 1 = restart auto-negotiation process 0 = normal operation. Bit is self-clearing 1 = full duplex 0 = half duplex 1 = enable COL test 0 = disable COL test 0 = enable transmitter 1 = disable transmitter June 2009 0 Set by DUPLEX Revision 1.04 26 Micrel Address KSZ8001 Name Description Mode Default RO 0 RO 1 RO 1 RO 1 RO 1 RO RO 0 1 RO 0 1 = remote fault 0 = no remote fault 1 = capable to perform auto-negotiation 0 = unable to perform auto-negotiation RO/ LH RO 0 1 = link is up 0 = link is down 1 = jabber detected 0 = jabber not detected. Default is Low 1 = supports extended capabilities registers RO/ LL RO/ LH RO 0 RO 0022h RO 000101 RO RO 100001 1010 RW 0 RO RW 0 0 RO 0 Register 1h - Basic Status 1.15 100BASE-T4 1.14 100BASE-TX Full Duplex 1.13 100BASE-TX Half Duplex 1.12 10BASE-T Full Duplex 1.11 10BASE-T Half Duplex 1.10:7 1.6 Reserved No Preamble 1.5 AutoNegotiation Complete 1.4 Remote Fault 1.3 1.2 AutoNegotiation Ability Link Status 1.1 Jabber Detect 1.0 Extended Capability 1 = T4 capable 0 = not T4 capable 1 = capable of 100BASE-X full duplex 0 = not capable of 100BASE-X full duplex 1 = capable of 100BASE-X half duplex 0 = not capable of 100BASE-X half duplex 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex capability 1 = 10Mbps with half duplex 0 = no 10Mbps with half duplex capability 1 = preamble suppression 0 = normal preamble 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 1 0 1 Register 2h - PHY Identifier 1 2.15:0 PHY ID Number rd th Assigned to the 3 through 18 bits of the Organizationally Unique Identifier (OUI). Kendin Communication's OUI is 0010A1 (hex) Register 3h - PHY Identifier 2 3.15:10 PHY ID Number 3.9:4 3.3:0 Model Number Revision Number th th Assigned to the 19 through 24 bits of the Organizationally Unique Identifier (OUI). Kendin Communication's OUI is 0010A1 (hex) Six bit manufacturer's model number Four bit manufacturer's model number Register 4h - Auto-Negotiation Advertisement 4.15 Next Page 4.14 4.13 Reserved Remote Fault 4.12 : 11 Reserved 1 = next page capable 0 = no next page capability. 1 = remote fault supported 0 = no remote fault June 2009 Revision 1.04 27 Micrel KSZ8001 Address 4.10 Name Pause 4.9 100BASE-T4 4.8 100BASE-TX Full Duplex 4.7 100BASE-TX 4.6 10BASE-T Full Duplex 4.5 10BASE-T 4.4:0 Selector Field Description 1 = pause function supported 0 = no pause function 1 = T4 capable 0 = no T4 capability 1 = TX with full duplex 0 = no TX full duplex capability 1 = TX capable 0 = no TX capability 1 = 10Mbps with full duplex 0 = no 10Mbps full duplex capability 1 = 10Mbps capable 0 = no 10Mbps capability [00001] = IEEE 802.3 Mode RW Default 0 RO 0 RW Set by SPD100 & DUPLEX RW Set by SPD100 RW RW Set by DUPLEX 1 RW 00001 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 00001 RO 0 Register 5h - Auto-Negotiation Link Partner Ability 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved 5.11:10 Pause 5.9 100 BASE-T4 5.8 100BASE-TX Full Duplex 5.7 100BASE-TX 5.6 10BASE-T Full Duplex 5.5 10BASE-T 5.4:0 Selector Field 1 = next page capable 0 = no next page capability 1 = link code word received from partner 0 = link code word not yet received 1 = remote fault detected 0 = no remote fault 5.10 5 .11 0 No PAUSE 1 Asymmetric PAUSE (link partner) 0 Symmetric PAUSE 1 Symmetric & Asymmetric PAUSE (local device) 1 = T4 capable 0 = no T4 capability 1 = TX with full duplex 0 = no TX full duplex capability 1 = TX capable 0 = no TX capability 1 = 10Mbps with full duplex 0 = no 10Mbps full duplex capability 1 = 10Mbps capable 0 = no 10Mbps capability [00001] = IEEE 802.3 Register 6h - Auto-Negotiation Expansion 6.15:5 Reserved June 2009 Revision 1.04 28 Micrel KSZ8001 Address 6.4 Name Parallel Detection Fault 6.3 Link Partner Next Page Able 6.2 Next Page Able 6.1 Page Received 6.0 Link Partner AutoNegotiation Able Description 1 = fault detected by parallel detection 0 = no fault detected by parallel detection. 1 = link partner has next page capability 0 = link partner does not have next page capability 1 = local device has next page capability 0 = local device does not have next page capability 1 = new page received 0 = new page not yet received 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability Mode RO/ LH RO Default 0 RO 1 RO/ LH RO 0 RW 0 RO 0 RW 1 RW 0 RO 0 RW 001 1 = additional Next Page(s) will follow 0 = last page 1 = successful receipt of link word 0 = no successful receipt of link word 1 = Message Page 0 = Unformatted Page 1 = able to act on the information 0 = not able to act on the information RO 0 RO 0 RO 0 RO 0 1 = previous value of transmitted Link Code Word equal to logic zero 0 = previous value of transmitted Link Code Word equal to logic one RO 0 RO 0 RO 0000 0 0 Register 7h - Auto-Negotiation Next Page 7.15 Next Page 7.14 Reserved 7.13 Message Page 7.12 Acknowledge2 7.11 Toggle 7.10:0 Message Field 1 = additional next page(s) will follow 0 = last page 1 = message page 0 = unformatted page 1 = will comply with message 0 = cannot comply with message 1 = previous value of the transmitted link code word equaled logic One 0 = logic Zero 11-bit wide field to encode 2048 messages Register 8h - Link Partner Next Page Ability 8.15 Next Page 8.14 Acknowledge 8.13 Message Page 8.12 Acknowledge2 8.11 Toggle 8.10:0 Message Field Register 15h - RXER Counter 15.15:0 RXER Counter RX Error counter for the RX_ER in each package June 2009 Revision 1.04 29 Micrel Address KSZ8001 Name Description Mode Default 1=Enable Jabber Interrupt 0=Disable Jabber Interrupt RW 0 1=Enable Receive Error Interrupt 0=Disable Receive Error Interrupt RW 0 1=Enable Page Received Interrupt 0=Disable Page Received Interrupt RW 0 1= Enable Parallel Detect Fault Interrupt 0= Disable Parallel Detect Fault Interrupt RW 0 1= Enable Link Partner Acknowledge Interrupt 0= Disable Link Partner Acknowledge Interrupt RW 0 1= Enable Link Down Interrupt 0= Disable Link Down Interrupt RW 0 1= Enable Remote Fault Interrupt 0= Disable Remote Fault Interrupt RW 0 1= Enable Link Up Interrupt 0= Disable Link Up Interrupt RW 0 1= Jabber Interrupt Occurred 0= Jabber Interrupt Does Not Occurred 1= Receive Error Occurred 0= Receive Error Does Not Occurred 1= Page Receive Occurred 0= Page Receive Does Not Occurred 1= Parallel Detect Fault Occurred 0= Parallel Detect Fault Does Not Occurred 1= Link Partner Acknowledge Occurred 0= Link Partner Acknowledge Does Not Occurred 1= Link Down Occurred 0= Link Down Does Not Occurred 1= Remote Fault Occurred 0= Remote Fault Does Not Occurred 1= Link Up Interrupt Occurred 0= Link Up Interrupt Does Not Occurred RO/ SC RO/ SC RO/ SC RO/ SC RO/ SC 0 RO/ SC RO/ SC RO/ SC 0 RW/ SC 0 Register 1bh - Interrupt Control/Status Register 1b.15 1b.14 1b.13 1b.12 1b.11 1b.10 1b.9 1b.8 1b.7 Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Enable Link Up Interrupt Enable Jabber Interrupt 1b.6 Receive Error Interrupt 1b.5 Page Receive Interrupt 1b.4 Parallel Detect Fault Interrupt 1b.3 Link Partner Acknowledge Interrupt 1b.2 Link Down Interrupt 1b.1 Remote Fault Interrupt 1b.0 Link Up Interrupt 0 0 0 0 0 0 Register 1dh - LinkMD Control/Status Register 1d.15 Cable diagnostic test enable 0 = Indicates cable diagnostic test has completed and the status information is valid for read. 1 = the cable diagnostic test is activated. This bit is self-clearing. June 2009 Revision 1.04 30 Micrel KSZ8001 Address 1d.14:13 Name Cable diagnostic test result 1d.12:9 Reserved 1d.8:0 Cable fault counter Description [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test failed Mode RO Default 0 Distance to fault, approximately 0.39m*cabfaultcnt value RO 0 RW 0 Register 1eh - PHY Control 1e:15:14 LED mode [00] = LED3 <- collision LED2 <- full duplex LED1 <- speed LED0 <- link/activity [01] = LED3 <- activity LED2 <- full duplex/collision LED1 <- speed LED0 <- link [10] = LED3 <- activity LED2 <- full duplex LED1 <- 100Mbps link LED0 <- 10Mbps link 1e.13 Polarity 1e.12 Far end fault detect 1e.11 MDIX/MDI state 1e:10:8 Reserved 1e:7 Remote loopback 1e:6:0 Reserved [11] = reserved 0 = Polarity is not reversed 1 = Polarity is reversed 0 = Far end fault detected 1 = Far end fault not detected 0 = MDIX 1 = MDI 0: normal mode 1: remote (analog) loop back is enable RO RO RO RW 0 RW 1 Register 1fh - 100BASE-TX PHY Controller 1f:15 HP_MDIX 0: Micrel Auto MDI/MDI-X mode 1: HP Auto MDI/MDI-X mode June 2009 Revision 1.04 31 Micrel Address 1f:14 KSZ8001 Name MDI/MDI-X Select Description When Auto MDI/MDI-X is disabled, Default 0 RW 0 RO 0 RW 0 RW 1 RW 0 RW 1 RO 0 RO 0 RO 0 RO 0 RW 0 RW 0 0= 1f:13 Pairswap disable 1f.12 Energy detect 1f.11 Force link 1f.10 Power Saving 1f.9 Interrupt Level 1f.8 Enable Jabber 1f.7 AutoNegotiation Complete 1f.6 Enable Pause (Flow-Control Result) PHY Isolate 1f.5 1f.4:2 Operation Mode Indication 1f.1 Enable SQE test 1f.0 Disable Data Scrambling Transmit on TX+/- (pins 41,40) Receive on RX+/- (pins 33,32) 1 = Transmit on RX+/- (pins 33,32) Receive on TX+/- (pins 41,40) 1 = disable MDI/MDIX 0 = enable MDI/MDIX 1 = presence of signal on RX+/- analog wire pair 0 = no signal detected on RX+/1 = force link pass 0 = normal link operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. 1 = enable power saving 0 = disable 1 = interrupt pin active high 0 = active low 1 = enable jabber counter 0 = disable 1 = auto-negotiation complete 0 = not complete This bit has the same definition as register 1.5. 1 = flow control capable 0 = no flow control Mode RW 1 = PHY in isolate mode 0 = not isolated [000] = still in auto-negotiation [001] = 10BASE-T half duplex [010] = 100BASE-TX half duplex [011] = default [101] = 10BASE-T full duplex [110] = 100BASE-TX full duplex [111] = PHY/MII isolate 1 = enable SQE test 0 = disable 1 = disable scrambler 0 = enable June 2009 Revision 1.04 32 Micrel KSZ8001 Absolute Maximum Rating (Note 1) Operating Range (Note 2) Storage Temperature (TS) ............ -55C to +150C Supply Referenced to GND...... ..........-0.5V to +4.0 All pins ...........................................-0.5V to +4.0 Supply Voltage (VDDPLL, VDDRX, VDDC)..........................1.8V 5% (VDDRCV, VDDIO)..................................3.3V 5% Ambient Temperature Commercial (TAC)......0C to +70C Ambient Temperature Industrial (TAI).......-40C to +85C Important: Please read the Notes at the end of the Electrical Characteristics. June 2009 Revision 1.04 33 Micrel KSZ8001 Package Thermal Resistance (JA)(Note 3) JA Thermal Resistance JA JA JC Airflow Velocity (m/s) 0 1 2 0 KSZ8001L / KSZ8001LI 83.56 77.08 72.36 35.90 KSZ8001SL / KSZ8001SLI 75.19 68.20 66.43 42.65 KSZ8001S 42.43 36.19 34.24 6.75 Electrical Characteristics (Note4) Symbol Parameter Condition Min Typ Max Unit (Note 5) Total Supply Current KSZ8001L - Current consumption is for the single 3.3V supply KSZ8001L device only, and includes the 1.8V supply voltages (VDDRX, VDDPLL) that are provided by the KSZ8001L via power output pin 13 (VDDC). - Transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for 10BASE-T. IDD1 100BASE-TX Chip only, no transformer 52 mA IDD2 10BASE-T Chip only, no transformer 32 mA mA IDD3 Power Saving Mode Ethernet cable disconnected 35 IDD4 SW Power Down Mode Register (software) power down 5 mA IDD5 Power down pin (PD#) Chip (hardware) power down 3 mA TTL Inputs VIH Input High Voltage VIL Input Low Voltage IIN Input Current 2.0 VIN = GND - VDD V -10 0.8 V 10 A TTL Outputs VOH Output High Voltage IOH = -4mA 2.4 V VOL Output Low Voltage 0.4 V I IOZ I Output Tri-State Leakage 10 A 100BASE-TX Transmit (measured differentially after 1:1 transformer) VO Peak Differential Ouput Voltage 50 from each output to VDD VIMB Output Voltage Imbalance 50 from each output to VDD tr, tt VSET 0.95 1.05 V 2 % Rise/Fall Time 3 5 ns Rise/Fall Time Imbalance 0 0.5 ns Duty Cycle Distortion 0.25 ns Overshoot 5 % Refernce Voltage of ISET 0.75 Propagation Delay 45 60 Ns Jitter 0.7 1.4 ns(pk-pk) June 2009 V Revision 1.04 34 Micrel KSZ8001 10BASE-T Transmit (measured differentially after 1:1 transformer) VP Peak Differential Ouput Voltage 50 from each output to VDD VIMB Output Voltage Imbalance 50 from each output to VDD tr, tt Rise/Fall Time 2.2 2.8 3.5 25 V ns ns Clock Outputs X1, X2 Crystal Oscillator 25 MHz RXC100 Receive Clock, 100TX 25 MHz RXC10 Receive Clock, 10T 2.5 MHz Receive Clock Jitter 3.0 ns(pk-pk) TXC100 Transmit Clock, 100TX 25 MHz TXC10 Transmit Clock, 10T 2.5 MHz Transmit Clock Jitter 1.8 ns(pk-pk) Note 1: Note 2: Note 3: Note 4: Note 5: Exceeding the absolute rating(s) may cause permanent damage to the device. Operating at maximum conditions for extended periods may affect device reliability. This device is not guaranteed to operate beyond its specified operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground to VDD). No HS (heat spreader) in package. Specification for packaged product only. 100% data transmission in full-duplex mode and minimum IPG with 130-meter cable. June 2009 Revision 1.04 35 Micrel KSZ8001 Timing Diagrams 10 B aseT M II T ra n sm it T im in g tH D 2 TXC TXEN T X D [3:0] CRS T X P /T X M tSU 2 tH D 1 tSU 1 tC R S1 t C R S2 t LA T V a lid D a ta S Q E T im in g TXC TXEN COL tSQ E t SQ E P m in. t SU 1 t SU 2 tH D 1 tH D 2 t C R S1 t C R S2 t LA T t SQ E t SQ E P T X D [3 :0 ] S etup to T X C H igh T X E N S etup to T X C H igh T X D [3 :0 ] H o ld after T X C H ig h T X E N H o ld after T X C H ig h T X E N H igh to C R S asserted laten cy T X E N L o w to C R S d e-asserted laten cy T X E N H igh to T X P /T X M o utp ut (T X laten cy) C O L (S Q E ) D elay after T X E N d e-asserted C O L (S Q E ) P u lse D uratio n June 2009 typ . m ax . 1 0 ns 1 0 ns 0 ns 0 ns 4BT 8BT 4BT 2 .5 u s 1 .0 u s Revision 1.04 36 Micrel KSZ8001 100BaseTX MII Transmit Timing TXC tSU2 tHD2 TXEN tSU1 TXD[3:0], TXER tHD1 Data In tCRS2 tCRS1 CRS tLAT TX+/TX- Symbol Out min. tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT TXD[3:0] Setup to TXC High TX_ER Setup to TXC High TXD[3:0] Hold after TXC High TXER Hold after TXC High TXEN Hold after TXC High TXEN High to CRS asserted latency TXEN Low to CRS de-asserted latency TXEN High to TX+/TX- output (TX latency) typ. max. 10ns 10ns 0ns 0ns 0ns 4BT 4BT 7BT June 2009 Revision 1.04 37 Micrel KSZ8001 1 00 B aseT X M II R eceiv e T im in g R X + /R X - S tart o f S tream End of S tream tC R S1 CRS tC R S2 tR L A T RXDV R X D [3 :0 ] RXER tH D tS U tW H RXC tW L tP m in . tP tW L tW H tSU tH D tR L A T tC R S1 tC R S2 R X C p erio d R X C p u lse w id th R X C p u lse w id th R X D [3 :0 ], R X E R , R X D V setu p to risin g ed g e o f R X C R X D [3 :0 ], R X E R , R X D V h o ld fro m risin g ed g e o f R X C C R S to R X D laten cy , 4 B o r 5B alig n ed "S tart o f S tream " to C R S asserted "E n d o f S tream " to C R S d e-asserted June 2009 1B T ty p . m ax . 40ns 20ns 20ns 20ns 20ns 2B T 140ns 170ns 3B T Revision 1.04 38 Micrel KSZ8001 Auto Negotiation / Fast Link Pulse Timing FLP Burst FLP Burst TX+/TX- tFLPW tBTB TX+/TX- Clock Pulse Data Pulse tPW tPW Clock Pulse Data Pulse tCTD tCTC tBTB tFLPW tPW tCTD tCTC FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst min. typ. max. 8ms 16ms 2ms 100ns 69us 136us 24ms 17 June 2009 33 Revision 1.04 39 Micrel KSZ8001 Serial Management Interface Timing tP MDC tMD1 MDIO (Into Chip) tMD2 Valid Data Valid Data tMD3 MDIO (Out of Chip) Valid Data min. tP tMD1 tMD2 tMD3 MDC period MDIO Setup to MDC (MDIO as input) MDIO Hold after MDC (MDIO as input) MDC to MDIO Valid (MDIO as output) typ. max. 400 ns 10ns 10ns 222ns June 2009 Revision 1.04 40 Micrel KSZ8001 Reset Timing Diagram Supply Voltage tsr RST_N Strap-In Value Reset Timing Parameters Parameter tsr Description Stable supply voltages to reset high Min 50 Max Units us Reset Circuit Diagram Micrel recommends the following discrete reset circuit when powering up the KSZ8001 device. VCC D1: 1N4148 KSZ8001 D1 R 10K RST# C 10uF Recommended Reset Circuit June 2009 Revision 1.04 41 Micrel KSZ8001 For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), the following reset circuit is recommended. VCC KSZ8001 R 10K D1 CPU/FPGA RST# RST_OUT_n D2 C 10uF D1, D2: 1N4148 Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommend to power up VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. June 2009 Revision 1.04 42 Micrel KSZ8001 Reference Circuit for Strapping Option Configuration The following figure shows the reference circuits for external pull-up and pull-down on the LED strapping pins. 3.3 V 220 Pull U p 10 LED pin KSZ8001 3.3 V Pull Down 220 LED pin KSZ8001 1 Reference circuits for unm anaged programm ing through LED ports June 2009 Revision 1.04 43 Micrel KSZ8001 Selection of Isolation Transformer A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Transformer Selection Criteria Parameter Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) Value 1 CT : 1 CT 350 uH 0.4 uH 12 pF 0.9 Ohms 1.0 dB 1500 Vrms Test Condition 100 mV, 100 kHz, 8 mA 1 MHz (min.) 0-65 MHz Magnetic Vendor Selection Lists Single Port Magnetic manufacturer Pulse Bel Fuse Bel Fuse Bel Fuse YCL Transpower Delta LanKom Part number H1102 S558-5999-U7 SI-46001 SI-50170 PT163020 HB726 LF8505 LF-H41S AUTO MDIX Yes Yes Yes Yes Yes Yes Yes Yes Number of port 1 1 1 1 1 1 1 1 Selection of Reference Crystal An oscillator or crystal with the following typical characteristics is recommended. Charateristics Frequency Frequency Tolerance(max) Load Capacitance (max) Series Resistance Value 25.00000 Units MHz ppm 50 20 40 pF June 2009 Revision 1.04 44 Micrel KSZ8001 Package Information June 2009 Revision 1.04 45 Micrel KSZ8001 MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL: +1 (408) 944-0800 FAX: +1 (408) 944-0970 WEB: http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. June 2009 Revision 1.04 46