STiH271EL HD cable/terrestrial STB processor with integrated demodulator and low-power standby controller Features Description * ST40 applications CPU with 256 Kbyte L2 cache The STiH271EL uses the latest process technology to provide a cost-effective, feature rich, highly integrated SoC for set-top boxes (STBs). It is targeted at the advanced decoding STB market across cable and terrestrial networks, and is suitable for operator markets and retail markets worldwide. * 16-bit LMI supporting DDR3 up to 667 MHz ti a l * Decoding of H.264, MPEG2, VC-1 video streams * 3DTV signaling compatible with HDMI 1.4b * Integrated low-power standby controller The STiH271EL provides a solution for operators and manufacturers to specify and quickly deploy a range of cost-effective, high-performance zapper STBs. Fast time to market is enabled by the STiH271EL's pre-defined profile with DolbyTM audio enabled (license required), without RoviTM and without advanced security features. en * Low-power process and architecture fid * High-quality video resizing and de-interlacing * Targets two layer PCBs for cost-effective zapper and STB applications The STiH271EL integrates a high-performance dual mode, cable/terrestrial receiver, supporting DVB-C or DVB-T reception, channel demodulation, and forward error correction (FEC). The DVB-C receiver is compliant with ITU-T J.83 Annex A/C, and the DVB-T receiver is compliant with ETSI EN-300744 v1.5.1, NorDig Unified (v2.2.1), DTG 7.2. * Integrated Ethernet PHY JTAG CPU/FPU ST40-300 650 MHz MMU Interrupts I cache D cache Timer Debug on * Integrates dual mode DVB-T/DVB-C demodulation and FEC C Confidential * Extensive connectivity (2 x USB 2.0 ports; Ethernet MII/RMII/TMII port; SD/MMC card port) Resets Clocks Modes Clock Gen System serv Dual FDMA Information classified Confidential - Do not copy (See last page for obligations) Datasheet - production data Analog out PCM I/O S/PDIF out STB peripherals I/O External interrupts Audio I/O System interfaces Peripherals PCM players PCM reader DACs SSC UART RTC PWM GPIOs IR/UHF Smartcard Key scan L2 cache Audio decoder ST231 CPU Video decoder Display Video I/O Blitter Tile SRAM Video planes Graphic planes Main VDP Aux VDP DEI, IQI Dual DENC Teletext DACs VTGs EMI SPI SLC NAND Flash Serial Flash CI-Plus cards DDR3 LMI DDR3 STBus Transport Security STFE STBE ST231 CPU Delta Mu Low power standby controller DVB-C/DVB-T demodulator Transport streams parallel/serial in/out Transport IF in stream November 2014 This is information on a product in full production. Dual USB Connectivity HDMI 1.4b HDCP Ethernet SD-MMC/SDIO Analog video HDMII DocID023557 Rev 10 1/604 www.st.com 1 Contents STiH271EL Contents Related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Integrated DVB-C/DVB-T dual mode demodulator/FEC . . . . . . . . . . . . 13 2.1.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.3 Video decoding and post processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.4 High-quality video reformatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.5 Display and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.6 3DTV signaling capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.7 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.8 Memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.9 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.10 Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.11 Low power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1.12 STB peripherals, system services and package . . . . . . . . . . . . . . . . . . 17 2.1.13 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 en ti a l 2.1.1 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 2/604 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DVB decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 DVB-T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.2 DVB-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Applications CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 Video decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Audio/multimedia decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 Video post-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Display composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 Blitter engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 3DTV support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 3 STiH271EL C Confidential 2.1 fid 2 CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 on 1 STiH271EL 3.12 Audio inputs and audio/video outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 DVR support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14 High-capacity storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.15 STB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16 Booting/code storage options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Applications CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 On-chip memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 HDMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 External memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5 Local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ti a en NAND Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.2 Serial Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.3 MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 fid 4.5.1 Transport subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.6.1 Transport subsystem description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 on 4.6 l 4.1 4.7 High-definition video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 Video display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8.1 4.8.2 4.9 High quality video display processor (HQVDP) lite . . . . . . . . . . . . . . . . 31 Auxiliary processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Graphic display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.9.1 Graphics layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.9.2 Cursor layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.9.3 Display compositor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.9.4 Main display output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.9.5 Auxiliary display output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.9.6 3DTV on HDMI 1.4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.10 2D graphics processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.11 Audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.12 4.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.11.2 Functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Multichannel DMA support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DocID023557 Rev 10 3/604 Information classified Confidential - Do not copy (See last page for obligations) System-on-chip subsystems overview . . . . . . . . . . . . . . . . . . . . . . . . . 26 C Confidential 4 Contents Contents STiH271EL USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.13.2 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.13.3 SD-MMC, SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.13.4 Standard peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.14 STBus interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.15 Clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.16 Standby controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.17 System services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 l Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 Environmentally friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 BGA footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 Ball list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/604 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2 Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.5 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.6 Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.7 HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.8 EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.9 LMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.10 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.11 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.12 Front-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.13 Signals and interfaces on PIO alternate functions . . . . . . . . . . . . . . . . . . 91 on 8 Sorted on ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 fid 7.1 en 6 C Confidential 4.13.1 ti a 5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.13.1 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.13.2 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.13.3 External DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 4.13 STiH271EL Contents 8.13.4 External interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.13.5 IRB10/UHF Rx, IRB0 Tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.13.6 Key scanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.13.7 Multi-media card (MMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.13.8 Pulse width modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.13.9 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.13.10 Serial Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.13.11 Serial Flash interface - dual and quad modes . . . . . . . . . . . . . . . . . . . . 96 l 8.13.13 Transport streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.14 en Front-end overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.1.2 Write operation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.1.3 Read operation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.1.4 I C interface in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.1.5 I C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 fid 9.1.1 on 9.1 Confidential Pad reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.2 General-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.3 Interrupt generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4 Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.5 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.6 9.7 C 9 ti a 8.13.14 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9.5.1 Crystal frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.5.2 Clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.5.3 Auxiliary clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.6.1 Dual analog-to-digital converter (ADC 12-bit) . . . . . . . . . . . . . . . . . . . 115 9.6.2 RF signal strength indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.6.3 Automatic gain control for COFDM reception . . . . . . . . . . . . . . . . . . . 116 9.6.4 ADC overflow rate control for COFDM reception . . . . . . . . . . . . . . . . . 117 9.6.5 Automatic gain control for QAM reception . . . . . . . . . . . . . . . . . . . . . . 117 Signal processing for COFDM demodulation . . . . . . . . . . . . . . . . . . . . . .118 9.7.1 Impulsive noise rejection (INR) and canceller . . . . . . . . . . . . . . . . . . . 118 9.7.2 Digital filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 DocID023557 Rev 10 5/604 Information classified Confidential - Do not copy (See last page for obligations) 8.13.12 Synchronous serial controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 STiH271EL Zero-IF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.7.5 Timing and carrier correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.7.6 Co-channel and adjacent-channel interference suppressor . . . . . . . . 119 9.7.7 Symbol timing /recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.7.8 Carrier and timing recovery loop (CRL and TRL) . . . . . . . . . . . . . . . . 120 9.7.9 Fast Fourier transform (FFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.7.10 Channel estimation and correction (CHC) . . . . . . . . . . . . . . . . . . . . . . 120 9.7.11 Echo protection quality (EPQ) loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.7.12 Symbol de-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.7.13 De-mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.7.14 Bit de-interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.7.15 Carrier monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 ti a en Forward error correction (FEC) for COFDM demodulation . . . . . . . . . . 121 9.8.1 Viterbi decoder and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.8.2 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.8.3 Convolutional de-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.8.4 Reed-Solomon decoder and descrambler . . . . . . . . . . . . . . . . . . . . . 123 Signal processing for QAM demodulation . . . . . . . . . . . . . . . . . . . . . . . 123 9.9.1 IF to baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.9.2 9.9.5 9.9.6 Phase noise canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.9.7 Differential decoding and symbol-to-byte mapping . . . . . . . . . . . . . . . 125 9.9.3 C 9.9.4 Adjacent channels removal filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Symbol timing recovery and Nyquist filtering . . . . . . . . . . . . . . . . . . . . 124 Carrier recovery loop (CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.10 Master state machine for QAM demodulation . . . . . . . . . . . . . . . . . . . . 126 9.11 Forward error correction (FEC) block for QAM demodulation . . . . . . . . 128 9.11.1 FEC-A/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.12 DVB-T/DVB-C transport stream interface . . . . . . . . . . . . . . . . . . . . . . . 128 9.13 DVB-T transport stream overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.14 DVB-T transport stream output processing . . . . . . . . . . . . . . . . . . . . . . 129 9.14.1 6/604 l 9.7.4 fid 9.9 IF to baseband conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 on Confidential 9.8 9.7.3 Data rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.15 DVB-T serial output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.16 DVB-T parallel output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.17 DVB-C transport stream output processing . . . . . . . . . . . . . . . . . . . . . . 134 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Contents STiH271EL 9.17.2 Alternative parallel format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.17.3 Serial format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 COFDM reception registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.2 COFDM reception super FEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.3 QAM global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 10.4 QAM AGC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10.5 QAM demod registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10.6 QAM all-pass filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 10.7 QAM FEC A and C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 ti a l 10.1 External memories and on-chip peripherals address map . . . . . . . . . . . 287 11.1.1 12 ST40 interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 12.1.1 12.1.2 12.1.3 14 LPM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 12.1 13 en Memory and on-chip peripherals address map . . . . . . . . . . . . . . . . . 286 Internal and external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Interrupt service routine address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Interrupt vectors table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 DeltaMu (video) and audio ST231 interrupt network . . . . . . . . . . . . . . . 304 12.3 Comms ILC3 interrupt network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 12.4 Comms ILC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 12.5 CPU mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 C 12.2 DMA network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 13.1 FDMA and driver communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 13.2 FDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 13.3 FDMA request table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 14.1 Clock input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14.2 Clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 DocID023557 Rev 10 7/604 Information classified Confidential - Do not copy (See last page for obligations) Front-end registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.1 Confidential DVB common interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 fid 11 9.17.1 on 10 Contents Contents STiH271EL 14.3.1 Clock generator A functional description . . . . . . . . . . . . . . . . . . . . . . . 323 14.3.2 Clock generator A clock observation . . . . . . . . . . . . . . . . . . . . . . . . . . 323 14.3.3 Clock generator A clock observation counter . . . . . . . . . . . . . . . . . . . 324 14.3.4 Clock generator A0: clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 14.3.5 Clock generator A1: clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 14.4.1 Video clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 14.4.2 VID-FS0 and VID-FS1 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . 330 General purpose FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 14.6 Clock generator USB: USB clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 14.7 Clock observation pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 14.8 MPEG clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 14.9 Clock generation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 16 Power-on and system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.1 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.2 POR reset (cold reset) versus system reset (warm reset) . . . . . . . . . . . 356 on 15 ClockGen A - CPUs and interconnect clock gen registers . . . . . . . . . 335 fid 14.9.1 en ti a 14.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 16.1 Boot modes system configuration registers . . . . . . . . . . . . . . . . . . . . . . 358 16.2 ST40 reset outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 16.2.1 Masked ST40 reset outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 17 Reset configuration (mode pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 18 Standby controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 19 System configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 8/604 19.1 Registers summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 19.2 Bank 0 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 19.3 Bank 1 registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 19.4 Bank 2 registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 19.5 Bank 3 registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) VID-FS0 and VID-FS1: display, video output stage, audio, pace, USB . 327 C Confidential 14.4 Clock generator A: CPUs, interconnect and processing clock generation . . 320 l 14.3 STiH271EL External circuitry recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 20.1.2 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 20.3 On-chip voltage sensing feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 20.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 20.5 Video analog output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 20.6 HDMI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 20.7 Audio analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 20.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 20.9 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 MII mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 20.9.2 RMII (reduced MII) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 en 20.9.1 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 21.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 21.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 21.3 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.3.1 21.3.2 22 ti a l 20.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.4 Quad DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.5 DDR electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.5.1 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.5.2 General electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 21.6 External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 21.7 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 21.8 3V3 IO pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 22.1 JTAG interfaces AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 22.2 Transport stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 22.2.1 Serial input AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 22.2.2 Parallel input AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 22.2.3 Serial output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 DocID023557 Rev 10 9/604 Information classified Confidential - Do not copy (See last page for obligations) 20.1.1 fid 21 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 C Confidential 20.1 on 20 Contents Contents STiH271EL Parallel output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 22.3 HDMI AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511 22.4 PIO output AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511 22.5 LMI DDR3-SDRAM timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 22.6 PCM audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 22.6.1 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 22.6.2 Output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 Ethernet interface AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 22.8 USB AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 22.9 Serial Flash controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 ti a l 22.7 22.9.1 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 22.9.2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 en 22.10 MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 22.11 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 PIO port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 24 PIO port multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 24.1.1 24.1.2 25 on 24.1 fid 23 PIO bank organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Alternate functions controlled by system configuration registers . . . . . 524 C Confidential 22.10.1 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 Alternate functions on PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 25.1 PIO global summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 25.2 PIO details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 25.2.1 PIO0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 25.2.2 PIO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 25.2.3 PIO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 25.2.4 PIO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 25.2.5 PIO4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 25.2.6 PIO5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 25.2.7 PIO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 25.2.8 PIO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 25.2.9 PIO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 25.2.10 PIO9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 10/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 22.2.4 STiH271EL Contents 25.2.11 PIO10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 25.2.12 PIO11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 25.2.13 PIO12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 25.2.14 PIO13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 25.2.15 PIO14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 27 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 C on fid Confidential en ti a l 26 DocID023557 Rev 10 11/604 Information classified Confidential - Do not copy (See last page for obligations) 25.2.16 PIO15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Related documents 1 STiH271EL Related documents This datasheet is part of the STiH271EL documentation suite which forms a complete system description and programming guide. This datasheet is intended for hardware engineers, and describes the pins, package, electrical characteristics and timing information for the STiH271EL device. To obtain an up-to-date specification of this product, this datasheet should be read in conjunction with the latest product errata sheet (buglist) obtainable from STMicroelectronics. l CPU documentation ti a 1.1 The ST40 core and its instruction set are documented in the ST40 CPU Core Architecture Manual. C on fid Confidential en The ST231 core and its instruction set are documented in the ST231 CPU Core and Instruction Set Architecture Manual. 12/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The documents related to this datasheet are described in the sections below. STiH271EL 2 Introduction Introduction STiH271EL features summary 2.1.1 Integrated DVB-C/DVB-T dual mode demodulator/FEC en DVB-T channel impairments management: NorDig Unified (v2.2.1) compliant and DTG 7.2 - Outstanding performance in various channel configurations: dynamic fading, urban environment - Built-in channel reception quality indicators - Out-of-guard interval echoes compatible fid - - Impulsive noise rejection capable - Outstanding adjacent and co-channel rejection capability with integrated and flexible digital channel filtering - High-performance digital carrier, timing and symbol recovery loops on Confidential Dual 12-bit ADCs: - Differential I/Q inputs compatible with terrestrial tuners - Low-to-high IF input compatible with cable and/or terrestrial tuners COFDM demodulator/FEC: - ETSI EN-300744 v1.5.1 compatible - 2-K and 8-K FFT - 6-, 7- and 8 MHz channel bandwidths - 1/4, 1/8, 1/16, 1/32 guard-interval length - QPSK - 16QAM - 64QAM modulations - Hierarchical modulation capability - TPS decoding - Puncture rates are 1/2, 2/3, 3/4, 5/6, 7/8 C ti a l 2.1 - Outer Reed-Solomon decoder as per DVB-T standard - Energy dispersal descrambler DocID023557 Rev 10 13/604 Information classified Confidential - Do not copy (See last page for obligations) The STiH271EL offers current users of ST's growing family of advanced decoding ICs enhancements in performance and features, enabling operators to offer consumers new multimedia-rich services and viewing experiences, including new 3DTV features. Faster DDR3 memory is also supported, and the applications CPU benefits from an L2 cache. The STiH271EL has an integrated standby controller that enables the STiH271EL to target stringent low power regulations. Introduction QAM demodulator/FEC: - Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams - Supports 16, 32, 64, 128 and 256 point constellations - Variable symbol rates - Compliant to NorDig Unified (v2.2.1) and SARFT - Front derotator for better low symbol rate performance and relaxed tuner constraints - Integrated matched filtering - Robust integrated adaptive pre- and post-high multi-tap equalizer - On-chip FEC A/C with ability to bypass individual blocks - Fast signal acquisition Channel quality monitoring and reporting Additional 8-bit ADC for RF signal strength indication Dual digital split AGC for RF and IF/BB gain control I2C repeater for host control of the terrestrial/cable tuner over a dedicated I2C port Transport stream output: en - Fine-grain clocking for shutting down individual modules fid Channel acquisition and re-acquisition efficiency CPU 2.1.3 - ST40-300 applications CPU: on 2.1.2 MPEG2 TS compatible, serial, parallel (DVB-CI plus compliant) Power saving features: - Includes 2-way 32K I and 2-way 32K D Level 1 caches - Includes an L2 cache, 256KB, 2-way set associative - 650 MHz delivering 1200 DMIPS - Includes a tightly coupled vector FPU to accelerate 3D graphics transformations C Confidential - ti a l Video decoding and post processing Latest generation `Delta' video decoder with ST231 programmable CPU core: - MPEG2, H.264, VC-1/WMV9, HD or SD advanced video decoding - Provides flexibility to support other codes, for example, MPEG4 Part2 including DivX and XviD with QPEL up to 1080p30 with QPEL, H.263 encode/decode, AVS-SD, MJPEG (up to 100 Mpixel/s) - Flash (Sorenson, ON2/VP6), and Theora up to VGA - HD + SD decoding, PIP and Mosaic capable Unique motion compensation cache reduces memory bandwidth required for video decoding Advanced deblocking, deringing/mosquito noise reduction of the decoded video sources 14/604 Available for MPEG2 HD/SD sources as well as SD web content (MPEG4pt2, DivX, Flash/Sorenson) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) STiH271EL STiH271EL High-quality video reformatting High-quality motion and detail adaptive spatial and temporal de-interlacing. Support for 1080i60 >1080p60 deinterlacing. Features Faroudja DCDi deinterlacing with best-in-class directional interpolation performance for highquality low-angle diagonals. Film mode detection (FMD) with cadence break supported. - High-quality reformatting/resizing engines (H and V) using 8 taps polyphase interpolation filters. Advanced features include built-in global sharpness, overshoot and edge adaptive controls. - Image quality Improvement capabilities including luma enhancement, chroma transient improvement and horizontal peaking. Aux video display pipeline for concurrent SD video display: - Display and output en Independent Main and Aux display compositors (video/graphics mixing): - Main display composition for HD/SD display, comprising background graphics plane, video plane and full-featured graphics plane with H and V resize, CLUT and anti-flicker filter. - Aux display composition for SD display, comprising background graphics plane, video plane and full-featured graphics plane with H and V resize, CLUT and antiflicker filter. - Symmetric assignment of two graphic planes and one video plane set on each compositor (Main/HD, Aux/SD). - Main display capture, down-conversion and display as SD with a single graphics plane on the aux compositor. The aux video plane can be used for PIP on the main display with this option. fid Confidential on 2.1.5 High-quality H and V reformatting/resizing with sample rate conversion/filtering Link-list-based, multi-operator, 2D graphics blitter. Supports rendering, formatting and pre-composition of 2D graphics, and 3D-like user interface effects: - Up to 666 Mpixel/s available for composition and application - Tile RAM, memory bandwidth saver, accelerates blitter-based pre-composition HDMI 1.4b-compatible interface with HDCP v1.3 copy protection: - Integrated HDMI CEC line controller, compressed audio and 8-ch PCM audio output, SD/HD display formats up to 1080p60 - Supported features include high bit rate audio, deep color modes (30/36 bits), xvYCC pass-through and 3DTV signaling Dwight Cavendish analog copy protection Dual PAL/NTSC/SECAM digital encoders Four high-drive 10-bit DACs for component/composite analog video output (HD/ED/SD formats up to 1080i): - DACs available for HD + SD output, or all DACs can be used for SD output with concurrent HD over HDMI - Integrated buffers eliminate the need for external video amplifiers DocID023557 Rev 10 15/604 Information classified Confidential - Do not copy (See last page for obligations) - l Main display pipeline for main HD/SD video display: ti a C 2.1.4 Introduction Introduction 3DTV signaling capability Audio decoding of MPEG1 I/II, MP3, Dolby Digital/DD+/Pulse, MPEG4 AAC/AAC+, WMA/WMA-pro - Multi-channel audio decoding up to 7.1 channels with down-mixing - Concurrent audio description decoding and mixing with the main audio - DD+ to DD and AAC+ to DD/DTS conversion for SPDIF output - Flexibility to support other codecs, DTS, FLAC and Ogg Vorbis ti a l - Integrated stereo audio DACs (single-ended voltage outputs): - Stereo audio PCM input and output interface - Independent SPDIF output fid Memory interfaces 16-bit DDR3 LMIs at up to 667 MHz (DDR3-1333). Supports up to 1 GB using up to 4Gbit devices. DDR3L (1.35 V) devices are also supported SLC(1) NAND Flash memory interface with four banks: - Supports 1 bit/512 bytes and multi-bit (4 bits and 8 bits/512 bytes) ECC - Small page, large page and very large page NAND Flash devices - Error-free NAND also supported - DVB CI-Plus card host interface supported in two of the banks High-speed SPI interface for Read/Write of Serial Flash, supporting standard SPI protocol and Dual and Quad I/O protocols: - Supports 32-bit addressing for 256 Mbits (and higher) Serial Flash devices 1. MLC/TLC NAND Flash is not supported on this interface. 16/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) ST231 VLIW CPU-based audio processor: en Confidential Compliant with HDMI v1.4b mandatory 3DTV display formats Audio 2.1.8 Cross-conversion processing and display, using SbS/TaB up to 1080p60, or frame/field packing up to 1080p60L60R, 1080i60L60R or 720p60L60R on 2.1.7 Display of DVB Phase 1 compatible (SbS/TaB) 3DTV content up to 1080i60, 1080p60, 720p60 C 2.1.6 STiH271EL STiH271EL Dual USB 2.0 host ports with integrated PHYs Integrated Ethernet MAC: - Multiple hardware address filters, 10/100 MII/RMII, turbo-MII up to 200 Mbit/s - Energy efficient Ethernet supported 10/100 Ethernet PHY 8-bit eMMC/SD-MMC interface: - For managed NAND devices or SD/MMC memory cards - Supports v4.3 of eMMC/MMC and v2.0 for SD cards l Transport Transport stream front-end PID pre-processor: - Four external TS inputs - TS I/O routing for CI-Plus cards Transport processor with security coprocessor: 2.1.11 DRMs supported include DTCP-IP, DivX, MSDRM-PD/ND, Play Ready, Marlin, DVBCPCM Dual multi-channel flexible DMA controllers Low power management 2.1.12 Multistream AES/TDES encryption/decryption for local copy protection or network DRM schemes fid DVB/DES/TDES/AES/Multi-2 descrambling, DVB CI-Plus descrambling, DVB-CSA3 supported on Multi-stream transport stream de-multiplexing, descrambling from any source (broadcast, IP network, DVR), section filtering and dual clock recovery Integrated standby controller (SBC) within its own power island and with its own peripheral set C Confidential - Support for internal controller-based passive standby mode with LMI retention, secure hibernate to DDR and fast resume (without reboot) on wake up Energy efficient Ethernet (EEE) supported when coupled with an EEE PHY Wake on HDMI CEC, wake on IR/UHF RC input, timer or interrupt, wake on UART/SSC data packet, wake on key press Flexible host passive standby mode also available, where SoC resources need to be powered and accessed Advanced power-down management (multiple clock domains, clock gearing, clock agility, DDR APPD) for optimizing active standby modes STB peripherals, system services and package Two smartcards, five UARTs, seven SSC/I2C, 16 GPIO banks with alternate functions, IR Tx/Rx, UHF Rx/SCD, PWM, ILC, 4 X 4 key matrix scanner, long time-out reset input Package: FPBGA 27 mm X 27 mm, 0.8 mm and 1.0 mm pitches, 761 balls DocID023557 Rev 10 17/604 Information classified Confidential - Do not copy (See last page for obligations) ti a 2.1.10 Connectivity en 2.1.9 Introduction Introduction Fast Ethernet transceiver Supports 100-Base-TX/FX media interface Supports auto MDI/MDIX function Power management tool: - APS, auto power saving while link-off - 802.3az, protocol based power saving - WOL+, light traffic power saving - PWD, force-off power saving Supports MDC and MDIO to communicate with the MAC EMI management tool: l Firmware-based control - Four levels for mapping the difference layout length on the PCB ti a - C on fid Confidential 18/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Ethernet PHY en 2.1.13 STiH271EL STiH271EL Functional overview 3 Functional overview Figure 1. STiH271EL block diagram Serial Flash Analog SLC L/R NAND DDR3 2Ch PCM Out S/PDIF CI+ card memory In Out Out Host SoC peripheral I/O Resets clocks modes debug SBC peripheral I/O TMII/MII/ RMII & external interrupts Tx/Rx JTAG 4 LMI Audio players/ reader Applications CPU CPU/FPU core TMUs/INTC 32K 32K MMU I cache D cache ST40-300 core L2 cache 256KB Audio DACs UDI Dual FDMA EMI ti a ST231 audio processor GPIOs GPIOs UART Clock Gen IRRx UART SSC IR 3 & System UHF Tx 3 2 V Smart SSCs Services RTC Key Wake reg I C 4 card scan on LAN WD 2 Eth PWM CEC INTC FP MAC LED HPD Reset SPI Microcontroller Eth PHY STiH271EL interconnect Tile RAM Blitter AGC I2C DiSEqC TXT fid SWTS Transport FE processor ADCs Demodulator DVB-C/T FEC TS TS TS TS In3 In2 In1 In0 Dual DENC 4DACs Main video DCDi display IQI HDMI Analog TMDS video HD/SD Aux video display Dual USB 2.0 host Output stage PHY PHY SD/MMC host controller VTGs SD/MMC card, eMMC on IQ in 4 Gfx layers Main / Aux display compositions 3.1 DVB decoder 3.1.1 DVB-T C Confidential Input streams 4 Delta Mu HD video decoder ST231 en Transport processor The COFDM receiver is fully compliant with the DVB-T standard framing structure, channel coding and modulation. The symbol, timing, and carrier recovery loops are completely digital and tailored to comply with the state-of-the-art RF down-converting tuner devices. The radio-frequency level is monitored by a dedicated single-ended 8-bit ADC. The RF power can be left under the control of the tuner, or it can be derived from the baseband power using a dedicated power-split algorithm. If required, the tuner serial I C bus can be isolated using the I C bus repeater. The terrestrial DVB-T network is particularly subject to multiple interference sources, which include the neighboring digital and analog channels, and the in-band analog channels. The STiH271EL embeds robust algorithms to cope with this interference as well as impulsive noise effects. The channel equalizer is capable of static and dynamic echo cancellation even in severe urban environments. The embedded algorithms are enhanced to cope with out-of-guard interval echoes. 3.1.2 DVB-C The STiH271EL front-end quadrature amplitude modulation (QAM) section is a complete QAM demodulation and forward error correction (FEC) solution that performs IF-to-transport stream block processing of QAM signals. It is intended for the digital transmission of DocID023557 Rev 10 19/604 Information classified Confidential - Do not copy (See last page for obligations) 8 l 16 Functional overview STiH271EL compressed television, video, sound and data services over cable and is fully compliant with ITU-T J.83 Annexes A/C or DVB-C specification bitstreams. It can handle square (16-, 64-, 256-QAM) and non-square (32-, 128-QAM) constellations. Figure 2. STiH271EL front-end demodulator Demodulator control en Demodulator clock C_Ix C_Qx on C_AGC_BB Tuner C_RF_LEVEL C C_SDAT C_SCLT Generic demodulator PIO 3.2 C_XTAL_I C_XTAL_O fid C_SCL C_NOT_RESET C_SDA Confidential ti a l The STiH271EL provides all demodulation and FEC functions required for the recovery of QAM bitstreams, with outstanding BER results. In addition, it includes several features that give simple and immediate access to various quality and status monitoring parameters. The demodulator provides error-corrected MPEG transport stream outputs, which can be routed to the transport sub-system. The dynamic performance of the STiH271EL is close to theoretical limits thanks to new demodulation algorithms and a wide equalizer allowing the STiH271EL to correct both pre- and post-echoes. C_DATA[7:0] C_D_NOT_P C_STR_OUT C_CLK_OUT C_ERROR Transport streams STiH271EL front-end demodulator C_GPIOx Applications CPU The STiH271EL has a state-of-the-art embedded applications CPU, the ST40-300 with MMU, FPU and Instruction and Data L1 caches of 32 Kbyte each. The applications CPU executes applications, middleware, drivers, and network protocol stacks on the Linux 20/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The IF can be up to 57 MHz, and the sampling clock can be selected freely from a given range (constrained by the SAW filter and symbol rate characteristics). All further processing is fully digital, therefore, no external feedback loop is required. The STiH271EL handles a wide range of symbol rates, from the highest practical rates to rates as low as 0.87 Mbaud, even when there is a significant frequency offset. STiH271EL Functional overview operating system. OS21 is also supported for cost-effective zapper STBs. At 650 MHz, the applications CPU delivers 1200 DMIPS. A 256 Kbyte Level 2 cache is available to the applications CPU to enhance the performance of applications software. 3.3 Local memory interface The local memory interface (LMI) provides a unified memory resource for the STiH271EL for CPU code/data, graphics, video, audio, network, and HDD buffers. DDR3 memory at up to 667 MHz (DDR3-1333) Up to 4-Gbit memory devices DDR3 (1.5 V) and DDR3L (1.35 V) memory devices l Total addressable memory capacities ranging from 128 Mbytes up to 1 Gbyte ti a 3.4 Transport en 3.5 on fid Transport stream routing into and out of the STiH271EL for CI-Plus cards is supported. A transport front-end processor PID filters and timestamps the incoming broadcast transport streams before buffering to memory. Transport streams are then processed by a highperformance programmable Transport Stream engine coupled with a security co-processor. This performs demultiplexing, descrambling and section filtering on multiple transport streams received from broadcast, IP network and HDD sources. Connectivity The STiH271EL has a wide range of options for connecting to external peripherals or IP network devices (for example, wired Ethernet, MoCA, xDSL, DOCSIS, Wi-Fi, and so on), enabling the delivery of IP streams received over broadband networks. These interfaces include two USB 2.0 host ports, and 10/100 Ethernet MAC supporting MII and RMII interfaces. The STiH271EL also integrates a 10/100 Ethernet PHY. Turbo MII at 200 Mbps is also supported. An 8-bit SD/MMC card controller interface is also available for direct attachment to memory cards, or interfacing to e-MMC devices. Transport streams received through IP or from the HDD are stored in memory, and are available to the transport processor for demultiplexing and descrambling in a similar way to the broadcast TS streams. C Confidential The STiH271EL receives transport streams from broadcast networks through up to four transport stream inputs. 3.6 Video decoding The STiH271EL has a high-performance ST231-based video decoder that can decode H.264,VC-1/WMV9, and MPEG2 HD and SD streams. The decoder can decode a single H.264/MPEG2 HD stream concurrently with an H.264/MPEG2 SD stream for PIP applications. Decoding of AVS1-P2 Jizhun profile Level 4.0 (SD) and Level 2.0 (CIF) is also supported. DocID023557 Rev 10 21/604 Information classified Confidential - Do not copy (See last page for obligations) The LMI supports: Functional overview STiH271EL The decoder is well proven in the industry and is powerful and flexible enough to decode other video formats such as MPEG4 part2, DivX, and XviD up to1080p30 with quarter-pixel motion compensation. The decoder is also able to support MJPEG decoding up to 100 Mpixel/s, and Flash codecs (Sorenson, VP6 and H.264). Audio/multimedia decoding l A programmable 650 MHz ST231 CPU core provides the flexibility and performance for decoding multimedia content, offloading the ST40 CPUs from these tasks. Audio processing is the primary function of this CPU core, but processing power not used for audio can be used for other application tasks. Many applications may need only part of the ST231 CPU capacity for the required audio processing, leaving the remainder available for applications use. 3.8 fid en Concurrent decoding and mixing of an audio description channel is also supported. The STiH271EL is able to decode multi-channel streams concurrently with down-mixing, postprocessing, and transcoding for simultaneous S/PDIF output, and fully supports the Dolby MS10 multistream audio decoder. PCM mixing, volume equalization, and channel virtualization are also supported. As with the video decoder it is possible to download and run other web-oriented media codecs, such as Real Audio, Vorbis, and FLAC. Video post-processing on High-quality video post-processing can be applied to resize, reformat, and de-interlace video between the decoded format and the formats needed for display. Two video planes are available. The main compositor video plane provides very high-quality horizontal and vertical scalers using 8-tap interpolation filters, motion and detail adaptive spatial and temporal deinterlacing for 480p/576p and1080p60 progressive output, and film mode detection (FMD). Deinterlacing is based on the state-of-the-art Faroudja DCDi spatial interpolation technology, providing unrivalled quality for low-angle deinterlacing. Further image quality improvement (IQI) capabilities are available, including luma enhancement, luma/chroma transient improvement and horizontal peaking. C Confidential ti a Decoding of multichannel audio streams is supported compliant to the following standards: MPEG1, MPEG2, MP3, MPEG4 AAC, AAC+ (v1/v2), Dolby Digital, Dolby Digital Plus, Dolby Pulse, DTS, WMA, and WMApro. The auxiliary compositor video plane provides high-quality SRC-based resizing, reformatting, and downscaling of HD content for simultaneous SD output. For noise reduction of the decoded MPEG2/DivX content, an advanced deblocking and deringing filter is provided that is also capable of mosquito noise reduction. 3.9 Display composition Graphics can be displayed on any one of four physical graphics planes. Two planes are optimized for background graphics/stills and two planes are optimized for foreground graphics. The graphics planes are combined with video, using alpha blending and color keying. The graphics and video planes are combined by two independent display compositors, one for the main TV and a second for output to a VCR or DVD-R. Graphics 22/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 3.7 STiH271EL Functional overview planes are typically symmetrically assigned, with one pair of foreground/background graphics planes on each compositor. 3.10 Blitter engine 3.12 fid en The STiH271EL is 3DTV-capable. Decoding of side-by-side (SbS) and top-and-bottom (TaB) stereo video content up to 720p60/1080i60/1080p24, is supported using H.264 AVC. Decoded left and right views can then be output through HDMI using any of the supported HDMI version 1.4b-compatible 3DTV display formats. These are format 0 progressive (frame packing up to 720p120 or 1080p48); format 0 interlace (field packing up to 1080i120); format 6 (top and bottom half-resolution up to 1080p60); and format 8 (side-byside half-resolution up to 1080p60). Audio inputs and audio/video outputs on The STiH271EL has both HDMI and analog interfaces for outputting video to the TV. In addition to the standard 720p and 1080i HD formats, the STiH271EL supports 1080p60 display output on the HDMI interface. The analog interface comprises four video DACs, with CGMSA, and Dwight-Cavendish copy protection, whilst the HDMI interface supports HDCP copy protection. The Video DACs are available for concurrent HD and SD output, or can be used for just SD output (component and composite video). Audio is output over HDMI, S/PDIF, stereo analog DACs, and a digital PCM output interface (stereo). It is possible to output both compressed and decoded audio streams at the same time over different interfaces (for example, Dolby Digital 5.1 over S/PDIF with decoded and down-mixed AAC+ audio through the analog output). A two-channel PCM input is also available for inputting audio from external sources, such as a microphone (for example, for VOIP telephony). The HDMI interface is further capable of outputting HDMI version 1.4b-compatible 3DTV formats. 3.13 DVR support The STiH271EL is suited to the realization of stand-alone DVR applications. The STiH271EL supports the processing and recording of multiple transport streams, which can be concurrently sourced from broadcast tuners and IP networks. At the same time, delayed-live or recorded streams can be processed for local playback with trick modes. Streams can be independently encrypted to and from the HDD. DocID023557 Rev 10 23/604 Information classified Confidential - Do not copy (See last page for obligations) ti a 3DTV support C Confidential 3.11 l A list-based, multi-operator blitter is provided to accelerate the rendering of 2D graphics and 3D-like graphics effects. It supports rendering, formatting, and pre-composition of 2D graphics from virtual planes at up to 300 Mpixel/s with destination alpha blending. The blitter supports efficient interleaving of application and composition 2D graphics tasks, and includes a Tile RAM memory bandwidth saver to accelerate pre-composition. The blitter is also used by ST's ST3FX library to provide 3D-like graphics effects to enhance user interface and EPGs. Functional overview 3.14 STiH271EL High-capacity storage High-capacity local storage devices, such as USB Flash drives and SD/MMC cards can be attached to the STiH271EL to provide storage for DVR time slip, push VOD buffering, or storing user content. In addition to providing USB ports to support this capability through external controllers, the STiH271EL integrates a host controller that supports SD-MMC/SDIO interface V4.3, and SD HC V2.0 PART A2 standards. It can be used to connect an external (removable) SD/MMC memory card, or to connect an on-board eMMCbased managed NAND Flash. STB peripherals en 3.16 Booting/code storage options fid The STiH271EL supports two Flash memory options for code storage and booting. These are SLC NAND Flash and Serial NOR Flash. SLC NAND Flash can be attached directly without the need for an external controller. on Hardware ECC is supported for SLC NAND flash devices correcting up to a maximum of 18 bits/1 Kbyte, including devices supporting 4 bits/512 bytes and 8 bits/512 bytes. Serial Flash booting uses a dedicated high-speed SPI interface. This Serial Flash interface features single I/O, dual I/O, and quad I/O accesses, with dual/quad output reads possible at speeds of 50 MHz. 3.17 C Confidential ti a l The STiH271EL integrates a range of peripherals and interfaces to minimize or eliminate the external cost of implementing basic STB functions. These include five UARTs and seven SSCs used for SPI or I C control buses, two smartcard controllers, a PWM module, IR receiver and transmitter, UHF remote digital input, General Purpose Programmable I/O (GPIO), external interrupt inputs, a long-time-out front panel reset, and a controller for scanning/debouncing a 4 4 key matrix. For HDMI interfacing, an I C port is available together with a hardware CEC line controller. Low-power management A low-power design process is combined with a low-power architecture to provide a best-inclass host passive standby mode, as well as providing a clock agile dynamic power management system for power efficient active standby modes. In active standby modes, selected features and interfaces can be powered-down dynamically, while required features can remain clocked at full or low speed. The STiH271EL provides high granularity of clock domains, and on-the-fly clock gearing to provide the most power-efficient configuration for applications. Auto-precharge power down support for DDR memory provides further power saving. For the lowest power consumption the STiH271EL supports a controller-based passive standby mode targeting STB standby power under 0.5 W. A standby controller (SBC) is integrated within its own power island and with its own peripheral set including interrupts, keyscan, UARTs, I C ports, IR Inputs and a Real Time Clock (RTC). In this mode the SBC, LMI and DDR memory remain powered while the rest of the SoC and STB can be completely powered off to achieve very low power consumption. The Standby Controller is responsible for managing secure hibernation to DDR and fast 24/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 3.15 STiH271EL Functional overview resume from wake up triggers that include an IR remote control event, an internal timer event, an external interrupt, Wake-on-LAN event, or Wake-on-CEC event. 3.18 Ethernet PHY C on fid Confidential en ti a l For more information on Ethernet PHY, contact STMicroelectronics customer support. DocID023557 Rev 10 25/604 Information classified Confidential - Do not copy (See last page for obligations) The integrated Ethernet PHY is an IEEE 802.3/802.3u compliant single-port fast Ethernet transceiver for both 100 Mbps and 10 Mbps operations. It supports auto MDI/MDIX function to simplify the network installation and reduce the system maintenance cost. The PHY is designed to use category 5 unshielded twisted-pair cable connecting to other LAN devices. A PECL interface is supported to connect with an external 100Base-FX transceiver. The PHY supports several power saving modes including APS, IEEE 802.3az Energy Efficient Ethernet (EEE) and Wake-on-LAN (WOL). System-on-chip subsystems overview 4 STiH271EL System-on-chip subsystems overview This section gives a top-level overview of the device components. Applications CPU ti a l The STiH271EL has an ST40-300 applications CPU core (also described as the Host CPU). At 650 MHz, it delivers over 1200 DMIPS and can support Linux or OS21 operating systems. The CPU is intended for applications, middleware, drivers and network protocol stacks. The ST40 CPU core includes an IEEE-754 compliant FPU (floating point unit); an MMU (memory management unit); 2-way, set-associative L1 caches (32 Kbyte of instruction cache and 32 Kbyte of data cache); and core support peripherals such as a timer unit, a watchdog timer and an interrupt controller. The performance of real application code is further enhanced by the integration of 256 Kbyte of L2 cache available to the ST40 CPU. en On-chip memories 4.3 HDMI interface fid The STiH271EL also includes a shared on-chip memory of 40 Kbyte. This memory is primarily intended to be used by the 2D blitter engine for tile composition, but is available for general use if required. This memory is referred to as `Tile SRAM' in this document. 26/604 3D video: on The STiH271EL supports the following features compliant to HDMI 1.4b specification: - 3D video format timings -- video resolution up to 1920 x 1080p @60 Hz - 3D over HDMI -- side-by-side (half) and top-and-bottom and frame packed formats C Confidential 4.2 Deep Color x.v.Color Content Type Audio formats -- LPCM, Dolby Digital, and Dolby Digital Plus HDMI Rx sense HDCP CEC DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 4.1 STiH271EL 4.4 System-on-chip subsystems overview External memory interface The EMI is a general-purpose interface for attaching NAND and Serial NOR Flash devices. The interface supports: 8-bit NAND Flash Four banks Single-level cell (SLC) NAND Flash and boot from SLC NAND Flash DVB-CI/CI-Plus host interface Local memory interface ti a l The STiH271EL supports high-performance, DDR3-SDRAM memory interfaces, providing optimal memory system performance with the opportunity for BOM optimization through the use of differing amounts of memory attached to DDR memory devices. Total addressable memory capacities ranging from 128 Mbyte up to 1 Gbyte DDR3 memory at up to 667 MHz (DDR3-1333) Up to 4-Gbit memory devices DDR3 (1.5 V) and DDR3L (1.35 V) memory devices en 16-bit DDR3 device fid 4.5.1 NAND Flash interface The features supported by the NAND controller are: - Large page (2048 bytes) and small page (512 bytes) devices - 8-bit devices - Devices with 3 to 5 address cycles Software programmable Flex mode for all the NAND Flash modes ECC support in Flex mode for read/write FDMA/host managed, Advance Flex mode, for bulk data movement 4.5.2 Boot capability from: on C Confidential The LMI supports: ECC support in Advance Flex mode. Provision for writing the ECC data into the spare location of the memory Serial Flash interface The Serial Flash interface features dual I/O and quad I/O accesses, with dual/quad output reads possible at 50 MHz speed. The STiH271EL supports booting from Serial NOR Flash (through the SPI interface). The controller is capable to support large memories up to 512 Mbyte. 4.5.3 MMC interface The STiH271EL integrates a host controller that supports SD-MMC/SDIO interface V4.3, and SD HC V2.0 PART A2 standards. It can be used to connect an external (removable) SD/MMC memory card or to connect an on-board eMMC-based managed NAND Flash that uses low-cost MLC NAND technology. DocID023557 Rev 10 27/604 Information classified Confidential - Do not copy (See last page for obligations) 4.5 System-on-chip subsystems overview 4.6 STiH271EL Transport subsystem Figure 3. Transport subsystem simplified block diagram DDR3 TSin0-S/P STBE TSin2-S/P ti a Front end transport stream pre-processor TSin3-S Note: See associated multiplexing table fid Key to transport I/O multiplexing TS I/O Type TSin0 Serial or Parallel TSin1 Serial or Parallel - TSin2 Serial or Parallel - TSin3 Serial TSin3 is available if either TSin0 or TSin2 is serial Serial or Parallel If TSout is used then TSin1 is not available Notes - on Figure 4. C TSOut Example use cases for external transport stream interfacing Four tuners and demodulator (serial output) Tuner/ demod TSin0 Tuner/ demod TSin1 Tuner/ demod TSin2 Tuner/ demod Two tuners and demodulator (serial output) plus DVB-CI/CI-Plus Two tuners + X-coder Tuner/ demod TSin0 Tuner/ demod TSin0 Tuner/ demod TSin3 Tuner/ demod TSin3 TSin2 DVB-CI or CI-Plus card X-coder TSin2P TSin3 TSOutP TSout 28/604 Transport and security processor en Confidential TSOut-S/P/ TSIN1-S/P Table 1. l STFE DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Software transport streams Live streams to circular buffers STiH271EL 4.6.1 System-on-chip subsystems overview Transport subsystem description The STiH271EL receives transport streams from broadcast networks through up to four transport stream inputs. STMicroelectronics provides a range of front-end channel processor ICs for cable, satellite and terrestrial networks that can be interfaced directly with the STiH271EL. Transport stream routing for dual DVB-CI+ (HD/SD profiles) can also be supported. Transport streams are processed by a single high-performance Programmable Transport Stream engine (STBE). This performs demultiplexing, descrambling and section filtering on multiple transport streams received from Broadcast, IP and HDD sources. l ti a It handles streams that conform to the DVB or DSS legacy standard. It filters transport packets so that only required packets are extracted based on the PID/SCID value held in the packet header. It handles transport errors and continuity count errors in the packet headers. It extracts PCR value from adaptation field header of packets with specified PIDs and to associate this value with the corresponding arrival time of the packet so that clock recovery can be performed. It replaces specific or unwanted packets with alternative packets. It provides parallel output TS streams for external X-coders. C 4.7 It captures the system memory transport stream packets from live transport stream inputs; that is, from a tuner/demodulator attached to a satellite, terrestrial or cable system. en Confidential It merges transport streams received from live inputs or local storage, and to convert the packet header format to be accepted by an external decryption device, and send the merged stream to that device. fid It handles multiple transport streams either directly from live inputs (from an external tuner/demodulator); from system memory (originally from local storage or from a network source); or CI+ source. on High-definition video decoder The STiH271EL has a high-performance ST231-based video decoder that can decode H.264, VC-1/WMV9, and MPEG2 HD and SD streams. Decoding of AVS1-P2 Jizhun profile Level 4.0 (SD) and Level 2.0 (CIF) is also supported. Multiple decoding of lower resolution streams can also be supported for Mosaic applications. The decoder is well proven in the industry and is powerful and flexible enough to decode other video formats such as MPEG4 part2, HD DivX in real time (30 fps) up to 1080p30, MJPEG (up to 100 Mpixel/s), and Flash. It can also support concurrent H263 encode and decode for video conference applications. For noise reduction of decoded MPEG2/MP4pt2/DivX/Flash source material, a secondgeneration deblocking and deringing filter is provided, based on DSE (Digital Source Enhancer) Technology with 2D Analysis window and Texture Adaptive Filter. DocID023557 Rev 10 29/604 Information classified Confidential - Do not copy (See last page for obligations) General transport packet handling features are listed below. System-on-chip subsystems overview STiH271EL Decoding and display of DVB phase 1 compatible 3DTV content up to 1080i60, 1080p24 and 720p60 is supported in the following formats: 4.8 Side-by-side Top and bottom Video display The STiH271EL displays video using the Main and Auxiliary display processors. The video is decoded and reconstructed by the multi-standard high-definition video decoder. Display, composition and output Cursor Background Main video display processor VID2 VID2 ti a HQVDPLite l Cursor HDCP HDMI Main VID1 display en Graphics [4:1] GDP4 Lite on NOTE: GDP[1,2], GDP3, GDP4 can be assigned to Main or Aux Mixer. GDP1 and GDP2 are restricted to be attached to the same mixer, which can be either Main or Aux. fid GDP3 Auxiliary composition Main output stage Main mixer GDP2 Lite Main analog outputs YPbPr or RGB Auxiliary display Aux mixer composition Auxiliary output stage Auxiliary analog VID1 video display processor STBus C Confidential GDP1 outputs Compositor YPbPr or YC, CVBS Background The main video program is displayed through the Main video display processor (HQVDPlite). Either the same video program or a different program (in the case of PIP) is displayed through the auxiliary video display processor. Each display processor can be configured to format the video differently and display the video with different timing. Separate VTGs (video timing generators) are provided to support this feature. The display processors adapt the decoded video to a format suitable for display, taking into account differences in scanning method, resolution, aspect ratio and scanning frequency. The Main display processor receives decoded or acquired video from memory, and performs block-to-line conversion, pan and scan, and vertical and horizontal format conversion. There is also a DEI (de-interlacer) to perform interlace-to-progressive conversion on standard or high definition pictures using motion estimation. The Auxiliary display processor receives decoded or acquired (and possibly decimated) video, and performs pan and scan, vertical format conversion, horizontal format conversion and color tint and saturation control. 30/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Figure 5. STiH271EL 4.8.1 System-on-chip subsystems overview High quality video display processor (HQVDP) lite The STiH271EL integrates a High Quality Video Display Processor (HQVDPlite) implementing VC1 Range Engine, Deinterlacing with Film Mode Detection, Rescale, Image Quality improvement. The HQVDPlite performs motion and detailed adaptive deinterlacing on video sources up to 1080i. Film mode detection enables original film sources to be deinterlaced without losing vertical resolution. The HQVDPlite engine has also been upgraded with CSD+ and DCDI+ algorithms for a higher deinterlacing quality. Peaking, programmable frequency, adaptive coring, HD and SD compatible CTI, 2D transition improvements, improved sensitivity to noise Contrast enhancement, fully programmable, chroma saturation compensation en Auxiliary processor fid The auxiliary video display processor is a high-quality video scaling engine used to read pictures in frame buffers either reconstructed by the video decoder or captured by the video input in raster format. on The auxiliary video display processor (VDP) is flexible and can scale from the various input formats to various output formats; it manages the 4:3-to-16:9 and reverse conversion. Those conversions can be done either through pan and scan, or letter box, and side bars. C Confidential 4.8.2 ti a l Image quality improvement (IQI) processing is provided to enhance video quality for IDTV applications. The following features are supported for the processing of decoded primary video for the main display: DocID023557 Rev 10 31/604 Information classified Confidential - Do not copy (See last page for obligations) The STiH271EL HQVDPlite is able to upscale and downscale images by applying extra algorithms on top of the classical H and V SRC. System-on-chip subsystems overview 4.9 Graphic display 4.9.1 Graphics layers STiH271EL The STiH271EL has four independent graphics layers known as GDPs (graphics display pipelines) (see Figure 5). Two GDPs are fully featured and two are lighter version. Each GDP receives pixel data from memory and features the following: Supports ARGB formats, including ARGB1555, ARGB4444, RGB565, RGB888, ARGB8565, ARGB8888 Supports YCbCr4:2:2R, YCbCr888 formats Supports pre-multiplied or non pre-multiplied RGB components Color space conversion matrix, (YCbCr 601/709, chroma signed / unsigned to RGB) Gain and offset adjustment Per-pixel alpha channel combined with per view port global alpha ti a l Five-tap horizontal sample rate converter, for horizontal up-sampling. The resolution is 1/8th pixel (polyphase filter with eight sub-positions). This feature is not present in GDPlite en Color keying capability Three-tap vertical filter (this feature is not present in GDPlite) fid In STiH271EL, the graphics layers delivered by GDP1 and GDP2 can be routed to the main composition mixer or the auxiliary composition mixer. GDP1 and GDP2 are restricted to be routed to the same mixer (either Main or Aux mixer). However, there is no such restriction for GDP3 and GDP4. 4.9.2 Cursor layer on Note: The cursor is defined as a 128 128 pixel area held in local memory, in ACLUT8 format. Each cursor entry is a 16-bit ARGB4444 color plus alpha value. The alpha factor of 4 bits handles an anti-aliased cursor pattern on top of the composed output picture. C Confidential Link-list based display engine, for multiple viewport capabilities Cursor plane features The cursor plane incorporates the following features: 32/604 ACLUT8 format, with ARGB4444 CLUT entries. 256 colors can be simultaneously displayed for the cursor pattern, among 4096 colors associated with a 16-level translucency channel Size is programmable up to 128 128 Hardware rectangular clipping window, out of which, the cursor is never displayed (perpixel clipping, so only part of the cursor can be out of this window, and consequently transparent) Current bitmap is specified using a pointer register to an external memory location, making cursor animation very easy Programmable pitch, so that all cursor patterns can be stored in a single global bitmap DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) STiH271EL 4.9.3 System-on-chip subsystems overview Display compositor The display compositor consists of an 8-layer digital mixer (mixer 1) (Figure 6), intended for the Main TV display, and a 3-layer digital mixer (mixer 2) (Figure 7), intended for an Auxiliary display for applications including connection to a VCR/DVD-R. Each mixer alpha blends graphics and video layers on a pixel-by-pixel basis, based on alpha component values provided by each layer. Mixer 1 planes Up to four graphics layers GDP1, GDP2, GDP3, GDP4 Main video display Aux video display Cursor plane ti a l A background color (RGB888 format, programmable through registers) Gamma mixer 1 planes: example with 2 GDP layers only en Figure 6. Information classified Confidential - Do not copy (See last page for obligations) The mixer 1 display planes are as follows: Background color GDP3, GDP4 and main video ordering is interchangeable Confidential GDP3 graphics GDP4 graphics cursor 75:45 75:45 Mixer 2 planes AF T de nt ia l C on fid Main video The mixer 2 display planes are as follows: A background color (RGB888 format, programmable through registers) Up to four graphics layers GDP1, GDP2, GDP3, GDP4 Main video display Aux video display DocID023557 Rev 10 33/604 STiH271EL Gamma mixer 2 planes: example with 1 GDP only Auxiliary video D Figure 7. C System-on-chip subsystems overview 75:45 Main display output stage Main analog output HDMI output en fid Confidential The display composition from mixer 1 can be output on any of the Main display output interfaces (see Figure 5). These are: The main analog output interface supports YPbPr or RGB analog output with or without embedded syncs. on Programming flexibility is provided to support different display timings and resolutions. These include support for SMPTE and ARIB SD and HD formats (720p, 1080i ...) and panel displays with a pixel clock up to 148.5 MHz. Timings and levels can be programmed to comply with EIA770.x (x = 1, 2, 3) requirements. 4.9.5 C The HDMI output provides HDCP-compliant, copy-protected, digital output of the Main display composition. Auxiliary display output stage The display composition from mixer 2 is output on the Auxiliary display output interface. This interface contains a digital encoder that encodes the output from the auxiliary mixer into a standard analog baseband PAL/NTSC signal and into YPbPr/RGB components. The digital encoder performs closed-caption, CGMS, WSS, Teletext and VPS encoding. An integrated quad-DAC provides analog TV output on which it is possible to output S-VHS(Y/C) + CVBS. The output of the digital encoder can be routed both to the auxiliary DACs (YC, CVBS) and to the main output DACs (YPbPr / RGB) at the same time, allowing all quad DACs to be used for SD output while the HDMI output is displaying in the HD format. For information on the video format outputs on quad-DAC, refer to Table 12: Video format. 34/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 4.9.4 ti a l GDP2 graphics STiH271EL 4.9.6 System-on-chip subsystems overview 3DTV on HDMI 1.4b The STiH271EL integrates an upgraded HDMI formatter, which is able to transmit in the following HDMI 1.4b modes: Format 0 progressive (frame packing up to 720p60L60R or 1080p60L60R) Format 0 interlaced (field packing up to 1080i60L60R) Format 6 (top and bottom half resolution) Format 8 (side-by-side half resolution) l 2D graphics processing unit ti a 4.10 en fid The 2D blitter receives data from the local memory through three input sources, source 1, source 2 and source 3. Source 1 is used for frequent operations such as color-fill or simple source-copy; it has a 64-bit wide internal bus and performs according to the pixel format. All operators always apply to source 2. Source 3 is an additional source working with source 2 to retrieve macro block (MB) formats from memory in a single node. The processing pipeline bus is always a pixel bus (ARGB8888 or AYCbCr8888 format), whatever the format of the source inputs. Sources 1, 2 and 3 are used simultaneously for read, modify, and write operations. on The 2D blitter is software controlled by a link-list mechanism. Each node of the link list is an instruction that contains all the necessary information to proceed. C Confidential The 2D graphics processor (also called the blitter engine) is a CPU-independent engine for graphics picture processing. It functions as a triple-source 2D DMA, with a set of powerful operators, and is used as an accelerator for graphics picture handling. DocID023557 Rev 10 35/604 Information classified Confidential - Do not copy (See last page for obligations) These 3D output formats can be of any of the following 3DTV decoded contents: 720p50/60 Side-by-Side (SbS), 720p50/60 Top-and-Bottom (TaB), 1080i50/60 SbS, 1080p24 SbS, 1080p24 TaB. System-on-chip subsystems overview STiH271EL The blitter features are as follows: Solid color fill of rectangular window Solid color shade (fill + alpha blending) Bi-endian support Two-source copy with alpha blending or logical operation between them 4:2:2 raster / macro-block and 4:2:0 macro-block as source format Color space conversion RGB to/from YCbCr Color expansion (CLUT to true color) Color correction (gamma, contrast, gain) 2D resize engine with high-quality filtering Adaptive flicker filter from memory to memory Spatial de-interlacing Color keying capability Rectangular clipping en ti a l Programmable source / target scanning direction, both horizontally and vertically, in order to cope correctly with overlapping source and destination area 1-bit / 8-bit clip-mask bitmap for random shape clipping can be achieved in two passes Plane mask feature available fid on Source and destination windows can all be defined using an XY descriptor, with pixel accuracy whatever the format, from 1 to 32 bpp. Most of these operators can be combined in a single blitter display pass: For instance, take a YCbCr 4:2:2 bitmap, convert it to 4:4:4 RGB, resize it and finally blend it on an RGB565 background picture. 4.11 Audio subsystem 4.11.1 Overview C Confidential One source copy, with one or several operators enabled (color format conversion 2Dscaling) The main function of the STiH271EL audio subsystem is to decode and play different standards of multi-channel compressed audio streams. The audio stream (encoded or decoded) can be received from an external source through the PCM input interface, or from an internal source such as the transport subsystem through the memory. The audio decoder may have to decode simultaneously two different encoded audio streams when an audio description channel is provided (the main audio stream and a 2-channel audio description channel) or when listening to and recording to VCR two different audio streams. A programmable 650 MHz ST231 CPU core provides the flexibility and performance for decoding multi-channel advanced audio streams. Concurrent decoding of an audio description channel is also supported. The STiH271EL can decode MPEG1, MPEG2, MP3, MPEG4 AAC, AAC+ (v1/v2), Dolby Digital, Dolby Digital Plus, WMA, and WMApro audio streams. The ST231 audio processor is able to decode multi-channel streams concurrently with down-mixing, post-processing and transcoding for simultaneous S/PDIF output. PCM mixing and volume equalization (for example, SRS TruVolume) are also supported. As with video there is the flexibility and performance to download and run other web-oriented media codecs, such as Real Audio, Vorbis, and FLAC. 36/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) STiH271EL System-on-chip subsystems overview Figure 8. Audio architecture pcmrd0_lrclk_sel PCMP #1 2-ch analog ADAC clk_pcm1 FS2[3] pcmp_valid_sel clk_pcm2 FS1[2] clk_pcm0 FS0[2] 2-ch I S en HDMI SS I2S to ch1,2,3 HDMI interface S/PDIF fid ch0 PCM mixing HDMI cell PHY S/PDIF interface on S/PDIF HDMI Each decoded audio stream can be mixed with a PCM file stored in memory, following an optional sample rate conversion to adapt the sampling rate of the two streams. C Confidential ti a PCMR #0 PCMP #0 2-ch I S l pcmrd0_lrclk_ret_sel PCM output, downmixing Each multi-channel decoded PCM stream can be downmixed to generate a 2-channel PCM stream. The downmixed stream can then be played through a stereo 24-bit DAC. An 2-channel digital PCM output and a digital S/PDIF output are available and can be used independently. Compressed data, S/PDIF output Compressed audio data can also be delivered on the S/PDIF output to be decoded by an external decoder/amplifier. HDMI output The STiH271EL HDMI output supports compressed and uncompressed audio formats, and can deliver audio data to an HDMI sink device. The audio data is delivered by the audio subsystem to the HDMI subsystem through an internal I S-to-S/PDIF player. Compressed data is sent through an S/PDIF player. Uncompressed data is sent through a PCM player using I S-to-S/PDIF translation. DocID023557 Rev 10 37/604 Information classified Confidential - Do not copy (See last page for obligations) clk_spdif PIO multiplexing PCMP #2 FS2[0] System-on-chip subsystems overview STiH271EL Audio decoder features The audio decoder features are as follows: MP3 - MPEG-2 layer II, MPEG-2 AAC - MPEG-4 AAC LC 2-channel / 5.1-channel - MPEG-4 AAC+SBR 2-channel / 5.1-channel Dolby(R) Digital EX - Dolby(R) Digital+ - Pro Logic(R) II - DTS-HD - DTS 5.1 downmixed to two channels for analog output - MLPTM - DTS(R) - WMA-9, WMA9-Pro - AC3 Dolby Digital 5.1 downmixed to two channels for analog output - AAC/Adts, AAC+/Adts (AAC SBR) en ti a l - Encoded (IEC 61937) or decoded (IEC 60958) digital audio on S/PDIF output with Dolby Digital 5.1 compressed stream passed through for local TV decoding Integrated audio DACs TV outputs, providing left and right outputs plus programmable left and right to mono output Programmable tone generator for dish alignment Simultaneous output of PCM stereo (downmixed Dolby Digital) on HDMI and BTSC on PCM outputs, plus downmixed Dolby Digital on audio DAC and compressed Dolby on S/PDIF BTSC stereo encoding PCM mixing with internal or external source with sample rate conversion (32, 44.1, 48 kHz) 6-to-2 channel downmixing PCM audio input (I S format) Stereo PCM digital outputs Stereo analog outputs Post-processing (channel virtualization): 38/604 - - Dolby(R) Pro 1.0 - TruSurround XTTM - Dolby(R) 6-to-2 channel down-mixing - Karaoke, volume control, bass redirection - 8-channel 9-band equalizer Re-encoding: - DTS re-encoding before digital S/PDIF output - Dolby(R) Digital re-encoding before S/PDIF output DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) MPEG-1 layer I, II and III fid - on Programmable audio decoding for each TV output: C Confidential STiH271EL 4.11.2 System-on-chip subsystems overview Functional units The audio subsystem includes the following functional units: ST231 audio processor core, running at 650 MHz, which executes the decoding algorithms, sample rate conversion, postprocessing and volume control One stereo PCM reader that captures the data at the PCM input and stores it in memory using an FDMA channel One stereo PCM player Two 2-channel PCM players Three frequency synthesizer banks that generate the PCM clocks (oversampling clock 256 Fs) used by the S/PDIF, PCM players and audio DACs en Multichannel DMA support The STiH271EL has two, multi-channel, burst-capable, RISC-based FDMA controllers that support the following: 16 channels Fast 2D unaligned memory-to-memory transfers of graphics and stills Real-time stream transfers to and from memory with or without pacing Three external pacing signals for paced transfers to and from external peripherals 4.13 Interfaces 4.13.1 USB on fid C Confidential 4.12 Stereo 24-bit audio DACs ti a l One S/PDIF player that reads decoded PCM data or encoded data from memory through an FDMA channel and outputs it on the S/PDIF output, or that feeds the HDMI output External consumer peripherals are supported by two USB 2.0 interfaces The USB 2.0 interfaces include: 4.13.2 One USB 2.0 Dual PHY: it handles the low-level USB protocol and signaling. This includes features such as: data serialization and de-serialization, bit stuffing and clock recovery and synchronization. The `dual PHY' supports three USB physical layers, all Full USB 1.1 (FS and LS) and USB 2.0 (HS) compliant Two ECHI / OHCI USB host controllers with integrated linked-list DMA engines Efficient bus access for DMA controllers Individual power control for each USB port A 480-MHz PLL Ethernet Ethernet MAC The STiH271EL integrates a full-duplex, Ethernet MAC controller. PHY layer technologies that can be connected to the integrated Ethernet MAC controller include 802.11 WLAN, DocID023557 Rev 10 39/604 Information classified Confidential - Do not copy (See last page for obligations) System-on-chip subsystems overview STiH271EL HomePlug AV, MoCA, standard Ethernet 802.3, and so on. MAC signals are internally connected to the PHY via MII interface and are also coming onto the pad which can be connected to an external PHY. Each Ethernet MAC supports the interface standards and interface frequencies shown in the following table. STiH271EL Ethernet MAC interface standards Frequencies Number of pins RMII 50 MHz 8 MII/TMII 25 MHz, 50 MHz 18 Rev MII 25 MHz 18 l Interface ti a fid en The integrated Ethernet PHY is an IEEE 802.3/802.3u compliant single-port fast Ethernet transceiver for both 100 Mbps and 10 Mbps operations. It supports auto MDI/MDIX function to simplify the network installation and reduce the system maintenance cost. The PHY is designed to use category 5 unshielded twisted-pair cable connecting to other LAN devices. A PECL interface is supported to connect with an external 100Base-FX transceiver. The PHY supports several power saving modes including APS, IEEE 802.3az Energy Efficient Ethernet (EEE) and Wake-on-LAN (WOL). The Ethernet PHY comprises a built-in 49.9 resistors for simplifying BOM. 4.13.3 on Clock to the PHY may be sourced through a dedicated external crystal (mandatory to support wake up on LAN feature) or from an internal source as described in Section 20.9: Ethernet PHY. SD-MMC, SDIO The STiH271EL integrates an SD-MMC, SDIO controller that supports SD-MMC/SDIO interface v4.3 and SD HC v2.0 Part A2. It can be used to connect an external (removable) memory card or to connect an on-board eMMC Flash device. This enables the use of lowcost MLC NAND Flash for content storage (music, photos and so on), or for HDD-less DVR time-shift applications. C Confidential Ethernet PHY The controller supports data transfers in 1-bit, 4-bit and 8-bit modes, and SPI mode at variable host clock rates between 0 and 52 MHz. CRC checking of commands/data and card detection are also supported. 4.13.4 Standard peripherals The STiH271EL has many dedicated internal peripherals for digital set-top box applications (some of these peripherals are in the always on domain during power standby, see Section 4.16: Standby controller), including: 40/604 Two smartcard interfaces: - Smartcard interface 1 can be configured as a generic smartcard (UART-based) - Smartcard interface 0 can be configured as a generic smartcard (UART-based), but also as an ISO7816, EMV2000 and NDS compliant smartcard. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 2. STiH271EL System-on-chip subsystems overview A programmable hardware power controller allows the power control signal to be switched when card insertion or removal is detected. Five ASCs (UARTs), two of which may be used by the smartcard interfaces Seven SSCs for I C/SPI master / slave interfaces Sixteen 8-bit general purpose IO (PIO) ports (3.3 V capable) Multi-channel, infrared blaster/decoder interface module One 4 4 front panel key matrix scanner Long time-out (approximately 4 seconds) front panel reset l STBus interconnect ti a 4.14 Four-channel PWM module with two PWM outputs, two capture inputs and two compare inputs en 4.15 Clock generation The STiH271EL includes five clock generator subsystems: Clock generator A0 for the CPUs, GPU, EMI and interconnect clocks Clock generator A1 for the display pipeline, STFE, FDMAs slim and interconnect clocks FS0 for the main display, video output stage and peripheral clocks FS1 for the aux video and aux audio clocks FS2 for the peripheral clocks on fid The clock generators are associated with two external sources: A 30-MHz oscillator One alternate system clock input C Confidential The STiH271EL on-chip communication network is implemented with a mixed STBus/STNoc interconnect which connects all the system initiators (CPUs, DMAs,...) to the target resources (EMI, LMI, and so on). The VCXO functionality is provided internally by digitally controllable frequency synthesizers and an integrated clock recovery module. 4.16 Standby controller The STiH271EL has a standby controller to support passive powerdown mode. It consists of microcontroller and support peripheral to bring the system in required state. The bring up of STiH271EL is fully software controlled. DocID023557 Rev 10 41/604 Information classified Confidential - Do not copy (See last page for obligations) System-on-chip subsystems overview STiH271EL The main features of the standby controller are listed below. Power supply - single 3V3 input with embedded core voltage regulator and low voltage monitoring. Remote control - IR, UHF receiver, and IR transmitter. Key scan - digital, front panel device up to 16 buttons. Standby button with reset on sustained push. External interrupt for generic wakeup triggers. HDMI CEC. Clocking - internal crystal free or external crystal (32 kHz or up to 50 MHz) options. RTC - internal clock or external 32768 kHz in system trim. Ethernet with and without WOL, unicast, broadcast and magic packet. l Two UARTs Two IR receiver and 1 transmitter PIO 0 to PIO 3 Key scan Ethernet Two PWMs (2x capture/compare) CEC ti a Three SSCs fid en 4.17 on Please refer to the Chapter 25: Alternate functions on PIO for exact identification of the peripherals belonging to the standby mode feature. System services The STiH271EL supports a number of on-chip system service functions including: Reset control Three watchdog controllers and a reset out RTC (real-time clock) Protected JTAG boundary scan port Diagnostic control for ST40 toolset Diagnostic control for ST231 toolset Low-power control with wake up from internal timer, or external interrupt, or IR receiver 42/604 C Confidential The following are the peripherals available in the standby domain: Flexible low-power architecture; subsystems can be on, off, or clocked slowly to allow the standby modes to be tailored to the application DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) STiH271EL Package mechanical data Package mechanical data Figure 9. Bottom view (package type: FPBGA 27 x 27 x 2.19 761 R32/P0.8 and R19/P1.0 Ball 0.5) C on fid Confidential en ti a l Information classified Confidential - Do not copy (See last page for obligations) 5 DocID023557 Rev 10 43/604 Package mechanical data STiH271EL 44/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) C on fid Confidential en ti a l Figure 10. Top view (package type: FPBGA 27x27x2.19 761 R32/P0.8 and R19/P1.0 Ball 0.5) STiH271EL Package mechanical data Table 3. JEDEC standard package dimensions Millimeters Inches Min. Typ. Max. A - - 2.19 - - 0.086 A1 0.27 - - 0.011 - - A2 - 0.52 - - 0.020 - A4 - 1.20 - - 0.047 - b 0.45 0.50 0.55 0.018 0.020 0.022 D 26.80 27.00 27.20 1.055 1.063 1.071 D1 - 24.80 - - 0.976 - D2 - 24.00 - - l 0.945 - E 26.80 27.00 27.20 1.055 1.063 1.071 E1 - 24.80 - - 0.976 - E2 - 24.00 - - 0.945 - e - 0.80 - - 0.031 - e1 - 1.00 - - 0.039 - F - 1.10 - - 0.043 - F1 - 4.50 - - 0.177 - F2 - 9.50 - - 0.374 - ddd - - 0.20 - - 0.008 eee - - 0.15 - - 0.006 fff - - 0.08 - - 0.003 on en ti a Max. fid Typ. Environmentally friendly packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. DocID023557 Rev 10 45/604 Information classified Confidential - Do not copy (See last page for obligations) 5.1 Min. C Confidential Dimension BGA footprint 6 STiH271EL BGA footprint The ball grid array (BGA) diagram gives the allocation of balls to the package, shown from the top looking down using the PCB footprint. Signal names include `NOT' if they are active low; otherwise they are active high. Signal names prefixed with "C_" represent the front-end signals. Signal names prefixed with "Q_" represent the Ethernet PHY signals. Key to BGA diagrams Transport SIG PIO/peripheral SIG Video/HDMI SIG SIG en Audio System (JTAG, interrupts) Confidential Memory (EMI, LMI) Front end fid Ethernet PHY Power connection(1) Do not connect(2) No ball on Ground No Key SIG SIG SIG SIG VDD GND NC DNC C 1. There is no internal connection. Routing is allowed over these balls. 2. There is an internal connection. Routing is NOT allowed over these balls. 46/604 DocID023557 Rev 10 NC DNC Information classified Confidential - Do not copy (See last page for obligations) Type ti a Function l Table 4. Confidential 1 Ball map 2 3 4 5 A NC DNC DNC DNC B VDD3V3_DE CAP DNC DNC DNC DNC C DNC DNC DNC DNC DNC D PIO10[3] E PIO10[2] PIO10[7] PIO10[4] PIO10[5] PIO10[6] PIO10[0] PIO10[1] DNC PIO8[1] PIO8[4] PIO8[0] DNC BA F BB G PIO8[2] PIO8[3] PIO8[5] DNC J PIO9[1] PIO9[3] PIO9[0] DNC PIO7[2] PIO7[4] PIO7[7] PIO6[7] DNC PIO6[6] EMI_DATA[7] PIO6[5] EMI_DATA[6] DNC EMI_DATA[4] K N DocID023557 Rev 10 P EMI_DATA[2] EMI_DATA[1] DNC EMI_DATA[0] EMI_NOTOE EMI_ADD[10] T EMI_ADD[9] EMI_NOTCS[ 0] U EMI_RDNOT WR EMI_NANDR DY EMI_NOTCS[ 2] EMI_NOTCS[ 1] EMI_NOTCS[ 3] EMI_DATA[3] GND DNC DNC DNC DNC DNC DNC DNC DNC LMIPLL_TES T GND GND 11 LMI_VREFDQ [1] DNC PIO12[5] PIO12[6] PIO12[4] DNC Y PIO12[7] PIO12[3] PIO6[0] PIO6[1] AA PIO12[2] PIO5[6] NC PIO5[7] NC AC C_SCL PIO5[5] AD NC NC C_GPIO3 C_DATA2 AE C_AGC_BB NC NC C_DATA0 C_AVDD2V5 C_AVDD2V5 C_AVDD2V5 GND C_SCLT NC LMI_ZQ C_QP C_QM NC C_RF_LEVEL LMI_ADD[7] LMI_ADD[13] LMI_ADD[0] LMI_ADD[15] LMI_ADD[1] LMI_ADD[14] LMI_ADD[6] LMI_ADD[10] GND LMI_VREFCA LMI_BA[1] GND LMI_CKP[0] LMI_DATA[7] LMI_DATA[14 ] LMI_DATA[12 ] LMI_CKN[0] LMI_DATA[5] LMI_DATA[1] LMI_DATA[8] GND LMI_NOTRET ENTION GND LMI_CKE GND LMI_DQSP[1] LMI_DQSN[1] 14 15 16 17 18 PIO4[4] PIO9[5] PIO4[5] GND PIO9[4] GND GND GND GND GND GND GND GND LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 PIO11[5] PIO11[4] PIO11[3] DNC PIO8[6] PIO9[2] PIO7[1] DNC GND PIO9[7] PIO8[7] PIO9[6] PIO7[0] PIO7[3] DNC PIO7[6] EMI_ADD[12] DNC EMI_ADD[8] EMI_ADD[14] PIO6[4] EMI_ADD[13] DNC EMI_ADD[7] EMI_ADD[5] DNC PIO11[0] LMI_VDD1V5 LMI_VDD1V5 C PIO11[1] PIO7[5] GND VDD1V1 CA EMI_ADD[4] DNC EMI_DVBCIR EG EMI_NOTBE[ 1] DNC BM NC DNC PIO12[1] PIO12[0] DNC BN NC PIO4[6] PIO6[2] PIO4[7] VDD3V3 NC PIO6[3] C_DATA3 GND 47/604 AK C_IM C_IP C_INCM NC C_CS1 AL C_XTAL_I C_XTAL_O NC NC GND AM NC NC NC NC 1 2 3 4 C_VDD1V2 6 GND GND 2 C_VDD1V2 GND GND 3 C_VDD1V2 PIO5[4] GND 8 9 10 11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND fid GND GND GND GND GND GND CB GND GND GND GND GND GND GND CC GND GND GND GND GND GND GND GND CF VDD1V1 GND GND GND GND GND GND CG VDD1V1 GND GND GND GND GND GND en GND C_VREG_1V2 C_VDD3V3 GND C_AGC_RF C_VDD3V3 GND 8 9 10 VDD1V1 VDD1V1 GND GND VDD1V1 CE GND GND GND VDD1V1 CF GND GND GND VDD1V1 CG VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD3V3 VDD3V3 VDD3V3 VDD3V3 VDD3V3 VDD3V3 CJ VDD3V3 VDD3V3 VDD3V3 VDD3V3 VDD3V3 GND GND GND GND VDD2V5_1 CK GND GND GND GND GND GND GND HDMI_VDD1V 1 HDMI_VDD1V 1 HDMI_VDD1V 1 VDD2V5_1 1 2 3 4 5 6 7 8 9 10 11 GND C_DATA7 GND C_ERROR C_AUX_CLK C_GPIO9 GND C_GPIO5 6 C_GPIO1 11 GND GND GND 9 GND DNC GND GND GND C_GPIO8 GND GND GND VDD3V3_DE CAP C_GPIO4 13 14 12 15 VDD1V1_2 GND 10 VDD1V1_2 GND 16 DNC 17 VDD1V1_2 PIO4[0] VDD1V1_2 VDD1V1_2 DNC USB0_DP USB0_DM SYS_CLKOS C PIO4[3] 19 20 18 21 CORESENSE _DVDD1V1 C LMI_DM[0] LMI_DATA[13 ] CORESENSE _DGND1V1 THS_AVDD2 V5 VDD2V5_2 D LMIPLL1_VD D2V5 LMIPLL0_VD D2V5 LMIPLL2_VD D2V5 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 DNC PIO13[6] PIO14[6] PIO13[5] DNC PIO14[7] PIO13[0] PIO14[1] PIO15[7] PIO15[0] PIO15[4] K PIO15[5] M PIO13[7] DNC JTAG_NOTT RST VDD1V1 PIO14[5] BD SYS_AONOT BG RESETIN JTAG_TMS VDD1V1 VDD1V1 F VDD1V1 G BC BF JTAG_TCK E LMI_VDD1V5 BB PIO14[0] BH VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 BJ VDD3V3 VDD3V3 VDD3V3 VDD3V3 VDD3V3 BK VDD3V3 SBC_VDD3V3 Q_TEST_ON SBC_VDD1V1 SBC_VDD1V1 BL OUT VDD3V3 Q_VDD3V3 PIO1[5] PIO3[3] PIO1[3] BM GND Q_VDD3V3 PIO1[2] PIO1[0] DNC BN l GND USB_VDD2V5 USB_VDD2V5 15 PIO4[2] LMIVSENSE_ VDD1V5 DNC 14 SYS_CLKIN LMI_DATA[6] JTAG_TDI VDD2V5_3 USB_TXRTU NE LMI_DM[1] JTAG_TDO USB_VDD3V3 DNC B LMI_DQSN[0] VDD1V1 HDMI_VDD2V 5 DNC LMI_VREFDQ [0] BE HDMIPLL_DV DD1V1 USB_VDD3V3 LMI_DATA[4] DNC VDD2V5_1 13 GND LMI_DATA[0] PIO15[1] HDMI_VDD1V 1 USB_VDD3V3 GND VDD1V1_2 CL HDMIPLL_AV DD2V5 HDMIPLL_AV DD2V5 12 11 DNC GND VDD2V5_4 VDD1V1_2 VDD1V1_2 GND GND 8 GND GND GND GND VDD2V5_4 VDD2V5_4 GND GND GND GND GND GND GND 7 C_GPIO7 GND NC C_NOT_RES ET DNC C_GPIO2 GND LMI_DATA[15 ] 32 H J L DNC PIO14[3] PIO15[2] PIO15[6] SYS_AONOT WDOGRSTO UT SYS_CLKINA LT SYS_NOTAS EBRK SYS_NOTRE SETIN VDD1V1 VDD1V1 SYS_32KOSC IN SYS_32KOSC OUT VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD1V1 VDD3V3 VDD3V3 PIO2[5] PIO1[7] PIO0[2] Q_RESET_N PIO3[6] PIO3[5] PIO3[4] PIO3[1] N P R T U V CH VDD3V3 CL A LMI_DQSP[0] PIO14[4] ti a VDD1V1 VDD1V1 VDD1V1 VDD1V1 5 C_VDD3V3 VDD1V1 GND CJ C_SCANMOD E C_VDD1V2 GND NC CD CK C_GPIO6 C_VBASE GND GND 31 LMI_DATA[2] LMI_VDD1V5 BA PIO13[4] PIO14[2] PIO13[2] 30 LMI_DATA[11 ] 19 LMI_VDD1V5 PIO13[1] PIO13[3] 29 LMI_DATA[9] PIO15[3] VDD1V1 GND GND GND LMI_VDD1V5 LMI_VDD1V5 28 VDD1V1 VDD1V1 GND VDD1V1 GND CA GND CE C_GPIO0 C_VDD1V2 7 7 VDD1V1 NC 4 DNC 6 VDD1V1 C_D_NOT_P C_CLK_OUT GND GND GND GND C_CS0 C_STR_OUT GND C_DATA5 PIO5[3] PIO5[2] C_DATA1 C_DATA6 PIO5[0] 5 CB VDD1V1 VDD1V1 GND GND 4 DNC EMI_ADD[3] EMI_NOTBE[ 0] PIO5[1] GND GND 3 CC VDD1V1 GND VDD1V1 VDD1V1 GND GND 2 DNC EMI_ADD[6] BL DNC GND GND VDD1V1 VDD1V1 VDD1V1 VDD1V1 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 LMI_VDD1V5 VDD1V1 GND GND DNC EMI_ADD[11] EMI_ADD[1] C_DATA4 GND LMI_VDD1V5 VDD1V1 VDD1V1 on VDD1V1 LMI_VDD1V5 LMI_VDD1V5 VDD1V1 GND VDD1V1 PIO11[7] LMI_VDD1V5 VDD1V1 VDD1V1 PIO11[2] EMI_ADD[2] 5 GND LMI_BA[2] LMI_ADD[4] 27 13 EMI_TRDYO RWAIT BT GND LMI_ADD[2] LMI_ADD[8] 26 12 1 AJ LMI_ADD[9] GND 25 LMI_DATA[10 ] 23 USB1_DM USB1_DP 22 PIO0[3] PIO1[6] DNC PIO1[4] BP GND GND PIO2[0] PIO0[5] BR HDMIPLL_GN D GND HDMIPLL_GN D GND HDMI_VDD3V 3 HDMICK_VD D3V3 GND 18 19 DNC GND GND HDMI_REXT HDMI_TX1N GND HDMI_TXCKN HDMI_TX0N HDMI_TX1P HDMI_TXCKP HDMI_TX0P 24 25 23 Information classified Confidential - Do not copy (See last page for obligations) 26 DNC ADAC_VHI 17 GND BT Q_REGOUT ADAC_VCM GND GND Q_MDC PIO0[1] PIO4[1] 16 GND PIO1[1] DNC PIO3[2] PIO3[0] PIO0[7] PIO2[6] PIO2[4] Y AA AB DNC PIO2[7] PIO2[1] PIO2[2] PIO2[3] PIO0[6] PIO0[4] Q_X2 Q_X1 AD Q_REGOUT PIO0[0] Q_REGIN Q_REGIN AE PIO3[7] Q_REGOUT Q_REGOUT AC BU AF BV BW Q_LED1_PHY AD1 Q_ISET Q_LED3_PHY ALL Q_LED2_PHY AD2 Q_LED0_PHY AD0 GND GND Q_MDI_TN HDMI_TX2N ADAC_VLO HDMI_TX2P VDAC_REXT N GND GND VDAC_REXT P ADAC_RIGHT VDAC_VOUT ADAC_LEFT ADAC_VDD3 V3 29 30 27 W 28 AG AH Q_MDI_TP AJ Q_MDI_RN Q_MDI_RP AK VDAC_UOUT VDAC_XOUT AL VDAC_WOU T NC AM 31 32 BGA footprint GND C_SDAT LMI_BA[0] LMI_ADD[12] 24 LMI_DATA[3] 22 11 BW AH LMI_ODT 21 10 EMI_DVBCIN OTWE BV AG LMI_NOTRAS 20 LMI_ADD[11] 9 EMI_DVBCIIO RD BU AF LMI_NOTRES ET 19 LMI_VDD1V5 _DECAP 8 BR C_SDA LMI_ADD[5] 18 7 BK BP AB LMI_NOTCS 17 6 CH W LMI_NOTCAS GND 16 15 5 BJ V 14 LMI_ADD[3] 1 BH 13 LMI_NOTWE 4 CD R 12 3 BG EMI_DATA[5] 10 DNC DNC BF M 9 DNC 2 BE L 8 LMI_VDD1V5 _DECAP PIO11[6] BD 7 1 BC H 6 STiH271EL Figure 11. Ball list 7 STiH271EL Ball list This chapter gives the ball list for package FPBGA 27 X 27, sorted numerically on ball number. 7.1 Sorted on ball number Table 5. Ball list - sorted on ball number Description NC Not connected A2 DNC Do not connect A3 DNC Do not connect A4 DNC Do not connect A8 LMI_VDD1V5_DECAP Decoupling location for LMI1 digital 1V5 supply, internally connected to the supply (no need to connect to the supply on the board) A9 DNC A13 LMI_NOTWE A14 LMI_ADD[3] A19 LMI_VDD1V5_DECAP A20 LMI_ADD[11] LMI address A24 LMI_DATA[3] LMI data A25 LMI_DATA[10] LMI data A29 LMI_DATA[9] LMI data A30 LMI_DATA[11] LMI data A31 LMI_DATA[2] LMI data A32 NC Not connected B1 VDD3V3_DECAP 3.3 power supply for decoupling B2 DNC Do not connect B3 DNC Do not connect B4 DNC Do not connect B5 DNC Do not connect B7 DNC Do not connect B8 GND Ground B9 DNC Do not connect B10 DNC Do not connect 48/604 en ti a l A1 on fid Do not connect Write enable LMI address Decoupling location for LMI1 digital 1V5 supply, internally connected to the supply (no need to connect to the supply on the board) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Ball name C Confidential Ball STiH271EL Ball list - sorted on ball number (continued) Ball name Description LMI_NOTCAS Column select B13 LMI_NOTCS Chip Select B14 LMI_ADD[5] LMI address B15 LMI_NOTRESET LMI address B18 LMI_ADD[12] LMI address B19 GND Ground B20 LMI_ADD[8] LMI address B21 LMI_ADD[4] LMI address B23 LMI_CKP[0] Differential clock positive B24 LMI_DATA[7] LMI data B25 LMI_DATA[14] LMI data B26 LMI_DATA[12] LMI data B28 LMI_DQSP[0] B29 LMI_DATA[15] B30 LMI_DATA[0] B31 LMI_DATA[4] B32 LMI_VREFDQ[0] C1 DNC C2 DNC C3 DNC C4 DNC C5 DNC C6 DNC C7 DNC C8 DNC Do not connect C9 DNC Do not connect C10 DNC Do not connect C11 LMI_VREFDQ[1] Reference voltage for DQ C12 LMI_NOTRAS Row select C13 LMI_ODT LMI on die termination C14 LMI_BA[0] Bank address C15 LMI_ADD[9] LMI address C16 LMI_ADD[2] LMI address C17 LMI_BA[2] Bank address C18 LMI_ADD[15] LMI address on en ti a l B12 C Differential data strobe positive LMI data LMI data fid Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list LMI data Reference voltage for DQ Do not connect Do not connect Do not connect Do not connect Do not connect Do not connect Do not connect DocID023557 Rev 10 49/604 Ball list Ball list - sorted on ball number (continued) Ball name Description LMI_ADD[1] LMI address C20 LMI_ADD[14] LMI address C21 LMI_ADD[6] LMI address C22 LMI_VREFCA Reference voltage for CA C23 LMI_CKN[0] Differential clock negative C24 LMI_DATA[5] LMI data C25 LMI_DATA[1] LMI data C26 LMI_DATA[8] LMI data C27 LMI_DQSP[1] Differential data strobe positive C28 LMI_DQSN[0] Differential data strobe negative C29 LMI_DM[1] Data mask C30 LMI_DATA[6] LMI data C31 LMIVSENSE_VDD1V5 C32 CORESENSE_DVDD1V1 D1 PIO10[3] D2 PIO10[2] D3 PIO10[7] D4 PIO10[4] D5 DNC D6 DNC D7 LMIPLL_TEST PLL test output D8 GND Ground D9 GND D10 DNC D11 GND Ground D12 LMI_ZQ Reference ball for ZQ calibration D13 GND Ground D14 GND Ground D15 LMI_ADD[7] LMI address D16 LMI_ADD[13] LMI address D17 LMI_ADD[0] LMI address D18 LMI_ADD[10] LMI address D19 GND Ground D20 GND Ground D21 LMI_BA[1] Bank address 50/604 en ti a l C19 LMI voltage sense output 1.5 V power supply for DDR3 Core voltage sensing diagnostic pad on fid Programmable input/output C Confidential Ball Programmable input/output Programmable input/output Programmable input/output Do not connect Do not connect Ground Do not connect DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description GND Ground D23 LMI_CKE Clock enable D24 GND Ground D25 GND Ground D26 LMI_NOTRETENTION Power retention for LMI 1v5 IO ring D27 LMI_DQSN[1] Differential data strobe negative D28 LMI_DM[0] Data mask D29 LMI_DATA[13] LMI data D30 CORESENSE_DGND1V1 Core voltage sensing diagnostic pad D31 THS_AVDD2V5 Thermal sensor 2.5 V analog supply D32 VDD2V5_2 2.5 V power supply (VDD2V5_1 and VDD2V5_2 should be interconnected on PCB) E2 PIO10[5] E3 PIO10[6] E4 PIO10[0] E29 LMIPLL1_VDD2V5 E30 LMIPLL0_VDD2V5 E31 LMIPLL2_VDD2V5 F3 PIO10[1] F4 DNC F29 LMI_VDD1V5 1.5 V power supply for DDR3 F30 LMI_VDD1V5 1.5 V power supply for DDR3 G2 PIO8[1] Programmable input/output G3 PIO8[4] Programmable input/output G4 PIO8[0] Programmable input/output G29 LMI_VDD1V5 1.5 V power supply for DDR3 G30 LMI_VDD1V5 1.5 V power supply for DDR3 G31 LMI_VDD1V5 1.5 V power supply for DDR3 H1 PIO8[2] Programmable input/output H2 PIO8[3] Programmable input/output H3 PIO8[5] Programmable input/output H4 DNC Do not connect H29 DNC Do not connect H30 PIO13[6] Programmable input/output H31 PIO14[6] Programmable input/output en ti a l D22 Programmable input/output Programmable input/output on fid Programmable input/output C Confidential Ball Dedicated 2.5 V power for LMI PLL0 Dedicated 2.5 V power for LMI PLL1 Dedicated 2.5 V power for LMI PLL2 Programmable input/output Do not connect DocID023557 Rev 10 51/604 Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list Ball list Ball list - sorted on ball number (continued) Ball name Description PIO13[5] Programmable input/output J1 PIO9[1] Programmable input/output J2 PIO9[3] Programmable input/output J3 PIO9[0] Programmable input/output J4 DNC Do not connect J29 DNC Do not connect J30 PIO14[7] Programmable input/output J31 PIO13[0] Programmable input/output J32 PIO14[1] Programmable input/output K2 PIO7[2] Programmable input/output K3 PIO7[4] Programmable input/output K4 PIO7[7] Programmable input/output K29 PIO15[7] K30 PIO15[0] K31 PIO15[4] L3 PIO6[7] L4 DNC L29 DNC L30 PIO14[3] M2 PIO6[6] M3 EMI_DATA[7] EMI data input/output M4 PIO6[5] Programmable input/output M29 PIO15[2] Programmable input/output M30 PIO15[6] Programmable input/output M31 PIO15[5] Programmable input/output N1 EMI_DATA[5] EMI data input/output N2 EMI_DATA[6] EMI data input/output N3 DNC Do not connect N4 EMI_DATA[4] EMI data input/output N29 SYS_AONOTWDOGRSTOUT System always-on reset output from watchdog timer N30 SYS_CLKINALT Alternate reference clock for clock generators N31 SYS_NOTASEBRK ST40 debugger breakpoint N32 SYS_NOTRESETIN Voltage monitor / maskable system reset P1 EMI_DATA[3] EMI data input/output P2 EMI_DATA[2] EMI data input/output 52/604 en ti a l H32 Programmable input/output Programmable input/output on fid Programmable input/output Programmable input/output Do not connect Do not connect Programmable input/output Programmable input/output C Confidential Ball DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description EMI_DATA[1] EMI data input/output P4 DNC Do not connect P29 VDD1V1 1.1 V power supply P30 VDD1V1 1.1 V power supply P31 SYS_32KOSCIN 32 kHz oscillator external crystal inputs for real time counter P32 SYS_32KOSCOUT 32 kHz oscillator external crystal inputs for real time counter R2 EMI_DATA[0] EMI data input/output R3 EMI_NOTOE Write enable R4 EMI_ADD[10] EMI address R29 VDD1V1 1.1 V power supply R30 VDD1V1 1.1 V power supply R31 VDD1V1 T3 EMI_ADD[9] T4 EMI_NOTCS[0] T29 VDD1V1 T30 VDD1V1 U3 EMI_RDNOTWR U4 EMI_NANDRDY NAND-Flash Ready U29 VDD3V3 3.3 V power supply U30 VDD3V3 V2 EMI_NOTCS[2] Chip select V3 EMI_NOTCS[1] Chip select V4 EMI_NOTCS[3] Chip select V29 PIO2[5] Programmable input/output V30 PIO1[7] Programmable input/output V31 PIO0[2] Programmable input/output W1 PIO12[5] Programmable input/output W2 PIO12[6] Programmable input/output W3 PIO12[4] Programmable input/output W4 DNC Do not connect W29 Q_RESET_N Reset enable W30 PIO3[6] Programmable input/output W31 PIO3[5] Programmable input/output en ti a l P3 on 1.1 V power supply C EMI address Chip select fid Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list 1.1 V power supply 1.1 V power supply Read write bit 3.3 V power supply DocID023557 Rev 10 53/604 Ball list Ball list - sorted on ball number (continued) Ball name Description PIO3[4] Programmable input/output Y1 PIO12[7] Programmable input/output Y2 PIO12[3] Programmable input/output Y3 PIO6[0] Programmable input/output Y4 PIO6[1] Programmable input/output Y29 DNC Do not connect Y30 PIO3[2] Programmable input/output Y31 PIO3[0] Adaptive Voltage Scaling feedback Y32 PIO3[1] Programmable input/output AA2 PIO12[2] Programmable input/output AA3 PIO5[6] Programmable input/output AA4 NC Not connected AA29 PIO0[7] AA30 PIO2[6] AA31 PIO2[4] AB3 PIO5[7] AB4 NC AB29 DNC AB30 PIO2[7] AC2 C_SDA AC3 C_SCL AC4 PIO5[5] AC29 PIO2[1] Programmable input/output AC30 PIO2[2] Programmable input/output AC31 PIO2[3] Programmable input/output AD1 NC Not connected AD2 NC Not connected AD3 C_GPIO3 General purpose input/output ports AD4 C_DATA2 Parallel MPEG data (bit 2) AD29 PIO0[6] Programmable input/output AD30 PIO0[4] Programmable input/output AD31 Q_X2 25 MHz crystal input AD32 Q_X1 25 MHz crystal input AE1 C_AGC_BB IF AGC control AE2 NC Not connected 54/604 en ti a l W32 C Programmable input/output Programmable input/output fid Programmable input/output on Confidential Ball Programmable input/output Not connected Do not connect Programmable input/output Serial data (open drain) Serial clock (open drain) Programmable input/output DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description NC Not connected AE4 C_DATA0 Parallel MPEG data (bit 0) AE29 Q_REGOUT Regulator power output AE30 PIO0[0] Programmable input/output AE31 Q_REGIN Regulator power input AE32 Q_REGIN Regulator power input AF2 C_AVDD2V5 Analog 2.5 V power supply AF3 C_AVDD2V5 Analog 2.5 V power supply AF4 C_AVDD2V5 Analog 2.5 V power supply AF29 PIO3[7] Programmable input/output AF30 Q_REGOUT Regulator power output AF31 Q_REGOUT Regulator power output AG3 GND AG4 GND AG29 Q_LED1_PHYAD1 AG30 Q_ISET AH2 C_SDAT AH3 C_SCLT AH4 NC AH29 Q_LED3_PHYALL LED 3 or PHY Address ALL AH30 Q_LED2_PHYAD2 PHY address[2] AH31 Q_LED0_PHYAD0 PHY address[0] AJ1 C_QP Positive Q analog input for baseband configuration AJ2 C_QM Negative Q analog input for baseband configuration AJ3 NC Not connected AJ4 C_RF_LEVEL ADC-8 input for RF level monitoring AJ5 C_CS0 Chip select LSB AJ6 C_VDD1V2 Digital 1.2 V power supply AJ7 C_VDD1V2 Digital 1.2 V power supply AJ8 DNC Do not connect AJ9 GND Ground AJ10 C_VBASE Analog regulator output AJ11 C_GPIO2 General purpose input/output ports AJ12 C_GPIO7 General purpose input/output ports AJ13 GND Ground en ti a l AE3 Ground Ground PHY address[1] fid on C Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list Transmit bias resistor SDA tuner (open drain) SCL tuner Not connected DocID023557 Rev 10 55/604 Ball list Ball list - sorted on ball number (continued) Ball name Description GND Ground AJ15 GND Ground AJ16 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) AJ17 DNC Do not connect AJ18 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) AJ19 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) AJ20 GND Ground AJ21 USB_VDD3V3 USB 3.3 V power supply AJ22 USB1_DM USB negative differential signal AJ23 GND Ground AJ24 GND AJ25 GND AJ26 DNC AJ27 HDMI_TX2N AJ28 ADAC_VLO AJ29 GND AJ30 GND AJ31 Q_MDI_TN AJ32 Q_MDI_TP AK1 C_IM AK2 C_IP AK3 C_INCM Internal common mode AK4 NC Not connected AK5 C_CS1 Chip select MSB AK6 C_VDD1V2 Digital 1.2 V power supply AK7 C_VDD1V2 Digital 1.2 V power supply AK8 C_VDD3V3 Digital 3.3 V power supply AK9 GND Ground AK10 C_VREG_1V2 Analog regulator input AK11 C_GPIO1 General purpose input/output ports AK12 DNC Do not connect AK13 GND Ground AK14 GND Ground 56/604 en ti a l AJ14 Ground Ground on fid Do not connect C Confidential Ball HDMI transmitter channel 2 negative differential signal Analog low reference generated in reference block Ground Ground Transmit output pair Transmit output pair Negative I analog input for IF and baseband configuration Positive I analog input for IF and baseband configuration DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description GND Ground AK16 GND Ground AK17 DNC Do not connect AK18 DNC Do not connect AK19 SYS_CLKIN System oscillator external crystal signal AK20 DNC Do not connect AK21 USB0_DP USB positive differential signal AK22 USB1_DP USB positive differential signal AK23 GND Ground AK24 GND Ground AK25 HDMI_REXT HDMI compensation reference AK26 HDMI_TX1N HDMI transmitter channel 1 negative differential signal AK27 HDMI_TX2P AK28 VDAC_REXTN AK29 GND AK30 GND AK31 Q_MDI_RN AK32 Q_MDI_RP AL1 C_XTAL_I AL2 C_XTAL_O AL3 NC AL4 NC AL5 GND AL7 C_VDD1V2 Digital 1.2 V power supply AL8 C_VDD3V3 Digital 3.3 V power supply AL9 GND Ground AL10 C_AGC_RF RF AGC AL12 C_GPIO8 General purpose input/output ports AL13 GND Ground AL14 GND Ground AL15 GND Ground AL18 DNC Do not connect AL19 USB_TXRTUNE Transmitter resistor tune pin AL20 PIO4[2] Programmable input/output AL21 USB0_DM USB negative differential signal en ti a l AK15 HDMI transmitter channel 2 positive differential signal Video-DAC external voltage compensation reference on fid Ground C Confidential Ball Ground Receive input pair Receive input pair Crystal oscillator input/external clock Crystal oscillator output Not connected Not connected Ground DocID023557 Rev 10 57/604 Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list Ball list Ball list - sorted on ball number (continued) Ball name Description GND Ground AL24 HDMI_TXCKN HDMI transmitter clock negative differential signal AL25 HDMI_TX0N HDMI transmitter channel 0 negative differential signal AL26 HDMI_TX1P HDMI transmitter channel 1 positive differential signal AL28 VDAC_REXTP Video-DAC external voltage compensation reference AL29 ADAC_RIGHT Audio-DAC right-channel signal 0 AL30 VDAC_VOUT Video output AL31 VDAC_UOUT Video output AL32 VDAC_XOUT Video output AM1 NC Not connected AM2 NC Not connected AM3 NC Not connected AM4 NC AM8 C_VDD3V3 AM9 GND AM13 VDD3V3_DECAP AM14 C_GPIO4 AM19 SYS_CLKOSC AM20 PIO4[3] AM24 HDMI_TXCKP HDMI transmitter clock positive differential signal AM25 HDMI_TX0P HDMI transmitter channel 0 positive differential signal AM29 ADAC_LEFT Audio-DAC left-channel signal 0 AM30 ADAC_VDD3V3 3.3 V power supply for ADAC AM31 VDAC_WOUT Video output AM32 NC Not connected BA1 PIO4[4] Programmable input/output BA2 PIO9[5] Programmable input/output BA3 PIO4[5] Programmable input/output BA4 GND Ground BA5 PIO9[4] Programmable input/output BA6 GND Ground BA7 GND Ground BA8 GND Ground BA9 GND Ground BA10 GND Ground 58/604 en ti a l AL23 Not connected Digital 3.3 V power supply on fid Ground C Confidential Ball 3.3 power supply for decoupling General purpose input/output ports System oscillator external crystal signal Programmable input/output DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description GND Ground BA12 GND Ground BA13 GND Ground BA14 LMI_VDD1V5 1.5 V power supply for DDR3 BA15 LMI_VDD1V5 1.5 V power supply for DDR3 BA16 LMI_VDD1V5 1.5 V power supply for DDR3 BA17 LMI_VDD1V5 1.5 V power supply for DDR3 BA18 LMI_VDD1V5 1.5 V power supply for DDR3 BA19 LMI_VDD1V5 1.5 V power supply for DDR3 BB1 PIO11[6] Programmable input/output BB2 PIO11[5] Programmable input/output BB3 PIO9[7] Programmable input/output BB4 GND BB5 PIO11[0] BB6 LMI_VDD1V5 BB7 LMI_VDD1V5 BB8 LMI_VDD1V5 BB9 LMI_VDD1V5 BB10 LMI_VDD1V5 1.5 V power supply for DDR3 BB11 LMI_VDD1V5 1.5 V power supply for DDR3 BB12 LMI_VDD1V5 1.5 V power supply for DDR3 BB13 LMI_VDD1V5 1.5 V power supply for DDR3 BB14 LMI_VDD1V5 1.5 V power supply for DDR3 BB15 LMI_VDD1V5 1.5 V power supply for DDR3 BB16 LMI_VDD1V5 1.5 V power supply for DDR3 BB17 LMI_VDD1V5 1.5 V power supply for DDR3 BB18 LMI_VDD1V5 1.5 V power supply for DDR3 BB19 LMI_VDD1V5 1.5 V power supply for DDR3 BC1 DNC Do not connect BC2 PIO8[7] Programmable input/output BC3 PIO11[3] Programmable input/output BC4 PIO11[4] Programmable input/output BC5 PIO11[1] Programmable input/output BC6 VDD1V1 1.1 V power supply BC7 VDD1V1 1.1 V power supply en ti a l BA11 Ground on Programmable input/output C 1.5 V power supply for DDR3 fid Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list 1.5 V power supply for DDR3 1.5 V power supply for DDR3 1.5 V power supply for DDR3 DocID023557 Rev 10 59/604 Ball list Ball list - sorted on ball number (continued) Ball name Description VDD1V1 1.1 V power supply BC9 VDD1V1 1.1 V power supply BC10 VDD1V1 1.1 V power supply BC11 VDD1V1 1.1 V power supply BC12 VDD1V1 1.1 V power supply BC13 VDD1V1 1.1 V power supply BC14 VDD1V1 1.1 V power supply BC15 VDD1V1 1.1 V power supply BC16 PIO13[3] Programmable input/output BC17 PIO13[1] Programmable input/output BC18 PIO13[4] Programmable input/output BC19 PIO13[7] Programmable input/output BD1 PIO9[6] BD2 DNC BD3 PIO9[2] BD4 PIO8[6] BD5 PIO11[2] BD6 VDD1V1 BD7 GND BD8 GND BD9 GND BD10 GND BD11 GND BD12 GND BD13 GND Ground BD14 VDD1V1 1.1 V power supply BD15 VDD1V1 1.1 V power supply BD16 PIO13[2] Programmable input/output BD17 PIO14[2] Programmable input/output BD18 DNC Do not connect BD19 PIO14[5] Programmable input/output BE1 DNC Do not connect BE2 PIO7[1] Programmable input/output BE3 PIO7[3] Programmable input/output BE4 PIO7[0] Programmable input/output 60/604 en ti a l BC8 Programmable input/output Do not connect fid Programmable input/output on C Confidential Ball Programmable input/output Programmable input/output 1.1 V power supply Ground Ground Ground Ground Ground Ground DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description PIO11[7] Programmable input/output BE6 VDD1V1 1.1 V power supply BE7 GND Ground BE8 GND Ground BE9 GND Ground BE10 GND Ground BE11 GND Ground BE12 GND Ground BE13 GND Ground BE14 VDD1V1 1.1 V power supply BE15 VDD1V1 1.1 V power supply BE16 PIO15[3] Programmable input/output BE17 PIO14[4] BE18 PIO15[1] BE19 DNC BF1 PIO7[6] BF2 DNC BF3 PIO6[4] BF4 EMI_ADD[14] EMI address BF5 PIO7[5] Programmable input/output BF15 VDD1V1 BF16 JTAG_TDO BF17 JTAG_TDI JTAG test data input BF18 DNC Do not connect BF19 PIO14[0] Programmable input/output BG1 DNC Do not connect BG2 EMI_ADD[13] EMI address BG3 EMI_ADD[12] EMI address BG4 EMI_ADD[11] EMI address BG5 DNC Do not connect BG15 VDD1V1 1.1 V power supply BG16 JTAG_TCK JTAG test clock BG17 JTAG_NOTTRST JTAG test reset BG18 JTAG_TMS JTAG test mode select BG19 SYS_AONOTRESETIN Unmaskable global system reset en ti a l BE5 Programmable input/output Programmable input/output on fid Do not connect C Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list Programmable input/output Do not connect Programmable input/output 1.1 V power supply JTAG test data output DocID023557 Rev 10 61/604 Ball list Ball list - sorted on ball number (continued) Ball name Description EMI_ADD[8] EMI address BH2 DNC Do not connect BH3 EMI_ADD[7] EMI address BH4 EMI_ADD[6] EMI address BH5 DNC Do not connect BH15 VDD1V1 1.1 V power supply BH16 VDD1V1 1.1 V power supply BH17 VDD1V1 1.1 V power supply BH18 VDD1V1 1.1 V power supply BH19 VDD1V1 1.1 V power supply BJ1 DNC Do not connect BJ2 EMI_ADD[5] EMI address BJ3 EMI_ADD[4] BJ4 EMI_ADD[3] BJ5 DNC BJ15 VDD1V1 BJ16 VDD1V1 BJ17 VDD1V1 BJ18 VDD1V1 BJ19 VDD1V1 BK1 EMI_DVBCIIORD EMI DVBCI IO read BK2 EMI_DVBCINOTWE EMI DVBCI not write enable BK3 EMI_TRDYORWAIT Target ready BK4 EMI_ADD[2] EMI address BK5 EMI_ADD[1] EMI address BK15 VDD3V3 3.3 V power supply BK16 VDD3V3 3.3 V power supply BK17 VDD3V3 3.3 V power supply BK18 VDD3V3 3.3 V power supply BK19 VDD3V3 3.3 V power supply BL1 EMI_NOTBE[0] Byte enable BL2 DNC Do not connect BL3 EMI_DVBCIREG DVBCI REG signal BL4 EMI_NOTBE[1] Byte enable BL5 DNC Do not connect 62/604 en ti a l BH1 EMI address EMI address on fid Do not connect C Confidential Ball 1.1 V power supply 1.1 V power supply 1.1 V power supply 1.1 V power supply 1.1 V power supply DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Table 5. Ball list Ball list - sorted on ball number (continued) Ball name Description VDD3V3 3.3 V power supply BL16 SBC_VDD3V3 3.3 V input power supply for standby controller BL17 Q_TEST_ON Test enable BL18 SBC_VDD1V1 1.1 V input power supply for standby controller BL19 SBC_VDD1V1OUT 1.1 V output from internal regulator for standby controller BM1 NC Not connected BM2 DNC Do not connect BM3 PIO12[1] Programmable input/output BM4 PIO12[0] Programmable input/output BM5 DNC Do not connect BM15 VDD3V3 3.3 V power supply BM16 Q_VDD3V3 3V3 power supply BM17 PIO1[5] BM18 PIO3[3] BM19 PIO1[3] BN1 NC BN2 PIO4[6] BN3 PIO6[2] BN4 PIO4[7] BN5 VDD3V3 BN15 GND BN16 Q_VDD3V3 BN17 PIO1[2] Programmable input/output BN18 PIO1[0] Programmable input/output BN19 DNC Do not connect BP1 C_DATA4 Parallel MPEG data (bit 4) BP2 DNC Do not connect BP3 PIO5[1] Programmable input/output BP4 PIO5[0] Programmable input/output BP5 PIO5[4] Programmable input/output BP15 GND Ground BP16 PIO0[3] Programmable input/output BP17 PIO1[6] Programmable input/output BP18 DNC Do not connect BP19 PIO1[4] Programmable input/output en ti a l Information classified Confidential - Do not copy (See last page for obligations) BL15 C Programmable input/output Programmable input/output fid Programmable input/output on Confidential Ball Not connected Programmable input/output Programmable input/output Programmable input/output 3.3 V power supply Ground 3V3 power supply DocID023557 Rev 10 63/604 Ball list Ball list - sorted on ball number (continued) Ball name Description NC Not connected BR2 PIO6[3] Programmable input/output BR3 PIO5[2] Programmable input/output BR4 PIO5[3] Programmable input/output BR5 C_D_NOT_P MPEG data valid/parity BR6 C_DATA7 Parallel MPEG data (bit 7) BR7 GND Ground BR8 GND Ground BR9 GND Ground BR10 GND Ground BR11 GND Ground BR12 VDD2V5_4 2.5 V power supply (VDD2V5_1, VDD2V5_2 and VDD2V5_4 should be interconnected on PCB) BR13 GND BR14 HDMI_VDD1V1 BR15 VDD2V5_1 BR16 GND BR17 GND BR18 PIO2[0] BR19 PIO0[5] BT1 C_DATA3 BT2 C_DATA1 Parallel MPEG data (bit 1) BT3 C_STR_OUT MPEG first byte sync BT4 C_CLK_OUT MPEG byte or bit clock BT5 NC Not connected BT6 C_ERROR Transport stream error BT7 GND Ground BT8 NC Not connected BT9 GND Ground BT10 GND Ground BT11 VDD2V5_4 2.5 V power supply (VDD2V5_1, VDD2V5_2 and VDD2V5_4 should be interconnected on PCB) BT12 VDD2V5_4 2.5 V power supply (VDD2V5_1, VDD2V5_2 and VDD2V5_4 should be interconnected on PCB) BT13 GND Ground 64/604 en ti a l BR1 Ground 1.1 V power supply for HDMI fid on C Confidential Ball 2.5 V power supply (VDD2V5_1 and VDD2V5_2 should be interconnected on PCB) Ground Ground Programmable input/output Programmable input/output Parallel MPEG data (bit 3) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description HDMIPLL_DVDD1V1 HDMI PLL 1.1 V power supply BT15 HDMI_VDD2V5 2.5 V power supply for HDMI BT16 HDMIPLL_GND HDMI PLL ground BT17 GND Ground BT18 PIO1[1] Programmable input/output BT19 Q_MDC Management data interface BU1 C_DATA6 Parallel MPEG data (bit 6) BU2 GND Ground BU3 GND Ground BU4 GND Ground BU5 C_GPIO0 General purpose input/output ports BU6 DNC Do not connect BU7 C_NOT_RESET BU8 GND BU9 GND BU10 GND BU11 GND BU12 VDD1V1_2 BU13 HDMIPLL_AVDD2V5 HDMI PLL 2.5 V power supply BU14 HDMIPLL_AVDD2V5 HDMI PLL 2.5 V power supply BU15 USB_VDD2V5 USB 2.5 V power supply BU16 HDMIPLL_GND HDMI PLL Ground BU17 GND Ground BU18 PIO0[1] Programmable input/output BU19 Q_REGOUT Regulator power output BV1 C_DATA5 Parallel MPEG data (bit 5) BV2 GND Ground BV3 GND Ground BV4 GND Ground BV5 C_GPIO6 General purpose input/output ports BV6 C_GPIO9 General purpose input/output ports BV7 C_AUX_CLK Auxiliary clock BV8 GND Ground BV9 GND Ground en ti a l BT14 "Hardware reset Ground on fid Ground C Confidential Ball Ground Ground 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) DocID023557 Rev 10 65/604 Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list Ball list Ball list - sorted on ball number (continued) Ball name Description GND Ground BV11 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) BV12 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) BV13 GND Ground BV14 USB_VDD3V3 USB 3.3 V power supply BV15 USB_VDD2V5 USB 2.5 V power supply BV16 HDMI_VDD3V3 3.3 V power supply for HDMI BV17 PIO4[1] Programmable input/output BV18 ADAC_VCM Common mode reference generated in reference block BV19 DNC Do not connect BW1 GND Ground BW2 GND BW3 GND BW4 GND BW5 C_SCANMODE BW6 C_GPIO5 BW7 GND BW8 GND BW9 GND BW10 GND BW11 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) BW12 VDD1V1_2 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) BW13 PIO4[0] Programmable input/output BW14 USB_VDD3V3 USB 3.3 V power supply BW15 VDD2V5_3 2.5 V power supply BW16 HDMICK_VDD3V3 3.3 V power for the HDMI clock channel BW17 GND Ground BW18 ADAC_VHI Analog high reference generated in reference block BW19 GND Ground CA1 VDD1V1 1.1 V power supply CA2 GND Ground CA3 GND Ground 66/604 en ti a l BV10 Ground Ground on fid Ground C Confidential Ball Reserved test mode - must be grounded General purpose input/output ports Ground Ground Ground Ground DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description GND Ground CA5 GND Ground CA6 GND Ground CA7 GND Ground CA8 GND Ground CA9 GND Ground CA10 GND Ground CA11 GND Ground CB1 VDD1V1 1.1 V power supply CB2 GND Ground CB3 GND Ground CB4 GND Ground CB5 GND CB6 GND CB7 GND CB8 GND CB9 GND CB10 GND CB11 GND CC1 VDD1V1 CC2 GND CC3 GND CC4 GND CC5 GND CC6 GND Ground CC7 GND Ground CC8 GND Ground CC9 GND Ground CC10 GND Ground CC11 GND Ground CD1 VDD1V1 1.1 V power supply CD2 GND Ground CD3 GND Ground CD4 GND Ground CD5 GND Ground en ti a l CA4 Ground Ground on fid Ground C Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list Ground Ground Ground Ground 1.1 V power supply Ground Ground Ground Ground DocID023557 Rev 10 67/604 Ball list Ball list - sorted on ball number (continued) Ball name Description GND Ground CD7 GND Ground CD8 GND Ground CD9 GND Ground CD10 GND Ground CD11 GND Ground CE1 VDD1V1 1.1 V power supply CE2 GND Ground CE3 GND Ground CE4 GND Ground CE5 GND Ground CE6 GND Ground CE7 GND CE8 GND CE9 GND CE10 GND CE11 VDD1V1 CF1 VDD1V1 CF2 GND CF3 GND CF4 GND CF5 GND CF6 GND CF7 GND CF8 GND Ground CF9 GND Ground CF10 GND Ground CF11 VDD1V1 1.1 V power supply CG1 VDD1V1 1.1 V power supply CG2 GND Ground CG3 GND Ground CG4 GND Ground CG5 GND Ground CG6 GND Ground CG7 GND Ground 68/604 en ti a l CD6 Ground Ground on fid Ground C Confidential Ball Ground 1.1 V power supply 1.1 V power supply Ground Ground Ground Ground Ground Ground DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL Ball list - sorted on ball number (continued) Ball name Description GND Ground CG9 GND Ground CG10 GND Ground CG11 VDD1V1 1.1 V power supply CH1 VDD1V1 1.1 V power supply CH2 GND Ground CH3 GND Ground CH4 GND Ground CH5 VDD1V1 1.1 V power supply CH6 VDD1V1 1.1 V power supply CH7 VDD1V1 1.1 V power supply CH8 VDD1V1 1.1 V power supply CH9 VDD1V1 CH10 VDD1V1 CH11 VDD1V1 CJ1 VDD1V1 CJ2 VDD1V1 CJ3 VDD1V1 CJ4 VDD1V1 CJ5 VDD1V1 CJ6 VDD3V3 CJ7 VDD3V3 CJ8 VDD3V3 3.3 V power supply CJ9 VDD3V3 3.3 V power supply CJ10 VDD3V3 3.3 V power supply CJ11 VDD3V3 3.3 V power supply CK1 VDD3V3 3.3 V power supply CK2 VDD3V3 3.3 V power supply CK3 VDD3V3 3.3 V power supply CK4 VDD3V3 3.3 V power supply CK5 VDD3V3 3.3 V power supply CK6 VDD3V3 3.3 V power supply CK7 GND Ground CK8 GND Ground CK9 GND Ground en ti a l CG8 C 1.1 V power supply 1.1 V power supply fid 1.1 V power supply on Confidential Ball Information classified Confidential - Do not copy (See last page for obligations) Table 5. Ball list 1.1 V power supply 1.1 V power supply 1.1 V power supply 1.1 V power supply 1.1 V power supply 3.3 V power supply 3.3 V power supply DocID023557 Rev 10 69/604 Ball list Ball list - sorted on ball number (continued) Ball name Description GND Ground CK11 VDD2V5_1 2.5 V power supply (VDD2V5_1 and VDD2V5_2 should be interconnected on the PCB) CL1 GND Ground CL2 GND Ground CL3 GND Ground CL4 GND Ground CL5 GND Ground CL6 GND Ground CL7 GND Ground CL8 HDMI_VDD1V1 1.1 V power supply for HDMI CL9 HDMI_VDD1V1 1.1 V power supply for HDMI CL10 HDMI_VDD1V1 CL11 VDD2V5_1 ti a en 1.1 V power supply for HDMI fid 2.5 V power supply (VDD2V5_1 and VDD2V5_2 should be interconnected on the PCB) on 70/604 l CK10 C Confidential Ball DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 5. STiH271EL STiH271EL 8 Connections Connections This chapter gives details of the STiH271EL ball-out, arranged in functional groups or interfaces. The tables give details of each ball name, its description and direction (input, output or both). See Section 8.14 for pad I/O conditions after reset. Ground - see Section 8.2: Ground on page 78 System - see Section 8.3: System on page 83 JTAG - see Section 8.4: JTAG on page 84 Audio DAC - see Section 8.5: Audio DAC on page 84 Video DAC - see Section 8.6: Video DAC on page 84 HDMI - see Section 8.7: HDMI on page 85 EMI - see Section 8.8: EMI on page 86 LMI - see Section 8.9: LMI on page 87 USB - see Section 8.10: USB on page 89 Ethernet PHY- see Section 8.11: Ethernet PHY on page 89 Front end - see Section 8.12: Front-end on page 90 Information classified Confidential - Do not copy (See last page for obligations) Power supplies (analog and digital) - see Section 8.1: Power supply on page 72 en ti a l fid The tables below describe interfaces and signals on PIO alternate functions: Audio - see Section 8.13.1: Audio on page 91 Ethernet - see Section 8.13.2: Ethernet on page 91 External DMA - see Section 8.13.3: External DMA requests on page 93 External interrupt - see Section 8.13.4: External interrupt on page 93 IR blaster - see Section 8.13.5: IRB10/UHF Rx, IRB0 Tx on page 93 Key scanner - see Section 8.13.6: Key scanner on page 93 MMC - see Section 8.13.7: Multi-media card (MMC) on page 94 PWM - see Section 8.13.8: Pulse width modulator (PWM) on page 94 Smartcard - see Section 8.13.9: Smartcard on page 95 Serial Flash interface - see Section 8.13.10: Serial Flash interface on page 95 SSC - see Section 8.13.12: Synchronous serial controller (SSC) on page 97 Transport - see Section 8.13.13: Transport streams on page 98 UART - see Section 8.13.14: UART on page 100 on C Confidential The tables are arranged as follows: DocID023557 Rev 10 71/604 Connections STiH271EL 8.1 Power supply Table 6. Power supply Ball Signal name Voltage Type Description VDD1V1 P29 P30 R29 l R31 ti a T29 T30 BC6 en BC7 BC9 fid BC10 BC11 BC12 on BC13 BC14 VDD1V1 BC15 BD6 BD14 BD15 BE6 1.1 Digital C Confidential BC8 BE14 BE15 BF15 BG15 BH15 BH16 BH17 BH18 BH19 BJ15 BJ16 72/604 DocID023557 Rev 10 1.1 V power supply Information classified Confidential - Do not copy (See last page for obligations) R30 STiH271EL Table 6. Ball Connections Power supply (continued) Signal name Voltage VDD1V1 1.1 Type Description BJ17 BJ18 BJ19 CA1 CB1 CC1 CD1 l ti a CE11 CF1 CF11 CG11 CH1 Digital 1.1 V power supply Digital 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) fid CH5 en CG1 CH6 CH7 on CH8 CH9 CH10 CH11 CJ1 C Confidential Information classified Confidential - Do not copy (See last page for obligations) CE1 CJ2 CJ3 CJ4 CJ5 VDD1V1_2 AJ19 AJ16 AJ18 BU12 VDD1V1_2 1.1 BV11 BV12 BW11 DocID023557 Rev 10 73/604 Connections Table 6. STiH271EL Power supply (continued) Ball Signal name Voltage Type Description BW12 VDD1V1_2 1.1 Digital 1.1 V power supply (VDD1V1 and VDD1V1_2 should be interconnected on PCB) VDD2V5_1 2.5 Digital 2.5 V power supply (VDD2V5_1 and VDD2V5_2 should be interconnected on PCB) VDD2V5_2 2.5 Digital 2.5 V power supply (VDD2V5_1 and VDD2V5_2 should be interconnected on PCB) VDD2V5_3 2.5 Digital VDD2V5_4 2.5 VDD2V5_1 BR15 CK11 CL11 BT11 Digital 2.5 V power supply (VDD2V5_1, VDD2V5_2 and VDD2V5_4 should be interconnected on PCB) Digital 3.3 V power supply fid BR12 BT12 VDD3V3 on U29 U30 BK15 BK16 C Confidential VDD2V5_4 2.5 V power supply BK17 BK18 BK19 BL15 BM15 VDD3V3 3.3 BN5 CJ6 CJ7 CJ8 CJ9 CJ10 CJ11 CK1 74/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) BW15 en VDD2V5_3 l D32 ti a VDD2V5_2 STiH271EL Table 6. Ball Connections Power supply (continued) Signal name Voltage Type Description VDD3V3 3.3 Digital 3.3 V power supply CK2 CK3 CK4 CK5 CK6 VDD3V3 Ethernet PHY power supply 3.3 3.3 V power supply Digital ti a BN16 VDD3V3_DECAP B1 VDD3V3_DECAP 3.3 ADAC_VDD3V3 3.3 Digital AM30 3.3 V power supply for ADAC 2.5 Analog Thermal sensor 2.5 V analog supply 1.1 Digital 1.1 V input power supply for standby controller 3.3 Digital 3.3 V input power supply for standby controller fid D31 THS_AVDD2V5 on Stand by controller 3.3 power supply for decoupling Analog Thermal sensor BL18 SBC_VDD1V1 BL16 SBC_VDD3V3 BL19 SBC_VDD1V1OUT 1.1 Digital 1.1 V output from internal regulator for standby controller HDMICK_VDD3V3 3.3 Analog 3.3 V power for the HDMI clock channel HDMI_VDD1V1 1.1 Analog 1.1 V power supply for HDMI BT15 HDMI_VDD2V5 2.5 Analog 2.5 V power supply for HDMI BV16 HDMI_VDD3V3 3.3 Analog 3.3 V power supply for HDMI BT14 HDMIPLL_DVDD1V1 1.1 Digital HDMI PLL 1.1 V power supply HDMIPLL_AVDD2V5 2.5 Analog HDMI PLL 2.5 V power supply HDMI BW16 C Confidential Audio DAC en AM13 BR14 CL8 CL9 CL10 BU13 BU14 USB DocID023557 Rev 10 75/604 Information classified Confidential - Do not copy (See last page for obligations) Digital Q_VDD3V3 l BM16 Connections Table 6. Ball STiH271EL Power supply (continued) Signal name Voltage Type Description USB_VDD2V5 2.5 Analog USB 2.5 V power supply USB_VDD3V3 3.3 Analog USB 3.3 V power supply Decoupling location for LMI1 digital 1V5 supply, internally connected to the supply (no need to connect to the supply on the board) BU15 BV15 AJ21 BV14 BW14 A8 LMI_VDD1V5_DECAP 1.5 Analog C31 LMIVSENSE_VDD1V5 1.5 Digital LMI voltage sense output 1.5 V power supply for DDR3 E29 LMIPLL1_VDD2V5 2.5 Analog Dedicated 2.5 V power for LMI PLL0 E30 LMIPLL0_VDD2V5 2.5 E31 LMIPLL2_VDD2V5 2.5 G29 G30 BA14 BA15 BA16 BA19 en Analog Dedicated 2.5 V power for LMI PLL2 Digital 1.5 V power supply for DDR3 on G31 BA18 ti a l F30 BA17 Dedicated 2.5 V power for LMI PLL1 fid F29 Analog C Confidential A19 LMI_VDD1V5 1.5 BB6 BB7 BB8 BB9 BB10 BB11 BB12 BB13 BB14 BB15 76/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) LMI STiH271EL Table 6. Ball Connections Power supply (continued) Signal name Voltage Type Description LMI_VDD1V5 1.5 Digital 1.5 V power supply for DDR3 2.5 Analog Analog 2.5 V supply BB16 BB17 BB18 BB19 C_AVDD2V5 front-end power supply AF3 C_AVDD2V5 ti a l AF4 C_VDD1V2 front-end power supply Digital Digital 1.2 V supply fid C_VDD1V2 1.2 1.2 Analog Analog regulator input 0 Analig Analog regulator output 3.3 Digital Digital 3.3 V supply AK7 AL7 AK10 C_VREG1V2 on C_VREG_1V2 front-end power supply C_VBASE front-end power supply AJ10 C_VBASE C Confidential AJ7 en AJ6 AK6 Information classified Confidential - Do not copy (See last page for obligations) AF2 C_VDD3V3 front-end power supply AK8 AL8 C_VDD3V3 AM8 DocID023557 Rev 10 77/604 Connections STiH271EL 8.2 Ground Table 7. Ground Ball Signal name Voltage GND 0 Type Description B8 B19 D8 D9 D11 ti a l D14 D19 D20 en D22 D24 AG3 fid AG4 AJ13 AJ15 on AJ14 AJ23 AJ24 AJ25 AJ30 AK13 - C Confidential D25 AK14 AK15 AK23 AK24 AL5 AL13 AL14 AL15 AL23 BA4 BA6 78/604 DocID023557 Rev 10 Ground Information classified Confidential - Do not copy (See last page for obligations) D13 STiH271EL Table 7. Ball Connections Ground (continued) Signal name Voltage GND 0 Type Description BA7 BA8 BA9 BA10 BA11 BA12 BA13 l ti a BD7 BD8 BD9 en BD10 BD12 fid BD13 BE7 BE10 BE11 BE12 BE13 BN15 BP15 - Ground on BE8 C Confidential BD11 BE9 Information classified Confidential - Do not copy (See last page for obligations) BB4 BR7 BR8 BR9 BR10 BR11 BR13 BR16 BR17 BT7 BT9 BT10 DocID023557 Rev 10 79/604 Connections Table 7. Ball STiH271EL Ground (continued) Signal name Voltage GND 0 Type Description BT13 BT17 BU2 BU3 BU4 BU8 l BU10 ti a BU11 BU17 BV2 en BV3 BV8 fid BV9 BV10 BW1 BW2 BW3 BW4 BW7 BW8 BW9 - on BV13 C Confidential BV4 BW10 BW17 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 CA10 80/604 DocID023557 Rev 10 Ground Information classified Confidential - Do not copy (See last page for obligations) BU9 STiH271EL Table 7. Ball Connections Ground (continued) Signal name Voltage GND 0 Type Description CA11 CB2 CB3 CB4 CB5 CB6 CB7 l ti a CB9 CB10 CB11 en CC2 CC4 fid CC5 CC6 CC9 CC10 CC11 CD2 CD3 CD4 - Ground on CC7 C Confidential CC3 CC8 Information classified Confidential - Do not copy (See last page for obligations) CB8 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CE2 CE3 CE4 CE5 DocID023557 Rev 10 81/604 Connections Table 7. Ball STiH271EL Ground (continued) Signal name Voltage GND 0 Type Description CE6 CE7 CE8 CE9 CE10 CF2 l CF4 ti a CF5 CF6 CF7 en CF8 CF10 fid CG2 CG3 CG5 CG6 CG7 CG8 CG9 CG10 CH2 - on CG4 C Confidential CF9 CH3 CH4 CK7 CK8 CK9 CK10 CL1 CL2 CL3 CL4 CL5 82/604 DocID023557 Rev 10 Ground Information classified Confidential - Do not copy (See last page for obligations) CF3 STiH271EL Table 7. Ball Connections Ground (continued) Signal name Voltage Type Description GND 0 - Ground HDMIPLL_GND 0 - CL6 CL7 AJ29 AK29 AK30 BW19 AJ20 BT16 System Table 8. System HDMI PLL ground en 8.3 Description Direction BG19 SYS_AONOTRESETIN Unmaskable global system reset I C32 CORESENSE_DVDD1V1 Core voltage sensing diagnostic pad I/O D30 CORESENSE_DGND1V1 Core voltage sensing diagnostic pad I/O N29 SYS_AONOTWDOGRSTOUT System always-on reset output from watchdog timer O N30 SYS_CLKINALT Alternate reference clock for clock generators I N31 SYS_NOTASEBRK ST40 debugger breakpoint I/O N32 SYS_NOTRESETIN Voltage monitor / maskable system reset I P31 SYS_32KOSCIN 32 kHz oscillator external crystal inputs for real time counter I P32 SYS_32KOSCOUT 32 kHz oscillator external crystal inputs for real time counter O AK19 SYS_CLKIN System oscillator external crystal signal I AM19 SYS_CLKOSC System oscillator external crystal signal I fid Signal name on Ball C Confidential BU16 ti a l HDMI DocID023557 Rev 10 83/604 Information classified Confidential - Do not copy (See last page for obligations) AK16 JTAG Table 9. JTAG Signal name Description Direction BF16 JTAG_TDO JTAG test data output O BF17 JTAG_TDI JTAG test data input I BG16 JTAG_TCK JTAG test clock I BG17 JTAG_NOTTRST JTAG test reset I BG18 JTAG_TMS JTAG test mode select I Audio DAC Table 10. Audio DAC ti a 8.5 l Ball Signal name Description AJ28 ADAC_VLO Analog low reference generated in reference block I AL29 ADAC_RIGHT Audio-DAC right-channel signal 0 O AM29 ADAC_LEFT Audio-DAC left-channel signal 0 O BV18 ADAC_VCM Common mode reference generated in reference block I BW18 ADAC_VHI Analog high reference generated in reference block I Table 11. Video DAC Signal name AK28 VDAC_REXTN AL28 VDAC_REXTP AL30 fid Video DAC on 8.6 Ball Direction en Ball Description Direction Video-DAC external voltage compensation reference I Video-DAC external voltage compensation reference I VDAC_VOUT Video output O AL31 VDAC_UOUT Video output O AL32 VDAC_XOUT Video output O AM31 VDAC_WOUT Video output O 84/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 8.4 STiH271EL C Confidential Connections STiH271EL Table 12. Connections Video format Video format Main HD - HDMI + Aux on 4 DACs S.No Rm Ra 2 Ym Gm Ga Ya 3 Pbm Bm Ba Ca 4 CVBSa CVBSa CVBSa CVBSa 8.7 HDMI Table 13. HDMI Ball Main SD + Aux SD Ca Cm VDAC_UOUT AL31 Ya Ym VDAC_VOUT AL30 CVBSm VDAC_WOU T CVBSa VDAC_XOUT AL32 l Prm Europe SCART Yc CVBSa en 1 DAC pins ti a Europe SCART RGB HD + Aux SD AM31 Signal name Description Direction AJ27 HDMI_TX2N HDMI transmitter channel 2 negative differential signal O AK25 HDMI_REXT HDMI compensation reference I AK26 HDMI_TX1N HDMI transmitter channel 1 negative differential signal O AK27 HDMI_TX2P HDMI transmitter channel 2 positive differential signal O AL24 HDMI_TXCKN HDMI transmitter clock negative differential signal O AL25 HDMI_TX0N HDMI transmitter channel 0 negative differential signal O AL26 HDMI_TX1P HDMI transmitter channel 1 positive differential signal O AM24 HDMI_TXCKP HDMI transmitter clock positive differential signal O AM25 HDMI_TX0P HDMI transmitter channel 0 positive differential signal O on fid Ball C Confidential HD + Aux SD NonEurope CVBS + S video Dual TV SD DocID023557 Rev 10 85/604 Information classified Confidential - Do not copy (See last page for obligations) Main HD - HDMI + 3 DAC / Aux - SD BK5 EMI_ADD[1] BK4 EMI_ADD[2] BJ4 EMI_ADD[3] BJ3 EMI_ADD[4] BJ2 EMI_ADD[5] BH4 EMI_ADD[6] BH3 EMI_ADD[7] BH1 EMI_ADD[8] T3 EMI_ADD[9] R4 EMI_ADD[10] BG4 EMI_ADD[11] BG3 EMI_ADD[12] BG2 EMI_ADD[13] BF4 EMI_ADD[14] R2 EMI_DATA[0] P3 EMI_DATA[1] P2 EMI_DATA[2] p1 EMI_DATA[3] N4 EMI_DATA[4] N1 EMI_DATA[5] N2 EMI_DATA[6] M3 EMI_DATA[7] BK1 Description Direction EMI address I/O EMI address I/O EMI data input/output I/O EMI_DVBCIIORD EMI DVBCI IO read O BK2 EMI_DVBCINOTWE EMI DVBCI not write enable O U4 EMI_NANDRDY NAND Flash ready I/O BL1 EMI_NOTBE[0] Byte enable I/O BL4 EMI_NOTBE[1] Byte enable I/O T4 EMI_NOTCS[0] V3 EMI_NOTCS[1] Chip select I/O V2 EMI_NOTCS[2] V4 EMI_NOTCS[3] BL3 EMI_DVBCIREG DVBCI REG signal O R3 EMI_NOTOE Output enable O 86/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Signal name l Ball ti a EMI en Table 14. fid EMI on 8.8 STiH271EL C Confidential Connections STiH271EL Ball Signal name Description Direction U3 EMI_RDNOTWR Read not Write I/O BK3 EMI_TRDYORWAIT Target ready I Additional NAND interface signals are multiplexed as follows: NAND_ALE on EMI_ADD[10] NAND_CLE on EMI_ADD[9] NAND_REN on EMI_NOTOE NAND_WEN on EMI_RDNOTWR 2 Additional DVB-CI signals are multiplexed as DVBCI_NOTOE on EMI_NOTOE. LMI Ball Signal name D17 LMI_ADD[0] C19 LMI_ADD[1] C16 LMI_ADD[2] A14 LMI_ADD[3] B21 LMI_ADD[4] B14 LMI_ADD[5] C21 LMI_ADD[6] D15 LMI_ADD[7] B20 LMI_ADD[8] C15 LMI_ADD[9] D18 LMI_ADD[10] A20 LMI_ADD[11] B18 LMI_ADD[12] D16 LMI_ADD[13] C20 LMI_ADD[14] C18 LMI_ADD[15] C14 LMI_BA[0] D21 LMI_BA[1] C17 LMI_BA[2] D23 Description ti a Table 15. en LMI Direction fid 8.9 l 1 on Note: LMI address O Bank address O LMI_CKE Clock enable O C23 LMI_CKN[0] Differential clock negative O B23 LMI_CKP[0] Differential clock positive O C Confidential EMI (continued) DocID023557 Rev 10 87/604 Information classified Confidential - Do not copy (See last page for obligations) Table 14. Connections Connections C25 LMI_DATA[1] A31 LMI_DATA[2] A24 LMI_DATA[3] B31 LMI_DATA[4] C24 LMI_DATA[5] C30 LMI_DATA[6] B24 LMI_DATA[7] C26 LMI_DATA[8] A29 LMI_DATA[9] A25 LMI_DATA[10] A30 LMI_DATA[11] B26 LMI_DATA[12] D29 LMI_DATA[13] B25 LMI_DATA[14] B29 LMI_DATA[15] D28 LMI_DM[0] C29 LMI_DM[1] C28 LMI_DQSN[0] D27 LMI_DQSN[1] B28 LMI_DQSP[0] C27 LMI_DQSP[1] B12 LMI_NOTCAS B13 LMI_NOTCS C12 LMI data input/output I/O l LMI_DATA[0] Direction ti a B30 Description en Signal name fid Ball O Differential data strobe negative I/O Differential data strobe positive I/O Command input (column select) O Chip Select O LMI_NOTRAS Command input (row select) O B15 LMI_NOTRESET Reset I A13 LMI_NOTWE Command input (write enable) O D26 LMI_NOTRETENTION Power retention for LMI 1v5 IO ring I C13 LMI_ODT LMI on die termination O D7 LMIPLL_TEST PLL test output O C22 LMI_VREFCA Reference voltage for CA I/O B32 LMI_VREFDQ[0] Reference voltage for DQ I/O C11 LMI_VREFDQ[1] Reference voltage for DQ I/O D12 LMI_ZQ Reference ball for ZQ calibration I 88/604 on Data mask DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) LMI (continued) C Confidential Table 15. STiH271EL 8.10 USB Table 16. USB Signal name Description Direction AL21 USB0_DM USB negative differential signal I/O AK21 USB0_DP USB positive differential signal I/O AJ22 USB1_DM USB negative differential signal I/O AK22 USB1_DP USB positive differential signal I/O AL19 USB_TXRTUNE Transmitter resistor tune pin I/O Ethernet PHY Table 17. Ethernet PHY ti a 8.11 l Ball Signal name Description W29 Q_RESET_N Reset enable AD31 Q_X2 25 MHz crystal input (applicable when wake up on LAN feature is required) O AD32 Q_X1 25 MHz crystal input (applicable when wake up on LAN feature is required) I AE29 Q_REGOUT Regulator power output - AE31 Q_REGIN Regulator power input - AE32 Q_REGIN Regulator power input - AF30 Q_REGOUT Regulator power output - AF31 Q_REGOUT Regulator power output - AG29 Q_LED1_PHYAD1 PHY address[1] I/O AG30 Q_ISET Transmit bias resistor I AH29 Q_LED3_PHYALL LED 3 or PHY Address ALL I/O AH30 Q_LED2_PHYAD2 PHY address[2] I/O AH31 Q_LED0_PHYAD0 PHY address[0] I/O AJ31 Q_MDI_TN Transmit output pair I/O AJ32 Q_MDI_TP Transmit output pair I/O AK31 Q_MDI_RN Receive input pair I/O AK32 Q_MDI_RP Receive input pair I/O BL17 Q_TEST_ON Test enable - BT19 Q_MDC Management data interface I BU19 Q_REGOUT Regulator power output - on fid en Ball DocID023557 Rev 10 Direction I 89/604 Information classified Confidential - Do not copy (See last page for obligations) Connections C Confidential STiH271EL 8.12 Front-end Table 18. Front end Ball Signal name Description Direction C_SDA Serial data (open drain) I/O AC3 C_SCL Serial clock (open drain) I AD3 C_GPIO3 General purpose input/output ports I/O AD4 C_DATA2 Parallel MPEG data (bit 2) O AE1 C_AGC_BB IF AGC control I/O AE4 C_DATA0 Parallel MPEG data (bit 0) O AH2 C_SDAT SDA tuner (open drain) AH3 C_SCLT SCL tuner AJ1 C_QP Positive Q analog input for baseband configuration - AJ2 C_QM Negative Q analog input for baseband configuration I AJ4 C_RF_LEVEL ADC-8 input for RF level monitoring I AJ5 C_CS0 Chip select LSB I AJ11 C_GPIO2 General purpose input/output ports I/O AJ12 C_GPIO7 General purpose input/output ports I/O AK1 C_IM Negative I analog input for IF and baseband configuration I AK2 C_IP Positive I analog input for IF and baseband configuration I AK3 C_INCM AK5 C_CS1 AK11 C_GPIO1 AL1 C_XTAL_I AL2 C_XTAL_O AL10 on fid en ti a l AC2 I/O I Internal common mode - Chip select MSB I General purpose input/output ports I/O Crystal oscillator input/external clock I Crystal oscillator output O C_AGC_RF RF AGC I/O AL12 C_GPIO8 General purpose input/output ports I/O AM14 C_GPIO4 General purpose input/output ports I/O BP1 C_DATA4 Parallel MPEG data (bit 4) O BR5 C_D_NOT_P MPEG data valid/parity O BR6 C_DATA7 Parallel MPEG data (bit 7) O BT1 C_DATA3 Parallel MPEG data (bit 3) O BT2 C_DATA1 Parallel MPEG data (bit 1) O BT3 C_STR_OUT MPEG first byte sync O BT4 C_CLK_OUT MPEG byte or bit clock O BT6 C_ERROR Transport stream error O BU1 C_DATA6 Parallel MPEG data (bit 6) O 90/604 C Confidential STiH271EL DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Connections STiH271EL Front end (continued) Ball Signal name Description Direction C_GPIO0 General purpose input/output ports I/O BU7 C_NOT_RESET Hardware reset; active low I BV1 C_DATA5 Parallel MPEG data (bit 5) O BV5 C_GPIO6 General purpose input/output ports I/O BV6 C_GPIO9 General purpose input/output ports I/O BV7 C_AUX_CLK Auxiliary clock I/O BW5 C_SCANMODE Reserved test mode - must be grounded - BW6 C_GPIO5 General purpose input/output ports I/O 8.13 ti a l BU5 Signals and interfaces on PIO alternate functions en 8.13.1 Audio Table 19. Audio signals on PIO PIO Description Direction K30/K31 PIO15[0]/PIO15[4] AUDPCMIN0_DATA[0] PCMIN0 - data 0 I BE16/K29 PIO15[3]/PIO15[7] AUDPCMIN0_LRCLK PCMIN0 - left/right clock I BE18/M31 PIO15[1]/PIO15[5] AUDPCMIN0_MCLK PCMIN0 - master clock I M29/M30 PIO15[2]/PIO15[6] AUDPCMIN0_SCLK PCMIN0 - serial clock I K30 PIO15[0] AUDPCMOUT0_DATA[0] PCMOUT 0 - data 0 O BE16 PIO15[3] AUDPCMOUT0_LRCLK PCMOUT0 - left/right clock output O M29 PIO15[2] AUDPCMOUT0_SCLK PCMOUT0 - serial clock O BE18 PIO15[1] AUDPCMOUT0_MCLK PCMOUT0 - master clock O BV17/BD1 PIO4[1]/PIO9[6] AUDSPDIF_OUT S/PDIF out O 8.13.2 Signal name on Ball fid For full details of default and alternative functions on each PIO port, see Chapter 25: Alternate functions on PIO on page 528. C Confidential The tables below show the functional groups that are presented as alternate functions on PIO ports. Ethernet MII/TMII/RevMII interfaces Table 20. MII/TMII/RevMII signals on PIO Ball PIO Signal name Description Direction AE30 PIO0[0] ETH_TXD[0] MII/TMII/RevMII transmit data O BU18 PIO0[1] ETH_TXD[1] MII/TMII/RevMII transmit data O DocID023557 Rev 10 91/604 Information classified Confidential - Do not copy (See last page for obligations) Table 18. Connections Connections PIO Signal name Description Direction V31 PIO0[2] ETH_TXD[2] MII/TMII/RevMII transmit data O BP16 PIO0[3] ETH_TXD[3] MII/TMII/RevMII transmit data O AD30 PIO0[4] ETH_TXER MII/TMII/RevMII transmit error O BR19 PIO0[5] ETH_TXEN MII/TMII/RevMII TX enable O AD29 PIO0[6] ETH_TXCLK MII/TMII/RevMII transmit clock for TXD I AA29 PIO0[7] ETH_COL MII/TMII/RevMII collision detected I BN18 PIO1[0] ETH_MDIO MII/TMII/RevMII management data I/O BT18 PIO1[1] ETH_MDC MII/TMII/RevMII management data clock O BN17 PIO1[2] ETH_CRS MII/TMII/RevMII carrier sense detected BM19 PIO1[3] ETH_MDINT MII/TMII/RevMII management data interrupt I BP19 PIO1[4] ETH_RXD[0] MII/TMII/RevMII receive data I BM17 PIO1[5] ETH_RXD[1] MII/TMII/RevMII receive data I BP17 PIO1[6] ETH_RXD[2] MII/TMII/RevMII receive data I V30 PIO1[7] ETH_RXD[3] MII/TMII/RevMII receive data I BR18 PIO2[0] ETH_RXDV MII/TMII/RevMII receive data valid (RXDV) I AC29 PIO2[1] ETH_RXER AC30 PIO2[2] ETH_RXCLK AC31 PIO2[3] ETH_PHYCLK Table 21. ti a en fid I MII/TMII/RevMII receive error I MII/TMII/RevMII receive clock for RXD I MII/TMII/RevMII clock to PHY O on RMII interface l Ball RMII signals on PIO Ball PIO Signal name Description Direction AE30 PIO0[0] ETH_TXD[0] RMII transmit data O BU18 PIO0[1] ETH_TXD[1] RMII transmit data O BR19 PIO0[5] ETH_TXEN RMII TX enable O BN18 PIO1[0] ETH_MDIO RMII management data I/O BT18 PIO1[1] ETH_MDC RMII management data clock O BM19 PIO1[3] ETH_MDINT RMII management data interrupt I BP19 PIO1[4] ETH_RXD[0] RMII receive data I BM17 PIO1[5] ETH_RXD[1] RMII receive data I BR18 PIO2[0] ETH_RXDV RMII receive data valid (RXDV) I AC29 PIO2[1] ETH_RXER RMII receive error I AC31 PIO2[3] ETH_PHYCLK RMII clock to PHY O 92/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) MII/TMII/RevMII signals on PIO (continued) C Confidential Table 20. STiH271EL 8.13.3 External DMA requests Table 22. External DMA signals on PIO Ball PIO Signal name Description Direction BD4 PIO8[6] EXTDMA_REQ0 External DMA request I BC2 PIO8[7] EXTDMA_REQ1 External DMA request I 8.13.4 External interrupt Table 23. External interrupt signals on PIO PIO Signal name Description Direction V29 PIO2[5] EXT_IT0 External interrupt AA29 PIO0[7] EXT_IT1 External interrupt I/O Y32 PIO3[1] EXT_IT2 External interrupt I/O AC29 PIO2[1] EXT_IT3 External interrupt I/O BD1 PIO9[6] EXT_IT4 External interrupt I/O K29 PIO15[7] EXT_IT5 External interrupt I/O IRB10/UHF Rx, IRB0 Tx Table 24. IRB0/IRB10 signals on PIO fid 8.13.5 en ti a l Ball Ball PIO Signal name W30 PIO3[6] IRB10_DATAOUTOD IR Blaster data output - open drain (IRB receiver is in O always-on domain) W31 PIO3[5] IRB10_IRDATAOUT IR Blaster data output (IRB receiver is in always-on domain) O V29 PIO2[5] IRB0_IRIN1 IR Blaster UHF data input (IRB transmitter is inside the comms) I W32 PIO3[4] IRB0_IRIN0 IR Blaster IR data input (IRB transmitter is inside the I comms) on Description I/O 8.13.6 Key scanner Table 25. Key scanner signals on PIO Direction Ball PIO Signal name Description Direction V31 PIO0[2] KEYSCAN_IN[0] Key scanning I BP16 PIO0[3] KEYSCAN_IN[1] Key scanning I Y31 PIO3[0] KEYSCAN_IN[2] Key scanning I Y30 PIO3[2] KEYSCAN_IN[3] Key scanning I AD30 PIO0[4] KEYSCAN_OUT[0] Key scanning O DocID023557 Rev 10 93/604 Information classified Confidential - Do not copy (See last page for obligations) Connections C Confidential STiH271EL Connections Key scanner signals on PIO (continued) Ball PIO Signal name Description Direction AD29 PIO0[6] KEYSCAN_OUT[1] Key scanning O Y32 PIO3[1] KEYSCAN_OUT[2] Key scanning O AF29 PIO3[7] KEYSCAN_OUT[3] Key scanning O 8.13.7 Multi-media card (MMC) Table 26. MMC signals on PIO Signal name J31 PIO13[0] MMC_DATA[0] BC17 PIO13[1] MMC_DATA[1] BD16 PIO13[2] MMC_DATA[2] BC16 PIO13[3] MMC_DATA[3] Description H30 PIO13[6] MMC_DATA[6] BC19 PIO13[7] MMC_DATA[7] BF19 PIO14[0] MMC_LED J32 PIO14[1] MMC_CLK BD17 PIO14[2] MMC_CMD L30 PIO14[3] MMC_WP BD19 PIO14[5] MMC_CP H31 PIO14[6] MMC_CD en PIO13[5] MMC_DATA[5] fid H32 on PIO13[4] MMC_DATA[4] I/O I/O I/O I/O I/O I/O I/O I/O MMC - LED On O MMC clock I/O MMC command I/O MMC - Write protection I MMC - Card power O MMC - Card detect I C Confidential MMC data BC18 Direction l PIO ti a Ball 8.13.8 Pulse width modulator (PWM) Table 27. PWM10[0] signals on PIO Ball PIO Signal name Description Direction Y31 PIO3[0] PWM10[0]_OUT Adaptive Voltage Scaling feedback O Y32 PIO3[1] PWM10[0]_COMPAREOUT PWM 10 - channel 0 O Y30 PIO3[2] PWM10[0]_CAPTUREIN PWM 10 - channel 0 I Table 28. PWM10[1] signals on PIO Ball PIO Signal name Description Direction AC30 PIO2[2] PWM10[1]_OUT PWM 10 - channel 1 O 94/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 25. STiH271EL STiH271EL PWM10[1] signals on PIO (continued) Ball PIO Signal name Description Direction AC31 PIO2[3] PWM10[1]_CAPTUREIN PWM 10 - channel 1 I AA31 PIO2[4] PWM10[1]_COMPAREOUT PWM 10 - channel 1 Smartcard Table 29. SC0 signals on PIO Direction PIO10[0] SC0_C4 Smartcard 0 I/O F3 PIO10[1] SC0_C7 Smartcard 0 I/O D2 PIO10[2] SC0_RESET Smartcard 0 reset O D1 PIO10[3] SC0_NOTSETVCC Smartcard 0 O D4 PIO10[4] SC0_NOTSETVPP Smartcard 0 E2 PIO10[5] SC0_CLKGEN Smartcard 0 clock generator I/O E3 PIO10[6] SC0_C8 Smartcard 0 I/O D3 PIO10[7] SC0_DETECT Smartcard 0 detection I Table 30. Ball SC1 signals on PIO PIO Signal name PIO11[0] SC1_C4 BC5 PIO11[1] SC1_C7 BD5 O Description Direction Smartcard 1 I/O Smartcard 1 I/O PIO11[2] SC1_RESET Smartcard 1 reset O BC3 PIO11[3] SC1_NOTSETVCC Smartcard 1 O BC4 PIO11[4] SC1_NOTSETVPP Smartcard 1 O BB2 PIO11[5] SC1_CLKGEN Smartcard 1 clock generator I/O BB1 PIO11[6] SC1_C8 Smartcard 1 I/O BE5 PIO11[7] SC1_DETECT Smartcard 1 detection I on BB5 l Description ti a E4 Signal name en PIO fid Ball O 8.13.10 Serial Flash interface Table 31. SPI signals on PIO - single mode Ball PIO AA2 Signal name Description Direction PIO12[2] SPI_CLOCK SPI Flash clock O Y2 PIO12[3] SPI_NOTCS SPI Flash chip select O W3 PIO12[4] SPI_DI SPI Flash data input to controller Note - Connected to Flash device DO I DocID023557 Rev 10 95/604 Information classified Confidential - Do not copy (See last page for obligations) 8.13.9 C Confidential Table 28. Connections Connections SPI signals on PIO (continued)- single mode Ball PIO W1 Description Direction PIO12[5] SPI_DO SPI Flash data output from controller Note - Connected to Flash device DI O W2 PIO12[6] SPI_HOLD SPI hold O Y1 PIO12[7] SPI_WRPROTECT SPI read/write protect O 8.13.11 Signal name Serial Flash interface - dual and quad modes PIO Description AA2 PIO12[2] SPI_CLOCK SPI Flash clock Y2 PIO12[3] SPI_NOTCS SPI Flash chip select O W3 PIO12[4] SPI_DI SPI Flash data I/O (SPI_DATA0) I/O W1 PIO12[5] SPI_DO SPI Flash data I/O (SPI_DATA1) I/O W2 PIO12[6] SPI_HOLD Y1 PIO12[7] SPI_WRPROTECT fid en Ball Direction O SPI hold O SPI read/write protect O SPI signals on PIO - quad mode Ball PIO AA2 on Table 33. Signal name ti a SPI signals on PIO - dual mode Description Direction PIO12[2] SPI_CLOCK SPI Flash clock O Y2 PIO12[3] SPI_NOTCS SPI Flash chip select O W3 PIO12[4] SPI_DI SPI Flash data I/O (SPI_DATA0) I/O W1 PIO12[5] SPI_DO SPI Flash data I/O (SPI_DATA1) I/O W2 PIO12[6] SPI_HOLD SPI Flash data I/O in quad mode (SPI_DATA2) else SPI hold I/O Y1 PIO12[7] SPI_WRPROTECT SPI Flash data I/O in quad mode (SPI_DATA3) else SPI read/write protect I/O 96/604 Signal name C Confidential Table 32. l The dual and quad modes are not programmed in the PIO alternate assignments at the SoC level, but are available for programming at the IP level. See the STiH207 (CD18328376) programming manual for details of dual and quad mode programming. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 31. STiH271EL 8.13.12 Synchronous serial controller (SSC) Table 34. SSC0 signals on PIO Ball PIO Signal name Description Direction BB3 PIO9[7] SSC0_MRST SSC 0 data: master receive, slave transmit (full duplex mode) I/O J2/BR2 PIO9[3]/PIO6[3] SSC0_MTSR SSC 0 data: master transmit, slave receive (full duplex mode and I2C data bit for half duplex) I/O BD3/BN3 PIO9[2]/PIO6[2] SSC0_SCL SSC 0 - serial clock I/O SSC1 signals on PIO l Table 35. Signal name Description BA3/BE5 PIO4[5]/PIO11[7] SSC1_MRST SSC 1 data: master receive, slave transmit (full duplex mode) I/O BN4/BM3 PIO4[7]/PIO12[1] SSC1_MTSR SSC 1 data: master transmit, slave receive (full duplex mode and I2C data bit for half duplex) I/O BN2/BM4 PIO4[6]/PIO12[0] SSC1_SCL SSC 1 - serial clock I/O Description Direction SSC2_MRST SSC 2 data: master receive, slave transmit (full duplex mode) I/O SSC2_MTSR SSC 2 data: master transmit, slave receive (full duplex mode and I2C data bit for half duplex) I/O SSC2_SCL SSC 2 - serial clock I/O SSC2 signals on PIO Ball PIO BE4/H3/ BB3/D3 PIO7[0]/PIO8[5]/ PIO9[7]/PIO10[7] K4/BC2/ BA2/E3 PIO7[7]/PIO8[7]/ PIO9[5]/PIO10[6] BF1/BD4/ BA5/E2 PIO7[6]/PIO8[6]/ PIO9[4]/PIO10[5] Table 37. Signal name on Table 36. en ti a PIO fid Ball C Confidential Connections Direction SSC3 signals on PIO Ball PIO H30/M29/ K29 Signal name Description Direction PIO13[6]/PIO15[2]/ SSC3_MRST PIO15[7] SSC 3 data: master receive, slave transmit (full duplex mode) I/O H32/BE18/ M30 PIO13[5]/PIO15[1]/ SSC3_MTSR PIO15[6] SSC 3 data: master transmit, slave receive (full duplex mode and I2C data bit for half duplex) I/O BC18/K30/ M31 PIO13[4]/PIO15[0]/ SSC3_SCL PIO15[5] SSC 3 - serial clock I/O DocID023557 Rev 10 97/604 Information classified Confidential - Do not copy (See last page for obligations) STiH271EL Connections Ball PIO Signal name Description Direction AF29 PIO3[7] SSC10_MRST SSC 10 data: master receive, slave transmit (full duplex mode) I/O W30 PIO3[6] SSC10_MTSR SSC 10 data: master transmit, slave receive (full duplex mode) I/O W31 PIO3[5] SSC10_SCL SSC 10 - serial clock I/O Direction Table 39. SSC11 signals on PIO PIO Signal name Description Y30 PIO3[2] SSC11_MRST SSC 11 data: master receive, slave transmit (full duplex mode) I/O AB30 PIO2[7] SSC11_MTSR SSC 11 data: master transmit, slave receive (full duplex mode) I/O AA30 PIO2[6] SSC11_SCL SSC 11 - serial clock I/O PIO Signal name BN17 PIO1[2] SSC12_MRST BP17 PIO1[6] SSC12_MTSR V30 PIO1[7] SSC12_SCL on Ball 8.13.13 ti a en SSC12 signals on PIO Description fid Table 40. l Ball Direction SSC 12 data: master receive, slave transmit (full duplex mode) I/O SSC 12 data: master transmit, slave receive (full duplex mode) I/O SSC 12 - serial clock I/O Transport streams C Confidential SSC10 signals on PIO TS in signals Table 41. TSIn0 signals on PIO Ball PIO Signal name Description Direction BR4 PIO5[3] TSIN0_BYTECLK Transport stream0 serial/parallel data clock input/output I/O BP5 PIO5[4] TSIN0_DATA[7] Transport stream0 serial/parallel data input I AC4 PIO5[5] TSIN0_DATA[6] Transport stream0 parallel data input I AA3 PIO5[6] TSIN0_DATA[5] Transport stream0 parallel data input I AB3 PIO5[7] TSIN0_DATA[4] Transport stream0 parallel data input I Y3 PIO6[0] TSIN0_DATA[3] Transport stream0 parallel data input I Y4 PIO6[1] TSIN0_DATA[2] Transport stream0 parallel data input I BN3 PIO6[2] TSIN0_DATA[1] Transport stream0 parallel data input I BR2 PIO6[3] TSIN0_DATA[0] Transport stream0 parallel data input I 98/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 38. STiH271EL STiH271EL Ball PIO Signal name Description Direction BP4 PIO5[0] TSIN0_ERROR Transport stream0 serial/parallel data error input I BR3 PIO5[2] TSIN0_PACKETCLK Transport stream0 serial/parallel packet clock input I BP3 PIO5[1] TSIN0_VALID Transport stream0 serial/parallel data valid input I Table 42. TSIn1 signals on PIO Signal name Description Direction L3 PIO6[7] TSIN1_BYTECLK Transport stream1 serial/parallel data clock input/output I/O BE4 PIO7[0] TSIN1_DATA[7] Transport stream1 serial/parallel data input I BE2 PIO7[1] TSIN1_DATA[6] Transport stream1 parallel data input I K2 PIO7[2] TSIN1_DATA[5] Transport stream1 parallel data input I BE3 PIO7[3] TSIN1_DATA[4] Transport stream1 parallel data input I K3 PIO7[4] TSIN1_DATA[3] Transport stream1 parallel data input I BF5 PIO7[5] TSIN1_DATA[2] Transport stream1 parallel data input I BF1 PIO7[6] TSIN1_DATA[1] Transport stream1 parallel data input I K4 PIO7[7] TSIN1_DATA[0] BF3 PIO6[4] TSIN1_ERROR M2 PIO6[6] TSIN1_PACKETCLK M4 PIO6[5] TSIN1_VALID Table 43. fid en ti a l PIO on Ball Transport stream1 parallel data input I Transport stream1 serial/parallel data error input I Transport stream1 serial/parallel packet clock input I Transport stream1 serial/parallel data valid input I TSIn2 signals on PIO Ball PIO Signal name Description Direction H2 PIO8[3] TSIN2_BYTECLK Transport stream2 serial/parallel data clock input/output I/O J2 PIO9[3] TSIN2_DATA[0] Transport stream2 parallel data input I BD3 PIO9[2] TSIN2_DATA[1] Transport stream2 parallel data input I J1 PIO9[1] TSIN2_DATA[2] Transport stream2 parallel data input I J3 PIO9[0] TSIN2_DATA[3] Transport stream2 parallel data input I BC2 PIO8[7] TSIN2_DATA[4] Transport stream2 parallel data input I BD4 PIO8[6] TSIN2_DATA[5] Transport stream2 parallel data input I H3 PIO8[5] TSIN2_DATA[6] Transport stream2 parallel data input I G3 PIO8[4] TSIN2_DATA[7] Transport stream2 serial/parallel data input I G4 PIO8[0] TSIN2_ERROR Transport stream2 serial/parallel data error input I H1 PIO8[2] TSIN2_PACKETCLK Transport stream2 serial/parallel packet clock input I G2 PIO8[1] TSIN2_VALID Transport stream2 serial/parallel data valid input I C Confidential TSIn0 signals on PIO (continued) DocID023557 Rev 10 99/604 Information classified Confidential - Do not copy (See last page for obligations) Table 41. Connections Connections TSIn3 signals on PIO PIO Signal name Description Direction J3/Y3 PIO9[0]/ PIO6[0] TSIN3_BYTECLK Transport stream3 serial data clock input/output I/O J1/Y4 PIO9[1]/ PIO6[1] TSIN3_DATA[7] Transport stream3 serial data input I H3/AC4 PIO8[5]/ PIO5[5] TSIN3_ERROR Transport stream3 serial data error input I BC2/AB3 PIO8[7]/ PIO5[7] TSIN3_PACKETCLK Transport stream3 serial packet clock input I BD4/AA3 PIO8[6]/ PIO5[6] TSIN3_VALID Transport stream3 serial data valid input I TS out signals TSOut0 signals on PIO Signal name Description BF3 PIO6[4] TSOUT0_ERROR Transport stream0 serial/parallel data error output O M4 PIO6[5] TSOUT0_VALID Transport stream0 serial/parallel data valid output O M2 PIO6[6] TSOUT0_PACKETCLK Transport stream0 serial/parallel packet clock output O L3 PIO6[7] TSOUT0_BYTECLK Transport stream0 serial/parallel data clock input/output I/O K4 PIO7[7] TSOUT0_DATA[0] Transport stream0 parallel data output O BF1 PIO7[6] TSOUT0_DATA[1] Transport stream0 parallel data output O BF5 PIO7[5] TSOUT0_DATA[2] Transport stream0 parallel data output O K3 PIO7[4] TSOUT0_DATA[3] Transport stream0 parallel data output O BE3 PIO7[3] TSOUT0_DATA[4] Transport stream0 parallel data output O K2 PIO7[2] TSOUT0_DATA[5] Transport stream0 parallel data output O BE2 PIO7[1] TSOUT0_DATA[6] Transport stream0 parallel data output O BE4 PIO7[0] TSOUT0_DATA[7] Transport stream0 serial/parallel output O Description Direction 8.13.14 UART Table 46. UART0 signals on PIO fid Direction Ball PIO E4 PIO10[0] UART0_TXD UART 0 Transmit data O F3 PIO10[1] UART0_RXD UART 0 Receive data I D2 PIO10[2] UART0_CTS UART 0 Clear to Send I D1 PIO10[3] UART0_RTS UART 0 Ready to Send O D4 PIO10[4] UART0_NOTOE UART 0 Output Enable O 100/604 Signal name en PIO on Ball C Confidential Table 45. ti a l Ball DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 44. STiH271EL STiH271EL Ball PIO Description Direction BB5 PIO11[0] UART1_TXD UART 1 Transmit data O BC5 PIO11[1] UART1_RXD UART 1 Receive data I BD5 PIO11[2] UART1_RTS UART 1 Ready to Send O BC3 PIO11[3] UART1_NOTOE UART 1 Output Enable O BC4 PIO11[4] UART1_CTS UART 1 Clear to Send I Description Direction Table 48. Signal name UART2 signals on PIO PIO BE17 PIO14[4] UART2_NOTOE UART 2 Output Enable O K31 PIO15[4] UART2_TXD UART 2 Transmit data O M31 PIO15[5] UART2_RXD UART 2 Receive data I M30 PIO15[6] UART2_CTS UART 2 Clear to Send I K29 PIO15[7] UART2_RTS UART 2 Ready to Send PIO Signal name BR18 PIO2[0] UART10_NOTOE W32 PIO3[4] UART10_RTS W31 PIO3[5] W30 AF29 O ti a Description Direction UART 10 Output Enable O UART 10 Ready to Send O UART10_TXD UART 10 Transmit data O PIO3[6] UART10_RXD UART 10 Receive data I PIO3[7] UART10_CTS UART 10 Clear to Send I on Ball Table 50. en UART10 signals on PIO fid Table 49. Signal name l Ball C Confidential UART1 signals on PIO UART11 signals on PIO Ball PIO Signal name Description Direction AA30 PIO2[6] UART11_TXD UART 11 Transmit data O AB30 PIO2[7] UART11_RXD UART 11 Receive data I Y31 PIO3[0] UART11_CTS UART 11 Clear to Send I Y32 PIO3[1] UART11_RTS UART 11 Ready to Send O Y30 PIO3[2] UART11_NOTOE UART 11 Output Enable O DocID023557 Rev 10 101/604 Information classified Confidential - Do not copy (See last page for obligations) Table 47. Connections Connections 8.14 STiH271EL Pad reset conditions This section contains information about the state of functional chip I/Os during, and immediately after, reset. Table 51 shows the direction of the pads, I/O value for output pads and the presence of internal pull-up or pull-downs for inputs. Table 51. Pad reset conditions Direction in primary function Pad name Pad reset conditions Reset direction I/O value Weak pull-up SYS_NOTRESETIN I I SYS_AONOTWDOGRSTOUT O O SYS_AONOTRESETIN I I SYS_CLKINALT I SYS_32KOSCIN I SYS_32KOSCOUT O en High impedance Strong 1 High impedance High impedance Analog pad - Analog pad - I High impedance I High impedance I I High impedance O I High impedance I I High impedance I/O I High impedance I/O I High impedance EMI_ADD[3] I/O I High impedance EMI_ADD[4] I/O I High impedance EMI_ADD[5] I/O I High impedance EMI_ADD[6] I/O I High impedance EMI_ADD[7] I/O I High impedance EMI_ADD[8] I/O I High impedance EMI_ADD[9] I/O I High impedance EMI_ADD[10] I/O I High impedance EMI_ADD[11] I/O I High impedance EMI_ADD[12] I/O I High impedance EMI_ADD[13] I/O I High impedance JTAG I JTAG_TCK I on JTAG_NOTTRST JTAG_TDI JTAG_TDO JTAG_TMS EMI EMI_ADD[1] EMI_ADD[2] 102/604 fid I DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) I/O l I/O ti a SYS_NOTASEBRK C Confidential SYSTEM STiH271EL Pad reset conditions (continued) Direction in primary function Pad reset conditions Reset direction I/O value I/O I High impedance EMI_DATA[0] I/O I High impedance EMI_DATA[1] I/O I High impedance EMI_DATA[2] I/O I High impedance EMI_DATA[3] I/O I High impedance EMI_DATA[4] I/O I High impedance EMI_DATA[5] I/O I High impedance EMI_DATA[6] I/O I EMI_DATA[7] I/O I EMI_NANDRDY I/O I/O Weak pull-up EMI_DVBCIIORD O O Weak pull-up EMI_NOTBE[0] I/O EMI_NOTBE[1] I/O EMI_NOTCS[0] I/O EMI_NOTCS[1] I/O EMI_NOTCS[2] I/O EMI_NOTCS[3] I/O en ti a l EMI_ADD[14] High impedance High impedance I High impedance I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up O O Weak pull-up O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-down PIO0[0] I/O I/O Weak pull-up (Always ON) PIO0[1] I/O I/O Weak pull-up (Always ON) PIO0[2] I/O I/O Weak pull-up (Always ON) PIO0[3] I/O I/O Weak pull-up (Always ON) PIO0[4] I/O I/O Weak pull-up (Always ON) PIO0[5] I/O I/O Weak pull-up (Always ON) PIO0[6] I/O I/O Weak pull-up (Always ON) PIO0[7] I/O I/O Weak pull-up (Always ON) PIO1[0] I/O I/O Weak pull-up (Always ON) PIO1[1] I/O I/O Weak pull-up (Always ON) PIO1[2] I/O I/O Weak pull-up (Always ON) EMI_DVBCINOTWE EMI_NOTOE EMI_RDNOTWR EMI_TRDYORWAIT PIO fid High impedance on I C Confidential Pad name DocID023557 Rev 10 103/604 Information classified Confidential - Do not copy (See last page for obligations) Table 51. Connections Connections Pad reset conditions (continued) Direction in primary function Pad reset conditions Reset direction I/O value I/O I/O Weak pull-up (Always ON) PIO1[4] I/O I/O Weak pull-up (Always ON) PIO1[5] I/O I/O Weak pull-up (Always ON) PIO1[6] O O Weak pull-up (Always ON) PIO1[7] O O Weak pull-up (Always ON) PIO2[0] O O Weak pull-up (Always ON) PIO2[1] I I Weak pull-up (Always ON) PIO2[2] I I PIO2[3] I I PIO2[4] I/O I/O Weak pull-up (Always ON) PIO2[5] I/O I/O Weak pull-up (Always ON) PIO2[6] I/O PIO2[7] I/O PIO3[0] I/O PIO3[1] I/O PIO3[2] I/O PIO3[3] I/O en ti a l PIO1[3] Weak pull-up (Always ON) Weak pull-up (Always ON) I/O Weak pull-up (Always ON) I/O Weak pull-up (Always ON) I/O Weak pull-up (Always ON) I/O Weak pull-up (Always ON) I/O Weak pull-up (Always ON) I/O I/O Weak pull-up (Always ON) I/O I/O Weak pull-up (Always ON) I/O I/O Weak pull-up (Always ON) I/O I/O Weak pull-up (Always ON) I/O I/O Weak pull-up PIO4[1] I/O I/O Weak pull-up PIO4[2] I/O I/O Weak pull-up PIO4[3] I/O I/O Weak pull-up PIO4[4] I/O I/O Weak pull-up PIO4[5] I/O I/O Weak pull-up PIO4[6] I/O I/O Weak pull-up PIO4[7] I/O I/O Weak pull-up PIO5[0] I/O I/O Weak pull-up PIO5[1] I/O I/O Weak pull-up PIO5[2] I/O I/O Weak pull-up PIO5[3] I/O I/O Weak pull-up PIO3[4] PIO3[5] PIO3[6] PIO3[7] PIO4[0] 104/604 fid Weak pull-up (Always ON) on I/O C Confidential Pad name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 51. STiH271EL STiH271EL Pad reset conditions (continued) Direction in primary function Pad reset conditions Reset direction I/O value I/O Weak pull-up PIO5[5] I/O I/O Weak pull-up PIO5[6] I/O I/O Weak pull-up PIO5[7] I/O I/O Weak pull-up PIO6[0] I/O I/O Weak pull-up PIO6[1] I/O I/O Weak pull-up PIO6[2] I/O I/O Weak pull-up PIO6[3] I/O I/O PIO6[4] I/O I/O Weak pull-up PIO6[5] I/O I/O Weak pull-up PIO6[6] I/O I/O Weak pull-up PIO6[7] I/O PIO7[0] I/O PIO7[1] I/O PIO7[2] I/O PIO7[3] I/O PIO7[4] I/O en l I/O ti a PIO5[4] Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up PIO8[2] I/O I/O Weak pull-up PIO8[3] I/O I/O Weak pull-up PIO8[4] I/O I/O Weak pull-up PIO8[5] I/O I/O Weak pull-up PIO8[6] I/O I/O Weak pull-up PIO8[7] I/O I/O Weak pull-up PIO9[0] I/O I/O Weak pull-up PIO9[1] I/O I/O Weak pull-up PIO9[2] I/O I/O Weak pull-up PIO9[3] I/O I/O Weak pull-up PIO9[4] I/O I/O Weak pull-up PIO7[5] PIO7[6] PIO7[7] PIO8[0] PIO8[1] fid Weak pull-up on I/O C Confidential Pad name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 51. Connections 105/604 Connections Pad reset conditions (continued) Direction in primary function Pad reset conditions Reset direction I/O value I/O I/O Weak pull-up PIO9[6] I/O I/O Weak pull-up PIO9[7] I/O I/O Weak pull-up PIO10[0] I I Weak pull-up PIO10[1] I I Weak pull-up PIO10[2] I I Weak pull-up PIO10[3] O O Weak pull-up PIO10[4] I I PIO10[5] O O PIO10[6] O O PIO10[7] I/O I/O PIO11[0] I/O PIO11[1] I/O PIO11[2] I/O PIO11[3] I/O PIO11[4] I/O PIO11[5] I/O en ti a l PIO9[5] Weak pull-up Weak pull-up Weak pull-up Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up I/O I/O Weak pull-up PIO12[3] I/O I/O Weak pull-up PIO12[4] I/O I/O Weak pull-up PIO12[5] I/O I/O Weak pull-up PIO12[6] I/O I/O Weak pull-up PIO12[7] I/O I/O Weak pull-up PIO13[0] I/O I/O Weak pull-up PIO13[1] I/O I/O Weak pull-up PIO13[2] I/O I/O Weak pull-up PIO13[3] I/O I/O Weak pull-up PIO13[4] I/O I/O Weak pull-up PIO13[5] I/O I/O Weak pull-up PIO11[6] PIO11[7] PIO12[0] PIO12[1] PIO12[2] 106/604 fid Weak pull-up on I/O C Confidential Pad name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 51. STiH271EL STiH271EL Pad reset conditions (continued) Direction in primary function Pad reset conditions Reset direction I/O value I/O Weak pull-up PIO13[7] I/O I/O Weak pull-up PIO14[0] I/O I/O Weak pull-up PIO14[1] I/O I/O Weak pull-up PIO14[2] I/O I/O Weak pull-up PIO14[3] I/O I/O Weak pull-up PIO14[4] I/O I/O Weak pull-up PIO14[5] I/O I/O PIO14[6] I/O I/O Weak pull-up PIO14[7] I/O I/O Weak pull-up PIO15[0] I/O I/O Weak pull-up PIO15[1] I/O PIO15[2] I/O PIO15[3] I/O PIO15[4] I/O PIO15[5] I/O PIO15[6] I/O en l I/O ti a PIO13[6] Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O Weak pull-up I/O I/O Weak pull-up O O Strong 0 O O Strong 0 O O Strong 0 LMI_ADD[3] O O Strong 0 LMI_ADD[4] O O Strong 0 LMI_ADD[5] O O Strong 0 LMI_ADD[6] O O Strong 0 LMI_ADD[7] O O Strong 0 LMI_ADD[8] O O Strong 0 LMI_ADD[9] O O Strong 0 LMI_ADD[10] O O Strong 0 LMI_ADD[11] O O Strong 0 LMI_ADD[12] O O Strong 0 LMI_ADD[13] O O Strong 0 PIO15[7] LMI LMI_ADD[0] LMI_ADD[1] LMI_ADD[2] fid Weak pull-up on I/O C Confidential Pad name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 51. Connections 107/604 Connections Pad reset conditions (continued) Direction in primary function Pad reset conditions Reset direction I/O value O O Strong 0 LMI_ADD[15] O O Strong 0 LMI_BA[0] O O Strong 0 LMI_BA[1] O O Strong 0 LMI_BA[2] O O Strong 0 LMI_CKE O O Strong 0 LMI_CKN[0] O O Strong 0 or 1 LMI_CKP[0] O O LMI_DM[0] I I LMI_DM[1] I I LMI_DATA[0] I I LMI_DATA[1] I LMI_DATA[2] I LMI_DATA[3] I LMI_DATA[4] I LMI_DATA[5] I LMI_DATA[6] I en ti a l LMI_ADD[14] Strong 0 or 1 High impedance High impedance High impedance I High impedance I High impedance I High impedance I High impedance I High impedance I I High impedance I I High impedance I I High impedance I I High impedance I I High impedance LMI_DATA[12] I I High impedance LMI_DATA[13] I I High impedance LMI_DATA[14] I I High impedance LMI_DATA[15] I I High impedance LMI_DQSN[0] I I High impedance LMI_DQSN[1] I I High impedance LMI_DQSP[0] I I High impedance LMI_DQSP[1] I I High impedance LMI_NOTCAS O O Strong 1 LMI_NOTCS O O Strong 1 LMI_NOTRAS O O Strong 1 LMI_DATA[7] LMI_DATA[8] LMI_DATA[9] LMI_DATA[10] LMI_DATA[11] 108/604 fid High impedance on I C Confidential Pad name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 51. STiH271EL STiH271EL Pad reset conditions (continued) Direction in primary function Pad name Pad reset conditions Reset direction I/O value O O Strong 1 LMI_NOTWE O O Strong 1 LMI_ODT O O Strong 0 LMIPLL_TEST I/O Analog pad High impedance LMI_NOTRETENTION I I High impedance C on fid Confidential en ti a l LMI_NOTRESET Information classified Confidential - Do not copy (See last page for obligations) Table 51. Connections DocID023557 Rev 10 109/604 Front-end overview STiH271EL 9 Front-end overview 9.1 IC interface Note: The ID register identifies the release of the STiH271EL demodulator. It can be used by the driver software to identify the appropriate algorithms to be used. 9.1.1 Addresses ti a l Address = 00111 CS1 CS0 READNOTWRITE. For example, selecting CS1 = 0 and CS0 = 0 sets 0x38. 9.1.2 Write operation (normal mode) en The first byte gives the device address, plus the direction bit (READNOTWRITE = 0). 2. The second byte contains the internal address of the first register to be accessed. 3. The third byte is written in the internal register. fid 1. Any bytes that follow are written in successive internal registers. If gaps exist in the address table, the transfer has to be stopped and restarted from the next valid address. 9.1.3 Do not change values in undefined/reserved addresses because this might cause problems in engineering test registers. on Note: 4. The transfer lasts until stop conditions are encountered. 5. The STiH271EL demodulator acknowledges every byte transfer. C Confidential The byte sequence is as follows: Read operation (normal mode) The address of the first register to read is programmed in a write operation without data, and terminated by the stop condition. Another start is then followed by the device address and READNOTWRITE = 1. All the following bytes are data to be read at consecutive locations, starting from the initial address. The Figure 12 shows the I C normal mode write and read registers. The I C block supports restarts in read mode. Figure 12. Example of IC read and write operations in normal mode Write registers 0 to 3 with AA, BB, CC, DD Start Device write address ACK Register address 00 ACK Data AA ACK Data BB ACK Data CC ACK Data DD ACK Stop Read registers 2 and 3 110/604 Start Device write address ACK Register address 02 ACK Start Device read address ACK Data read CC ACK DocID023557 Rev 10 Stop Data read DD ACK Stop Information classified Confidential - Do not copy (See last page for obligations) The high-speed I C protocol is utilized. Four I C addresses are allocated, from which the first byte is one of 0x38, 0x3A, 0x3C or 0x3E for a write operation, or one of 0x39, 0x3B, 0x3D or 0x3F for a read operation, depending on the CS1 and CS0 values. STiH271EL 9.1.4 Front-end overview IC interface in standby mode In the standby mode, a limited number of registers are addressed to enable programming of I/O configuration, analog mode and basic COFDM or QAM configuration. These registers are identified in Chapter 10: Front-end registers on page 139. The I C protocol is identical both in the standby and normal modes. Figure 13. Generic IC read and write operations Write operation Start Device write address ACK Register address Register address ACK Data ACK Stop ACK Start Device read address ACK Read data Note 1: ACK is not mandatory after data. Stop ACK (or no ACK )Stop en IC bus repeater fid Traffic on the C_SDA/C_SCL lines of the I C bus may degrade the front-end tuner's performance. To avoid this, the STiH271EL demodulator has a dedicated I C bus repeater, so that C_SDAT and C_SCLT are active only when necessary, and become muted after the tuner's configuration has settled. on Pins C_SDAT and C_SCLT are set high at reset. When the microprocessor writes 1 into register I2CRPT.I2CT_ON, the next I C message on C_SDA and C_SCL is repeated on pins C_SDAT and C_SCLT respectively, until stop conditions are detected (if 1 is programmed into the I2CRPT.STOP_ENABLE bit). To write to the tuner, for each tuner message the external microprocessor must carry out the following steps: If 1 is programmed in I2CRPT.STOP_ENABLE in order to disable the I C repeater at the I C stop instruction: C Confidential 9.1.5 ACK l Device write address ti a Start 1) Program 1 in I2CRPT.I2CT_ON. 2) Send the message to the tuner. Else, if 0 is programmed in I2CRPT.STOP_ENABLE: 1) Program 1 in I2CRPT.I2CT_ON. 2) Send the message to the tuner. 3) Program 0 in I2CRPT.I2CT_ON. Any size of byte transfer is allowed, regardless of the address, until the stop conditions are detected. Transfers are fully bi-directional. Bit I CT_ON is automatically reset at the stop condition. The I CT speed is programmable through I2CRPT.ENARPT_LEVEL[2:0]. The maximum operating frequency of the I C bus repeater is 400 kHz. DocID023557 Rev 10 111/604 Information classified Confidential - Do not copy (See last page for obligations) Read operation Front-end overview STiH271EL Figure 14. IC repeater Repeater on/off C_SCL C_SCLT I C master Tuner C_SDAT C_SDA The general-purpose I/O pins are C_GPIO1, C_GPIO2, C_GPIO3, C_GPIO4, C_GPIO5, C_GPIO6 and C_GPIO7. en fid GPIO1_: active high, emulates GPIO1_DACVALUE[11:0] on the related pin, or else displays GPIO1_VAL. GPIO2_: active high, emulates GPIO2_DACVALUE[11:0] on the related pin, or else displays LOCK/GPIO2. GPIO1_VAL, GPIO3_VAL: logic value to be output. GPIO1_OD, GPIO2_OD, GPIO3_OD: active high, emulates an open-drain on the related pin. on GPIO1_IV, GPIO2_IV: active high, inverts the normal value to be delivered, either or logic value. GPIO1_DACVALUE[11:0], GPIO2_DACVALUE[11:0]: analog value to be delivered in a way on related pins. This value is unsigned and represents the fraction of power supply to be delivered: 0xFFF represents 3.3 V and 0x000 represents 0 V. The related pins must be low-pass filtered to obtain an analog level. The frequency can also be controlled by GPIO1_FREQ[3:0] or GPIO2_FREQ[3:0]. C Confidential C_GPIO1 and C_GPIO2 operate in a generic way, and can either deliver a output in open-drain or push-pull CMOS level, or a programmed logic value. Their behavior is controlled by the following commands extracted from registers IOCFG0, IOCFG1 and IOCFG2. GPIO1_FREQ[3:0], GPIO2_FREQ[3:0]: relative frequency of related pins. The internal modulators operate at maximum COFDM and QAM core frequency, that is, the quantum has a COFDM core period width. This width can be multiplied by the value of these registers. Pins C_GPIO2 and C_GPIO3 have a specific behavior for lock information display, refer to Section 9.3. The flexible C_GPIO4 to C_GPIO7 implementation facilitates debug. Their function is defined by programming the GPIO_CFG and GPIO_CMD registers. 112/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) General-purpose input/output ti a 9.2 l Front-end internal register STiH271EL 9.3 Front-end overview Interrupt generator Pins LOCK/GPIO2 and LOCK/GPIO3 can be programmed as a logic value copied in the register map, or they are the representation of specific lock information in the device. Register IOCFG2 sets the five lock indicators that can be output on the LOCK/GPIO2 and LOCK/GPIO3 port lock. 9.4 Standby modes ti a l The standby mode can be initiated or stopped by the I C bus commands. This guarantees low power consumption for the standalone modules (PCMCIA size front-end modules) before any command is initiated. C on fid Confidential en The two main parts of the device can be programmed to standby mode by software in DVB-T configuration. The COFDM core power may therefore be stopped when in FEC-only mode, or the FEC part may be stopped when in the acquisition phase of the COFDM signal. DocID023557 Rev 10 113/604 Information classified Confidential - Do not copy (See last page for obligations) A low power consumption mode (standby) is available in DVB-T or DVB-C configuration. In the standby mode, the I C decoder still operates, but with some restrictions. Front-end overview STiH271EL 9.5 Clock management 9.5.1 Crystal frequency An external crystal may be connected to pins C_XTAL_O and C_XTAL_I (see figure below), or an external clock may be forced on C_XTAL_I. The XTAL frequency can be from 4 to 30 MHz, and provides the device master clock. Figure 15. Application diagram for IF tuners RF in RF l ti a IF 100 nF COFDM/QAM IF tuner on 4.7 k 150 k 100 pF 100 nF C_IM C_INCM C_AGC_BB C_AGC_RF 100 pF 10 k en fid Confidential Private I C bus 3.3 V 180 1 SAW filter IF 36 MHz 4.7 k IF_AGC C_RF_LEVEL C_IP RF ADC C_SCLT A/D converter C_SDAT C I C bus C_SCL Dual AGC C_SDA 3.3 V 20 pF Digital core 4.7 k C_XTAL_O 2.5 V 30 MHz LOCK_OP2 (GPIO2) C_XTAL_I 20 pF 4.7 k STiH271EL C_CLK_OUT C_ERROR C_STR_OUT C_DATA[7:0] C_D_NOT_P DVB conditional access module or packet demultiplexer/transport IC (for example, STm5105 Omega chips) 114/604 DocID023557 Rev 10 2.5 V Information classified Confidential - Do not copy (See last page for obligations) 3V3 Automatic gain control signal STiH271EL 9.5.2 Front-end overview Clock register The STiH271EL demodulator includes a 2N x frequency multiplier. This means that the COFDM core always runs from 40 to 54 MHz, while the FEC is programmed from 80 to 108 MHz. 9.5.3 Auxiliary clock output C_XTAL_I 2N Osc. en fCOFDM/QAM fid Div/ COFDM/QAM demodulator N [1, 2, 4, 8] C_AUX_CLK FEC > < Analog interface 9.6.1 Dual analog-to-digital converter (ADC 12-bit) TS Divider ENA8_LEVEL on 9.6 / A dual 12-bit ADC is provided. The maximum ADC differential input is 2 V (p-p) or 1.6 V (p-p) (between IP and IM or QP and QM). The ADC is connected to the IF tuner by an external serial capacitor and resistor for impedance matching. C Confidential C_XTAL_O ti a l Figure 16. Clocks For IF reception, the ADC I (IP IM inputs) must be connected. The COFDM demodulator can operate in IF or ZIF. The QAM demodulator can only operate in IF. 9.6.2 RF signal strength indicator When the RF tuner is managing its own AGC loop, the RF signal strength indicator function can be activated by keeping the RSSI ADC active holding EN_RF_AGC.STDBY_ADC to logic zero. The RF signal level can be extrapolated from the unsigned value RF_AGC_LEVEL[7:0] in register RF_AGC. DocID023557 Rev 10 115/604 Information classified Confidential - Do not copy (See last page for obligations) The auxiliary clock is derived by dividing the C_XTAL_I, the STANDBY or the COFDM clock and is output on pin C_AUX_CLK (see Figure 16) by coding AUX_CLK.CKSEL. The division ratio (/M) set by the CKDIV_PROG bits [2:1] of AUX_CLK can be 1, 2, 4 or 8. This clock has to be programmed after power-on reset through the I C serial link. It is not intended to be active during the active reset phase. Front-end overview 9.6.3 STiH271EL Automatic gain control for COFDM reception Registers Two registers indicate the automatic gain control (AGC) loop gain values: AGC_RFVAL1 or AGC_RFVAL2 and AGC_RFVAL1 or AGC_RFVAL2. These registers are in read-only mode when respective gains are within the AGC loop, or in write mode when they are in a software-controlled loop. Register AGCCTRL2 provides further program gain control by means of AGCCTRL2.FRZ1_CTRL and AGCCTRL2.FRZ2_CTRL. ti a l Dual control point AGC for COFDM reception en The STiH271EL demodulator has two outputs for AGC, one for tuner gain control (C_AGC_RF) and the other for the IF stage gain control (C_AGC_BB). The analog gain control commands are obtained by simple low-pass filtering of these signals. The behavior of dual AGC is listed below. For high-level RF, the overall gain must be low, and acting on C_AGC_BB alone is no longer satisfactory: for these levels, the RF gain must participate in the overall gain variation. on For a low-level RF signal, a relatively large overall analog gain is needed. Since the tuner performs better at stable gain, C_AGC_RF (RF gain control) is stabilized by programming it to its maximum value and C_AGC_BB (IF gain control) is adjusted for correct signal level at the ADC input. fid Confidential C The boundary between these two operating zones is user defined. This boundary is known as the take-over point. The take-over point is programmable through register AGC_IFTH. Below the take-over point, when both C_AGC_RF and C_AGC_BB are active, the distribution of the actions between C_AGC_RF and C_AGC_BB is user controlled by register AGCR (RATIO_A, RATIO_B, RATIO_C). If the C_AGC_BB rate varies by a term delta2 (= AGC - AGC_IFTH), AGC_RF varies by delta1: delta1 = delta2 ratio = (2RATIO_A ratio + 2RATIO_B) / 2RATIO_C C_AGC_RF and C_AGC_BB values may also be saturated through registers AGC_RFMAX, AGC_RFMIN, FREESYS1 and AGC_IFMIN. C_AGC_RF and C_AGC_BB rates can be saturated to minimum and maximum values. They can be frozen independently under software control, or automatically on detection of AGC lock by the STiH271EL demodulator. 116/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Register AGCCTRL2 configures the operating mode of the three available gains. Either AGC_RF or AGC_IF can be in the AGC loop, or in a software-controlled mode. AGC_IF is available when in dual control mode AGC. STiH271EL Front-end overview Figure 17. AGC control level AGC control level (SD rate) C_AGC_BB (max.) C_AGC_RF (max.) C_AGC_RF C_AGC_BB_threshold C_AGC_BB C_AGC_BB (min.) C_AGC_RF (min.) ti a l Single control point AGC for COFDM reception A single AGC control point can be used if required. Pin C_AGC_BB can be used for this purpose. en AGC pins configuration for COFDM reception 9.6.4 fid They can be programmed to behave either as push-pull outputs or as open-drain through register AGC_RF_IF_C (even in open-drain configuration, the maximum output level is 3.3 V). ADC overflow rate control for COFDM reception on The ADC overflow rate is controlled through register AGCCTRL2 bits TIME_CST[2:0] and observed in registers OVF_RATE1 and OVF_RATE2. The maximum value of OVF_RATE (0xFFF) is obtained from the programmed time constant when the ADC continuously overflows. When the ADC overflows for half the time, the value is divided by 2. The register provides the ratio of overflow data to total sampled data. 9.6.5 C Confidential The AGC outputs are mapped to the dedicated pins C_AGC_RF or C_AGC_BB. Automatic gain control for QAM reception Dual control point AGC The demodulator has two PWM outputs for AGC, one for tuner gain control (AGC RF) and the other for IF stage gain control (AGC IF). The analog gain control commands are obtained by simple low-pass filtering of these PWM signals. With two AGC control points, the tuner may be operated as close to maximum gain as possible to obtain the best performance. For low RF signal levels, the AGC RF PWM rate is fixed at its threshold and AGC IF is set so the desired level is obtained at the ADC output. If AGC IF reaches its high threshold (very low input level) then RF AGC starts increasing; and if AGC IF reaches its low threshold (high input level) then AGC RF starts decreasing. The point where this occurs is called the take-over point (TOP), which is programmable and defined by the AGC IF low threshold. The loop response is user-programmable and controls the overall AGC action. The input reference level is also programmable. DocID023557 Rev 10 117/604 Information classified Confidential - Do not copy (See last page for obligations) Take-over RF input level point *Set by C Front-end overview STiH271EL See registers at addresses from 0xF410 to 0xF423 (QAM_AGC_CTL to QAM_AGC_PWM_RFCMD_H). In the demodulator, AGC RF and AGC IF can be frozen independently under software control. When both AGCs are active, the overall action is distributed between AGC RF and AGC IF following a specific algorithm that depends on the different thresholds and gains. Figure 18. AGC control level AGC RF ti a l AGC RF Threshold AGC IF High Thresh. AGC IF AGC IF Low Thresh. Confidential en 0% RF power increase fid Single control point AGC for QAM reception A single AGC control point may still be used for QAM reception, if required. Use pin C_AGC_BB. on AGC pin configuration for QAM reception The AGC outputs are mapped to the dedicated pins C_AGC_RF or C_AGC_BB. C They can be programmed to behave either as push-pull outputs or as open drain through registerAGC_RF_IF_C (even in open drain configuration, the maximum output level is 3.3 V). 9.7 Signal processing for COFDM demodulation 9.7.1 Impulsive noise rejection (INR) and canceller This module removes the effect of impulsive noise on the COFDM demodulator. Because of the oversampling, the COFDM signal is correlated while the impulsive noise is not, which gives a criterion to detect the presence in a signal of burst noise. This translates by the fact that the difference between two consecutive samples uncorrupted by impulsive noise should be limited. The second observation is that the impulsive noise is present in the entire frequency band, thus leading to power fluctuation in the extra bandwidth, which gives a second criterion to detect impulsive noise. This last criterion is more efficient as the bandwidth of the SAW filter is large. 118/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 100% STiH271EL 9.7.2 Front-end overview Digital filter Digital filters are able to filter DVB-T adjacent channels depending on COFDM channel bandwidth (BW): 8, 7, 6 or 5 MHz. By default, digital filters are based on a 54 MHz system frequency, 8 MHz channel bandwidth and 200 kHz offset. Filter coefficients are programmable by I C registers. It is necessary to set the cell number (address 0xF060) and the coefficients. Note: For further information on IIR programming, please refer to your local ST application support. IIR CELL6 iir_c6_coeff[5:1][15:0] IIR CELL5 iir_c5_coeff[5:1][15:0] l iir_c4_coeff[5:1][15:0] ti a IIR CELL4 fid en iir_c3_coeff[5:1][15:0] iir_c2_coeff[5:1][15:0] iir_c1_coeff[5:1][15:0] 9.7.3 IIR CELL3 IIR CELL2 IF to baseband conversion 9.7.4 Zero-IF mode on The received OFDM signal may typically be at a nominal IF of 4.57 MHz or around 36 MHz. For this signal, the IF-to-baseband module performs a down-conversion to the baseband; and also real demodulation. The received OFDM signal may typically be at a Zero-IF. For this signal, the ZIF-tobaseband module performs a down-conversion to the baseband; and also real demodulation. C Confidential IIR CELL1 9.7.5 Timing and carrier correction ADC clock recovery is performed digitally, so that no external VCXO is required. The carrier recovery and derotator loop re-samples the output of the IF-to-baseband module to take into account any frequency offset between the received and transmitted clocks. The interpolation rate may be programmed to accommodate various IF frequency channel bandwidths. 9.7.6 Co-channel and adjacent-channel interference suppressor This module filters any residual adjacent and co-channel interference, such as NICAM energy leakage through the edges of the saw filter. Digital AGC is also performed so that the signal power into the FFT is constant, since the adjacent and co-channel suppression may remove significant signal energy. DocID023557 Rev 10 119/604 Information classified Confidential - Do not copy (See last page for obligations) Figure 19. Filter diagram Front-end overview 9.7.7 STiH271EL Symbol timing /recovery This module determines the optimum time point to trigger the FFT. To help with the decision on guard/mode detection, a programmable threshold is controlled through register SYR_THR. Correlation techniques are used in the time domain for acquisition, along with advanced filtering techniques to ensure robust operation in low noise and dispersive channels. Frequency domain methods are used to extract the channel impulse response, and hence to track dynamic changes in the channel and ensure robust operation in single frequency networks (SFN). Carrier and timing recovery loop (CRL and TRL) ti a l This module calculates the timing error and filters it to drive an NCO that controls the sample timing correction applied in the interpolator and carrier detection module. The nominal sample timing rate (BWn) is 9.14, 8.00 or 6.86 MHz depending on the COFDM channel bandwidth (BW): 8, 7 or 6 MHz respectively. The timing loop working with the external crystal oscillator uses the value TRL_NOMRATE[16:0] (TRL_NOMRATE2[16:9], TRL_NOMRATE1[8:1], TRL_CTL[7]). Confidential en In addition to TRL_NOMRATE1 programming, the loop working with the external crystal oscillator is controlled through registers GAIN_SRC1 and GAIN_SRC2. These registers provide the ratio between sampling frequency and the COFDM signal bandwidth. This ratio is quantified on 12 bits, and is a gain to optimize input level for the FFT block. The sample rate conversion uses the TRL_NOMRATE value. GAINSRC = (2 fid TRL_NOMRATE[16:0] = ((64/7) (64 / 7) ChanBW / (fCOFDM (BW / 8) / (fCOFDM / 2)) 4)) 217 212 on The frequency loop is controlled through registers INC_DEROT1 and INC_DEROT2 to recover input samples at the ADC output. These registers provide the front-end derotator increment. It is calculated with respect to the tuner intermediate frequency value (fIF) and the sampling frequency, and is quantified on 16 bits. INCDEROT = ((fCOFDM - fIF) / fCOFDM) 216 C For sampled IF at 36.166 MHz, the spectrum can be inverted using bit 7 in register GAIN_SRC1. See Figure 16: Clocks on page 115. 9.7.9 Fast Fourier transform (FFT) This module performs a complex 2048/8192 point FFT. It is performed on a suitable block of data as defined by the trigger pulse from the symbol timing recovery module. 9.7.10 Channel estimation and correction (CHC) This module uses both the scattered and continuous pilot tones to derive an accurate timevarying estimate of the complex frequency response of the channel for every third carrier. This estimate is then interpolated in the frequency domain and used to correct each of the individual data OFDM carriers. Channel state information for each pilot is also calculated here in order to generate the software decision metrics that are used by the Viterbi decoder. 120/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 9.7.8 STiH271EL 9.7.11 Front-end overview Echo protection quality (EPQ) loop The goal of automatic EPQ loop is to follow the dynamic echo position to finely adjust the FFT trigger point in tracking mode (with CHC information). It is possible to adjust the FFT trigger by the hardware or the software algorithm in order to optimize synchronization for echo outside GI. 9.7.12 Symbol de-interleaver This module implements the frequency domain reordering of the data carriers within the symbols as defined in the DVB-T specification. De-mapper Bit de-interleaving en 9.7.14 ti a l This module decodes the complex QPSK, 16 QAM or 64 QAM constellations of the OFDM data carriers into a software decision bit stream. It takes into account individual data carrier SNR information. Carrier monitoring fid 9.7.15 For test purposes, a set of carriers can be selected for monitoring. This is controlled through registers CONSTMODE, CONSTCARR1 and CONSTCARR2. Bits CAR_TYPE[1:0] (register CONSTMODE) select the carrier type to be sorted. Data is output on the I C bus. 9.8 on CONST_MODE[1:0] controls the way the carriers are sorted. Registers CONSTCARR1 and CONSTCARR2 identify the first carrier out of 16 to be stored in the FIFO for display. Forward error correction (FEC) for COFDM demodulation C Confidential This module implements the bit de-interleaving and demultiplexing to the high- and lowpriority software decision data stream. The FEC can run in automatic mode to search the puncture rate (no need for TPS) or in the TPS forced mode: Phase search Code rate search Refer to Section 9.8.1 for details. 9.8.1 Viterbi decoder and synchronization The convolution codes are generated by the polynomial Gx = 171 octal and Gy = 133 octal. The puncture rate and phase are estimated on the error rate basis. Either several rates are allowed and may be enabled or disabled by programming register PRVIT, or the COFDM core forces the rate to the value it extracted from the TPS (transmitter parameter signaling): 1/2, 2/3, 3/4, 5/6, 7/8 For each enabled rate, the current error rate (registerVERROR) is compared to a programmable threshold (registers VTH12 to VTH78). If it is greater than the threshold, another phase (or another rate) is tried until the best rate is obtained. DocID023557 Rev 10 121/604 Information classified Confidential - Do not copy (See last page for obligations) 9.7.13 Front-end overview STiH271EL A programmable hysteresis is added to avoid losing the phase during short-term instability. The rate may be imposed only by an external software, and the phase is incremented only upon request by the microprocessor. The error rate may be read at any time in order to use an external puncture rate recovery algorithm. The Viterbi decoder produces an absolute decoding. The decoder is controlled using several Viterbi threshold registers. For each Viterbi threshold register (VTH12 to VTH78), bits from 6 to 0 represent an error rate threshold that is compared to the average number of errors occurring during 256 bit periods. The maximum programmable value is 127/256 (higher error rates are of no practical use). l VAVSRVIT.P1_VAVSRVITPR) and VAVSRVIT.FROZENVIT program the automatic/manual (or computer-aided) search mode. If P1_VAVSRVIT= 0 and FROZENVIT = 0, the automatic mode is set. Successive enabled puncture rates are tried with all possible phases, until the system is locked and the block sync found. This is the default (reset) mode. If P1_VAVSRVIT = 0 and FROZENVIT = 1, the current puncture rate is frozen. If no sync is found, the phase is incremented, but not the rate number. This mode allows shortening of the recovery time in the case of noisy conditions. The puncture rate is not supposed to change in a given channel. In a typical computer-aided implementation, the search begins in automatic mode. The microprocessor reads the error rate at STATUS.PRF to detect signal capture, then it switches FROZENVIT to 1, until a new channel is requested by the remote control. If P1_VAVSRVIT = 1, manual mode is set. In this case, only one puncture rate should be validated. The system is forced to this rate, on the current phase value, ignoring the time-out register and the error rate. In this mode, each 0-to-1 transition of the bit FROZENVIT leads to a phase indentation, allowing full control of the operation by an external microprocessor by choosing the lowest error rate. fid on Confidential en ti a The reset values are P1_VAVSRVIT = 0, and FROZENVIT = 0 (automatic search mode). C Register VERROR is a read-only register. The last value of the error rate may be read at any time. Unlike the VTH12 to VTH78 register values, the possible range is from 0 to 255/256. Register STATUS is a read-only register. 9.8.2 Synchronization The packet length after inner decoding is 204 bytes. The sync word is the first byte of each packet. Its value is 0x47, but this value is complemented every eight packets. An up/down sync counter counts up whenever a sync word is recognized with the correct timing, and counts down for each missing sync word. This counter is bounded by a programmable maximum. When this value is reached, bit LK (locked) is set in register STATUS. When the event counter counts down to 0, this flag is reset. 9.8.3 Convolutional de-interleaver The convolutional de-interleaver is 17 12. The period of 204 bytes per sync byte is retained. The de-interleaver may be bypassed. For details, see Section 9.8.4. 122/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The automatic rate search is only performed using the enabled rates (see the corresponding bit set in the puncture rate register PRVIT). STiH271EL 9.8.4 Front-end overview Reed-Solomon decoder and descrambler The input blocks are 204-bytes long with 16 parity bytes. The sync byte is the first byte of the block. Errors up to 8 bytes can be fixed. The code generator polynomial is: g(x) = (x - 0)(x - 1)....(x - 15) over the Galois Field generated by: x8 + x4 + x3 + x2 + 1 = 0 Energy dispersal descrambler and the output energy dispersal descrambler generator: l The polynomial is initialized every eight blocks with the sequence 100 1010 1000 0000 (0x4A80). ti a Signal processing for QAM demodulation 9.9.1 IF to baseband en 9.9 f1 = fADC - ftuner fid The signal centered on the tuner IF is down-converted by ADC sub-sampling (ADC is clocked at frequency fADC). The replica used is typically centered on the sampled IF f1: on For example, when ftuner = 36 MHz, and fADC = 54 MHz, f1 = 18 MHz. The sampling clock can be freely chosen as long as no aliasing is introduced (using SAW filter characteristics and symbol rate). Refer to Figure 20. This sampled IF is then down-converted from f1 to quasi-baseband by a programmable derotator. This block down-converts any signal from 0 to fADC to baseband. It can therefore be used as a virtual tuner to bring signals for which the carrier is not at the center of the channel, to baseband frequency. This is useful for low symbol rate SCPCs where channel switching can be speeded up and adjacent channel interference removed. C Confidential The sync words are unscrambled, and the scrambler is reset every eight packets. Figure 20. Frequency spectra after direct down-conversion PSD WSTOP Useful signal spectrum fs(1 + SAW filter template WPASS ) f -f1 0 f1 fADC/2 fADC - f1 fADC f1 = fADC - ftuner It also provides compensation for locally generated frequency offsets (due to the tuner, for example) before matched filtering, so that even large offsets are no longer a problem. This DocID023557 Rev 10 123/604 Information classified Confidential - Do not copy (See last page for obligations) x15 + x14 + 1 Front-end overview STiH271EL may, for example, enable the use of larger tuner steps (which generally means lower phase noise). The derotator can also introduce a frequency mirroring effect to cancel spectral inversion introduced by the network. Any phase or frequency offset remaining after this stage is coherently tracked by the derotator present further down the chain. The derotator consists of a digital oscillator controlled by the registers MIX_NCO_LL to MIX_NCO_LH (addresses 0xF425 to 0xF427). The derotator obeys the following equation: 23 ( F ADC - F tuner ) 2 MIX_NCO_INC = -----------------------------------------------------F ADC 23 l or en Adjacent channels removal filter fid A specific filter has been introduced to eliminate the residual adjacent channels after the analog-to-digital conversion. The filter coefficients are programmed in registers IQDEM_ADJ_COEFF0 to IQDEM_ADJ_COEFF2 so that the filter can be adjusted to the symbol rate. 9.9.3 on At the output of the adjacent filter, an All Pass filter allows the cancellation of the group delay induced by the adjacent filter. This can be programmed by registers ALLPASSFILT(1)(2)(3) to ALLPASSFILT(10)(11). Symbol timing recovery and Nyquist filtering The correct symbol values at the optimum sampling instant are obtained by time-domain interpolation under the control of a timing loop. C Confidential 9.9.2 ti a Two DC offset cancellation mechanisms are implemented. The first is just after the ADC to remove external DC offsets. The second takes place after the derotator where a carrier residual is moved to a DC offset by the derotator. A digital gain stage adjusts the amplitude of the demodulated symbols to compensate for: The energy that is filtered out by the Nyquist interpolating filter (including any cochannel interference) The gain of this same filter, which depends on the ratio between the (fixed) sampling clock frequency and the (arbitrary) symbol rate The SRC derotator is controlled by SRC_NCO_LL, SRC_NCO_LH, SRC_NCO_HL and SRC_NCO_HH registers for the steps as well as the IQDEM_GAIN_SRC_L and IQDEM_GAIN_SRC_H registers for the gain as described in the following equations: SRC_NCO_INC is a user programmable register such that: SRC_NCO = 2 fSYMBOL 230 / (Fsystem/2) where, fADC is the sampling frequency of the analog-to-digital converter and fSYMBOL is the symbol frequency. The global gain of the SRC is programmable by software through a 10-bit register to compensate for the ratio of the converted frequencies: 124/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) F tuner 2 MIX_NCO_INC = ----------------------------F ADC STiH271EL Front-end overview SRC_GAIN = 220 fSYMBOL / (878 Fsystem/2) The timing recovery module operates in two modes. First, during acquisition, the block is set to use a timing acquisition window as wide as possible with a reduced acquisition time. When acquisition is achieved (TRL 1 acq lock is detected), the TRL is automatically switched to tracking mode, which gives the best demodulation performance. The quasi-baseband complex data stream is filtered by a complex square-root Nyquist filter, which can cope with 0.12, 0.13, 0.15 or 0.18 transmission roll-off factors setup in register bits TRL_LPF_CFG.NYQ_COEFF_SEL[1:0]. 9.9.4 Carrier recovery loop (CRL) ti a l Acquisition phase: to detect large carrier offsets and apply the necessary correction to the digital oscillator and mixer of the initial demodulator. Tracking phase: to finely adjust small carrier offsets. en 9.9.5 fid A sweep mechanism is also implemented in order to allow acquisition for a very large initial frequency error. This circuitry continuously monitors a large carrier offset range and stops the scanning when lock detection is flagged. Equalizer 9.9.6 on The linear adaptive equalizer consists of two filters: a feed-forward filter (FFE) and a decision feedback filter (DFE) processing complex values. Both filters have taps spaced at the symbol interval I/fs. The FFE input is the output of the initial demodulator with channel distortion. The DFE input is the sequence of decisions previously mapped and normalized. Phase noise canceller C Confidential The phase estimation is integrated by a loop filter, which produces a control value to drive the digital oscillator. This control value is monitored by the lock detect module, which indicates that the acquisition is complete. A phase noise canceller block has been implemented at the equalizer output to increase the robustness of the demodulator against system phase noise. This block can be enabled or disabled through register bit EQU_PNT_CFG1.PNT_EN. 9.9.7 Differential decoding and symbol-to-byte mapping The QAM demodulator differentially decodes the symbol stream as required by DVB-C/ITU J83-A/C specifications. The symbol stream (4-bit symbols for 16-QAM up to 8-bit symbols for 256-QAM) is turned into a byte stream following these same specifications, since the subsequent FEC (forward error correction) operates on bytes. DocID023557 Rev 10 125/604 Information classified Confidential - Do not copy (See last page for obligations) Carrier recovery is performed in the following two phases: Front-end overview 9.10 STiH271EL Master state machine for QAM demodulation The QAM demodulator is fully controlled by an internal state machine. This allows the QAM demodulator to be able to operate without a real-time CPU. A block diagram of the master state machine is shown in Figure 21. The different states of the demodulator state machine are listed below. 126/604 l ti a CRL2: switching to the CRL2 step, the CRL module operates in carrier tracking mode. The purpose of this level is to track the last carrier frequency offset that is not corrected by the derotator for the initial demodulator. This level ends when the SNR level is better than the SNR0 high threshold, SNR0_HTH. Note that the CRL2 step could be forced during at least the stage in time (MSM_SIT). The SIT is enabled by the SIT_EN configuration bit but is automatically activated if the MSM comes from a higher state. EQA1: the error generator is configured in the reduced constellation algorithm. This level can be bypassed by de-asserting the FSM_EQA1_EN configuration bit. This stage ends when the SNR is better than the SNR0 high threshold minus the EQA1 high threshold offset, written in the EQA1_HTH configuration register. EQA2: this is the same as EQA1 but with better accuracy. DDA: the error generator is configured with a data directed algorithm, using the distance between the mapped symbol and the equalized symbol. FEC: in this mode the equalizer is launched with the previous settings: - FFE/DFE narrow gain - Leakage (if LEAK_EN = 1) - Phase noise tracker (if PNT_EN = 1) - Carrier tracking care (if CRL_CARE = 1) - Bad point token (if BDP_EN = 1) FEC2: in the FEC2 mode the DFE part of the equalizer is shut down. WST FEC: if an SNR worse than the low threshold (SNR1_LTH) is detected, the wait stabilization time (MSM_WST) counter is triggered. When the waiting stabilization time ends, the state machine returns to the DDA mode if the SNR is bad, or to the FEC mode if the SNR is OK. WST DDA: if an SNR worse than the low threshold (SNR0_LTH) is detected, the wait stabilization time (MSM_WST) counter is triggered. When the waiting stabilization time DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Confidential CRL1: this is used to compensate for the carrier frequency offset. The CRL lock-detect signal indicates the CRL end of processing. At this stage, the MIX_NCO receives the carrier offset adjustment coming from the CRL module. en TRL2: the state machine stays in this step for one-eighth of the time required to complete the acquisition stage. To speed up the global lock time, this time delay must be disabled so that TRL2 and CRL are performed simultaneously. fid TRL1: during this step, the SRC is synchronized with the symbol rate. When the symbol timing offset is found, the lock detector asserts the lock signal and switches to the Timing Recovery Loop in tracking. on AGC: after reset, the first operation is to calibrate the input signal level by activating the AGC module. A lock detect is generated to indicate the AGC end of processing. The TRL_AHEAD configuration bit allows AGC and TRL1 to run simultaneously. C STiH271EL Front-end overview ends, the state machine returns to the CRL2 mode if the SNR is always bad, or to the DDA mode if the SNR is OK. Elapsed time: the elapsed time counter is loaded with 2(20 + MSM_ELT) as soon as the CRL state begins. This counter is decremented for each new symbol. When it reaches 0, a MSM reset is generated. The threshold values to change states can be redefined by writing to the associated registers FSM_SNRn_LTH and FSM_SNRn_HTH. The current state of the state machine can be read in FSM_STS[3:0]. Note that the CLR2, EQA1, EQA2, DDA, FEC, FEC2 transitions are allowed only if a new SNR ready occurs. l ti a Reset Information classified Confidential - Do not copy (See last page for obligations) Figure 21. Master state machine diagram en AGC Lock detected TRL2 (Tracking) Time delay or immediate CRL1 (Acquisition) on fid Confidential TRL1 (Acquisition) Lock detected CRL2 C SNR < SNR0_hth EQA1 SNR < SNR0_hth - EQA1_hth EQA2 SNR < SNR1_hth Failed SNR > SNR0_lth WST DDA DDA SNR < SNR0_lth SNR < SNR2_hth Failed SNR > SNR1_lth FEC WST FEC SNR < SNR1_lth SNR < SNR3_hth SNR > SNR3_hth + 7 FEC2 DocID023557 Rev 10 127/604 Front-end overview STiH271EL 9.11 Forward error correction (FEC) block for QAM demodulation 9.11.1 FEC-A/C Convolutive de-interleaver ti a l A Forney-type de-interleaver is integrated in the demodulator. Its default interleaving depth is 12 and cell depth is 17 (values specified for DVB-C/ITU-J83-A and C). However, smaller depths can also be programmed for reduced latency applications. Reed-Solomon decoder en The Reed-Solomon block can be commanded not to perform correction to allow external evaluation of raw bit error rates (BER before Reed-Solomon correction, see register FEC_AC_CTRL_0). fid Note: Sync byte inversion and descrambling on The descrambler works according to the DVB-C/ITU J83-A and ITU J83-C specifications and is based on the polynomial 1 + x14 + x15. It is synchronized by the inverted sync bytes present at the start of every eighth transport packet. In the de-randomized data stream supplied to the output interface, the inverted sync byte is re-inverted back to normal. Control of the descrambler is achieved through the FEC_AC_CTRL_2 and FEC_AC_CTRL_0 registers. 9.12 C Confidential The Reed-Solomon decoder performs [t = 8, (n, k) = (204,188)] decoding as described in the DVB / ITU-J83-A and C standards. DVB-T/DVB-C transport stream interface The transport stream (TS) interface takes data from an additional DVB-T/DVB-C Reed- Solomon forward error correctors and formats the data for transmission to the back-end decoder. The data can be issued in parallel or in serial mode. The output pins can be disabled by software when bit TS_DIS of register TOPCTRL is active. The pins are then in tri-state even if a valid stream is decoded internally. This enables the connection of several demodulator device in parallel. 128/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) To reduce any burst or impulse noise and to increase the correction power of the Reed- Solomon FEC code, the bytes are interleaved after Reed-Solomon encoding at the transmitter side. They must then be de-interleaved before Reed-Solomon decoding at the receiver side. An interleaved frame is delimited by MPEG-2 sync bytes and inverted sync bytes (preserving the periodicity of 204 bytes), so the convolutive de-interleaver is able to synchronize by locking onto these words. Default behavior of the state machine that declares acquisition/tracking based on the data received can be modified if required. STiH271EL Front-end overview Pins presentation The pins forming the MPEG/TS output interface are C_CLK_OUT, C_Data[7:0], C_D_NOT_P, C_STR_OUT, and C_ERROR. Their role is listed below. C_D_NOT_P: strobe signal that indicates whether the byte (bit in serial mode) supplied on C_Data[7:0] (C_Data[7] in serial mode), to be clocked in by the active edge of C_CLK_OUT, is one of the 188 valid bytes of the MPEG packet. C_STR_OUT: this signal flags the first valid byte (bit in serial mode) of an MPEG/TS packet. C_ERROR: this signal goes high during transmission of an MPEG/TS packet if this packet contains errors that could not be corrected by the Reed-Solomon decoder. l C_CLK_OUT: the serial or parallel output clock with programmable polarity. According to the format selected, it can be either continuous or interrupted. ti a The DVB-C output interface formatter is controlled through registers OUTFORMAT_0 and OUTFORMAT_1 (0xF4B8 and 0xF4B9). 9.13 DVB-T transport stream overview en Note: fid The block diagram of the TS block is shown in Figure 22. 9.14 Stream manager Data Filter FIFO Packet rate control Bit rate estimation FIFO Demodulator info Packet check Header and footer signaling insertion on FEC FIFO Figure 22. Main transport stream diagram C Confidential The QAM demodulator can output data according to the DVB-specified common interface format, in a specific parallel format or in serial form at instantaneous bit rates up to 57 MHz. Stream out Bit/Byte rate control Latency control DVB-T transport stream output processing The stream may be formatted with or without sync bytes or header bytes and the output rate may be controlled manually or adjusted automatically. The register TSINSDELH allows the sync and header bytes in an MPEG packet to be removed. This is useful when using external bit error rate test equipment. The TS line is configured by the TSINSDELH register. The TS interface is DVB-CI compliant, but also supports some extended behavior. DocID023557 Rev 10 129/604 Information classified Confidential - Do not copy (See last page for obligations) Front-end overview STiH271EL General The transport bus is made of the following pins: C_CLK_OUT, C_STR_OUT, C_D_NOT_P, C_ERROR and either C_Data[7] to C_Data[0] in parallel mode or C_Data[7] to C_Data[0] in serial mode. After a hardware reset, the transport bus is set to high impedance (disabled) and must be configured to low impedance (enabled) by programming register TOPCTRL[3]. The transport stream can be serial or parallel. There are two control bits to configure the pins; one for the serial part (control signals + data 7) and one for the data bits 6:0. ti a l The C_D_NOT_P (data valid/parity negated) pin is high when payload data is being output from the FEC. The C_D_NOT_P signal is low when redundant data is present (redundant data can be the parity data or rate-regulation stuffing bits). Data is regulated by both C_CLK_OUT and C_D_NOT_P. There are two regulation modes, called "data valid" and "envelope". en 9.14.1 Data rate control fid The envelope mode indicates the periods of valid data on C_D_NOT_P and then uses a punctured clock for rate regulation. The regulation mode is selected by register bit TSCFGH.TSFIFO_DVBCI (1 for a data valid mode, 0 for the envelope mode). Table 52. on The TS interface controls the output data rate. Padding bits are generated automatically according to the instantaneous bit rate and actual output data rate. The configuration is set in field TSCFGM.TSFIFO_MANSPEED. Four modes are provided, three of them are fully automatic and the fourth allows manual control of the regulation. The fully automatic mode is recommended, see Table 52. TSFIFO_MANSPEED configuration TS Rate Control Mode Manual TSFIFO_MANSPEED C Confidential The data valid mode uses a continuous clock and selects valid data on C_D_NOT_P. 11 Fully automatic 00 Conservative automatic 01 Dynamic automatic 10 For all configurations, the output data rate is: 32 / TSFIFO_OUTSPEED Serial interface, data rate = bit rate = clk_FEC Parallel interface, data rate = byte rate = clk_FEC 4 / TSFIFO_OUTSPEED Some TSSPEED.TSFIFO_OUTSPEED values can create a clock with a duty cycle not equal to 50%. To ensure a clock duty cycle of 50%, the register bit TSCFGH.TSFIFO_DUTY50 can be set, and constrains TSFIFO_OUTSPEED to be: 130/604 A multiple of 32 in serial mode A multiple of 4 in parallel mode DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The transport stream is activated when one of the FEC decoders outputs valid data. The transport stream remains active until lock loss is detected. STiH271EL Front-end overview Automatic mode (recommended) In this case, the chip computes TSFIFO_OUTSPEED from the following: Packet rate Header and footer (if any) signaling rate Reed-Solomon parity (if any) rate In automatic mode the chip recomputes TSFIFO_OUTSPEED after any change in one parameter involved in the equations. 9.15 DVB-T serial output modes ti a l In manual mode, the user sets the desired speed by programming the TSSPEED.TSFIFO_OUTSPEED register. Should the required data rate exceed the capacity, the start of the next packet will overwrite the end of the current packet. The serial output mode with pin C_D_NOT_P used as a data valid signal for discriminating between wanted data and "do not care" bits, see Figure 24 and Figure 26. The serial output mode uses the C_D_NOT_P signal as an envelope for the valid data section of the transport stream; the C_CLK_OUT signal is then interrupted (`punctured') in order to skip the unwanted data, see Figure 25 and Figure 27. on fid In this mode, the C_CLK_OUT clock signal is continuous. The desired rate is obtained by skipping the unwanted data using the C_D_NOT_P signal. The `holes' in the C_D_NOT_P signal are automatically inserted with regard to both the actual data payload rate (including the parity bits when present) and the C_CLK_OUT frequency. In this mode, the C_D_NOT_P data valid signal is used as an envelope to the useful data, excluding the parity bits. The C_CLK_OUT signal is used to reach the actual payload rate: holes are automatically inserted in the regular periodic clock signal to adjust the mean frequency to the desired payload rate. C Confidential en In serial mode, MSB data is output first. The serial mode supports both the rate regulation modes. The C_STR_OUT pin is high during the first bit of the packet payload. The rate compensation mode (TSCFGH.TSFIFO_DVBCI bit) is set as in Table 53 Table 53. . Rate compensation mode settings TSFIFO_DVBCI Serial1 mode = data valid Serial2 mode = envelope 1 0 DocID023557 Rev 10 131/604 Information classified Confidential - Do not copy (See last page for obligations) Manual mode Front-end overview STiH271EL Figure 23. Serial output interface (CLKOUT_XOR = 1), data valid C_STR_OUTx 1/fCLK_FEC C_CLK_OUTx C_D_NOT_Px C_D7x Valid data section = Do not care section Do not care data*1 l Valid ti a Data Internal clock Confidential C_D_NOT_Px = Do not care section en C_CLK_OUTx Figure 25. Serial output interface (CLKOUT_XOR = 1), envelope fid C_STR_OUTx C_CLK_OUTx C_D_NOT_Px on First bit of packet C_D7x C_ERRORx C 1 packet Figure 26. Serial mode options in valid data section (CLKOUT_XOR = 0), envelope Valid Data Internal clock M_CLK/n C_CLK_OUTx C_D_NOT_Px TCLK_OUT = n x TM_CLK 132/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Figure 24. Serial mode options in valid data section (CLKOUT_XOR = 0), data valid STiH271EL 9.16 Front-end overview DVB-T parallel output modes The STiH271EL demodulator features the following two different parallel output modes. ST back-end (recommended mode): C_CLK_OUT is held high or low (depending on register bit TSCFGH.TSFIFO_DVBCI) for unknown data sections, see Figure 27 and Figure 29. DVB-CI: where C_D_NOT_P is held high or low for unknown data sections, see Figure 28 and Figure 30. In both parallel output modes, the C_STR_OUT pin is high during the first byte of the packet. The rate compensation mode (TSCFGH.TSFIFO_DVBCI bit) is set as in Table 54. ti a DVB-CI TSFIFO_DVBCI 1 Information classified Confidential - Do not copy (See last page for obligations) Rate compensation mode settings l Table 54. ST Back-end 0 en No error Uncorrectable packet No error fid C_Data[7]-C_Data[0] C_CLK_OUT on C_D_NOT_P C_STR_OUT C_ERROR C Confidential Figure 27. ST back-end output interface (CLKOUT_XOR = 0) = Do not care section Valid data section Do not Care data DocID023557 Rev 10 133/604 Front-end overview STiH271EL Figure 28. DVB-CI output interface (CLKOUT_XOR = 0) No error Uncorrectable packet No error C_Data[7]-C_Data[0]) C_CLK_OUT C_D_NOT_P C_STR_OUT en Figure 29. ST back-end in valid data section (CLKOUT_XOR = 0 example) Confidential Data[7]-Data[0] Internal clock fid C_CLK_OUT C_D_NOT_P = Do not care section TCLK_OUT = n x TCLK_FEC on Figure 30. DVB-CI in valid data section (CLKOUT_XOR = 0) Data[7]-Data[0] Internal clock C C_CLK_OUT C_D_NOT_P 9.17 = Do not care section DVB-C transport stream output processing The QAM demodulator can output data according to the DVB-specified common interface format, in a specific parallel format or in serial form at instantaneous bit rates up to 57 MHz. 134/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Valid data Do not Care section data ti a = Do not care section l C_ERROR STiH271EL Front-end overview The pins forming the MPEG/TS output interface are C_CLK_OUT, C_DATA[7:0], C_D_NOT_P, C_STR_OUT and C_ERROR. Their role is listed below. C_CLK_OUT: data clock with programmable polarity. According to the format selected, it can be either continuous or interrupted. C_D_NOT_P: strobe signal that indicates whether the byte (bit in serial mode) supplied on TS_DATA[7:0] (TS_DATA[0] or TS_DATA[7] in serial mode), to be clocked in by the active edge of TS_CKOUT, is one of the 188 valid bytes of the MPEG packet. C_STR_OUT: this signal flags the first valid byte (bit in serial mode) of an MPEG/TS packet. C_ERROR: this signal goes high during transmission of an MPEG/TS packet if this packet contains errors that could not be corrected by the Reed-Solomon decoder. The output interface formatter is controlled through registers OUTFORMAT_0 and OUTFORMAT_1 (0xF4B8 and 0xF4B9). 9.17.1 DVB common interface ti a l Note: en FCLK_OUT > Fsymbol in all QAM modes. fid By choosing appropriate division ratios, a number of output clock frequencies are available between 5 MHz and 9 MHz with duty cycle between 40% and 60%. When the common interface format is selected, the ERROR flag is still supplied, although it is not actually required by the DVB-CI specification. TS_CKOUT TS_VAL on Figure 31. DVB common interface format C Confidential The clock supplied on C_CLK_OUT is continuous and has programmable frequency and polarity (Figure 31). Frequency is specified by giving the high- and low-level pulse durations in terms of cycles of a base clock at the system clock frequency. The demodulator requires the common interface clock frequency to be always (strictly) greater than the symbol rate: TS_SYNC TS_DATA DocID023557 Rev 10 135/604 Information classified Confidential - Do not copy (See last page for obligations) Front-end overview 9.17.2 STiH271EL Alternative parallel format The alternative parallel format offered by the demodulator clocks out exactly 188 or 204 bytes (user programmable) per MPEG/TS packet. Any data byte clocked out is either a valid MPEG/TS data byte or (optionally) a Reed-Solomon redundancy byte. In either case, the 188 valid data bytes of a given packet are clocked out in a row. See Figure 32 and Figure 33. TS_CKOUT in this mode is not continuous. It is an interrupted data clock with the same frequency on average as the byte frequency. This clock may be running during the 188 data bytes and the 16 parity bytes, or during the 188 valid data bytes only and be inactive during the 16 parity bytes (user programmable). No error Uncorrected packet ti a C_CLK_OUT with bit CT_NBST = 1 and bit CLK_POLARITY = 1 en with bit CT_NBST = 0 and bit CLK_POLARITY = 1 Confidential with bit CT_NBST = 1 and bit CLK_POLARITY = 0 C_DATA[7:0] 204 clock pulses 188 MPEG bytes on with bit CT_NBST = 1 fid with bit CT_NBST = 0 and bit CLK_POLARITY = 0 C_D_NOT_P C_ERROR C with bit CT_NBST = 0 C_STR_OUT with bit CT_NBST = 1 with bit CT_NBST = 0 136/604 DocID023557 Rev 10 16 parity bytes No error Information classified Confidential - Do not copy (See last page for obligations) l Figure 32. MPEG output waveforms in parallel mode according to configuration bits STiH271EL Front-end overview Figure 33. MPEG/TS output interface waveforms and timings in parallel mode (with CLK_POLARITY set to 0 tCLK CKEXT tP_M tCLK N x tCLK C_CLK_OUT tCLK C_DATA[7:0] 3 tCLK or more 3 tCLK or more C_D_NOT_P ti a l C_ERROR First byte of an MPEG packet 9.17.3 Serial format en fid Figure 34. MPEG output waveforms in serial mode according to configuration bits No error C_CLK_OUT Uncorrected packet No error on with bit CB_NBST = 1 and bit CLK_POLARITY = 1 with bit CB_NBST = 0 and bit CLK_POLARITY = 1 with bit CB_NBST = 1 and bit CLK_POLARITY = 0 C Confidential In this mode, the data is supplied as a serial bitstream on D[0] or D[7] and the clock on C_CLK_OUT is a bit clock (See Figure 34 and Figure 35). with bit CB_NBST = 0 and bit CLK_POLARITY = 0 204 x 8 = 1632 clock pulses C_D_NOT_P 188x8 = 1054 MPEG bits 16 x 8 = 128 parity bits D[0] with bit CB_NBST = 1 with bit CB_NBST = 0 C_STR_OUT Duration = 1 bit C_ERROR with bit CB_NBST = 1 with bit CB_NBST = 0 DocID023557 Rev 10 137/604 Information classified Confidential - Do not copy (See last page for obligations) C_STR_OUT Front-end overview STiH271EL Figure 35. MPEG/TS output interface waveforms and timings in serial mode CLK_POLARITY = 0 tSYNTH C_CLK_OUT CLK_POLARITY = 1 tCLK (programmable clock) b7 D[0] b6 b5 b1 b0 b7 b6 C_STR_OUT C_D_NOT_P C on fid Confidential en ti a l Possible gap First serialized byte of an MPEG/TS packet (8 consecutive bits) 138/604 DocID023557 Rev 10 2nd serialized byte Information classified Confidential - Do not copy (See last page for obligations) C_ERROR STiH271EL 10 Front-end registers Front-end registers Registers are accessed from the processor interface. All writable register bits are reset to 0 unless otherwise stated. Read-only registers have no defined reset value. The processor should not write 1s to undefined register bits. Similarly, when reading a register, the processor should mask undefined bits. All register addresses are hexadecimal values. Signed registers are 2's complement. Note: 1 Do not access registers that are not listed. 2 Address 0xF026 is a reserved address but must be set to 0x03. I2C address Register l Register summary table ti a Table 55. Description en 0xF000 ID * Chip identification page 150 0xF001 I2CRPT * I C repeater control page 150 0xF002 TOPCTRL * Top control page 151 0xF003 IOCFG0 0xF004 DAC0R 0xF005 IOCFG1 0xF006 DAC1R 0xF007 IOCFG2 0xF008 SDFR 0xF009 STATUS 0xF00A AUX_CLK * 0xF00B Reserved 0xF00D Input/output configuration 0 page 151 Sigma-delta DAC control 1 page 152 Input/output configuration 1 page 152 Sigma-delta DAC control 2 page 152 Input/output configuration 2 page 153 Sigma-delta frequency control page 153 Status page 154 Auxiliary clock control page 154 Reserved register - fid on C Confidential COFDM reception registers Page 0xF00E GPIO_CFG GPIO Configuration page 155 0xF00F GPIO_CMD GPIO Command page 155 0xF010 AGC_IFMAX AGC_IF maximum value page 156 0xF011 AGC_IFMIN AGC_IF minimum value page 156 0xF012 AGC_RFMAX AGC_RF maximum value page 156 0xF013 AGC_RFMIN AGC_RF minimum value page 156 0xF014 AGCR AGC ratio control page 157 0xF015 AGC_IFTH AGC 2 threshold value page 157 0xF016 AGC_RF_IF_C AGC RF and IF output control page 157 0xF017 AGCCTRL1 AGC control 1 page 158 DocID023557 Rev 10 139/604 Information classified Confidential - Do not copy (See last page for obligations) Registers marked with an asterisk (*) are addressable in the standby mode. Front-end registers Register summary table (continued) Register Description Page AGCCTRL2 AGC control 2 page 158 0xF019 AGC_RFVAL1 AGC_RF LSB value page 159 0xF01A AGC_RFVAL2 AGC_RF MSB value page 159 0xF01B AGC_IFVAL1 AGC_IF LSB value page 159 0xF01C AGC_IFVAL2 AGC_IF MSB value page 159 0xF01D Reserved Reserved register - 0xF01E OVF_RATE1 ADC LSB overflow rate value page 160 0xF01F OVF_RATE2 ADC MSB overflow rate value page 160 0xF020 GAIN_SRC1 Sample rate converter gain 1 page 160 0xF021 GAIN_SRC2 Sample rate converter gain 2 page 161 0xF022 INC_DEROT1 Derotator increment 1 page 161 0xF023 INC_DEROT2 Derotator increment 2 page 161 0xF024 PPM_CP_AMPL PPM continuous pilot amplitude page 161 0xF025 PPM_CP_AMPL_INV PPM continuous pilot amplitude with inverted spectrum page 162 0xF026 Reserved 0xF027 SYR_THR 0xF028 DC_OFFSET 0xF029 0xF030 Reserved 0xF031 DC_OFFSET 0xF032 EPQ_AUTO 0xF033 fid en ti a l 0xF018 - Symbol recovery threshold page 162 DC_OFFSET status page 162 Reserved register - Echo position quality page 162 Echo position quality for tracking loop page 163 SYR_TRACK_CTL SYR tracking configuration register page 163 0xF034 DYN_COEFF Dynamic coefficient status page 164 0xF036 INR Impulse noise removal page 164 0xF037 EPQ_DIS_TPS_ID_CELL Transmission parameter signaling page 164 0xF038 0xF039 Reserved Reserved register - 0xF03A AUTORELOCK Autorelock page 165 0xF03E CCD CCD register page 165 0xF03F Reserved Reserved register - 0xF05B INC_CTL inc_control page 166 0xF05C INC_THRES_COR1 inc_threscorr1 page 166 0xF05D INC_THRES_COR2 inc_threscorr2 page 166 0xF05E INC_THRES_DET1 inc_thres_det1 page 167 140/604 on Reserved register C Confidential I2C address DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 55. STiH271EL STiH271EL Register summary table (continued) Register Description Page inc_thres_det2 page 167 0xF060 IIR_CELL_NB IIR cell number page 167 0xF061 IIR_Cx_COEFF1_MSB IIR CELLx COEFF1 MSBs page 168 0xF062 IIR_Cx_COEFF1_LSB IIR CELLx COEFF1 LSBs page 168 0xF063 IIR_Cx_COEFF2_MSB IIR CELLx COEFF2 MSBs page 168 0xF064 IIR_Cx_COEFF2_LSB IIR CELLx COEFF2 LSBs page 169 0xF065 IIR_Cx_COEFF3_MSB IIR CELLx COEFF3 MSBs page 169 0xF066 IIR_Cx_COEFF3_LSB IIR CELLx COEFF3 LSBs page 169 0xF067 IIR_Cx_COEFF4_MSB IIR CELLx COEFF4 MSBs page 170 0xF068 IIR_Cx_COEFF4_LSB IIR CELLx COEFF4 LSBs page 170 0xF069 IIR_Cx_COEFF5_MSB IIR CELLx COEFF5 MSBs page 170 0xF06A IIR_Cx_COEFF5_LSB IIR CELLx COEFF5 LSBs page 171 0xF06B FEPATH_CFG Long path IF page 171 0xF06C PMC1_CFG PMC1 configuration page 171 0xF06E PMC2_CFG PMC2 configuration page 172 0xF06F STATUS_ERR_DA ZIF AGC lock status page 172 0xF070 DIG_AGC_RST Digital AGC reset configuration page 173 0xF071 COM_TARGET_MSB Digital I/Q common AGC target MSB value page 173 0xF072 COM_TARGET_LSB Digital I/Q common AGC target LSB value page 174 0xF073 COM_AGC_CFG Common AGC target configuration page 174 0xF074 COM_AGC_GAIN1 Common AGC gain1 parameters page 174 0xF075 AUT_AGC_TARGET_I/Q Autonomous AGC target I/Q MSB page 175 0xF076 LOCK_DETECT_N Lock_detect_n MSB page 175 0xF077 AUT_AGC_TARG_LOCK Autonomous AGC target I/Q & lock_detect_n LSBs page 175 0xF078 AUT_GAIN_EN Autonomous AGC target gain2 and enable page 176 0xF079 AUT_AGC_CFG Autonomous AGC configuration page 176 0xF07A LOCKN Lock_n and config for autonomous AGC target page 176 0xF07B INT_X_3 MSB of integrator status page 177 0xF07C INT_X_2 Upper middle bits of integrator status page 177 0xF07D INT_X_1 Lower middle bits of integrator status page 177 0xF07E INT_X_0 LSB of integrator status page 177 0xF07F COM_AUT_ERROR Common or autonomous error page 178 0xF080 COR_CTL Core control page 178 0xF081 COR_STAT Core status page 179 fid en ti a l INC_THRES_DET2 on 0xF05F C Confidential I2C address DocID023557 Rev 10 141/604 Information classified Confidential - Do not copy (See last page for obligations) Table 55. Front-end registers Front-end registers Register summary table (continued) Register Description Page COR_INTEN Core interrupt page 179 0xF083 COR_INTSTAT Core interrupt status page 180 0xF084 COR_MODEGUARD COFDM core mode guard page 180 0xF085 AGC_CTL AGC control page 181 0xF088 AGC_TARGET AGC target page 181 0xF089 AGC_GAIN1 AGC gain (LSB) page 182 0xF08A AGC_GAIN2 AGC gain (MSB) and control page 182 0xF08E CAS_CTL Co- and adjacent-channel suppressor (CAS) control page 182 0xF08F CAS_FREQ CAS center frequency page 183 0xF090 CAS_DAGCGAIN CAS digital AGC gain page 183 0xF091 SYR_CTL Symbol recovery (SYR) control page 183 0xF092 SYR_STAT Symbol recovery status page 184 0xF095 SYR_OFFSET1 Symbol recovery offset 1 page 184 0xF096 SYR_OFFSET2 Symbol recovery offset 2 page 185 0xF097 Reserved Reserved register - 0xF098 SCR_CTL Slope correction page 185 0xF099 PPM_CTL1 Pilot processing controller 1 page 186 0xF09A TRL_CTL Timing recovery loop 1 page 186 0xF09B TRL_NOMRATE1 Timing recovery loop (TRL) nominal rate 1 page 187 0xF09C TRL_NOMRATE2 TRL nominal rate 2 page 187 0xF09D TRL_TIME1 TRL time offset 1 page 187 0xF09E TRL_TIME2 TRL time offset 2 page 188 0xF09F CRL_CTL Carrier recovery loop control page 188 0xF0A0 CRL_FREQ1 Carrier recovery loop (CRL) frequency 1 page 188 0xF0A1 CRL_FREQ2 CRL frequency 2 page 189 0xF0A2 CRL_FREQ3 CRL frequency 3 page 189 0xF0A3 CHC_CTL1 Channel correction (CHC) control 1 page 189 0xF0A4 CHC_SNR CHC signal-to-noise ratio page 190 0xF0A5 BDI_CTL Bit de-interleaver (BDI) control page 190 0xF0A7 TPS_RCVD1 Transmission parameter signaling (TPS) received 1 page 190 0xF0A8 TPS_RCVD2v TPS received 2 page 191 0xF0A9 TPS_RCVD3 TPS received 3 page 191 0xF0AA TPS_RCVD4 TPS received 4 page 192 0xF0AB TPS_CELLID1 TPS cell identifier1 page 192 142/604 on fid en ti a l 0xF082 C Confidential I2C address DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 55. STiH271EL STiH271EL Register summary table (continued) I2C address Register Page TPS_CELLID2 TPS cell identifier2 page 192 0xF0AD TPS_RCVD5_SET1 TPS_reserved page 193 0xF0B0 TPS_CTL TPS control page 193 0xF0B1 CTL_FFTOSNUM Control FFT output symbol number page 193 0xF0B2 CAR_DISP_SEL Carrier display select page 194 0xF0B4 PIR_CTL PIR control page 194 0xF0B5 SNR_CARRIER1 SNR carrier 1 page 195 0xF0B6 SNR_CARRIER2 SNR carrier 2 page 195 ti a l 0xF0AC 0xF0B7 Reserved 0xF0C0 Reserved register - ANA_CTRL Analog control page 195 0xF0C2 Reserved Reserved register - 0xF0CB CONSTMODE Constellation mode page 196 0xF0CC CONSTCARR1 Constellation carrier LSB number page 196 0xF0CD CONSTCARR2 Constellation carrier MSB number 0xF0CE ICONSTEL 0xF0CF QCONSTEL 0xF0D4 RF_AGC 0xF0D5 EN_RF_AGC 0xF0D7 ANA_DIG_CTRL 0xF0D8 PLLMDIV 0xF0D9 PLLNDIV 0xF0DA PLLPDIV 0xF0DB ADC12 CFG page 196 I constellation page 197 Q constellation page 197 AGC RF page 197 AGC RF enable page 197 Analog/digital control page 198 PLLMDIV page 198 PLLxn NDIV page 198 PLLPDIV page 199 ADC12 configuration page 199 on fid en 0xF0C1 C Confidential Description COFDM reception super FEC 0xF248 VITSCALE Additional configuration of Viterbi decoder page 200 0xF233 FECM Viterbi decoder configuration page 201 0xF234 VTH12 Error threshold for puncture rate 1/2 page 201 0xF235 VTH23 Error threshold for puncture rate 2/3 page 201 0xF236 VTH34 Error threshold for puncture rate 3/4 page 202 0xF237 VTH56 Error threshold for puncture rate 5/6 page 202 0xF238 VTH67 Error threshold for puncture rate 6/7 page 202 0xF239 VTH78 Error threshold for puncture rate 7/8 page 202 0xF23A VITCURPUN Current puncture rate on the Viterbi decoder page 203 DocID023557 Rev 10 143/604 Information classified Confidential - Do not copy (See last page for obligations) Table 55. Front-end registers Front-end registers Register summary table (continued) Register Description Page VERROR Current error rate page 203 0xF23C PRVIT List of authorized puncture rates page 203 0xF23D VAVSRVIT Viterbi decoder search speeds page 204 0xF23E VSTATUSVIT Viterbi decoder status page 205 0xF23F VTHINUSE Viterbi threshold currently in use page 205 0xF240 KDIV12 Gain (k_divider) of puncture rate 1/2 page 205 0xF241 KDIV23 Gain (k_divider) of puncture rate 2/3 page 206 0xF242 KDIV34 Gain (k_divider) of puncture rate 3/4 page 206 0xF243 KDIV56 Gain (k_divider) of puncture rate 5/6 page 206 0xF244 KDIV67 Gain (k_divider) of puncture rate 6/7 page 207 0xF245 KDIV78 Gain (k_divider) of puncture rate 7/8 page 207 0xF270 TSSTATEM Configuration of Merger/HWare Stream line 1 page 207 0xF272 TSCFGH Configuration of Merger/HWare Stream line 1 page 208 0xF273 TSCFGM Configuration of Merger/HWare Stream line 1 page 209 0xF274 TSCFGL Configuration of Merger/HWare Stream line 1 page 209 0xF276 TSINSDELH Insertion/deletion mask of output packet parts page 210 0xF280 TSSPEED CLKOUT frequency page 211 0xF281 TSSTATUS Merger/HWare Stream status page 211 0xF282 TSSTATUS2 Additional status of Merger/HWare Stream page 212 0xF283 0xF284 TSBITRATEy Observation of raw bit rate page 212 0xF298 ERRCTRL1 Configuration of error counter 1 page 213 0xF299 ERRCNT12 Result of error counter 1 page 214 0xF29A ERRCNT11 Result of error counter 1 page 214 0xF29B ERRCNT10 Result of error counter 1 page 214 0xF29C ERRCTRL2 Configuration of error counter 2 page 215 0xF29D ERRCNT22 Result of error counter 2 page 215 0xF29E ERRCNT21 Result of error counter 2 page 215 0xF29F ERRCNT20 Result of error counter 2 page 216 0xF2A0 FECSPY FEC Spy Configuration page 216 0xF2A1 FSPYCFG FEC Spy Configuration page 216 0xF2A2 FSPYDATA Tested packet contents page 217 0xF2A3 FSPYOUT FEC Spy miscellaneous configuration page 219 0xF2A4 FSTATUS FEC Spy Status page 219 144/604 on fid en ti a l 0xF23B C Confidential I2C address DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 55. STiH271EL STiH271EL Register summary table (continued) I2C address Description FBERCPT4 BER/PER Meter byte counter page 220 0xF2A9 FBERCPT3 BER/PER Meter byte counter page 220 0xF2AA FBERCPT2 BER/PER Meter byte counter page 221 0xF2AB FBERCPT1 BER/PER Meter byte counter page 221 0xF2AC FBERCPT0 BER/PER Meter byte counter page 221 0xF2AD 0xF2AE 0xF2AF FBERERRy BER/PER Meter error bit counter page 222 0xF2B2 FSPYBER BER/PER Meter configuration page 222 0xF230 TSGENERAL General configuration of Merger/HWare Stream page 223 page 223 ti a 0xF2A8 QAM global registers CTRL_0 Control 0 0xF402 CTRL_1 Control 1 page 224 0xF403 CTRL_2 Control 2 page 224 0xF408 IT_STATUS1 IT status 1 page 225 0xF409 IT_STATUS2 0xF40A IT_EN1 0xF40B IT_EN2 0xF40C CTRL_STATUS QAM AGC registers on fid en 0xF401 IT status 2 page 226 IT enable 1 page 227 IT enable 2 page 228 CTRL status page 229 Main AGC control page 229 0xF410 QAM_AGC_CTL 0xF411 QAM_AGC_IF_CFG AGC IF configuration page 230 0xF412 QAM_AGC_RF_CFG AGC RF configuration page 230 0xF413 QAM_AGC_PWM_CFG PWM AGC configuration page 231 0xF414 QAM_AGC_PWR_REF_L Main AGC power level page 231 0xF415 QAM_AGC_PWR_REF_H Main AGC power level page 232 0xF416 QAM_AGC_RF_TH_L AGC RF threshold page 232 0xF417 QAM_AGC_RF_TH_H AGC RF threshold page 232 0xF418 QAM_AGC_IF_LTH_L AGC IF low threshold page 233 0xF419 QAM_AGC_IF_LTH_H AGC IF low threshold page 233 0xF41A QAM_AGC_IF_HTH_L AGC IF high threshold page 233 0xF41B QAM_AGC_IF_HTH_H AGC IF high threshold page 234 0xF41C QAM_AGC_PWR_RD_L AGC word read page 234 0xF41D QAM_AGC_PWR_RD_M AGC word read page 234 C Confidential Page l Register DocID023557 Rev 10 145/604 Information classified Confidential - Do not copy (See last page for obligations) Table 55. Front-end registers Front-end registers Table 55. STiH271EL Register summary table (continued) I2C address Register Description Page 0xF41E QAM_AGC_PWR_RD_H AGC word read page 235 0xF420 QAM_AGC_PWM_IFCMD_L PWM AGC IF command page 235 0xF421 QAM_AGC_PWM_IFCMD_H PWM AGC IF command page 235 0xF422 QAM_AGC_PWM_RFCMD_L PWM AGC RF command page 236 0xF423 QAM_AGC_PWM_RFCMD_H PWM AGC RF command page 236 IQDEM configuration page 237 0xF425 MIX_NCO_LL Mixer NCO constant page 237 0xF426 MIX_NCO_HL Mixer NCO constant page 238 0xF427 MIX_NCO_LH Mixer NCO constant page 238 0xF428 SRC_NCO_LL SRC NCO constant page 239 0xF429 SRC_NCO_LH SRC NCO constant page 239 0xF42A SRC_NCO_HL SRC NCO constant page 239 0xF42B SRC_NCO_HH SRC NCO constant page 240 0xF42C IQDEM_GAIN_SRC_L 0xF42D IQDEM_GAIN_SRC_H 0xF430 IQDEM_DCRM_CFG_LL 0xF431 IQDEM_DCRM_CFG_LH 0xF432 ti a en IQDEM SRC gain page 240 DCRM forced values page 241 DCRM forced values page 241 IQDEM_DCRM_CFG_HL DCRM forced values page 241 0xF433 IQDEM_DCRM_CFG_HH DCRM forced values page 242 0xF434 IQDEM_ADJ_COEFF0 Adjacent IIR filter coefficient page 242 0xF435 IQDEM_ADJ_COEFF1 Adjacent IIR filter coefficient page 242 0xF436 IQDEM_ADJ_COEFF2 Adjacent IIR filter coefficient page 243 0xF437 IQDEM_ADJ_COEFF3 Adjacent IIR filter coefficient page 243 0xF438 IQDEM_ADJ_COEFF4 Adjacent IIR filter coefficient page 243 0xF439 IQDEM_ADJ_COEFF5 Adjacent IIR filter coefficient page 244 0xF43A IQDEM_ADJ_COEFF6 Adjacent IIR filter coefficient page 244 0xF43B IQDEM_ADJ_COEFF7 Adjacent IIR filter coefficient page 244 0xF43C IQDEM_ADJ_EN Adjacent IIR filter enable page 245 0xF43D IQDEM_ADJ_AGC_REF Adjacent AGC reference page 245 All pass coefficients page 246 fid page 240 on IQDEM SRC gain QAM all-pass filter registers 0xF440 0xF441 0xF442 146/604 ALLPASSFILT(1)(2)(3) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) IQDEM_CFG l 0xF424 C Confidential QAM demod registers STiH271EL Register summary table (continued) Register Description Page ALLPASSFILT(4)(5)(6) All pass coefficients page 246 0xF4460 xF447 0xF448 ALLPASSFILT(7)(8)(9) All pass coefficients page 246 0xF4490 xF44A ALLPASSFILT(10)(11) All pass coefficients page 247 0xF450 TRL_AGC_CFG AGC configuration page 247 0xF454 TRL_LPF_CFG Loop filter configuration page 248 0xF455 TRL_LPF_ACQ_GAIN Loop filter acquisition gains page 248 0xF456 TRL_LPF_TRK_GAIN Loop filter tracking gains page 249 0xF457 TRL_LPF_OUT_GAIN Loop filter output gain page 249 0xF458 TRL_LOCKDET_LTH Lock detection low threshold page 250 0xF459 TRL_LOCKDET_HTH Lock detection high threshold page 250 0xF45A TRL_LOCKDET_TRGVAL Lock detection trigger value page 250 0xF460 FSM_STATE 0xF461 FSM_CTL 0xF462 FSM_STS 0xF463 FSM_SNR0_HTH 0xF464 FSM_SNR1_HTH 0xF465 FSM_SNR2_HTH 0xF466 FSM_SNR0_LTH 0xF467 en ti a l 0xF443 0xF444 0xF445 page 251 State machine state control page 251 State machine status page 252 State machine SNR0 high threshold page 252 State machine SNR1 high threshold page 253 State machine SNR2 high threshold page 253 State machine SNR0 low threshold page 253 FSM_SNR1_LTH State machine SNR1 low threshold page 254 0xF468 FSM_RCA_HTH State machine SNR EQA threshold page 254 0xF469 FSM_TEMPO State machine temporization page 254 0xF474 EQU_I_TESTTAP_L I tap test bus page 255 0xF475 EQU_I_TESTTAP_M I tap test bus page 255 0xF476 EQU_I_TESTTAP_H I tap test bus page 255 0xF477 EQU_TESTTAP_CFG Tap test bus configuration page 256 0xF478 EQU_Q_TESTTAP_L Q tap test bus page 256 0xF479 EQU_Q_TESTTAP_M Q tap test bus page 257 0xF47A EQU_Q_TESTTAP_H Q tap test bus page 257 0xF47B EQU_TAP_CTRL Tap control page 257 0xF47C EQU_CTR_CRL_CONTROL_L Carrier control signal page 258 0xF47D EQU_CTR_CRL_CONTROL_H Carrier control signal page 258 on fid State machine state C Confidential I2C address DocID023557 Rev 10 147/604 Information classified Confidential - Do not copy (See last page for obligations) Table 55. Front-end registers Front-end registers Register Description Page EQU_CTR_HIPOW_L Fractional part extraction of ATAN value page 259 0xF47F EQU_CTR_HIPOW_H Fractional part extraction of ATAN value page 259 0xF480 EQU_I_EQU_L I equalized page 259 0xF481 EQU_I_EQU_H I equalized page 260 0xF482 EQU_Q_EQU_L Q equalized page 260 0xF483 EQU_Q_EQU_H Q equalized page 260 0xF484 EQU_MAPPER Equalizer mapper control page 261 0xF485 EQU_SWEEP_RATE Sweep rate page 261 0xF486 EQU_SNR_LO SNR value 0xF487 EQU_SNR_HI SNR value 0xF488 EQU_GAMMA_LO Gamma value for error generation 0xF489 EQU_GAMMA_HI Gamma value for error generator page 263 0xF48A EQU_ERR_GAIN Gain for CRL2 and EQA page 263 0xF48B EQU_RADIUS Radius for the EQA in error generator page 263 0xF48C EQU_FFE_MAINTAP FFE main tap initial value page 264 0xF48E EQU_LEAKAGE Leakage period page 264 0xF48F EQU_FFE_MAINTAP_POS FFE main tap position value page 264 0xF490 EQU_GAIN_WIDE Wide mode gain for error generator page 265 0xF491 EQU_GAIN_NARROW Narrow mode gain for error generator page 265 0xF492 EQU_CTR_LPF_GAIN Carrier tracker LPF gain page 265 0xF493 EQU_CRL_LPF_GAIN Carrier recovery LPF gain page 266 0xF494 EQU_GLOBAL_GAIN Carrier global gain page 266 0xF495 EQU_CRL_LD_CFG Carrier recovery lock detect sensitivity page 267 0xF496 EQU_CRL_LD_VAL Carrier recovery values page 267 0xF497 EQU_CRL_LD_TFR Carrier recovery lock detect transfer page 268 0xF498 EQU_CRL_BISTH_LO Carrier recovery bisector threshold page 268 0xF499 EQU_CRL_BISTH_HI Carrier recovery bisector threshold page 268 0xF49A EQU_SWEEP_RANGE_LO Sweep range page 269 0xF49B EQU_SWEEP_RANGE_HI Sweep range page 269 0xF49C EQU_CRL_LIMITER CRL limiter page 269 0xF49D EQU_PNT_CFG0 Phase noise tracker configuration 0 page 270 0xF49E EQU_PNT_CFG1 Phase noise tracker configuration 1 page 270 Descrambler formatter page 271 on fid en ti a l 0xF47E C Confidential I2C address Register summary table (continued) page 262 page 262 page 262 QAM FEC A and C registers 0xF4A8 148/604 FEC_AC_CTRL_0 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 55. STiH271EL STiH271EL Register summary table (continued) Register Description Page FEC_AC_CTRL_1 De-interleaver depth page 272 0xF4AA FEC_AC_CTRL_2 De-interleaver and descrambler configuration page 272 0xF4AB FEC_AC_CTRL_3 De-interleaver sync detector page 273 0xF4AC FEC_STATUS_0 State machine status page 273 0xF4AE RS_COUNTER_0 Block counter LSB page 274 0xF4AF RS_COUNTER_1 Block counter MSB page 274 0xF4B0 RS_COUNTER_2 Corrected block counter LSB page 274 0xF4B1 RS_COUNTER_3 Corrected block counter MSB page 275 0xF4B2 RS_COUNTER_4 Uncorrected block counter LSB page 275 0xF4B3 RS_COUNTER_5 Uncorrected block counter MSB page 275 0xF4B4 BERT_0 Descrambler counter control page 276 0xF4B5 BERT_1 Bert configuration page 276 0xF4B6 BERT_2 Error counter LSB page 277 0xF4B7 BERT_3 Error counter MSB page 277 0xF4B8 OUTFORMAT_0 Output formatter 0 page 277 0xF4B9 OUTFORMAT_1 Output formatter 1 page 278 0xF4C0 TSMF_CTRL_0 TSMF selection page 278 0xF4C1 TSMF_CTRL_1 TSMF control page 279 0xF4C4 TS_ON_ID_0 TS identifier page 279 0xF4C5 TS_ON_ID_1 TS identifier page 280 0xF4C6 TS_ON_ID_2 ON identifier page 280 0xF4C7 TS_ON_ID_3 ON identifier page 280 0xF4C8 RE_STATUS_0 Receive status 0 page 281 0xF4C9 RE_STATUS_1 Receive status 1 page 281 0xF4CA RE_STATUS_2 Receive status 2 page 281 0xF4CB RE_STATUS_3 Receive status 3 page 282 0xF4CC TS_STATUS_0 TS status page 282 0xF4CD TS_STATUS_1 TS status page 282 0xF4CE TS_STATUS_2 TSMF general status page 283 0xF4CF TS_STATUS_3 TSMF interrupt page 283 0xF4D0 T_O_ID_0 TS identifier extracted from header page 284 0xF4D1 T_O_ID_1 TS identifier extracted from header page 284 0xF4D2 T_O_ID_2 Original network identifier extracted from header page 284 0xF4D3 T_O_ID_3 Original network identifier extracted from header page 285 on fid en ti a l 0xF4A9 C Confidential I2C address DocID023557 Rev 10 149/604 Information classified Confidential - Do not copy (See last page for obligations) Table 55. Front-end registers Front-end registers 10.1 STiH271EL COFDM reception registers ID Chip identification 7 6 5 4 3 2 1 0 CHIP_IDENT Address: 0xF000 Type: R Reset: 0x60 Description: See Section 9.1.5: IC bus repeater on page 111. ti a l [7:0] CHIP_IDENT: Gives the release number of the circuit to ensure software compatibility. I2CRPT 6 4 3 2 1 0 SCLT_DELAY SCLT_NOD STOP_ENABLE SDAT_NOD 0xF001 Type: RW Reset: 0x22 Description: See Section 9.1.5: IC bus repeater on page 111. fid Address: Register accessible in standby mode. on [7] I2CT_ON: I C repeater for tuner on: active high (default is inactive). [6:4] ENARPT_LEVEL[2:0]: Repeater subsampling ratio. Division factors are: 000: 128001: 64 010: 32011: 16 100: 8101: 4 110: 64111: 32 C Confidential 5 ENARPT_LEVEL en 7 I2CT_ON IC repeater control [3] SCLT_DELAY: Active high, ENARPT_LEVEL is applied on SCLT). [2] SCLT_NOD: Active high, emulates an open-drain on pin SCLT (default is open drain). [1] STOP_ENABLE: Active high, disables I C repeater at I C stop instruction (default: no hardware interrupt). [0] SDAT_NOD: Must be set to 0. 150/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Register accessible in standby mode. STiH271EL Front-end registers TOPCTRL Top control 7 6 5 4 3 2 1 0 STDBY STDBY_FEC STDBY_CORE QAM_COFDM TS_DIS DIR_CLK_216 TUNER_BB RESERVED Address: 0xF002 Type: RW Reset: 0x08 Description: Register accessible in standby mode. [7] STDBY: Active high, stops whole device except some I C registers. All output buffers fixed at 0. l [5] STDBY_CORE: Active high, stops COFDM core clock (and thus opens AGC loop). ti a [4] QAM_COFDM: 0: COFDM demodulator is selected1: QAM demodulator is selected [3] TS_DIS: Active high, puts TS outputs in high impedance. en [1] TUNER_BB: 1: COFDM demodulator is compatible with direct conversion tuners IOCFG0 6 5 OP0_VAL OP0_OD on 7 OP0_ fid [0] RESERVED 4 Input/output configuration 0 3 OP0_IV 2 1 0 OP0_DACVALUE[11:8] Address: 0xF003 Type: RW Reset: 0x80 Description: See Section 9.2: General-purpose input/output on page 112. C Confidential [2] DIR_CLK_216: Active high, forces the 216 MHz internal clocks to be the external one. [7] OP0_: 0: Selects behavior with OP0_DACVALUE 1: Selects static configuration on GPIO1 pad with OP0_VAL [6] OP0_VAL: Value to be output when in static configuration. Also depends on OP0_IV value. [5] OP0_OD: Active high, emulates an open-drain (default is push-pull). [4] OP0_IV: Active high, inverts output. [3:0] OP0_DACVALUE[11:8]: 2's complement format. value issued on GPIO1 pad when in behavior. DocID023557 Rev 10 151/604 Information classified Confidential - Do not copy (See last page for obligations) [6] STDBY_COFDM_FEC: Active high, stops COFDM FEC clock. Warning: nothing can be output from the bit de-interleaver module in this case. Front-end registers STiH271EL DAC0R Sigma-delta DAC control 1 7 6 5 4 3 2 1 0 OP0_DACVALUE[7:0] Address: 0xF004 Type: RW Reset: 0x00 Description: Input/output configuration 1 0xF005 Type: RW Reset: 0x00 Description: 4 OP1_IV 3 2 1 0 OP1_DACVALUE[11:8] See Section 9.2: General-purpose input/output on page 112. [7:6] RESERVED: Always set to 0. fid [5] OP1_OD: Active high, emulates an open-drain (default is otherwise push-pull). [4] OP1_IV: Active high, inverts output. on [3:0] OP1_DACVALUE[11:8]: 2's complement format. value issued on GPIO2 pad when in behavior. DAC1R 7 6 5 C Confidential Address: 5 OP1_OD ti a 6 RESERVED en 7 l IOCFG1 Address: 0xF006 Type: RW Reset: 0x00 Sigma-delta DAC control 2 4 3 2 1 OP1_DACVALUE[7:0] Description: [7:0] OP1_DACVALUE[7:0]: Associated with OP1_DACVALUE[11:8]in IOCFG1 (lower bits) 152/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [7:0] OP0_DACVALUE[7:0]: Associated with OP0_DACVALUE[11:8] in IOCFG0 (lower bits). STiH271EL Front-end registers IOCFG2 Input/output configuration 2 6 5 OP2_LOCKS_CONF 4 3 OP2_OD OP2_VAL 2 1 0 OP1_LOCKS_CONF Address: 0xF007 Type: RW Reset: 0x00 Description: See Section 9.2: General-purpose input/output on page 112 l [7:5] OP2_LOCKS_CONF[2:0]: lock indicator output on GPIO3: 000: AGC_LOCK001: SYR_LOCK (symbol recovery) 010: TPS_LOCK011: puncture rate found in Viterbi decoder 100: de-interleaver locked (SYN_LOCK)101: COFDM core interrupt (see COR_INTEN) 110: scattered pilots found (SCAT_LOCK)111: OP2_VAL ti a [4] OP2_OD: Active high, emulates an open drain (default is otherwise push-pull). SDFR 7 6 5 Address: 0xF008 Type: RW Reset: 0x00 Description: 4 Sigma-delta frequency control 3 2 1 0 GPIO2_FREQ on GPIO1_FREQ fid en [2:0] OP1_LOCK_CONF[2:0]: Lock indicator output on GPIO2: 000: AGC_LOCK001: SYR_LOCK (symbol recovery) 010: TPS_LOCK011: puncture rate found in Viterbi decoder 100: de-interleaver locked (SYN_LOCK)101: COFDM core active 110: scattered pilots found (SCAT_LOCK)111: OP1_ C Confidential [3] OP2_VAL: Value to be output in static configuration. Sigma delta relative frequency: selects the frequency of the minimum pulse width (quantum) for the outputs. See Section 9.2: General-purpose input/output on page 112. [7:4] OP0_FREQ[3:0]. Sigma delta frequency for the GPIO1 port [3:0] OP1_FREQ[3:0]. Sigma delta frequency for the GPIO2 port. DocID023557 Rev 10 153/604 Information classified Confidential - Do not copy (See last page for obligations) 7 Front-end registers STiH271EL STATUS Status 7 6 5 4 3 TPS_LOCK SYR_LOCK AGC_LOCK PRF LK Address: 0xF009 Type: R Description: 2 1 0 RESERVED See Section 9.8.1: Viterbi decoder and synchronization on page 121, and Section 9.8.2: Synchronization on page 122. [7] TPS_LOCK: TPS locked information [6] SYR_LOCK: Symbol recovery loop is locked l [4] PRF: Puncture rate found in Viterbi decoder ti a [3] LK: De-interleaver locked (sync byte found at RS block input) AUX_CLK 6 5 4 RESERVED 0xF00A Type: RW Reset: 0x00 Auxiliary clock control 2 1 CKDIV_PROG fid Address: [7:5] RESERVED [4:3] CKSEL[1:0]: Division of either clock XTAL, STDBY, FEC, COFDM: 00: XTAL clock01: COFDM core clock (PLLx2) 10: FEC clock (PLLx4)11: STAND-BY clock (PLLx2) [2:1] CKDIV_PROG[1:0]: Division rate choice from selected clock: 00: division by 1 01: division by 2 10: division by 4 11: division by 8 [0] AUXCLK_ENA: Enables auxiliary clock output. 154/604 0 AUXCLK_ENA Register accessible in standby mode. See Section 9.5.3: Auxiliary clock output on page 115. on Description: 3 CKSEL C Confidential 7 en [2:0] RESERVED DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [5] AGC_LOCK: Automated gain control is locked STiH271EL Front-end registers GPIO_CFG GPIO Configuration 7 6 5 4 3 2 1 0 GPIO7_OD GPIO7_CFG GPIO6_OD GPIO6_CFG GPIO5_OD GPIO5_CFG GPIO4_OD GPIO4_CFG Address: 0xF00E Type: RW Reset: 0x55 Description: ti a [5] GPIO6_OD: 0: Emulates push-pull1: Emulates open-drain l [6] GPIO7_CFG: o: Emulates a GP output1: Emulates a GP input [4] GPIO6_CFG: o: Emulates a GP output1: Emulates a GP input Confidential en [3] GPIO5_OD: 0: Emulates push-pull1: Emulates open-drain fid [2] GPIO5_CFG: o: Emulates a GP output1: Emulates a GP input [1] GPIO4_OD: 0: Emulates push-pull1: Emulates open-drain on [0] GPIO4_CFG: o: Emulates a GP output1: Emulates a GP input 7 6 C GPIO_CMD 5 GPIO Command 4 RESERVED Address: 0xF00F Type: RW Reset: 0x00 3 2 1 0 GPIO7_VAL GPIO6_VAL GPIO5_VAL GPIO4_VAL Description: [7:4] RESERVED: always set to 0. [3] GPIO7_VAL: When the GPIO7_CFG bit is 1, GPIO7 pin is configured by GPIO7_VAL, else GPIO7_VAL gives GPIO7 status. [2] GPIO6_VAL: When the GPIO6_CFG bit is 1, GPIO6 pin is configured by GPIO6_VAL, else GPIO6_VAL gives GPIO6 status. [1] GPIO5_VAL: When the GPIO5_CFG bit is 1, GPIO5 pin is configured by GPIO5_VAL, else GPIO5_VAL gives GPIO5 status. [0] GPIO4_VAL: When the GPIO4_CFG bit is 1, GPIO4 pin is configured by GPIO4_VAL, else GPIO4_VAL gives GPIO4 status. DocID023557 Rev 10 155/604 Information classified Confidential - Do not copy (See last page for obligations) [7] GPIO7_OD: 0: Emulates push-pull1: Emulates open-drain Front-end registers STiH271EL AGC_IFMAX 7 AGC_IF maximum value 6 5 4 3 2 1 0 AGC_IFMAX Address: 0xF010 Type: RW Reset: 0x00 Description: The value of the AGC_IF can be limited to AGC_IFMAX. No flag when the limits are reached. AGC_IFMAX can be read to determine if AGC_IF is at maximum or minimum. See Dual control point AGC for COFDM reception on page 116. 6 5 ti a 7 AGC_IF minimum value l AGC_IFMIN 4 3 2 1 0 0xF011 Type: RW Reset: 0x00 See Dual control point AGC for COFDM reception on page 116. [7:0] AGC_IFMIN[7:0]. 7 6 on AGC_RFMAX 5 fid Description: en Address: AGC_RF maximum value 4 3 2 1 0 AGC_RFMAX Address: 0xF012 Type: RW Reset: 0x00 Description: See Dual control point AGC for COFDM reception on page 116. C Confidential AGC_IFMIN [7:0] AGC_RFMAX[7:0]. AGC_RFMIN 7 AGC_RF minimum value 6 5 4 3 2 AGC_RFMIN Address: 0xF013 Type: RW Reset: 0x00 Description: See Dual control point AGC for COFDM reception on page 116. [7:0] AGC_RFMIN[7:0]. 156/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:0] AGC_IFMAX[7:0]. STiH271EL Front-end registers AGCR AGC ratio control 7 6 5 4 3 RATIO_A 2 1 RATIO_B 0 RATIO_C Address: 0xF014 Type: RW Reset: 0x00 Description: See Dual control point AGC for COFDM reception on page 116. [7:5] RATIO_A l [2:0] RATIO_C 7 6 5 ti a AGC_IFTH 4 3 AGC 2 threshold value 2 1 0 0xF015 Type: RW Reset: 0x00 Description: See Dual control point AGC for COFDM reception on page 116. fid en Address: AGC_RF_IF_C 7 6 AGC_RF_IV AGC_RF_OD on [7:0] AGC_IF_THRES[7:0]: Take-over point for AGC_RF start. AGC RF and IF output control 5 4 3 2 AGC_RF_LOAD AGC_IF_IV AGC_IF_OD AGC_IF_LOAD Address: 0xF016 Type: RW Reset: 0x49 Description: See AGC pins configuration for COFDM reception on page 117. 1 0 RESERVED C Confidential AGC_IF_THRES [7] AGC_RF_IV: Active high, inverts AGC_RF slope. [6] AGC_RF_OD: Active high, emulates an open-drain output on AGC_RF. [5] AGC_RF_LOAD: Active high, soft resetting AGC_RF loop. [4] AGC_IF_IV: Active high, inverts AGC_IF slope. [3] AGC_IF_OD: Active high, emulates an open-drain output on AGC_IF. [2] AGC_IF_LOAD: Active high, soft resetting AGC_IF loop. [1:0] RESERVED: Always set to 1. DocID023557 Rev 10 157/604 Information classified Confidential - Do not copy (See last page for obligations) [4:3] RATIO_B Front-end registers STiH271EL AGCCTRL1 7 AGC control 1 6 5 DAGC_ON 4 RESERVED Address: 0xF017 Type: RW Reset: 0x00 Description: 3 2 AGC_RF_MODE 1 0 AGC_IF_MODE Control of AGC_RF and AGC_IF of the dual AGC. The AGC may be fixed during symbols. It is updated each time the symbols are changed. See Section 9.6.3: Automatic gain control for COFDM reception on page 116. l [6:4] RESERVED: always set to 0. ti a [3] AGC_RF_MODE: loop or software control for RF: 0: AGC loop1: Software control 6 5 FRZ2_CTRL 0xF018 Type: RW Reset: 0x00 Description: AGC control 2 3 FRZ1_CTRL 2 1 See Section 9.6.4: ADC overflow rate control for COFDM reception on page 117 and Section 9.6.3: Automatic gain control for COFDM reception on page 116. [7] RESERVED: Always set to 0. [6:5] FRZ2_CTRL: Freezes AGC_IF gain: 00: No freeze 01: AGC rate is frozen as soon as AGC loop locks. 10: AGC rate is frozen as soon as AGC loop locks and unfreeze as soon as it unlocks. 11: AGC rate is immediately frozen. [4:3] FRZ1_CTRL: Freezes AGC_RF gain: 00: No freeze 01: AGC rate is frozen as soon as AGC loop locks. 10: AGC rate is frozen as soon as AGC loop locks and unfreeze as soon as it unlocks. 11: AGC rate is immediately frozen. [2:0] TIME_CST: ADC overflow rate time constant value: 000: 3 s001: 6 s 010: 12 s011: 24 s 100: 48 s101: 96 s 110: 192 s111: 384 s 158/604 0 TIME_CST on Address: 4 fid 7 RESERVED en AGCCTRL2 C Confidential [2:0] AGC_IF_MODE[2:0]: loop or software control for IF: 010: AGC loop011: Software control Other values reserved. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7] DAGC_ON: Active high, it selects dual AGC operating mode. STiH271EL Front-end registers AGC_RFVAL1 7 AGC_RF LSB value 6 5 4 3 2 1 0 AGC_RF_VAL[7:0] Address: 0xF019 Type: RW Reset: 0x00 Description: See Section 9.6.3: Automatic gain control for COFDM reception on page 116. 6 5 4 3 ti a 7 AGC_RF MSB value 0xF01A Type: RW Reset: 0x00 Description: 1 0 en Address: 2 AGC_RF_VAL[11:8] See Section 9.6.3: Automatic gain control for COFDM reception on page 116. [3:0] AGC_RF_VAL[11:8] AGC_IFVAL1 6 5 Address: 0xF01B Type: RW Reset: 0xFF Description: on 7 fid [7:4] RESERVED: Always set to 0. 4 AGC_IF LSB value 3 2 1 0 AGC_IF_VAL[7:0] C Confidential RESERVED l AGC_RFVAL2 See Section 9.6.3: Automatic gain control for COFDM reception on page 116. [7:0] AGC_IF_VAL[7:0] AGC_IFVAL2 7 AGC_IF MSB value 6 5 4 3 RESERVED 2 1 0 AGC_IF_VAL[11:8] Address: 0xF01C Type: RW Reset: 0x0F Description: See Section 9.6.3: Automatic gain control for COFDM reception on page 116. [7:4] RESERVED: Always set to 0. [3:0] AGC_IF_VAL[11:8] DocID023557 Rev 10 159/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] AGC_RF_VAL[7:0] Front-end registers STiH271EL OVF_RATE1 7 ADC LSB overflow rate value 6 5 4 3 2 RESERVED 1 0 OVF_RATE[11:8] Address: 0xF01E Type: R Description: See Section 9.6.4: ADC overflow rate control for COFDM reception on page 117. [7:4] RESERVED 6 5 4 3 2 1 0 ti a 7 ADC MSB overflow rate value l OVF_RATE2 OVF_RATE[7:0] 0xF01F Type: R Description: See Section 9.6.4: ADC overflow rate control for COFDM reception on page 117. en Address: INR_BYPASS on 4 3 2 1 0 GAIN_SRC[11:8] 5 Sample rate converter gain 1 STATUS_INV_SPECT 6 ZIF_SPECINV 7 fid GAIN_SRC1 DER_INV_SPECTR Address: 0xF020 Type: RW Reset: 0xFA Description: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120. C Confidential [7:0] OVF_RATE[7:0]. [7] DER_INV_SPECTR: Spectrum inversion in derotator block. [6] ZIF_SPECINV: Spectrum inversion in Zif mode [5] INR_BYPASS: When set, bypasses impulsive noise removal module. [4] STATUS_INV_SPECT: Status concerning spectrum inversion. [3:0] GAIN_SRC[11:8]: GAINSRC = 212 * (4 160/604 (64 / 7) DocID023557 Rev 10 (BW / 8)) / fCOFDM/ Information classified Confidential - Do not copy (See last page for obligations) [3:0] OVF_RATE[11:8]. STiH271EL Front-end registers GAIN_SRC2 7 Sample rate converter gain 2 6 5 4 3 2 1 0 GAIN_SRC[7:0] Address: 0xF021 Type: RW Reset: 0xD6 Description: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120. 6 5 4 3 2 1 0 ti a 7 Derotator increment 1 l INC_DEROT1 0xF022 Type: RW Reset: 0x55 Description: en Address: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120 INC_DEROT2 7 6 5 fid [7:0] INC_DEROT[15:8]: INCDEROT = 216 4 ((fCOFDM) - fIF) / (fCOFDM) Derotator increment 2 3 2 1 0 on INC_DEROT[7:0] Address: 0xF023 Type: RW Reset: 0x45 Description: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120. C Confidential INC_DEROT[15:8] [7:0] INC_DEROT[7:0]. PPM_CP_AMPL 7 6 PPM continuous pilot amplitude 5 4 3 2 1 0 PPM_CONT_PILOT_CORR_AMP Address: 0xF024 Type: R Description: [7:0] PPM_CONT_PILOT_CORR_AMP: this value is the output of the PPM continuous pilot correlator. During continuous pilot correlation, it holds the peak value detected. At the end of scattered pilot correlation, it shows the peak value detected, and during normal operation, it shows the running measurement of the continuous pilot correlation. A value below 20 (2K), 40 (4K) or 80 (8K) indicates that the COFDM signal has probably disappeared, or is extremely noisy. A peak of 42 (2K), 84 (4K) or 176 (8K) is attained with a perfect signal. DocID023557 Rev 10 161/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] GAIN_SRC[7:0] Front-end registers STiH271EL PPM_CP_AMPL_INV 7 6 PPM continuous pilot amplitude with inverted spectrum 5 4 3 2 1 0 PPM_CONT_PILOT_CORR_AMP_INV_SPECT Address: 0xF025 Type: R ti a l [7:0] PPM_CONT_PILOT_CORR_AMP_INV_SPECT: this value is the output of the PPM continuous pilot correlator. During continuous pilot correlation, it holds the peak value detected. At the end of scattered pilot correlation, it shows the peak value detected, and during normal operation, it shows the running measurement of the continuous pilot correlation. A value below 20 (2K), 40 (4K) or 80 (8K) indicates that the COFDM signal has probably disappeared, or is extremely noisy. A peak of 42 (2K), 84 (4K) or 176 (8K) is attained with a perfect signal. SYR_THR 6 5 4 RESERVED 2 1 0 SYR_THR 0xF027 Type: RW Reset: 0x5A Description: See Section 9.7.7: Symbol timing /recovery on page 120. fid Address: [7:5] RESERVED: must be set to 000. (Reset value: 010). on [4:0] SYR_THR[4:0]: Threshold in order to recover the correct guard. If correlation result is higher than threshold then the guard is updated only during acquisition phase. DC_OFFSET 7 6 I/Q_SEL C Confidential 3 en 7 Symbol recovery threshold DC_OFFSET status 5 4 3 2 DC_OFFSET_STATUS[8:2] Address: 0xF028 Type: R Reset: 0x00 Description: See Section 9.7.7: Symbol timing /recovery on page 120. [7:5] I/Q_SEL: 0: I DC_OFFSET_STATUS is selected 1: Q DC_OFFSET_STATUS is selected [4:0] DC_OFFSET_STATUS[8:2]: 162/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL Front-end registers EPQ Echo position quality 7 6 5 4 3 2 1 0 ECHO_POSITION_QUALITY Address: 0xF031 Type: R Description: 6 5 4 3 2 1 0 ti a 7 Echo position quality for tracking loop l EPQ_AUTO ECHO_POSITION_QUALITY 0xF032 Type: R en Address: SYR_TRACK_CTL 6 5 TRACK_ADJ_GAIN[2:0] Address: 0xF033 Reset: 0x00 Description: on 7 fid [7:0] ECHO_POSITION_QUALITY: Best possible status achievable of echo position quality for tracking loop. The typical values are 4/6 in 2K mode and 17/25 in 8K mode when the value of SYR_CTL is correct, and 8 (2K) and 35 (8K) when the value of SYR_CTL is not correct. 4 TRACK_FILTERS SYR tracking configuration register 3 2 TRACK_THRESHOLD 1 0 RESERVED TRACK_DISABLE C Confidential Description: [7:5] TRACK_ADJ_GAIN[2:0]: Gain to adjust tracking position [4] TRACK_FILTER: Selection for tracking filter table [3:2] TRACK_THRESHOLD: Threshold factor: 00: 101: 1/2 10: 111: Reserved [1]] RESERVED: Always set to 0. [0] TRACK_DISABLE: Set to disable tracking of the symbol timing position in the SYR. DocID023557 Rev 10 163/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] ECHO_POSITION_QUALITY: Status of echo position quality. The typical values are 4/6 in 2K mode and 17/25 in 8K mode when the value of SYR_CTL is correct, and 8 (2K) and 35 (8K) when the value of SYR_CTL is not correct. Front-end registers STiH271EL DYN_COEFF 7 Dynamic coefficient status 6 5 4 3 2 1 0 DYN_COEFF[7:0] Address: 0xF034 Type: R Description: [7:0] DYN_COEFF: Impulse noise removal 7 6 5 4 3 2 1 0 l 0xF036 Type: RW Reset: 0xFF Description: See Section 9.7.1: Impulsive noise rejection (INR) and canceller on page 118. en ti a Address: EPQ_DIS_TPS_ID_CELL 6 5 4 EPQ_DIS_TPS_CELL_ID 3 Address: 0xF037 Type: RW Reset: 0x09 2 1 0 RESERVED C on ENABLE_CELL_ID_TO_BCH 7 fid [7:0] INR[7:0]: Best results are normally obtained with a value between 0xF0 and 0xFE. The function is enabled when INR_BYPASS is zero (GAIN_SRC1). Note: the reset value 0xFF should not be used. ENABLE_LENGTH_TO_CF Confidential INR Description: [7] ENABLE_LENGTH_TO_CFG: 0: Suppress TPS length indicator, TPS Frame number and TPS configuration (constellation, Hierarchy, code rates, Guard Interval, transmission mode) for EPQ auto algorithm. Recommended settings: 0x1 [6:4] ENABLE_CELL_ID_TO_BCH: 0: Suppress TPS reserved, TPS cell id and TPS BCH for EPQ auto algorithm. Recommended settings: 0x0 [3:0] RESERVED: Always set to 0x9 164/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) INR STiH271EL Front-end registers AUTORELOCK 3 Address: 0xF03A Type: RW Reset: 0x00 2 1 ti a l Description: 0 [7:4] RESERVED [3] BYPASS_COFDM_TEMPO: Set to disable bypass auto-relock feature. 5 2 0xF03E Type: RW Reset: 0x00 RESERVED on fid 3 1 0 C Address: Description: 4 CCD register CCD_THRESHOLD[3:0] 6 CCD_DETECTED_RESET 7 en CCD CCD_DETECTED Confidential [2:0] OFDM_FACTOR_TEMPO: Factor to adjust auto-relock tempo [7] CCD_DETECTED: 0: No CCD detected1: CCD detected [6] CCD_DETECTED_RESET: 0: Freeze CCD_DETECTED if 11: CCD_DETECTED set to 0 [5:4] RESERVED [3:0] CCD_THRESHOLD: Multiplication factor for threshold detection DocID023557 Rev 10 165/604 Information classified Confidential - Do not copy (See last page for obligations) 4 OFDM_FACTOR_TEMPO 5 BYPASS_OFDM_TEMPO 6 RESERVED 7 Autorelock Front-end registers STiH271EL INC_CTL 7 Inc control 6 5 INC_BYPASS 4 3 RESERVED Address: 0xF05B Type: RW Reset: 0x05 2 1 0 INC_NDEPTH INC_MADEPTH Description: [7] INC_BYPASS: 0: INC acting1: bypass 5 4 3 2 1 0 INC_THRES_CORR1 0xF05C Type: RW Reset: 0x60 Description: on Address: Value 1 for comparison for decision in the inc block [7:0] INC_THRES_CORR1 INC_THRES_COR2 7 6 inc_threscorr2 5 4 3 INC_THRES_CORR2 Address: 0xF05D Type: RW Reset: 0x50 Description: Value 2 for comparison for decision in the inc block. [7:0] INC_THRES_CORR2 166/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) 6 Inc threscorr1 fid 7 en INC_THRES_COR1 C Confidential [1:0] INC_MADEPTH: Depth for MAfilter 11: 4 00: 8 01: 1610: 32 ti a [3:2] INC_NDEPTH: depth for filter1 (1) 11: 4 00: 8 01: 1610: 32 l [6:4] RESERVED STiH271EL Front-end registers INC_THRES_DET1 7 inc_thres_det1 6 5 4 3 RESERVED Address: 0xF05E Type: RW Reset: 0x0E Description: 2 1 0 INC_THRES_DET1 The averaging block on the lowest branch computes a reference level which is multiplied by a factor thresholdDetector1 [7:6] RESERVED 7 6 5 ti a INC_THRES_DET2 4 3 1 0 0xF05F Type: RW Reset: 0x14 en Address: Description: 2 INC_THRES_DET2 fid The averaging blocks works the same way as for the first detector: it updates the output every 2048 samples. The multiplicative factor n is called in thresholdDetector2. [7:6] RESERVED on [5:0] INC_THRES_DET2: Multiplication factor for reference level 6 C 5 Address: 0xF060 Type: RW Reset: 0x00 4 3 RESERVED 7 IIR cell number 2 1 0 IIR_CELL_NB IIR_CELL_NB RESET_IIR_FILTER Confidential RESERVED inc_thres_det2 Description: [7] RESET_IIR_FILTER: active high. [6:3] RESERVED. [2:0] IIR_CELL_NB: determines coefficients of which cell are in IIR_Cx_COEFFx IIR_CELL_NB: 000: cell1001: cell2 010: cell3011: cell4 100: cell5101: cell6 11x: unused DocID023557 Rev 10 167/604 Information classified Confidential - Do not copy (See last page for obligations) l [5:0] INC_THRES_DET1: Multiplication factor for reference level Front-end registers STiH271EL IIR_Cx_COEFF1_MSB 7 6 IIR CELLx COEFF1 MSBs 5 4 3 2 1 0 IIR_Cx_COEFF1_MSB[7:0] Address: 0xF061 Type: RW Reset: 0x10 for cell1; 0x21 for cell2; 0x25 for cell3; 0x20 for cell4; 0x06 for cell5; 0x00 for cell6 Description: 6 5 ti a 7 IIR CELLx COEFF1 LSBs l IIR_Cx_COEFF1_LSB 4 3 2 1 0 0xF062 Type: RW Reset: en Address: 0xEF for cell1; 0x51 for cell2; 0x03 for cell3; 0xE9 for cell4; 0xEF for cell5; 0x00 for cell6 fid Description: IIR_Cx_COEFF2_MSB 7 6 5 Address: 0xF063 Type: RW Reset: on [7:0] IIR_CELLx_COEFF1_LSB: Coefficients depending on internal frequency (default value 54 MHz). IIR CELLx COEFF2 MSBs 4 3 2 1 0 IIR_Cx_COEFF2_MSB[7:0] C Confidential IIR_Cx_COEFF1_LSB[7:0] 0xE2 for cell1; 0xC5 for cell2; 0xC0 for cell3; 0xCA for cell4; 0xF8 for cell5; 0x0E for cell6 Description: [7:0] IIR_CELLx_COEFF2_MSB: Coefficients depending on internal frequency (default value 54 MHz). 168/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] IIR_CELLx_COEFF1_MSB: Coefficients depending on internal frequency (default value 54 MHz). STiH271EL Front-end registers IIR_Cx_COEFF2_LSB 7 6 IIR CELLx COEFF2 LSBs 5 4 3 2 1 0 IIR_Cx_COEFF2_LSB[7:0] Address: 0xF064 Type: RW Reset: 0x05 for cell1; 0x57 for cell2; 0x00 for cell3; 0x94 for cell4; 0x52 for cell5; 0xCC for cell6 Description: 6 5 ti a 7 l IIR_Cx_COEFF3_MSB 4 3 IIR CELLx COEFF3 MSBs 2 1 0 0xF065 Type: RW Reset: en Address: 0x10 for cell1; 0x21 for cell2; 0x25 for cell3; 0x20 for cell4; 0x06 for cell5; 0x0E for cell6 fid Description: IIR_Cx_COEFF3_LSB 7 6 5 Address: 0xF066 Type: RW Reset: on [7:0] IIR_CELLx_COEFF3_MSB: Coefficients depending on internal frequency (default value 54 MHz). IIR CELLx COEFF3 LSBs 4 3 2 1 0 IIR_Cx_COEFF3_LSB[7:0] C Confidential IIR_Cx_COEFF3_MSB[7:0] 0xEF for cell1; 0x51 for cell2; 0x03 for cell3; 0xE9 for cell4; 0xEF for cell5; 0xCC for cell6 Description: [7:0] IIR_CELLx_COEFF3_LSB: Coefficients depending on internal frequency (default value 54 MHz). DocID023557 Rev 10 169/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] IIR_CELLx_COEFF2_LSB: Coefficients depending on internal frequency (default value 54 MHz). Front-end registers STiH271EL IIR_Cx_COEFF4_MSB 7 6 IIR CELLx COEFF4 MSBs 5 4 3 2 1 0 IIR_Cx_COEFF4_MSB[7:0] Address: 0xF067 Type: RW Reset: 0x67 for cell1; 0xC7 for cell2; 0xC3 for cell3; 0xC1 for cell4; 0xC0 for cell5; 0x00 for cell6 Description: 6 5 ti a 7 IIR CELLx COEFF4 LSBs l IIR_Cx_COEFF4_LSB 4 3 2 1 0 0xF068 Type: RW Reset: en Address: 0x49 for cell1; 0xD5 for cell2; 0x75 for cell3; 0x54 for cell4; 0x57 for cell5; 0x00 for cell6 fid Description: IIR_Cx_COEFF5_MSB 7 6 5 Address: 0xF069 Type: RW Reset: on [7:0] IIR_CELLx_COEFF$_LSB: Coefficients depending on internal frequency (default value 54 MHz). IIR CELLx COEFF5 MSBs 4 3 2 1 0 IIR_Cx_COEFF5_MSB[7:0] C Confidential IIR_Cx_COEFF4_LSB[7:0] 0x6D for cell1; 0x6F for cell2; 071 for cell3; 0x71 for cell4; 0x72 for cell5; 0x36 for cell6 Description: [7:0] IIR_CELLx_COEFF5_MSB: Coefficients depending on internal frequency (default value 54 MHz). 170/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] IIR_CELLx_COEFF4_MSB: Coefficients depending on internal frequency (default value 54 MHz). STiH271EL Front-end registers IIR_Cx_COEFF5_LSB 7 IIR CELLx COEFF5 LSBs 6 5 4 3 2 1 0 IIR_Cx_COEFF5_LSB[7:0] Address: 0xF06A Type: RW Reset: 0xA7 for cell1; 0x93 for cell2; 0x94 for cell3; 0x94 for cell4; 0x07 for cell5; 0x47 for cell6 Description: 6 5 ti a 7 4 3 RESERVED 0xF06B Type: RW Reset: 0x00 2 1 0 DEMUX_SWAP RESERVED LONG_PATH_IF en Address: fid Description: [7:3] RESERVED [2] DEMUX SWAP: Active 1, I/Q permutation [1] RESERVED on [0] LONG_PATH_IR: Active 1, enable the path through front-end digital filter and AGC PMC1_CFG 7 6 RESERVED C Confidential Long path IF l FEPATH_CFG Address: 0xF06C Type: RW Reset: 0x25 5 PMC1 configuration 4 3 PMC1_AVERAGE_TIME 2 1 PMC1_WAIT_TIME 0 PMC_SEL Description: [7] RESERVED [6:3] PMC1_AVERAGE_TIME: 0000: 4 symbols for accumulation0001: 8 symbols for accumulation 0010: 16 symbols for accumulation0011: 32 symbols for accumulation 0100: 64 symbols for accumulation0101: 128 symbols for accumulation 0110: 256 symbols for accumulation0111: 512 symbols for accumulation 1000: 1024 symbols for accumulation1001: 2048 symbols for accumulation 1010: 4096 symbols for accumulation1011: 8192 symbols for accumulation 1100: 16384 symbols for accumulation1101: 32768 symbols for accumulation 111x: unused DocID023557 Rev 10 171/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] IIR_CELLx_COEFF5_LSB: Coefficients depending on internal frequency (default value 54 MHz). Front-end registers STiH271EL [2:1] PMC1_WAIT_TIME: Number of symbols before count again: 00: 4 symbols01: 8 symbols 10: 16 symbols11: 32symbols [0] PMC_SEL: 0: PMC2 is selected1: PMC1 is selected PMC2_CFG 5 4 3 PMC2_ACCU-TIME 0xF06E Type: RW Reset: 0x00 1 0 RESERVED l Address: 2 PMC2_CMDP_M Description: en [6:4] PMC2_ACCU-TIME: 000: 65536001: 131072 010: 262144011: 524288 100: 1048576101 to 111: 65536 fid [3] PMC2_CMDP_M: 0: pmc2_cmd_m is selected1: pmc2_cmdp is selected [2:0] RESERVED. Address: 0xF06F Type: R Reset: 0x00 4 PMC2 configuration 3 2 1 0 RESERVED AUT_AGCLOCK 5 C 6 COM_AGCLOCK 7 on STATUS_ERR_DA COM_USEGAIN_TRK Confidential [7] PMC2_RESET: PMC2 software reset, active low. Description: [7] COM_USEGAIN_TRK: Status in ZIF mode in order to set the common AGC gain applied during tracking [6] COM_AGCLOCK: Set when the common AGC is locked (only in ZIF mode). [5] AUT_AGCLOCK: Set when the autonomous AGC is locked (only in ZIF mode). [4:0] RESERVED 172/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 6 PMC2_RESET ti a 7 PMC2 configuration STiH271EL Front-end registers 0xF070 Type: RW Reset: 0x00 AUTONOM_EARLY 1 0 LOCK_RST 2 AUTONOM_ROT_EN 3 Description: ti a l [7] COM_RST: Active high, reset the I/Q common AGC module. [6] COM_AGC_EN: Active high, enable I/Q common AGC module. [5] COM_EARLY: Active high, I/Q common AGC starts before analog AGC lock indicator. en [4] AUTONOM_RST: Active high, reset the I/Q autonomous AGC module. [2] AUTONOM_EARLY: Active high, I/Q autonomous AGC starts before I/Q common AGC lock indicator. fid [1] AUTONOM_ROT_EN: Active high, enable the phase rotator controlled by the PMC module. COM_TARGET_MSB 7 6 on [0] LOCK_RST: Active high, reset the I/Q common and autonomous lock indicators. 5 Address: 0xF071 Type: RW Reset: 0x10 4 Digital I/Q common AGC target MSB value 3 2 1 0 COM_TARGET [11:4] C Confidential [3] AUTONOM_AGC_EN: Active high, enable I/Q autonomous AGC module. Description: [7:0] COM_TARGET[11:4]: Reference value of the coarse AGC. DocID023557 Rev 10 173/604 Information classified Confidential - Do not copy (See last page for obligations) Address: 4 AUTONOM_AGC_EN 5 AUTONOM_RST 6 COM_EARLY COM_RST 7 Digital AGC reset configuration COM_AGC_EN DIG_AGC_RST Front-end registers STiH271EL COM_TARGET_LSB 7 Digital I/Q common AGC target LSB value 6 5 4 3 2 COM_TARGET [3:0] Address: 0xF072 Type: RW Reset: 0x01 1 0 RESERVED Description: [7:4] COM_TARGET[3:0]: Reference value of the coarse AGC. 6 5 ti a 7 Common AGC target configuration l COM_AGC_CFG 4 3 0xF073 Type: RW Reset: 0x6E 2 1 COM_STABMODE 0 ERR_SEL en Address: Description: fid [7:3] COM_N: Time constant of the coarse AGC filter: 2 (COM_N + 2) [2:1] COM_STABMODE: Force the coarse AGC to go from Acq to Trk mode in case of big error on [0] ERR_SEL: Selection for common or autonomous error (see COM_AUT_ERROR) 0: mean_err_com 1: mean_err_au COM_AGC_GAIN1 7 6 5 Common AGC gain1 parameters 4 3 C Confidential COM_N COM_GAIN1ACK Address: 0xF074 Type: RW Reset: 0x27 2 COM_GAIN1TRK Description: [7:4] COM_GAIN1ACK: Gain of the coarse AGC when unlocked [3:0] COM_GAIN1TRK: Gain of the coarse AGC when locked 174/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) [3:0] RESERVED STiH271EL Front-end registers AUT_AGC_TARGET_I/Q 7 6 Autonomous AGC target I/Q MSB 5 4 3 2 1 0 AUT_AGC_TARGET_I/Q[11:4] Address: 0xF075 Type: RW Reset: 0x10 Description: 6 5 4 3 2 1 0 ti a 7 Lock_detect_n MSB l LOCK_DETECT_N 0xF076 Type: RW Reset: 0x06 for Lock _detect_1/2; 0x01 for Lock _detect_3/4 en Address: Description: on fid [7:0] LOCK_DETECT_N [11:4]: Threshold used for the lock detection of AGC if com_error < LOCK_DETEC_1 (reset value: 0x064) => coarse AGC locked if com_error > LOCK_DETECT_2 (reset value: 0x064) => coarse AGC unlocked. if aut_error < LOCK_DETECT_3 (reset value: 0x010) => fine AGC locked if aut_error > LOCK_DETECT_4 (reset value: 0x010) => fine AGC unlocked. AUT_AGC_TARG_LOCK 7 6 5 Autonomous AGC target I/Q & lock_detect_n LSBs 4 3 LOCK_DETECT_N[3:0] 2 1 0 AUT_AGC_TARGET_I/Q[3:0] C Confidential LOCK_DETECT_N[11:4} Address: 0xF077 Type: RW Reset: 0x04 for Lock _detect_1/2; 0x00 for Lock _detect_3/4 Description: [7:4] LOCK_DETECT_N [3:0]: Threshold used for the lock detection of AGC [3:0] AUT_AGC_TARGET _I/Q [3:0]: Reference value of the fine AGC DocID023557 Rev 10 175/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] AUT_AGC_TARGET _I/Q [11:4]: Reference value of the fine AGC Front-end registers STiH271EL AUT_GAIN_EN 7 Autonomous AGC target gain2 and enable 6 5 4 3 2 AUT_ENMODE 1 0 AUT_AGC_GAIN2][3:0] Address: 0xF078 Type: RW Reset: 0x14 Description: Fine AGC filter parameter [7:4] AUT_ENMODE: Use to artificially reduce the time constant of the fine AGC filter. 6 5 ti a 7 Autonomous AGC configuration l AUT_AGC_CFG 4 3 0xF079 Type: RW Reset: 0x80 2 1 INT_CHOICE 0 INT_LOAD en Address: Description: fid [7:3] AUT_N: Time constant of the fine AGC filter: 2 (AUT_N + 2) [2:1] INT_CHOICE: Select for integrator status reading (registers INT_X_3 to INT_X_0). 00: I/Q_integrator 01: I_integrator 10: Q_integrator11: Reserved, do not use on [0] INT_LOAD: Reserved always set to 0 LOCKN 7 6 C Confidential AUT_N Address: 0xF07A Type: RW Reset: 0x20 5 Lock_n and config for autonomous AGC target 4 3 LOCK_N 2 SEL_IQ 1 0 LOCK_DETECT_CHOICE[1:0] Description: [7:3] LOCK_N [4:0]: The aim of this register is the seed up of convergence for lock detection [2] SEL_IQ: Selection for aut_agc_target_i/q writing (see AUT_AGC_TARGET_I/Q and LOCK_DETECT_N). 0: aut_agc_target_q.1: aut_agc_target_i [1:0] LOCK_DETECT_CHOICE: Selection for lock_detect_n writing (see LOCK_DETECT_N and AUT_AGC_TARG_LOCK). 00: lock_detect101: lock_detect2 10: lock_detect311: lock_detect4 176/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [3:0] AUT_AGC_GAIN2[3:0]: Gain of the fine AGC STiH271EL Front-end registers INT_X_3 7 MSB of integrator status 6 5 4 3 2 1 0 INTEGRATOR_STATUS[31:24] Address: 0xF07B Type: R Reset: 0x00 Description: 6 5 4 3 2 1 0 ti a 7 Upper middle bits of integrator status l INT_X_2 0xF07C Type: R Reset: 0x00 en Address: Description: INT_X_1 7 6 5 fid [7:0] INTEGRATOR_STATUS[23:16]: I/Q, I, Q integrator status 4 Lower middle bits of integrator status 3 2 1 0 Address: 0xF07D Type: R Reset: 0x00 on INTEGRATOR_STATUS[15:8] C Confidential INTEGRATOR_STATUS[23:16] Description: [7:0] INTEGRATOR_STATUS[15:8]: I/Q, I, Q integrator status INT_X_0 7 LSB of integrator status 6 5 4 3 2 1 0 INTEGRATOR_STATUS[7:0] Address: 0xF07E Type: R Reset: 0x00 Description: [7:0] INTEGRATOR_STATUS[7:0]: I/Q, I, Q integrator status DocID023557 Rev 10 177/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] INTEGRATOR_STATUS[31:24]: I/Q, I, Q integrator status Front-end registers STiH271EL COM_AUT_ERROR 7 Common or autonomous error 6 5 4 3 2 1 0 COM_AUT_ERROR Address: 0xF07F Type: R Reset: 0x00 Description: Core control 7 6 0xF080 Type: RW Reset: 0x00 4 HOLD 3 2 1 0 CORE_STATE en Address: 5 CORE_ACTIVE Description: fid [7:6] LOCK_CONFIG: AGC lock configuration: 00: AGC_locked for IF config 10: AGC_autonomous_locked in baseband config 01: AGC_common_locked (I/Q) in baseband config 11: all AGC_locked are required to be set to 1 on [5] CORE_ACTIVE: Enables core operation. 0: The core reverts back to and is held in its idle mode. This bit is the normal method of core enable and disable. Disabled means core is off. [4] HOLD: Prevents the state machine from changing state. For debugging only. C Confidential LOCK_CONFIG ti a l COR_CTL [3:0] CORE_STATE[3:0]: Core state override control. When a non-zero value is written into these bits, the core state machine is forced into a specific state as listed below: 0000: State machine not forced0001: WAIT_TRL 0010: WAIT_AGC0011: WAIT_SYR 0100: WAIT_PPM0101: WAIT_TPS 0110: MONITOR _TPS0111 to 1111: Reserved. This field is for debugging only and is not expected to be used in normal operation. In particular, backward transitions may give rise to unpredictable behavior. 178/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] COM_AUT_ERROR: If err_sel equal 0 (see COM_AGC_CFG on page 174) outputs the common mean_error status otherwise auto mean_error status STiH271EL Front-end registers COR_STAT Core status 7 6 5 4 RESERVED TPS_LOCKED SYR_LOCKED AGC_LOCKED Address: 0xF081 Type: R 3 2 1 0 CORE_STATE Description: [7] RESERVED: Always set to 0. ti a l [5] SYR_LOCKED (same as register STATUS bit 6): Set when SYR is locked (guard mode, interval and symbol position determined). COR_INTEN 6 5 RESERVED INTEN_SYR Address: 0xF082 Type: RW Reset: 0x00 Description: Core interrupt 4 3 2 1 0 INTEN_FFT INTEN_AGC INTEN_TPS1 INTEN_TPS2 INTEN_TPS3 on 7 INTEN_GLOBAL fid en [3:0] CORE_STATE[3:0]: Current core state: 0000: IDLE0001: WAIT_TRL 0010: WAIT_AGC0011: WAIT_SYR 0100: WAIT_PPM0101: WAIT_TPS 0110: MONITOR _TPS0111 to 1111: Reserved. C Confidential [4] AGC_LOCKED (same as register STATUS bit 5): Set when the AGC is locked. [7] INTEN_GLOBAL: Set to enable interrupts, this information can be observed on LOCK/OP2 pin. [6] RESERVED: Always set to 0. [5] INTEN_SYR: Set to enable an interrupt on SYR symbol end. [4] INTEN_FFT: Set to enable an interrupt on completion of FFT processing. [3] INTEN_AGC: Set to enable an interrupt on change of AGC lock. [2] INTEN_TPS1: Set to enable an interrupt on receipt of a TPS block with bad BCH check. This interrupt is not influenced by the TPS_CTL (TPS_BCH) register setting. [1] INTEN_TPS2: Set to enable an interrupt on a change of TPS data (except frame number). It indicates that the contents of registers TPS_RCVD2 to TPS_RCVD4 have changed. This only occurs at the end of a frame. [0] INTEN_TPS3: Set to enable an interrupt on receipt of a TPS block. It indicates that registers TPS_RCVD1 to TPS_RCVD4 have been updated. This only occurs at the end of a frame. DocID023557 Rev 10 179/604 Information classified Confidential - Do not copy (See last page for obligations) [6] TPS_LOCKED (same as register STATUS bit 7): Set when acceptable TPS data has been received. This depends on a good TPSBCH check (BCH_OK), unless TPS_CTL (TPS_BCH) is set. This differentiates TPS locked from TPS_RCVD1 (BCH_OK). Cleared when the state machine is forced back into idle state. Front-end registers STiH271EL COR_INTSTAT 7 Core interrupt status 6 RESERVED Address: 0xF083 Type: R 5 4 3 2 1 0 INSTAT_SYR INSTAT_FFT INSTAT_AGC INSTAT_TPS1 INSTAT_TPS2 INSTAT_TPS3 Description: [7:6] RESERVED: Always set to 0. [5] INTSTAT_SYR: Interrupt on SYR symbol end. [4] INTSTAT_FFT: interrupt on FFT completed. l [2] INTSTAT_TPS1: Interrupt on receipt of TPS block with bad BCH check. ti a [1] INTSTAT_TPS2: Interrupt on change of TPS data. 7 6 5 RESERVED 4 3 FORCE 0xF084 Type: RW Reset: 0x00 2 MODE 1 0 GUARD fid Address: COFDM core mode guard on Description: [7:5] RESERVED: Always set to 0. [4] FORCE: If set, this forces the core to use the set mode and guard. The core does not attempt to lock to any other mode and guard even if they are set incorrectly. [3:2] MODE: Sets the mode for which the core attempts initial lock. If this is set incorrectly, the core still automatically recovers the correct mode. If the mode is known, setting the mode here reduces lock times: 00: mode = 2K01: mode = 8K 10: mode = 4K11: reserved, do not use C Confidential COR_MODEGUARD en [0] INTSTAT_TPS3: Interrupt on receipt of TPS block. [1:0] GUARD: Sets the guard interval for which the core attempts initial lock. If this is set incorrectly, the core still automatically recovers the correct guard. If the guard is known, setting the guard here reduces lock times: 00: guard interval = 1/3201: guard interval = 1/16 10: guard interval = 1/811: guard interval = 1/4 Note: It is best to set the mode and guard values to the most likely configuration to reduce lock times (for example 2 Kbytes, 1/32 guard in the UK). Even if wrong, the core still automatically recovers the correct mode and guards. 180/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [3] INTSTAT_AGC: interrupt on change of AGC lock. STiH271EL Front-end registers AGC control 3 Address: 0xF085 Type: RW Reset: 0x08 AGC_BW_REDUCTION 2 0 ti a l Description: 1 [7:5] RESERVED: Bits 7 and 6 are always set to 0. en [4] AGC_USE_LAST_VALUE: After bit CORE_ACTIVE (COR_CTL) has been set, a value of zero causes the AGC to start at mid range and the DAGC to start at a gain of 1. In this case, it is necessary to wait for the external RC to settle. If this bit is set, the +AGC and DAGC retain their last gain settings, which is useful to reduce lock times for re-acquisition after loss of lock. fid Confidential [3:2] AGC_BW_REDUCTION: When the AGC loop locks, the loop bandwidth is reduced by the following factors: 00: no reduction01: BW reduced by 1/2 10: BW reduced by 1/4 (default)11: BW reduced by 1/8 on [1] AGC_NEG: 0: The AGC output level increases when a larger signal is required 1: The AGC output level decreases when a larger signal is required AGC_TARGET 7 6 C [0] AGC_SET: 1: The AGC output control value is set to AGC manual, and the AGC update output signal is asserted high continuously. AGC target 5 4 3 2 1 0 AGC_TARGET Address: 0xF088 Type: RW Reset: 0x1B Description: [7:0] AGC_TARGET: Target value for analog signal to optimize operation. DocID023557 Rev 10 181/604 Information classified Confidential - Do not copy (See last page for obligations) 4 AGC_NEG 5 AGC_USE_LAST_VALUE 6 RESERVED 7 AGC_SET AGC_CTL Front-end registers STiH271EL AGC_GAIN1 7 AGC gain (LSB) 6 5 4 3 2 1 0 AGC_GAIN[7:0] Address: 0xF089 Type: R Description: [7:0] AGC_GAIN: LSBs of current (or latched) AGC gain control. This represents the core output AGC_OUT during normal operation. Refer to register PIR_CTL for details of the latched mode. 5 4 Address: 0xF08A Type: R 2 1 0 AGC_GAIN[11:8] ti a AGC_LOCKED Description: [7:5] RESERVED: always set to 0. [4] AGC_LOCKED. fid [3:0] AGC_GAIN: Bits 11 to 8 of current (or latched) AGC control. Refer to register PIR_CTL for details of the latched mode. 7 6 CCS_ENABLE ACS_DISABLE 5 DAGC_DISABLE Address: 0xF08E Type: RW Reset: 0x0E Description: on CAS_CTL 4 Co- and adjacent-channel suppressor (CAS) control 3 DAGC_BW_REDUCTION 2 1 0 CCSMU C Confidential 3 l 6 RESERVED en 7 AGC gain (MSB) and control See Section 9.7.6: Co-channel and adjacent-channel interference suppressor on page 119. [7] CCS_ENABLE: Enable co-channel interference suppression within the CAS block. CCS is off by default during tracking phase. [6] ACS_DISABLE: Disable adjacent channel interference suppression in CAS block during tracking phase. ACS is on by default. [5] DAGC_DISABLE: Disable DAGC in CAS block. DAGC is on by default. [4:3] DAGC_BW_REDUCTION: Reduce DAGC bandwidth once the SYR has been locked: 00: no reduction01: reduce BW by 1/2 10: reduce BW by 1/4 11: reduce BW by 1/8 [2:0] CCSMU: Sets the bandwidth of the co-channel suppression filter. A large value corresponds to a wide bandwidth (111: maximum bandwidth) and vice versa (000: no action). The value of 4 gives good performance for PAL interference. 182/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) AGC_GAIN2 STiH271EL Front-end registers CAS_FREQ 7 CAS center frequency 6 5 4 3 2 1 0 CCS_FREQ Address: 0xF08F Type: RW Reset: 0xB3 See Section 9.7.6: Co-channel and adjacent-channel interference suppressor on page 119. ti a l [7:0] CCS_FREQ: Sets the center frequency of the co-channel suppression filter. The actual frequency is: CCS center frequency = CCS_FREQ 9.14 (BW / 8) / 256 MHz This is an 8-bit signed number, and the reset value of -77 corresponds to a center frequency of -2.75 MHz in 8 MHz channels. This is the same frequency as the vision carrier of PAL signals (38.9 MHz), and thus centers the co-channel suppression filter on the vision carrier. 7 6 5 4 en CAS_DAGCGAIN CAS digital AGC gain 3 2 1 0 0xF090 Type: R Description: fid Address: See Section 9.7.6: Co-channel and adjacent-channel interference suppressor on page 119. on [7:0] CAS_DAGC_GAIN: Digital automatic gain controller gain indication from CAS block. The actual gain of the digital AGC can be read from this register and is coded as follows: Actual gain = CAS_DAGC_GAIN / 16. Thus a gain of 1 is equivalent to a setting of 16 in this register. SYR_CTL 7 6 C Confidential CAS_DAGC_GAIN RESERVED Symbol recovery (SYR) control 5 4 3 LONG_ECHO_PROTECTION Address: 0xF091 Type: RW Reset: 0x80 2 EPQAUTO_EN 1 0 RESERVED Description: [7] RESERVED: must be set to 0 (not the reset value). DocID023557 Rev 10 183/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL [6:3] LONG_ECHO_PROTECTION: Used in 1/4 guard interval mode. LONG_ECHO_PROTECTION enables echoes beyond the guard interval up to 1/4 Tu to be correctly positioned within the CHC interpolator. Tu is the time duration of the useful part of a symbol (without the guard interval. The echo tracking window is from Tu (LONG_ECHO_PROTECTION + 8)/180 - Tu / 4 to Tu (LONG_ECHO_PROTECTION - 7) / 180 + Tu / 4. The value is a signed 4-bit number. A value of -8 (or +7) allows long pre- (or post-) cursive echoes. The default value of 0 gives equal bias to pre- and post-cursive echoes. SYR_STAT 7 6 5 4 3 Address: 0xF092 Type: R Symbol recovery status 2 1 SYR_MODE 0 SYR_GUARD en SYR_LOCKED Description: fid [7:5] RESERVED [4] SYR_LOCKED: SYR locked indication (guard detection and symbol position has been determined (same as bit 6 of register STATUS). on [3:2] SYR_MODE: SYR detected mode: 00: 2K mode01: 8K mode 10: 4K mode11: reserved [1:0] SYR_GUARD: SYR detected guard interval: 00: 1/3201: 1/16 10: 1/811: 1/4 SYR_OFFSET1 7 C Confidential RESERVED ti a l [1:0] RESERVED: Always set to 0 6 Symbol recovery offset 1 5 4 3 2 1 0 SYR_OFFSET[7:0] Address: 0xF095 Type: RW Reset: 0x00 Description: [7:0] SYR_OFFSET: Signed bits 7 to 0 of the FFT trigger offset from the correlated position. For normal operation, SYR_OFFSET should be set to 0. 184/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [2] EPQAUTO_EN: Enable EPQ auto loop: 1: synchronizing echo outside GI. STiH271EL Front-end registers SYR_OFFSET2 7 Symbol recovery offset 2 6 5 4 3 RESERVED 2 1 0 SYR_OFFSET[13:8] Address: 0xF096 Type: RW Reset: 0x00 Description: [7:6] RESERVED: Always set to 0. Type: RW Reset: 0x00 0 RESERVED 1 SCR_NO_COMMON_PHASE en 2 fid 0xF098 3 RESERVED 4 on Address: ti a 5 SYR_ADJUST_DECAY 6 RESERVED Description: [7] RESERVED: Always set to 0. [6:4] SYR_ADJUST_DECAY: Applies a fraction of any adjustment calculated when the SYR is tracking. Only applying a small amount ensures that the system retains lock on impulse noise: 000: 1001: 1/2 010: 1/4011: 1/8 100: 1/16101: 1/32 110: 1/64111: 1/128 C Confidential 7 Slope correction l SCR_CTL [3:2] RESERVED: Always set to 0. [1] SCR_NO_COMMON_PHASE: 1: Disables common phase error correction. [0] RESERVED: Always set to 0. DocID023557 Rev 10 185/604 Information classified Confidential - Do not copy (See last page for obligations) [5:0] SYR_OFFSET: Signed bits 13 to 8 of the FFT trigger offset from the correlated position. Front-end registers STiH271EL 3 Address: 0xF099 Type: RW Reset: 0xF0 2 PPM_MAXTIM 1 0 RESERVED 4 PPM_INV_SPECT 5 PPM_MAXFREQ 6 RESERVED 7 Pilot processing controller 1 PPM_SCAT_DIS PPM_CTL1 l [7:6] RESERVED: Always set to 0 (this is not the reset value). en [3] PPM_MAXTIM: Maximum search range setting for the coarse timing offset. fid [2] PPM_INV_SPECT: Set to evaluate the output of the PPM continuous pilot correlator (normal spectrum) compared with the output of the PPM continuous pilot correlator (inverted spectrum). [1] PPM_SCAT_DIS: Set to disable scattered pilot correlation. Determines the two LSBs of register CTL_FFTOSNUM. on [0] RESERVED: Always set to 0. TRL_CTL 7 6 TRL_NOMRATE[0] 5 C Confidential ti a [5:4] PPM_MAXFREQ[1:0]: Maximum search range setting for coarse frequency offset: 00: 32 FFT bins (142 kHz in 2K mode, 35 kHz in 8K mode) 01: 64 FFT bins (285 kHz in 2K mode, 71 kHz in 8K mode) 10: 128 FFT bins (570 kHz in 2K mode, 142 kHz in 8K mode) 11: 256 FFT bins (1140 kHz in 2K mode, 284 kHz in 8K mode). One FFT bin is the carrier spacing (1.116 kHz in 8K mode and 4.464 kHz in 2K mode. Timing recovery loop 1 4 3 TRL_GAIN_FACTOR 2 1 0 TRL_LOOP_GAIN Address: 0xF09A Type: RW Reset: 0x14 Description: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120. [7] TRL_NOMRATE[0]: LSB of TRL_NOMRATE[16:0] (register TRL_NOMRATE2). [6:3] TRL_GAIN_FACTOR: Sets the gain (= TRL_GAIN_FACTOR / 10) of the sample timing loop during acquisition. Also sets the gain (controlled with TRL track gain factor) during tracking. [2:0] TRL_LOOP_GAIN: TRL track gain factor sets the additional gain (= TRL_LOOP_GAIN / 16) applied during tracking (default is to reduce the gain by 1/8 during tracking). 186/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL Front-end registers TRL_NOMRATE1 7 Timing recovery loop (TRL) nominal rate 1 6 5 4 3 2 1 0 TRL_NOMRATE[8:1] Address: 0xF09B Type: RW Reset: 0xB0 Description: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120. 6 5 4 3 2 1 0 ti a 7 TRL nominal rate 2 l TRL_NOMRATE2 0xF09C Type: RW Reset: 0x56 Description: en Address: See Section 9.7.8: Carrier and timing recovery loop (CRL and TRL) on page 120. on fid [7:0] TRL_NOMRATE[16:9]: MSBs of TRL_NOMRATE, the nominal rate of the sample timing NCO. See also TRL_NOMRATE1 and TRL_CTL. TRL_NOMRATE can be used for reduced bandwidth (6 and 7 MHz) operation. TRL nominal rate is the ratio of the FFT time sample clock to the (fixed) ADC clock frequency. TRL_NOMRATE[16:0] = 217 9.1428 ChanBW / (fCOFDM 16) Some common settings are: FADC 54 MHz 54 MHz C Confidential TRL_NOMRATE[16:9] 54 MHz Channel BW Minimum TRL_NOMRATE 8 MHz 44384 7 MHz 38836 6 MHz 33288 TRL_TIME1 7 TRL time offset 1 6 5 4 3 2 1 0 TRL_OFFSET[7:0] Address: 0xF09D Type: R Description: [7:0] TRL_TOFFSET[7:0]: LSBs of current (or latched) TRL timing offset. See also TRL_TIME2. Refer to register PIR_CTL for details of the latched mode. The timing offset in ppm is equal to: Offset (ppm) = (TRL_TOFFSET 106) / (32 128 TRL_NOMRATE / 2) TRL_TOFFSET[15:0] is a signed quantity, in 2's complement format. DocID023557 Rev 10 187/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] TRL_NOMRATE: Middle bits of TRL_NOMRATE. See register TRL_NOMRATE2. Front-end registers STiH271EL TRL_TIME2 TRL time offset 2 7 6 5 4 3 2 1 0 TRL_OFFSET[15:8] Address: 0xF09E Type: R Description: [7:0] TRL_TOFFSET[15:8]: MSBs of current (or latched) TRL timing offset. See also TRL_TIME1. Refer to register PIR_CTL for details of the latched mode. Carrier recovery loop control 6 5 4 0xF09F Type: RW Reset: 0x1F 1 0 CRL_LOOP_GAIN en Address: 2 ti a CRL_GAIN_FACTOR Description: [7] CRL_DIS: Disables SYR fine offset correct on CRL during acquisition. fid [6:3] CRL_GAIN_FACTOR: The CRL track gain factor sets the additional gain (= CRL_GAIN_FACTOR / 16) applied during tracking (default is to reduce gain by 1/4 during tracking). on [2:0] CRL_LOOP_GAIN: Sets the gain (= CRL_LOOP_GAIN / 16) of the carrier loop during acquisition. Also sets the gain (combined with CRL_GAIN_FACTOR) during tracking. CRL_FREQ1 7 6 5 C Confidential 3 l 7 CRL_DIS Address: 0xF0A0 Type: R Carrier recovery loop (CRL) frequency 1 4 3 2 1 0 CRL_OFFSET[7:0] Description: [7:0] CRL_OFFSET[7:0]: LSBs of current (or latched) CRL frequency offset, CRL_OFFSET[23:0]. See also CRL_FREQ2 and CRL_FREQ3. The carrier offset in FFT bins is equal to CRL_OFFSET/16384. CRL_OFFSET[23:0] is a signed quantity, in 2's complement format. 1 FFT bin = 1 / Tu For 8K, 8 MHz, 1/4 guard, 1 FFT bin = 1.11 kHz. For 2K, 8 MHz, 1/4 guard, 1 FFT bin = 4.46 kHz. Refer to register PIR_CTL for details of the latched mode. 188/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) CRL_CTL STiH271EL Front-end registers CRL_FREQ2 7 CRL frequency 2 6 5 4 3 2 1 0 CRL_OFFSET[15:8] Address: 0xF0A1 Type: R Description: [7:0] CRL_OFFSET[15:8]: Middle bits of CRL_OFFSET[23:0]. See register CRL_FREQ1 above. 7 CRL frequency 3 6 5 4 3 2 1 0 Address: 0xF0A2 Type: R ti a l CRL_OFFSET[23:16] Description: 0xF0A3 Type: RW Reset: 0x01 Description: 2 1 DNOISENORM RESERVED 0 CHC_INT 3 DBADPILOT Channel correction (CHC) control 1 C Address: 4 MAN_PILOT_GAIN 5 fid 6 on 7 en CHC_CTL1 MEAN_PILOT_GAIN Confidential [7:0] CRL_OFFSET[23:16]: MSBs of CRL_OFFSET[23:0]. See register CRL_FREQ1 above. Note: The most efficient value for this register is 0x11. [7:5] MEAN_PILOT_GAIN: Sets the mean pilot gain used in the channel predictor if bit MAN_PILOT_GAIN is set: 000: 0001: 1/32 010: 1/16011: 1/8 100: 1/4101: 1/2 110: 1111: Reserved [4] MAN_PILOT_GAIN: 1: Allows the mean pilot gain to be adaptively adjusted to suit the channel conditions [3] DBADPILOT: Set to disable bad pilots from being dropped in the PPM. [2] DNOISENORM: Set to disable noise normalization between scattered and continuous pilots. [1] RESERVED: Always set to 0. DocID023557 Rev 10 189/604 Information classified Confidential - Do not copy (See last page for obligations) CRL_FREQ3 Front-end registers STiH271EL [0] CHC_INT: Sets the frequency domain interpolation method used. 0: FIR 36 taps1: FIT 72 taps CHC_SNR CHC signal-to-noise ratio 7 6 5 4 3 2 1 0 CHC_SNR Address: 0xF0A4 Type: R ti a l [7:0] CHC_SNR: Estimated signal-to-noise ratio (SNR) in dB. The estimated value is independent of the channel response, and accurate to about 1 dB. SNR = CHC_SNR / 4dB. Note: The value compresses near the extremes. BDI_CTL 6 5 4 Type: RW Reset: 0x00 2 1 0 BDI_LPSEL BDI_SERIAL fid 0xF0A5 Description: [7:2] RESERVED: Always set to 0. on [1] BDI_LPSEL: Selects priority of data for output on VDAT1 (and VDAT2 in parallel mode). VSTRB1 indicates when valid data is available from the selected data stream: 0: HP data and code rate.1: LP data and code rate. [0] BDI_SERIAL: Serial or parallel output mode select: 0: Parallel1: Serial C Confidential RESERVED Address: 3 en 7 Bit de-interleaver (BDI) control TPS_RCVD1 Transmission parameter signaling (TPS) received 1 7 6 5 4 RESERVED TPS_CHANGE BCH_OK TPS_SYNC Address: 0xF0A7 Type: R 3 2 RESERVED 1 0 TPS_FRAME Description: [7] RESERVED: Always set to 0. [6] TPS_CHANGE: Set when an update to TPS_RCVD2,3,4 causes the data contents of the registers to change. [5] BCH_OK: Set if the BCH check on the TPS data of the previous frame was correct. This bit is not influenced by TPS_CTL. 190/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL Front-end registers [4] TPS_SYNC: Set if a TPS sync sequence was received. If the control state machine is in MONITOR_TPS then this bit indicates presence / absence of a sync sequence in the previous frame (updated every time a new TPS frame is received). If the control state machine is not in MONITOR_TPS, this bit asserts as soon as a sync sequence is detected, de-asserting if the BCH check subsequently fails. [3:2] RESERVED: Always set to 0. [1:0] TPS_FRAME: Frame number (within super-frame) indicated by TPS data received in the previous frame. 7 TPS received 2 6 5 4 3 Address: 0xF0A8 Type: R Description: 1 0 TPS_CONST en [7] RESERVED fid [6:4] TPS_HIERMODE: Hierarchy information for current scheme: 000: non hierarchical001: alpha = 1 010: alpha = 2 011: alpha = 4 100-111: Reserved [3:2] RESERVED on [1:0] TPS_CONST: Constellation for current modulation scheme: 00: QPSK01: QAM-16 10: QAM-6411: Reserved TPS_RCVD3 7 6 5 C Confidential 2 RESERVED l TPS_HIERMODE ti a RESERVED RESERVED TPS_LPCODE Address: 0xF0A9 Type: R TPS received 3 4 3 RESERVED 2 1 0 TPS_HPCODE Description: [7] RESERVED [6:4] TPS_LPCODE: Low priority stream code rate. Refer to high priority enumeration below. [3] RESERVED [2:0] TPS_HPCODE: High priority stream code rate: 000: 1/2001: 2/3 010: 3/4011: 5/6 100: 7/8101-111: Reserved DocID023557 Rev 10 191/604 Information classified Confidential - Do not copy (See last page for obligations) TPS_RCVD2 Front-end registers STiH271EL TPS_RCVD4 7 TPS received 4 6 5 RESERVED 4 3 TPS_GUARD Address: 0xF0AA Type: R 2 1 RESERVED 0 TPS_MODE Description: [7:6] RESERVED TPS_CELLID1 6 5 4 3 TPS cell identifier1 2 1 0 TPS_CELLID[7:0] 0xF0AB Type: R fid Address: Description: on [7:0] TPS_CELLID: LSBs of TPS_CELLID[15:0] TPS_CELLID2 7 6 5 C Confidential 7 en ti a [1:0] TPS_MODE: Transmission mode information: 00: 2K mode01: 8K mode 10: Reserved11: Reserved l [3:2] RESERVED Address: 0xF0AC Type: R TPS cell identifier2 4 3 TPS_CELLID[15:8] Description: [7:0] TPS_CELLID: MSBs of TPS_CELLID[15:0]. 192/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) [5:4] TPS_GUARD: Guard interval: 00: 1/3201: 1/16 10: 1/811: 1/4 STiH271EL Front-end registers TPS_RCVD5_SET1 7 TPS_reserved 6 5 4 3 2 1 TPS_RESERVED Address: 0xF0AD Type: RW Reset: 0x00 0 TPS_SETFRAME[1:0] Description: 7 en 6 5 RESERVED 0xF0B0 Type: RW Reset: 0x00 4 TPS control 3 2 1 0 TPS_IU TPS_BCH TPS_DIS on Address: fid TPS_CTL Description: C Confidential ti a l [1:0] TPS_SETFRAME: Current frame number within super-frame as maintained by internal counters. The frame number determines super-frame boundaries (for TPS_SET_x updates). The frame counter is initialized to 1 on the first received TPS frame data (TPSRCVFrame), that is, TPS data received while the control state machine is in the WAIT_TPS state. The symbol counter increments at the end of the FFT processing. The frame counter increments when the symbol counter wraps from 67 to 0. With the control state machine in IDLE, writes to TPS_SET_1 take immediate effect. Otherwise, setting by the host takes effect at the beginning of the next frame (when FFT output symbol number wraps from 67 to 0). Only then will the register read back the data written by the host. [7:2] RESERVED: [2] TPS_IU: Active high, does not wait for superframe reception to update TPS data. [1] TPS_BCH: Active high, TPS is updated even if BCH code is not valid. [0] TPS_DIS: Active high, disables TPS update from TPS data received. CTL_FFTOSNUM 7 6 Control FFT output symbol number 5 4 RESERVED 3 2 1 0 CTL_FFTOSNUM Address: 0xF0B1 Type: R Reset: 0x7F Description: [7] RESERVED: Always set to 0. DocID023557 Rev 10 193/604 Information classified Confidential - Do not copy (See last page for obligations) [7:2] TPS_RESERVED: Read only: Symbol[53:48]: reserved part of TPS data received in the previous frame. Front-end registers STiH271EL 6 5 4 3 ti a 7 Carrier display select 0xF0B2 Type: RW Reset: 0x00 Description: [7:4] RESERVED: Always set to 0. 2 1 0 CAR_DISPLAY_SEL en Address: on fid [3:0] CAR_DISPLAY_SEL: To display the constellation, a selected carrier can be picked out on a selected block output: 0111: FFT1000: SCR (slope correction) 1010: PPM (pilot processor module)1100: CHC (channel correction) 1011: CHP (channel predictor) PIR_CTL 7 6 5 C Confidential RESERVED l CAR_DISP_SEL Address: 0xF0B4 Type: RW Reset: 0x00 PIR control 4 3 RESERVED 2 1 0 FREEZE Description: [7:1] RESERVED: Always set to 0. [0] FREEZE: Latches the bits of bitfields that cover more than 8 bits. These are AGC_GAIN[11:0], TRL_TOFFSET[15:0], and CRL_OFFSET[22:0]: 0: Data in the fields changes dynamically1: The field values are latched. 194/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [6:0] CTL_FFTOSNUM: FFT output symbol number counter (0 to 63). This counter increments every symbol when new symbol data is available at the output of the FFT. A value of 127 read from this register implies that the counter is not yet running (that is, symbol number is not valid). This counter can be initialized in three ways: - Valid TPS data received while in the WAIT_TPS state, in which case the counter is loaded with 0 at the start of the next symbol. - Host write, in which case the host data is loaded into the counter at the start of the next symbol. - An initial estimate of the three LSBs of the symbol number is calculated based on the pilots. If PPM_CTL (Disable find scat pilots) is not set, the lower three bits are loaded with (estimate + 1), that is, 1 to 4, at the start of the next symbol. Bits [6:3] are cleared. STiH271EL Front-end registers SNR_CARRIER1 7 SNR carrier 1 6 5 4 3 2 1 0 SNR_CARRIER[7:0] Address: 0xF0B5 Type: RW Reset: 0x00 Description: LSBs of the SNR carrier number SNR_CARRIER[12:0] 7 SNR carrier 2 6 5 4 0xF0B6 Type: RW Reset: 0x00 1 0 ti a Address: 2 SNR_CARRIER[12:8] en Description: [7] MEAN: If set this register outputs the means of SNR all the continuous pilots in the CHC_SNR register otherwise the SNR of the specific carrier is output [6:5] RESERVED: Set to 00 fid [4:0] SNR_CARRIER[12:0]: MSBs of the SNR carrier number SNR_CARRIER[12:0] 7 6 5 Address: 0xF0C1 Type: RW Reset: 0x01 Description: on ANA_CTRL 4 Analog control 3 RESERVED 2 1 0 STDBY_PLLxN C Confidential 3 RESERVED l MEAN [7:1] RESERVED: Always set to 0. [0] STDBY_PLLxn: 0: PLLxn active1: PLLxn in standby. DocID023557 Rev 10 195/604 Information classified Confidential - Do not copy (See last page for obligations) SNR_CARRIER2 Front-end registers STiH271EL CONSTMODE 7 Constellation mode 6 5 4 RESERVED 3 2 CAR_TYPE RESERVED Address: 0xF0CB Type: RW Reset: 0x00 Description: See Section 9.7.15: Carrier monitoring on page 121. 1 0 CONST_MODE [7:4] RESERVED: Always set to 0. l [2] RESERVED. 7 en 6 5 fid CONSTCARR1 4 Constellation carrier LSB number 3 2 1 0 CONST_CARR 0xF0CC Type: RW Reset: 0x00 Description: See Section 9.7.15: Carrier monitoring on page 121. on Address: [7:0] CONST_CARR[7:0]: LSBs of CONST_CARR[12:0], the first carrier out of 16 to be stored in the FIFO for display. C Confidential ti a [1:0] CONST_MODE: Output mode selection: 00: Not selected 01: FIFO mode: 16 carriers are stored for each OFDM symbol from CONSTCARR specified carrier and replayed until the next OFDM symbol arrives. 10: Repeat CONSTCARR specified carrier. 11: All available carriers are displayed whenever possible. CONSTCARR2 7 6 Constellation carrier MSB number 5 4 3 RESERVED Address: 0xF0CD Type: RW Reset: 0x00 2 1 CONST_CARR[12:8] Description: [7:5] RESERVED: Always set to 0. [4:0] CONST_CARR[12:8]: MSBs of CONST_CARR[12:0] (see CONSTCARR1 above) 196/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [3] CAR_TYPE: Displayed carrier type selection: 0: Data carriers1: TPS carriers STiH271EL Front-end registers ICONSTEL I constellation 7 6 5 4 3 2 1 0 ICONSTEL Address: 0xF0CE Type: R Description: See Section 9.7.15: Carrier monitoring on page 121. [7:0] ICONSTEL: Real part value of CONST_CARR carrier. Q constellation 7 6 5 4 3 2 1 0 Address: 0xF0CF Type: R Description: ti a l QCONSTEL See Section 9.7.15: Carrier monitoring on page 121. 6 5 4 fid 7 en RF_AGC AGC RF 3 2 1 0 RF_AGC_LEVEL 0xF0D4 Type: R on Address: Description: [7:0] RF_AGC_LEVEL[7:0]: AGC RF level. Eight MSBs of 10-bit ADC. Range from 0 to 3.3 V on IP0 equivalent to 0x00 to 0xFF in this register. EN_RF_AGC 7 6 C Confidential [7:0] QCONSTEL: Imaginary part value of CONST_CARR carrier. RESERVED AGC RF enable 5 4 3 STDBY_ADC Address: 0xF0D5 Type: RW Reset: 0x00 2 1 0 RESERVED Description: [7:6] RESERVED: Always set to 0. [5] STDBY_ADC: Standby analog ADC. [4:0] RESERVED: Always set to 0. DocID023557 Rev 10 197/604 Information classified Confidential - Do not copy (See last page for obligations) QCONSTEL Front-end registers STiH271EL ANA_DIG_CTRL Analog/digital control 7 6 5 4 DC_REG_POFF RESERVED BUFFER_Q_EN BUFFER_I_EN Address: 0xF0D7 Type: RW Reset: 0x1A 3 2 1 0 RESERVED Description: [7] DC_REG_POFF: Power down for DC_REGULATOR [5] BUFFER_Q_EN: Power on for BUFFER Q ti a [3:0] RESERVED 6 5 4 en PLLMDIV 7 l [4] BUFFER_I_EN: Power on for BUFFER I 3 PLLMDIV 2 1 0 0xF0D8 Type: RW Reset: 0x01 fid Address: Description: on [7:0] PLL_MDIV[7:0]: Coefficient M The output frequency of the PLLxn macrocell is controlled by the binary values applied to the programmable dividers M,N,P: PLLNDIV 7 6 C Confidential PLL_MDIV[7:0] Address: 0xF0D9 Type: RW Reset: 0x08 5 PLLxn NDIV 4 3 PLL_NDIV Description: [7:0] PLL_NDIV[7:0]: Coefficient N 198/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) [6] RESERVED: Always set to 0. STiH271EL Front-end registers PLLPDIV PLLPDIV 7 6 5 4 3 2 PLL_PDIV[3:0] Address: 0xF0DA Type: RW Reset: 0x18 1 0 RESERVED [7:4] PPL_PDIV[3:0]: Coefficients 2P (2P= 2pll_pdiv. If PLL_PDIV > 101 then 2P = 32). 6 5 4 3 ti a 7 ADC12 configuration 0xF0DB Type: RW Reset: 00 2 1 POWER_OFF_Q POWER_OFF_I 0 INMODE[1] en Address: INMODE[0] Description: [7:4] RESERVED. fid [3] INMODE[0]: INMODE[1:0] 00: Max differential voltage equal to 2Vpp.01: Max differential voltage equal to 1.6Vpp 10: Reserved11: Max differential voltage equal to 2Vpp on [2] POWER_OFF_Q: Power down for QADC12. [1] POWER_OFF_I: Power down for IADC12. [0] INMODE[1]: See INMODE[0] above. C Confidential RESERVED l ADC12 CFG DocID023557 Rev 10 199/604 Information classified Confidential - Do not copy (See last page for obligations) [3:0] RESERVED Front-end registers COFDM reception super FEC VITSCALE 0 RESERVED 1 DIS_RSFLOCK 2 RESERVED 3 NSLOWSN_LOCKED 4 RESERVED 5 VERROR_MAXMODE 6 NVTH_NOSRANGE 7 Additional configuration of Viterbi decoder RW RW R RW R RW R 0xF248 Type: RW Reset: 0x0 Description: Additional configuration of Viterbi decoder. ti a l Address: fid Confidential en [7] NVTH_NOSRANGE: Automatic calculation of Viterbi threshold as a function of noise. Used during acquisition. 0: The Viterbi threshold is calculated as a function of noise measured by the demodulator 1: No automatic adaptation of Vth. The Vth is taken from the VTHxx registers programmed by I C. (unsigned) [5:4] RESERVED on [6] VERROR_MAXMODE: Observation mode of Px_VERROR register. 0: Px_VERROR contains the instantaneous value of the number of errors. 1: Px_VERROR contains the maximum value achieved since its last re-initialization (through I2C write); very useful for adjusting the limits of each puncture rate or to obtain the maximum observed. C [3] NSLOWSN_LOCKED: Slow the VERROR calculation (for a smoother result) 0: slow down1: don`t slow down (unsigned) [2] RESERVED [1] DIS_RSFLOCK: False lock detection from Reed-Solomon decoder 0: ignore false lock detection, do nothing.1: Retrigger Viterbi if false lock detected [0] RESERVED 200/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 10.2 STiH271EL STiH271EL Front-end registers FECM 7 Viterbi decoder configuration 6 5 4 3 2 RESERVED RW R RW R Address: 0xF233 Type: RW Reset: 0x10 Description: Viterbi decoder configuration 1 0 SYNCVIT IQINV RW R l [1] SYNCVIT: 1: Freeze the synchro word search mechanism. Very dangerous in case of unlocking: the machine will be incapable of re-hooking. (unsigned) VTH12 6 5 4 Error threshold for puncture rate 1/2 3 2 1 0 VTH12 0xF234 Type: RW Reset: 0xE0 Description: Error threshold for puncture rate 1/2 on fid Address: [7:0] VTH12: (unsigned) VTH23 7 6 C Confidential 7 en ti a [0] IQINV: Observation of the local spectral inversion detected by the Viterbi decoder. In manual mode, i2csym = DEMOD.p2_specinv_control(0). Address: 0xF235 Type: RW Reset: 0x84 Description: 5 Error threshold for puncture rate 2/3 4 3 2 1 0 VTH23 Error threshold for puncture rate 2/3 [7:0] VTH23: (unsigned) DocID023557 Rev 10 201/604 Information classified Confidential - Do not copy (See last page for obligations) [7:2] RESERVED Front-end registers STiH271EL VTH34 7 Error threshold for puncture rate 3/4 6 5 4 3 2 1 0 VTH34 Address: 0xF236 Type: RW Reset: 0x5F Description: Error threshold for puncture rate 3/4 6 5 4 3 0xF237 Type: RW Reset: 0x3A VTH67 6 5 on 7 0 Error threshold for puncture rate 5/6 [7:0] VTH56: (unsigned) fid Description: 1 en Address: 2 Error threshold for puncture rate 6/7 4 3 2 1 0 VTH67 Address: 0xF238 Type: RW Reset: 0x36 Description: Error threshold for puncture rate 6/7 C Confidential VTH56 ti a 7 Error threshold for puncture rate 5/6 l VTH56 [7:0] VTH67: (unsigned) VTH78 7 Error threshold for puncture rate 7/8 6 5 4 3 VTH78 Address: 0xF239 Type: RW Reset: 0x22 Description: Error threshold for puncture rate 7/8 [7:0] Px_VTH78: (unsigned) 202/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:0] VTH34: (unsigned) STiH271EL Front-end registers VITCURPUN 7 Current puncture rate on the Viterbi decoder 6 5 4 3 2 RESERVED 1 0 VIT_CURPUN Address: 0xF23A Type: R Reset: Undefined Description: Current puncture rate on the Viterbi decoder 6 5 4 3 Current error rate 2 1 0 0xF23B Type: RW Reset: Undefined Description: Current error rate fid Address: C on [7:0] REGERR_VIT: Current error rate or maximum observed by the Viterbi decoder. Equation: proportion of errors = px_regerr_vit / 2048 Examples: 0x00 = no errors, signal perfect 0xFF = 6.23% errors (255 bits corrected out of 2048). (read put to 0 on a write,unsigned) PRVIT 0 E1_2VIT 1 E2_3VIT 2 E3_4VIT 3 E5_6VIT 4 E6_7VIT 5 E7_8VIT 6 DIS_VTHLOCK 7 List of authorized puncture rates RESERVED Confidential REGERR_VIT R RW RW RW RW RW RW RW Address: 0xF23C Type: RW Reset: 0x3F Description: List of authorized puncture rates [7] RESERVED DocID023557 Rev 10 203/604 Information classified Confidential - Do not copy (See last page for obligations) 7 en VERROR ti a [4:0] VIT_CURPUN: Current puncture rate 0x0D: 1/2 0x12: 2/3 0x15: 3/4 0x18: 5/6 0x19: 6/7 0x1A: 7/8 (unsigned) l [7:5] RESERVED Front-end registers STiH271EL [6] DIS_VTHLOCK: Automatic adjustment of VTH as a function of noise after decoder lock. 1: Automatic adjustment enabled0: Disabled (unsigned) [5] E7_8VIT: Authorization of rate 7/8 (unsigned) [4] E6_7VIT: Authorization of rate 6/7 (unsigned) [3] E5_6VIT: Authorization of rate 5/6 (unsigned) [2] E3_4VIT: Authorization of rate 3/4 (unsigned) [1] E2_3VIT: Authorization of rate 2/3 (unsigned) 6 P1_VAVSRVIT 5 FROZENVIT 3 P1_SNVIT R RW 0xF23D Type: RW Reset: 0x0 Description: Viterbi decoder search speeds 1 0 P1_TOVVIT P1_HYPVIT RW RW en Address: 2 fid [7] P1_VAVSRVIT: Puncture rate automatic bit. 0: Automatic search mode (note TPS_PR active disables this mode) 1: Manual mode on [6] FROZENVIT: Freeze phase puncture rate. [5:4] P1_SNVIT: Measuring time (number of symbols) for evaluating Px_VERROR.px_regerr_vit 00: 4096 bits01: 16384 bits 10: 65536 bits11: 262144 bits (unsigned) [3:2] P1_TOVVIT: Synchro word search time-out. If no synchro word has been found during this time, the internal puncture rate search mechanism switches itself back on. This time-out counter only starts once a puncture rate has been found (VSTATUSVIT.px_prfvit goes to 1). 00: 32768 bits or the time for 23 packets DVB 01: 65536 bits 46 packets DVB 10: 131072 bits 93 packets DVB 11: 262144 bits 186 packets DVB C Confidential 4 ti a 7 Viterbi decoder search speeds l VAVSRVIT [1:0] P1_HYPVIT: Viterbi decoder locking validation or devalidation limit If the specified number of consecutive synchro words are detected, then the Viterbi decoder is locked (VSTATUSVIT.px_lockedvit goes to 1). If the specified number of consecutive synchro words are lost, then the Viterbi decoder is unlocked (VSTATUSVIT.px_lockedvit goes to 0). The puncture rate search mechanism switches itself back on. 00: 16 consecutive synchro words found or lost 01: 32 consecutive synchro words found or lost 10: 64 consecutive synchro words found or lost 11: 128 consecutive synchro words found or lost (unsigned) 204/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [0] E1_2VIT: Authorization of rate 1/2 (unsigned) STiH271EL Front-end registers VSTATUSVIT 7 Viterbi decoder status 6 5 4 3 RESERVED PRFVIT LOCKEDVIT RESERVED R RW RW R Address: 0xF23E Type: RW Reset: Undefined Description: 2 1 0 Certain bits of this register reset themselves to 0 uniquely through I C writing (the value of the data written is unimportant, only the action of I C writing). ti a l [4] PRFVIT: Puncture Rate Found 0: Searching puncture rate 1: Puncture rate found (unsigned) [3] LOCKEDVIT: Viterbi Locked 0: Searching synchro word 1: Decoder locked (unsigned) 6 5 4 fid 7 en VTHINUSE Viterbi threshold currently in use 3 2 1 0 VIT_INUSE 0xF23F Type: R Reset: Undefined Description: Viterbi Threshold currently in use on Address: [7:0] VIT_INUSE: Actual Viterbi threshold in use (observation). During acquisition this is controlled by VITSCALE.NVTH_NOSRANGE After acquisition; PRVIT.DIS_VTHLOCK (unsigned) C Confidential [2:0] RESERVED KDIV12 7 Gain (k_divider) of puncture rate 1/2 6 5 4 3 RESERVED K_DIVIDER_12 R RW Address: 0xF240 Type: RW Reset: 0x27 Description: 2 1 0 Gain (k_divider) of puncture rate 1/2 [7] RESERVED [6:0] K_DIVIDER_12: Multiplying coefficient applied for the puncture rate. Equation: Metric = px_k_divider_12 / 256 |I or Q| (unsigned) DocID023557 Rev 10 205/604 Information classified Confidential - Do not copy (See last page for obligations) [7:5] RESERVED Front-end registers STiH271EL KDIV23 7 Gain (k_divider) of puncture rate 2/3 6 5 4 3 2 RESERVED K_DIVIDER_23 R RW Address: 0xF241 Type: RW Reset: 0x32 Description: Gain (k_divider) of puncture rate 2/3 1 0 ti a l [6:0] K_DIVIDER_23: Multiplying coefficient applied for the puncture rate. Equation: Metric = px_k_divider_23 / 256 |I or Q| (unsigned) KDIV34 6 5 4 RESERVED 1 0 0xF242 Type: RW Reset: 0x32 RW fid Address: on Gain (k_divider) of puncture rate 3/4 [7] RESERVED [6:0] K_DIVIDER_34: Multiplying coefficient applied for the puncture rate. Equation: Metric = px_k_divider_34 / 256 |I or Q| (unsigned) KDIV56 7 6 C Confidential 2 K_DIVIDER_34 R Description: 3 en 7 Gain (k_divider) of puncture rate 3/4 Gain (k_divider) of puncture rate 5/6 5 4 3 RESERVED K_DIVIDER_56 R RW Address: 0xF243 Type: RW Reset: 0x32 Description: Gain (k_divider) of puncture rate 5/6 2 1 [7] RESERVED [6:0] K_DIVIDER_56: Multiplying coefficient applied for the puncture rate. Equation: Metric = px_k_divider_56 / 256 |I or Q| (unsigned) 206/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [7] RESERVED STiH271EL Front-end registers KDIV67 Gain (k_divider) of puncture rate 6/7 7 6 5 4 3 2 RESERVED K_DIVIDER_67 R RW Address: 0xF244 Type: RW Reset: 0x32 Description: Gain (k_divider) of puncture rate 6/7 1 0 ti a l [6:0] K_DIVIDER_67: Multiplying coefficient applied for the puncture rate. Equation: Metric = px_k_divider_67 / 256 |I or Q| (unsigned) KDIV78 Gain (k_divider) of puncture rate 7/8 6 5 4 3 en 7 RESERVED R 1 0 0xF245 Type: RW Reset: 0x50 Description: RW fid Address: on Gain (k_divider) of puncture rate 7/8 [7] RESERVED [6:0] K_DIVIDER_78: Multiplying coefficient applied for the puncture rate. Equation: Metric = px_k_divider_78 / 256 |I or Q| (unsigned) TSSTATEM C Confidential 2 P1_K_DIVIDER_78 Configuration of Merger/HWare Stream line 1 7 6 5 4 3 TSDIL_ON RESERVED TSRS_ON RESERVED RW R RW R Address: 0xF270 Type: RW Reset: 0xF0 Description: Configuration of Merger/HWare Stream line 1 2 1 0 [7] TSDIL_ON: Use of de-interleaver 0: Inactive. (unsigned)1: De-interleaver active if authorized [6] RESERVED [5] TSRS_ON: Use of Reed-Solomon decoder if tsskiprs_on = 0: 0: Decode but do not correct (unsigned)1: Decode and correct the data flow DocID023557 Rev 10 207/604 Information classified Confidential - Do not copy (See last page for obligations) [7] RESERVED Front-end registers STiH271EL [4:0] RESERVED 1 0 0xF272 Type: RW Reset: 0x0 Description: Configuration of Merger/HWare Stream line 1 ti a l Address: fid Confidential en [7] TSFIFO_DVBCI: Treatment of the signals CLKOUT and Data/Parity 0: Normal mode: a CLKOUT pulse with each data, CLKOUT off if no data, D/P remains punctured In order to avoid a "hole" on D/P, there are three equivalent solutions: - do not connect it - program Px_TSCFGL/tsfifo_dpunact = 1 - deprogram the associated GPIO (unsigned) 1: Mode DVB-CI: CLKOUT continuous, D/P indicates the data pulses on [6] TSFIFO_SERIAL: 0: Parallel output. (unsigned)1: Serial output: [5] TSFIFO_TEIUPDATE: MPEG packets only (TSSTATEL/tsdss_packet=0) 1: Update of TEI bit in accordance with the output ERROR signal. (unsigned) C [4] TSFIFO_DUTY50: CLKOUT signal duty cycle: 0: Maximum granularity on the available frequencies, but duty cycle not guaranteed (though always as close as possible to 50%). (unsigned) 1: Guarantees 50% but causes larger granularity on the available frequencies. [3] TSFIFO_HSGNLOUT: Header signaling 0: No header output. (unsigned)1: Output the 16 byte Header Signaling. [2:1] TSFIFO_ERRMODE: treatment of ERROR signal: 00: ERROR label the packets or frames in error. 01: ERROR = 0 The false packets or frames are deleted before being output. 10: ERROR = start of frame byte indicator (packet mode) ERROR = start of packet byte indicator (frame mode) The false packets or frames are deleted before being output. 11: ERROR = reference start of frame of the latency regulation. The false packets or frames are deleted before being output. (unsigned) [0] RST_HWARE: 1: Reset of Merger/HWare Stream line 1. (unsigned) 208/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 2 RST_HWARE 3 TSFIFO_HSGNLOUT 4 TSFIFO_DUTY50 5 TSFIFO_TEIUPDATE 6 TSFIFO_SERIAL TSFIFO_DVBCI 7 Configuration of Merger/HWare Stream line 1 TSFIFO_ERRMODE TSCFGH STiH271EL Front-end registers TSCFGM Configuration of Merger/HWare Stream line 1 1 0 RW RW R RW 0xF273 Type: RW Reset: 0x0 Description: Configuration of Merger/HWare Stream line 1 ti a l Address: en [7:6] TSFIFO_MANSPEED: CLKOUT frequency processing: 00: Automatic calculation 01: Automatic calculation while progressively keeping only the highest frequency (for ACM) 10: Automatic calculation of the instantaneous frequency without memorizing the highest frequency found 11: Manual (unsigned) fid [5] TSFIFO_PERMDATA: (active in serial and parallel) 1: switch DATA7<->DATA0 (unsigned) [4:1] RESERVED on [0] TSFIFO_INVDATA: 1: Inverse DATA7..0 (unsigned) TSCFGL 1 0 RESERVED 2 TSFIFO_DPUNACT 3 TSFIFO_EMBINDVB RW 4 TSFIFO_NSGNL2DATA 5 BCHERROR_MODE 6 C 7 Configuration of Merger/HWare Stream line 1 RW RW RW RW R Address: 0xF274 Type: RW Reset: 0x20 Description: Configuration of Merger/HWare Stream line 1 [7:6] TSFIFO_BCLKDEL1CK: 270 MHz delay cycle on CLKOUT with respect to other signals (STROUT, D/P, ERROR, DATA7..0) 00: (0) No delay01: (+1) Advance by one 216 MHz cycle 11: (-1) Move back by one 216 MHz cycle10: (-2) -- (unsigned) DocID023557 Rev 10 209/604 Information classified Confidential - Do not copy (See last page for obligations) 2 TSFIFO_INVDATA 3 RESERVED 4 TSFIFO_PERMDATA 5 TSFIFO_MANSPEED 6 TSFIFO_BCLKDEL1CK Confidential 7 Front-end registers STiH271EL [5:4] BCHERROR_MODE: error packet construction bit 1 at 0: Insert BBHeader CRC8 error and BCH error bit 0 at 0: Insert CRC8 packet error 00=packet error = BBHeader CRC8 error+BCH error+CRC8 packet error In general, in packet mode, it is not useful to insert BBHeader CRC8 error+BCH error in the final error packet. It is better to only insert CRC8 packet error (therefore bcherror_mode=10). In fact, if BBHeader CRC8 error+BCH error=1, in most cases a certain number of correct packets remain. They are detected with the CRC8 packet error. (unsigned) l [2] TSFIFO_EMBINDVB: 1: Load the short packets in an MPEG packet (unsigned) ti a [1] TSFIFO_DPUNACT: 1: Deactivate D/P (unsigned) 2 0xF276 Type: RW Reset: 0x0 R C Address: Description: 3 RESERVED RW 4 on RW 5 fid 6 TSDEL_XXHEADER 7 Insertion/deletion mask of output packet parts TSDEL_SYNCBYTE Confidential TSINSDELH en [0] RESERVED Insertion/deletion mask of output packet parts [7] TSDEL_SYNCBYTE: (1 byte) deletion of synchro word. (unsigned) [6] TSDEL_XXHEADER: (3 bytes) deletion of Packet Header. (unsigned) [5:0] RESERVED 210/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) [3] TSFIFO_NSGNL2DATA: 0: D/P=1 during Signaling Header and Footer (unsigned) 1: D/P=0 during Signaling Header and Footer STiH271EL Front-end registers TSSPEED CLKOUT frequency 7 6 5 4 3 2 1 0 Address: 0xF280 Type: RW Reset: Undefined Description: CLKOUT frequency TSSTATUS 3 2 1 0 fid RESERVED 4 en 5 TSFIFO_NOSYNC 6 TSFIFO_ERROR TSFIFO_LINEOK 0xF281 Type: R Reset: Undefined Description: Merger/HWare Stream status on Address: [7] TSFIFO_LINEOK: Inverse of the ERROR signal: 1: The ERROR signal is currently at 0 - no packets with errors at the moment - line OK (unsigned) C Confidential 7 Merger/HWare Stream status RESERVED ti a l [7:0] TSFIFO_OUTSPEED: Stream output frequency Parallel: Fclkout = 4 2 F/ px_tsfifo_outspeed Limited at px_tsfifo_outspeed >= 8 (Fclkout < (fCOFDM) Serial: Fclkout = 32 fCOFDM / 2 px_tsfifo_outspeed Limited at px_tsfifo_outspeed >= 32 (Fclkout < 1/2 fCOFDM) (unsigned) [6] TSFIFO_ERROR: Stored value of the ERROR signal 1: A packet in error has passed since the last I C reading of Px_TSSTATUS. Automatically reset to 0 after an I C read (read put to 0 on a read,unsigned) [5] RESERVED [4] TSFIFO_NOSYNC: tsfifo_nosync: Stream Merger/Hware line activity: 0: Synchronization is ongoing1: Not synchronized, nothing is output. Set to 0 after an I C read (read put to 0 on a read,unsigned) [3:0] RESERVED DocID023557 Rev 10 211/604 Information classified Confidential - Do not copy (See last page for obligations) TSFIFO_OUTSPEED Front-end registers STiH271EL Additional status of Merger/HWare Stream 0 RESERVED 1 SCRAMBDETECT 2 RESERVED 3 TSSERIAL_IMPOS 4 DILXX_RESET 5 TSFIFOSPEED_STORE 6 RESERVED 7 RW RW RW RW R RW R 0xF282 Type: RW Reset: Undefined Description: Additional status of Merger/HWare Stream ti a l Address: [7] RESERVED Confidential en [6] TSFIFOSPEED_STORE: 1: A CLKOUT speed change event (TSSPEED.TSFIFO_OUTSPEED) has occurred. Reset to 0 by an I C write (read put to 0 on a write,unsigned) fid [5] DILXX_RESET: 1: A FIFO or de-interleaver reset has occurred. There was a break in the data flow. Reset to 0 by an I C write (read put to 0 on a write,unsigned) [3:2] RESERVED on [4] TSSERIAL_IMPOS: 1: Throughput too high for a serial transmission (unsigned) [1] SCRAMBDETECT: 1: Detection (stable) of inverse synchro word, indicating the presence of scrambling. (unsigned) C [0] RESERVED TSBITRATEy 7 Observation of raw bit rate 6 5 4 3 TSBITRATE1 TSFIFO_BITRATE[15:8] TSBITRATE0 TSFIFO_BITRATE[7:0] Address: 0xF283 and 0xF284 Type: RW Reset: Undefined Description: Observation of raw bit rate 2 1 [7:0] TSFIFO_BITRATE: Bit rate = 2 fCOFDM TSFIFO_BITRATE / 16384 It is possible to write in this register to reinitialize the bit rate calculation. (unsigned) 212/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) TSSTATUS2 STiH271EL Front-end registers 7 Configuration of error counter 1 6 5 4 3 2 1 ERR_SOURCE1 RESERVED NUM_EVENT1 RW R RW Address: 0xF298 Type: RW Reset: 0x35 Description: Configuration of error counter 1 0 en fid on C Confidential ti a l [7:4] ERR_SOURCE1: Measurement unit (byte, packet, frame.), decimal point location, measurement point by mode Example: For option 0000, measurement unit is in bytes, the measurement value = Reg_value / 219 and this option measures demod errors only. 0000: byte 19 Demod bit errors 0001: Viterbi errors 0010: byte 23 Viterbi (ReedSolo) bit error) 0011: packet 23 Viterbi (ReedSolo) byte error 0100: Reserved 0101: byte 23 Viterbi (ReedSolo) bit error ~BER 0110: byte 23 Viterbi (ReedSolo) byte error ~BER) 0111: byte 23 Viterbi (ReedSolo) bit error BER 1000: byte 23 Viterbi (ReedSolo) byte error BER 1001: packet 23 Viterbi (ReedSolo) packet error 1010: packet 19 Viterbi (ReedSolo) packet error nbr 1011: Reserved 1100: packet 23 TS error count, packet error final 1101: 2 fCOFDM / 4K 7 TS FIFO 1110: frame 7 DFL 1111: 2 fCOFDM/512 23 Packet Rate Notes: - errcpt_size: counting unit - byte: bytes - packet: packets - 2 fCOFDM/512: Master COFDM clock/256 - 2 fCOFDM/4K: Master COFDM clock/2048 (unsigned) [3] RESERVED [2:0] NUM_EVENT1: time constant 000: count mode (WITH reset of counter upon reading) 001: count mode (WITHOUT reset of counter upon reading) The reset to 0 is achieved by writing (any value) in any of the three bytes of ERRCNT12/11/10. byte packetframe 24 010:214 28 011:216 210 26 | rate modes 18 12 100:2 2 28 | 210 | 101:220 214 110:222 216 212 111: ---- average mode --- (unsigned) DocID023557 Rev 10 213/604 Information classified Confidential - Do not copy (See last page for obligations) ERRCTRL1 Front-end registers STiH271EL 5 4 3 ERR_CNT1[22:16] 6 ERRCNT1_OLDVALUE 7 Result of error counter 1 R RW 0xF299 Type: RW Reset: Undefined Description: Result of error counter 1 1 0 ti a l Address: 2 en [7] ERRCNT1_OLDVALUE: Validity of the information read 0: New value (read put to 0 on a read,unsigned) 1: This value is old and has already been read by I C. Do not use it. 7 6 5 fid ERRCNT11 4 Result of error counter 1 3 2 1 0 ERR_CNT1[15:8] 0xF29A Type: RW Reset: Undefined Description: Result of error counter 1 on Address: C Confidential [6:0] ERR_CNT1: Result of counting (read put to 0 on a write,unsigned) [7:0] ERR_CNT1: Result of counting (read put to 0 on a write,unsigned) ERRCNT10 7 Result of error counter 1 6 5 4 3 2 ERR_CNT1[7:0] Address: 0xF29B Type: RW Reset: Undefined Description: Result of error counter 1 [7:0] ERR_CNT1: Result of counting (read put to 0 on a write,unsigned) 214/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) ERRCNT12 STiH271EL Front-end registers ERRCTRL2 7 Configuration of error counter 2 6 5 4 3 2 1 ERR_SOURCE2 RESERVED NUM_EVENT2 RW R RW Address: 0xF29C Type: RW Reset: 0xC1 Description: Configuration of error counter 2 0 [3] RESERVED ti a ERRCNT22 5 4 3 fid R 0xF29D Type: RW Reset: Undefined Description: Result of error counter 2 2 1 0 RW C on Address: Result of error counter 2 ERR_CNT2[22:16] en 6 ERRCNT2_OLDVALUE Confidential 7 l [2:0] NUM_EVENT2: Time constant (unsigned) [7] ERRCNT2_OLDVALUE: Validity of the information read (read put to 0 on a read,unsigned) [6:0] ERR_CNT2: Result of counting (read put to 0 on a write,unsigned) ERRCNT21 7 Result of error counter 2 6 5 4 3 2 1 0 ERR_CNT2[15:8] Address: 0xF29E Type: RW Reset: Undefined Description: Result of error counter 2 [7:0] ERR_CNT2: Result of counting (read put to 0 on a write,unsigned) DocID023557 Rev 10 215/604 Information classified Confidential - Do not copy (See last page for obligations) [7:4] ERR_SOURCE2: Measuring point (unsigned) Front-end registers STiH271EL ERRCNT20 7 Result of error counter 2 6 5 4 3 2 1 0 ERR_CNT2[7:0] Address: 0xF29F Type: RW Reset: Undefined Description: Result of error counter 2 FEC Spy Configuration 5 4 2 1 0 RESERVED en RW 0xF2A0 Type: RW Reset: 0xA0, 0x80 Description: FEC Spy Configuration fid Address: R C [6:0] RESERVED on [7] SPY_ENABLE: Operational state of the spy 0: Stopped/reset1: Functioning To completely reset the spy, simply write a 0 on this bit. (unsigned) FSPYCFG 3 1 0 R RW RW RW R Address: 0xF2A1 Type: RW Reset: 0x2C Description: FEC Spy Configuration [7:6] RESERVED 216/604 2 RESERVED 4 I2C_MODE 5 ONE_SHOT 6 RST_ON_ERROR 7 FEC Spy Configuration RESERVED Confidential 3 ti a 6 SPY_ENABLE 7 l FECSPY DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] ERR_CNT2: Result of counting (read put to 0 on a write,unsigned) STiH271EL Front-end registers [5] RST_ON_ERROR: Impact of an error detection 0: The FEC Spy will give the global number of good packets. To obtain a ratio of good packets. (unsigned) 1: The FEC Spy searches a number of adjoining good packets. ti a l [3:2] I2C_MODE: FEC Spy general function mode 00: Reserved. 01: Reserved. 10: Reserved. 11: BER/PER Meter mode. FPACKCNT.px_fpacket_counter contains the previous result. The output signals represent the previous result. The BER/PER Meter is master of FEC Spy synchro. (unsigned) R RW 3 fid RW 4 on SPY_CNULLPKT 5 RESERVED 6 SPY_STUFFING Address: 0xF2A2 Type: RW Reset: 0x3A Description: Tested packet contents 2 1 0 RW C Confidential 7 Tested packet contents SPY_OUTDATA_MODE FSPYDATA en [1:0] RESERVED [7] SPY_STUFFING: 0: All packets must be analyzed in the same way. 1: Indicate the possible presence of stuffing packets to the FEC Spy. They will be specifically analyzed as stuffing packets. (unsigned) [6] RESERVED DocID023557 Rev 10 217/604 Information classified Confidential - Do not copy (See last page for obligations) [4] ONE_SHOT: 0: The FEC Spy continuously restarts the test once finished. 1: Stop once the operation is finished. Relaunch the FEC Spy by a positive edge on FECSPY.px_spy_enable. (unsigned) Front-end registers STiH271EL [5] SPY_CNULLPKT: presence of Packet Header 0: Non TS Packet mode 1 synchro word DVB: 47 187 payload bytes for an MPEG packet. Confidential en ti a l [4:0] SPY_OUTDATA_MODE: form And type of data that the spy must expect to confirm: 43.210 00.000: No content verification, simply the form 00.001: DVB (+others): auto decrement 00.010: Auto increment, rising 00.011: Auto decrement, falling 00.1xx: Toggling data:~00.100: 55/AA 00.101: 66/99 00.110: C3/3C 00.111: 00/FF on fid 01.xxx: (Pseudo) Constants: 01.000: 00 01.001: 1 byte non null (value 0x01) every 256. 01.010: 55 01.011: 66 01.100: 99 01.101: AA 01.111: FF (the official MEPG stuffing packet). C 1x.xxx: PRBS modes: 10.000 6 : X6 + X5 + 1 Validated on BER Meter 10.001 7 : X7 + X6 + 1 Unknown on BER Meter 10.010 9 : X9 + X5 + 1 Validated on BER Meter 10.011 10: X10 + X7 + 1 Unknown on BER Meter 10.100 11: X11 + X9 + 1 Validated on BER Meter 10.101 15: X15 + X14 + 1 NON Validated on BER Meter 10.110 15: X15 + X14 Validated on BER Meter 10.111 17: X17 + X14 + 1 Validated on BER Meter 11.000 11.001 11.010 11.011 11.100 11.101 11.110 11.111 218/604 20: X20 + X17 + 1 Validated on BER Meter 23: X23 + X18 + 1 NON Validated on BER Meter 23: X23 + X18 Validated on BER Meter 31: X31 + X28 + 1 Unknown on BER Meter 41: X41 + X3 + 1 49: X49 + x9 + 1 --- (unsigned) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 1: Null TS Packet mode 1 synchro word: DVB: 47 3 Packet Header bytes: DVB: 1F,FE/FF,10 184 payload bytes for an MPEG packet. STiH271EL Front-end registers 4 3 2 1 STUFF_MODE 5 RESERVED 6 FSPY_DIRECT 7 FEC Spy miscellaneous configuration RW R RW 0xF2A3 Type: RW Reset: 0x7 Description: FEC Spy miscellaneous configuration l Address: 0 en ti a [7] FSPY_DIRECT: 0: Provide the signaling indications to the FEC Spy. The signaling bytes (if present) will be removed from the test. 1: Raw output flow test (without the SGNL[1:0] pins). The signaling bytes (if present) may cause test failure. (unsigned) fid [2:0] STUFF_MODE: Payload description of a stuffing packet: 000: 0x00001: DVB (+others): auto decrement 010: (test bus)011: Reserved. 100: PRBS 11101: PRBS 15 110: PRBS 23111: 0xFF (the official MEPG stuffing packet). (unsigned) 2 1 RESULT_STATE 3 DSS_SYNCBYTE R 4 FEC Spy Status FOUND_SIGNAL R 5 C 6 VALID_SIM 7 on FSTATUS SPY_ENDSIM Confidential [6:3] RESERVED R R R Address: 0xF2A4 Type: R Reset: Undefined Description: FEC Spy Status 0 [7] SPY_ENDSIM: 1: Test finished, the number of packets designated by FSPYCFG.spy_hysteresis have been seen. (unsigned) [6] VALID_SIM: 1: Test positive, there is the right number of good packets (see FSPYCFG.spy_hysteresis). (unsigned) DocID023557 Rev 10 219/604 Information classified Confidential - Do not copy (See last page for obligations) FSPYOUT Front-end registers STiH271EL [5] FOUND_SIGNAL: 0: False packet 1: Good packet (unsigned) 7 en 6 5 fid FBERCPT4 4 BER/PER Meter byte counter 3 2 1 0 FBERMETER_CPT[39:32] 0xF2A8 Type: RW Reset: Undefined Description: BER/PER Meter byte counter on Address: [7:0] FBERMETER_CPT: BYTE counter or total packets C Confidential ti a l [3:0] RESULT_STATE: Status of work in progress 0000: No signal 0001: Data correct 0010: Warning, packet declared false by the ERROR signal 0011: Error, packet false 0100: Warning, detection of inverse synchro word 0101: Error, bad synchro word 0110: -0111: Error, packet too long 1000: -1001: Warning, packet correct but disconnected from previous 1010: Warning, MPEG TEI bit at 1 1011: Stuffing packet good 1100: Warning, stuffing packet correct but disconnected from previous 1101: Error, packet too short 1110: -1111: -- (unsigned) FBERCPT3 7 6 BER/PER Meter byte counter 5 4 3 2 1 0 FBERMETER_CPT[31:24] Address: 0xF2A9 Type: RW Reset: Undefined Description: BER/PER Meter byte counter [7:0] FBERMETER_CPT: BYTE counter or total packets FECSPY.bermeter_lmode = 1 -> multiply the counting by 256: this therefore becomes a 48-bit counter, of which the eight LSBs are not visible. Ensure that the value in px_fbermeter_cpt is big enough (and so waits long enough) so that the resulting imprecision becomes negligible. (read put to 0 on a write,unsigned) 220/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [4] DSS_SYNCBYTE: Reserved STiH271EL Front-end registers FBERCPT2 7 BER/PER Meter byte counter 6 5 4 3 2 1 0 Address: 0xF2AA Type: RW Reset: Undefined Description: BER/PER Meter byte counter ti a l [7:0] FBERMETER_CPT: BYTE counter or total packets FECSPY.bermeter_lmode = 1 -> multiply the counting by 256: this therefore becomes a 48-bit counter, of which the eight LSBs are not visible. Ensure that the value in px_fbermeter_cpt is big enough (and so waits long enough) so that the resulting imprecision becomes negligible. (read put to 0 on a write,unsigned) FBERCPT1 6 5 4 3 2 1 0 en 7 BER/PER Meter byte counter 0xF2AB Type: RW Reset: Undefined Description: BER/PER Meter byte counter fid Address: on [7:0] FBERMETER_CPT: BYTE counter or total packets FECSPY.bermeter_lmode = 1 -> multiply the counting by 256: this therefore becomes a 48-bit counter, of which the 8 LSBs are not visible. Ensure that the value in px_fbermeter_cpt is big enough (and so waits long enough) so that the resulting imprecision becomes negligible. (read put to 0 on a write,unsigned) C Confidential FBERMETER_CPT[15:8] FBERCPT0 7 6 BER/PER Meter byte counter 5 4 3 2 1 0 FBERMETER_CPT[7:0] Address: 0xF2AC Type: RW Reset: Undefined Description: BER/PER Meter byte counter [7:0] FBERMETER_CPT: BYTE counter or total packets FECSPY.bermeter_lmode = 1 -> multiply the counting by 256: this therefore becomes a 48-bit counter, of which the 8 LSBs are not visible. Ensure that the value in fbermeter_cpt is big enough (and so waits long enough) so that the resulting imprecision becomes negligible. (read put to 0 on a write,unsigned) DocID023557 Rev 10 221/604 Information classified Confidential - Do not copy (See last page for obligations) P1_FBERMETER_CPT[23:16] Front-end registers STiH271EL BER/PER Meter error bit counter 7 6 5 4 3 2 FBERERR2 FBERMETER_ERR[23:16] FBERERR1 FBERMETER_ERR[15:8] FBERERR0 FBERMETER_ERR[7:0] Address: 0xF2AD, 0xF2AE and 0xF2AF Type: RW Reset: Undefined Description: BER/PER Meter error bit counter 1 0 en fid 3 2 1 FSPYBER_CTIME R 4 FSPYBER_UNSYNC 5 BER/PER Meter configuration FSPYBER_SYNCBYTE 6 C 7 on FSPYBER RESERVED Confidential ti a l [7:0] FBERMETER_ERR: Counter of BITs or packets in error fbermeter_err is not affected by FECSPY/bermeter_lmode. Important note: Regardless of mode, fbermeter_cpt and fbermeter_err are read in coherence: reading register FBERCPT4 provokes a sampling of fbermeter_cpt and fbermeter_err in the register buffers. It is those register buffers that will be read as long as a new reading of the FBERCPT4 register has not been made. In rate mode (FSPYBER/fspyber_ctime different from 000 and 001), if a new measuring result arrives while a read is in progress (ie: FBERCPT4 has been read, but FBERERR0 has not yet been read), it will be lost. Writing in any of the FBERCPT4..FBERCPT0 or FBERERR2..FBERERR0 registers at any time resets fbermeter_cpt and fbermeter_err to 0 (reset). This also resets FSPYOBS7..0 (the FEC Spy observer, see below). (read put to 0 on a write,unsigned) RW RW RW Address: 0xF2B2 Type: RW Reset: 0x10 Description: BER/PER Meter configuration 0 [7:5] RESERVED [4] FSPYBER_SYNCBYTE: 1: Reset of BER/PER Meter if error on synchro word and if result_state = 0x7 or 0xD (that is, packet too short or too long). (unsigned) [3] FSPYBER_UNSYNC: 0: No reset, wait for it to come back by itself 1: reset of BER/PER Meter if desynchronization (unsigned) 222/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) FBERERRy STiH271EL Front-end registers [2:0] FSPYBER_CTIME: BER/PER measuring time 000: Counting the error bits or packets to infinity 001: Reserved 010: Measure on 216 bytes 29 packets 011: Measure on 218 bytes 211 packets 100: Measure on 220 bytes 213 packets 101: Measure on 222 bytes 215 packets 110: Measure on 234 bytes 217 packets 111: Measure on 226 bytes 219 packets The FECSPY.bermeter_lmode = 1 mode adds 8 to the exponent. (unsigned) 6 5 4 3 Type: RW Reset: 0x0 Description: RW R en 0xF230 0 RESERVED The bits 7..3 only apply in TSGENERAL/tsfifo_permparal=11 (MuxStream) mode. fid [7:3] RESERVED [0] RESERVED 10.3 on [2:1] TSFIFO_PERMPARAL: parallel bus allocation 00: On line 1 output 01: On line 2 output 10: On line RC output 11: MuxStream mode 1&2. Multiplexing DATA6..0 permitting the two data flows to be transmitted in parallel. (unsigned) C Confidential R 1 TSFIFO_PERMPARAL ti a RESERVED Address: 2 l 7 General configuration of Merger/HWare Stream QAM global registers CTRL_0 7 6 Control 0 5 4 3 RESERVED Address: 0xF401 Type: RW Reset: 0x42 Description: Control 0. 2 1 0 STANDBY RESERVED [7:2] RESERVED [1] STANDBY: When set, clock for all digital blocks (except I C and register block) are stopped. [0] RESERVED DocID023557 Rev 10 223/604 Information classified Confidential - Do not copy (See last page for obligations) TSGENERAL Front-end registers STiH271EL CTRL_1 Control 1 7 6 5 SOFT_RESET 4 RESERVED Address: 0xF402 Type: RW Reset: 0x3F 3 2 1 0 EQU_RST CRL_RST TRL_RST AGC_RST [6:4] RESERVED [3] EQU_RST: Equalizer soft reset 0: inactive1: active ti a l [7] SOFT_RESET: 1: Reset all blocks except the I C. This bit is self-clearing. en [1] TRL_RST: Timing recovery loop soft reset 0: inactive1: active fid [0] AGC_RST: AGC soft reset 0: inactive1: active Address: 0xF403 Type: RW Reset: 0x01 3 2 Description: [7:4] RESERVED [3] DEINT_RST: De-interleaver soft reset 0: Inactive1: Active [2] FECAC_RS_RST: Reed-Solomon soft reset. 0: Inactive1: Active [1:0] RESERVED 224/604 DocID023557 Rev 10 1 0 RESERVED 4 FECAC_RS_RST 5 Control 2 DEINT_RST 6 RESERVED 7 on CTRL_2 C Confidential [2] CRL_RST: Carrier recovery loop soft reset 0: inactive1: active Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL Front-end registers R Reset: 0x00 0 AGC_LOCK 1 Information classified Confidential - Do not copy (See last page for obligations) Type: 2 ti a l 0xF408 3 ADJ_AGC_LOCK CRL_LOCK Address: 4 TRL_LOCK 5 MFSM_CHANGED 6 CRL_FSM_CHANGED SWEEP_OUTOF_RANGE 7 IT status 1 TRL_AGC_THRES IT_STATUS1 Description: en [6] CRL_FSM_CHANGED: status enabled by register 0x0A 0: No change1: The CRL FSM is changed fid [5] CRL_LOCK: status enabled by register 0x0A 0: The CRL is unlocked1: The CRL is locked [4] MFSM_CHANGED: status enabled by register 0x0A 0: No change1: The main FSM has changed its mode on [3] TRL_LOCK: status enabled by register 0x0A 0: The TRL is unlocked1: The TRL is locked [2] TRL_AGC_THRES: status enabled by register 0x0A 0: No threshold reached1: One of the TRL AGC threshold is reached [1] ADJ_AGC_LOCK: status enabled by register 0x0A 0: Adjacent AGC is unlocked1: Adjacent AGC is locked C Confidential [7] SWEEP_OUTOF_RANGE: Status enabled by register 0x0A 0: Sweep is ok1: The sweep mode is out of range [0] AGC_LOCK: status enabled by register 0x0A 0: AGC is unlocked1: AGC is locked DocID023557 Rev 10 225/604 Front-end registers STiH271EL R Reset: 0x00 1 0 TAPMONITOR_ALARM ti a Description: en [7] CONTCNT: Status enabled by register 0x0B 0: Continuity is good 1: Receive header with an invalid continuity field mask Confidential [6] END_FRAME_HEADER: status enabled by register 0x0B 0: No header received1: Receive header with mask fid [5] UPDATE_READY: status enabled by register 0x0B 0: No new header received1: Receive new header with mask [4] RESERVED on [3] DESCR_SYNSTATE: Status enabled by register 0x0B 0: Descrambler is not in sync state1: Descrambler is in sync state [2] DEINT_LOCK: status enabled by register 0x0B 0: De-interleaver is unlocked1: De-interleaver is locked C [1] RESERVED [0] TAPMONITOR_ALARM: Status enabled by register 0x0B 0: No limiter reached1: The FFE or DFE tap has reached the limiter 226/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Type: 2 l 0xF409 3 RESERVED UPDATE_READY Address: 4 DESCR_SYNCSTATE 5 RESERVED 6 END_FRAME_HEADER CONTCNT 7 IT status 2 DEINT_LOCK IT_STATUS2 STiH271EL Front-end registers RW Reset: 0x00 AGC_LOCK_EN 0 ti a Description: en [7] SWEEP_OUTOF_RANGE_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 7 is enabled fid [6] CRL_FSM_CHANGED_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 6 is enabled on [5] CRL_LOCK_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 5 is enabled [4] MFSM_CHANGED_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 4 is enabled [3] TRL_LOCK_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 3 is enabled C Confidential 1 Information classified Confidential - Do not copy (See last page for obligations) Type: 2 l 0xF40A 3 ADJ_AGC_LOCK_EN CRL_LOCK_EN Address: 4 TRL_LOCK_EN 5 MFSM_CHANGED_EN 6 CRL_FSM_CHANGED_EN SWEEP_OUTOF_RANGE_EN 7 IT enable 1 TRL_AGC_THRES_EN IT_EN1 [2] TRL_AGC_THRES_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 2 is enabled [1] ADJ_AGC_LOCK_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 1 is enabled [0] AGC_LOCK_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x08 bit 0 is enabled DocID023557 Rev 10 227/604 Front-end registers STiH271EL RW Reset: 0x00 ti a Description: Confidential en [7] CONTCNT_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x09 bit 7 is enabled fid [6] END_FRAME_HEADER_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x09 bit 6 is enabled [4] RESERVED on [5] UPDATE_READY_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x09 bit 5 is enabled C [3] DESCR_SYNSTATE_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x09 bit 3 is enabled [2] DEINT_LOCK_EN: 0: Interrupt status disabled 1: Interrupt status of register 0x09 bit 2 is enabled [1] RESERVED [0] TAPMONITOR_ALARM: 0: Interrupt status disabled 1: Interrupt status of register 0x09 bit 0 is enabled 228/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) Type: l 0xF40B TAPMONITOR_ALARM 3 RESERVED UPDATE_READY_EN Address: 4 DESCR_SYNCSTATE_EN 5 RESERVED 6 END_FRAME_HEADER_EN CONTCNT_EN 7 IT enable 2 DEINT_LOCK_EN IT_EN2 STiH271EL Front-end registers CTRL_STATUS 7 CTRL status 6 5 4 3 RESERVED Address: 0xF40C Type: R Reset: 0x00 2 1 0 QAMFEC_LOCK TSMF_LOCK TSMF_ERROR Description: l [2] QAMFEC_LOCK: =1 when master state machine status = 0x0C or 0x0B and descr_syncstate = 1 ti a [1] TSMF_LOCK: 0: tsmf is unlocked1: tsmf is locked en QAM AGC registers QAM_AGC_CTL 7 6 5 Address: 0xF410 Type: RW Reset: 0x72 Description: 4 Main AGC control 3 RESERVED 2 1 0 AGC_ACCUMRSTSEL[2:0] on AGC_LCK_TH[3:0] fid 10.4 C Confidential [0] TSMF_ERROR: 0: Normal mode1: tsmf problem [7:4] AGC_LCK_TH[3:0]: AGC lock threshold. If the difference of two consecutive average power measures are lower than agc_lck_th, then the main AGC can be considered as locked. 0 is a forbidden value. This value is unsigned. [3] RESERVED [2:0] AGC_ACCUMRSTSEL[2:0]: AGC average magnitude calculation frequency: F = FADC/ (2(12+agc_accumrstsel[2:0])) The initial value is 12.2 kHz (82 s) when FADC = 50 MHz DocID023557 Rev 10 229/604 Information classified Confidential - Do not copy (See last page for obligations) [7:3] RESERVED Front-end registers STiH271EL 4 3 Address: 0xF411 Type: RW Reset: 0x60 2 RESERVED 0 ti a l Description: 1 [7:4] AGC_IF_BWSEL[3:0]: AGC IF/RF loop gain. The gain is equal to 2(11-agc_if_bwsel). The range of value used is 5... 11. This value is used for both IF and RF loops. Special: when agc_if_bwsel is equal to 0, the gain is 26. en [1] AGC_IF_FREEZE: 0: AGC IF running1: AGC IF frozen 0xF412 Type: RW Reset: 0x00 3 2 RESERVED C Address: 4 1 0 RESERVED 5 on 6 AGC_RF_BWSEL[2:0] 7 AGC RF configuration AGC_RF_FREEZE QAM_AGC_RF_CFG fid [0] RESERVED RESERVED Confidential [3:2] RESERVED Description: [7] RESERVED [6:4] AGC_RF_BWSEL[2:0]: AGC RF loop gain. The gain is proportional to 23+agc_rf_bwsel. [3:2] RESERVED [1] AGC_RF_FREEZE: 0: AGC RF running1: AGC RF frozen [0] RESERVED 230/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 5 AGC_IF_FREEZE 6 AGC_IF_BWSEL[3:0] 7 AGC IF configuration RESERVED QAM_AGC_IF_CFG STiH271EL Front-end registers 3 RESERVED 0xF413 Type: RW Reset: 0x03 1 0 l Address: 2 AGC_PWM_CLKDIV[1:0] 4 AGC_IF_PWM_INV 5 AGC_IF_PWM_TST 6 AGC_RF_PWM_INV AGC_RF_PWM_TST 7 PWM AGC configuration ti a Description: en [7] AGC_RF_PWM_TST: Internal RF AGC bypass 0: RF pwm output comes from AGC loop 1: RF pwm output comes from registers 0xF422 and 0xF423 Confidential [6] AGC_RF_PWM_INV: Polarity inversion of RF pwm output 0: No inversion1: Inversion [5:4] RESERVED fid [3] AGC_IF_PWM_TST: Internal IF AGC bypass 0: IF pwm output comes from AGC loop 1: IF pwm output comes from registers 0xF420 and 0xF421 on [2] AGC_IF_PWM_INV: Polarity inversion of IF pwm output 0: No inversion1: Inversion C [1:0] AGC_PWM_CLKDIV[1:0]: Frequency selection for pwm outputs 00: PWM frequency = FADC/201: PWM frequency = FADC/4 10: PWM frequency = FADC/811: PWM clock = FADC/16 QAM_AGC_PWR_REF_L 7 6 Main AGC power level 5 4 3 2 1 0 AGC_PWRREF[7:0] Address: 0xF414 Type: R Reset: 0x6E Description: [7:0] AGC_PWRREF[7:0]: AGC power level reference (lower part). This value depends on the QAM size of the signal. The value to be given should be unsigned. DocID023557 Rev 10 231/604 Information classified Confidential - Do not copy (See last page for obligations) QAM_AGC_PWM_CFG Front-end registers STiH271EL QAM_AGC_PWR_REF_H 7 6 Main AGC power level 5 4 3 2 RESERVED Address: 0xF415 Type: RW Reset: 0x00 1 0 AGC_PWRREF[9:8] Description: [7:2] RESERVED 7 6 5 ti a QAM_AGC_RF_TH_L 4 3 AGC RF threshold 2 1 0 Type: RW Reset: 0xCC en 0xF416 fid Address: Description: QAM_AGC_RF_TH_H 7 6 on [7:0] AGC_RF_TH[7:0]: RF AGC threshold (lower part). If IF AGC error signal is between IF AGC low and high thresholds, then RF AGC error signal is equal to RF AGC threshold. The value is signed. C Confidential AGC_RF_TH[7:0] 5 AGC RF threshold 4 3 RESERVED Address: 0xF417 Type: RW Reset: 0x04 2 1 AGC_RF_TH[11:8] Description: [7:4] RESERVED [3:0] AGC_RF_TH[11:8]: RF AGC threshold (higher part). See description above. 232/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) l [1:0] AGC_PWRREF[9:8]: AGC power level reference (higher part). See description above. STiH271EL Front-end registers QAM_AGC_IF_LTH_L 7 AGC IF low threshold 6 5 4 3 2 1 0 AGC_IF_THLO[7:0] Address: 0xF418 Type: RW Reset: 0x00 Description: 7 6 5 ti a QAM_AGC_IF_LTH_H 4 3 0xF419 Type: RW Reset: 0x08 2 1 0 AGC_IF_THLO[11:8] en Address: fid Description: [7:4] RESERVED QAM_AGC_IF_HTH_L 7 6 on [3:0] AGC_IF_THLO[11:8]: IF AGC low threshold (higher part). See description above. 5 C Confidential RESERVED AGC IF low threshold Address: 0xF41A Type: RW Reset: 0x00 AGC IF high threshold 4 3 2 1 0 AGC_IF_THHI[7:0] Description: [7:0] AGC_IF_THHI[7:0]: IF AGC high threshold (lower part). If IF AGC error signal is greater than this threshold, then the RF AGC is allowed to change. The value is signed. DocID023557 Rev 10 233/604 Information classified Confidential - Do not copy (See last page for obligations) l [7:0] AGC_IF_THLO[7:0]: IF AGC low threshold (lower part). if IF AGC error signal is lower than this threshold, then the RF AGC is allowed to change. The value is signed. Front-end registers STiH271EL QAM_AGC_IF_HTH_H 7 AGC IF high threshold 6 5 4 3 2 RESERVED Address: 0xF41B Type: RW Reset: 0x00 1 0 AGC_IF_THHI[11:8]] Description: [7:4] RESERVED 7 6 5 ti a QAM_AGC_PWR_RD_L 4 3 AGC word read 2 1 0 Type: R Reset: NA en 0xF41C fid Address: Description: on [7:0] AGC_PWR_WORD[7:0]: Power estimation performed in the Main AGC. This value is used for both IF and RF AGC loops. This value corresponds to the integration of the power over the time fixed by agc_accumrstsel[2:0]. The value to be read is signed and always negative. QAM_AGC_PWR_RD_M 7 6 C Confidential AGC_PWR_WORD[7:0] Address: 0xF41D Type: R Reset: NA 5 AGC word read 4 3 AGC_PWR_WORD[15:8] Description: [7:0] AGC_PWR_WORD[15:8]: See description above. 234/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) l [3:0] AGC_IF_THHI[11:8]: IF AGC high threshold (higher part). See description above STiH271EL Front-end registers QAM_AGC_PWR_RD_H 7 6 AGC word read 5 4 3 2 RESERVED Address: 0xF41E Type: R Reset: NA 1 0 AGC_PWR_WORD[17:16] Description: [7:2] RESERVED 7 6 5 ti a QAM_AGC_PWM_IFCMD_L 4 3 PWM AGC IF command 2 1 0 Type: RW Reset: 0x00 en 0xF420 fid Address: Description: on [7:0] AGC_IF_PWMCMD[7:0]: When agc_if_pwm_tst is active, this register is RW and its value is sent to the agc_pwm IF block. When agc_pwm_tst is inactive, this register is RO and its value corresponds to the command generated by the agc IF block. When agc_if_pwm_tst is active, the value to be written should be signed. The value is sent to AGC only when the MSB is written. This value is buffered when the LSB is read. C Confidential AGC_IF_PWMCMD[7:0] QAM_AGC_PWM_IFCMD_H 7 6 5 PWM AGC IF command 4 3 RESERVED Address: 0xF421 Type: RW Reset: 0x00 2 1 0 AGC_IF_PWMCMD[11:8] Description: [7:4] RESERVED [3:0] AGC_IF_PWMCMD[11:8]: See description above. DocID023557 Rev 10 235/604 Information classified Confidential - Do not copy (See last page for obligations) l [1:0] AGC_PWR_WORD[17:16]: See description above. Front-end registers STiH271EL QAM_AGC_PWM_RFCMD_L 7 6 5 PWM AGC RF command 4 3 2 1 0 AGC_RF_PWMCMD[7:0] Address: 0xF422 Type: RW Reset: 0x00 7 6 5 4 0xF423 Type: RW Reset: 0x08 Description: [7:4] RESERVED on Address: 3 fid RESERVED PWM AGC RF command [3:0] AGC_RF_PWMCMD[11:8]: See description above. C Confidential QAM_AGC_PWM_RFCMD_H en ti a l [7:0] AGC_RF_PWMCMD[7:0]: When agc_rf_pwm_tst is active, this register is RW and its value is sent to the agc_pwm RF block. When agc_pwm_tst is inactive, this register is RO and its value corresponds to the command generated by the agc RF block. When agc_rf_pwm_tst is active, the value to be written should be signed. The value is sent to AGC only when the MSB is written This value is buffered when the LSB is read 236/604 DocID023557 Rev 10 2 1 AGC_RF_PWMCMD[11:8] 0 Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL QAM demod registers 4 3 2 0xF424 Type: RW Reset: 0x00 ti a Description: [7:3] RESERVED en [2] IQDEM_CLK_SEL: Sampling frequency of ADC and derotator operating frequency. This bit works in conjunction with BKP_MODE (see IT_STATUS1 register). 0: FADC = sysclock1: FADC = sysclock/2 fid [1] IQDEM_INVIQ: swap of derotator outputs (i and q) 0: Inactive1: Active [0] IQDEM_A2DTYPE: ADC output format 0: Offset binary1: Two's complemented 7 on MIX_NCO_LL 6 5 4 Mixer NCO constant 3 2 1 0 MIX_NCO_INC[7:0] C Confidential 0 l Address: 1 Address: 0xF425 Type: RW Reset: 0x0A Description: [7:0] MIX_NCO_INC[7:0]: When writing, NCO increment value for the carrier recovery loop, computed according to the formula: (Ftuner 223) / FADC if no spectrum inversion (FADC - Ftuner) 223) / FADC if spectrum inversion The value is sent only when the MSB is written. When reading, this represents the summation of the NCO increment with the frequency correction. When the LSB of this value is read, this value is buffered. DocID023557 Rev 10 237/604 Information classified Confidential - Do not copy (See last page for obligations) 5 IQDEM_CLK_SEL 6 RESERVED 7 IQDEM configuration IQDEM_A2DTYPE IQDEM_CFG IQDEM_INVIQ 10.5 Front-end registers Front-end registers STiH271EL MIX_NCO_HL 7 Mixer NCO constant 6 5 4 3 2 1 0 MIX_NCO_INC[15:8] Address: 0xF426 Type: RW Reset: 0xD7 Description: ti a 5 4 Address: 0xF427 Type: RW Reset: 0x23 on Description: 2 fid en 3 MIX_NCO_INC[22:16] 6 MIX_NCO_INVCNST [7] MIX_NCO_INVCNST: indication of mixer nco way of turning 0: Clockwise1: Counterclockwise [6:0] MIX_NCO_INC[22:16]: See above for more information C Confidential 7 Mixer NCO constant l MIX_NCO_LH 238/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:0] MIX_NCO_INC[15:8]: See above for more information. STiH271EL Front-end registers SRC_NCO_LL 7 SRC NCO constant 6 5 4 3 2 1 0 SRC_NCO_INC[7:0] Address: 0xF428 Type: RW Reset: 0x33 7 6 5 4 SRC NCO constant 3 2 1 0 0xF429 Type: RW Reset: 0x33 on Address: fid SRC_NCO_INC[15:8] Description: [7:0] SRC_NCO_INC[15:8]: See above for more information. C Confidential SRC_NCO_LH en ti a l [7:0] SRC_NCO_INC[7:0]: When writing, this represents the NCO increment value for the timing recovery loop, computed according to the formula: (2 Fsymbol 230) / (Fsystem/2) The value is sent only when the MSB is written. When reading, this represents the summation of the NCO increment with the time correction (src_nco_inc_rd). When the LSB of this value is read, this value is buffered. SRC_NCO_HL 7 6 SRC NCO constant 5 4 3 2 1 0 SRC_NCO_INC[23:16] Address: 0xF42A Type: RW Reset: 0x33 Description: [7:0] SRC_NCO_INC[23:16]: See above for more information. DocID023557 Rev 10 239/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL SRC_NCO_HH 7 SRC NCO constant 6 5 4 RESERVED 3 2 1 0 SRC_NCO_INC[30:24] Address: 0xF42B Type: RW Reset: 0x23 Description: ti a l [6:0] SRC_NCO_INC[29:24]: For write only data and SRC_NCO_INC[30:24] for read only data. See above for more information. IQDEM_GAIN_SRC_L 6 5 4 3 2 1 0 en 7 IQDEM SRC gain 0xF42C Type: RW Reset: 0x22 fid Address: Description: on [7:0] IQDEM_GAIN_SRC[7:0]: Value of the SRC gain (low part). This value depends on both symbol rate frequency and Fsystem according to the formula: 2 x F symbol SRC_GAIN = -----------------------------------878 x F system 21 C Confidential IQDEM_GAIN_SRC[7:0] IQDEM_GAIN_SRC_H 7 6 IQDEM SRC gain 5 4 3 RESERVED Address: 0xF42D Type: RW Reset: 0x01 2 1 0 IQDEM_GAIN_SRC[9:8] Description: [7:2] RESERVED [1:0] QDEM_GAIN_SRC[9:8]: Value of the SRC gain (high part). See above for more information. 240/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7] RESERVED STiH271EL Front-end registers IQDEM_DCRM_CFG_LL 7 6 DCRM forced values 5 4 3 2 1 0 DCRM0_DCIN[7:0] Address: 0xF430 Type: RW Reset: 0x00 Description: 7 6 5 ti a IQDEM_DCRM_CFG_LH 4 3 0xF431 Type: RW Reset: 0x00 2 1 0 DCRM0_DCIN[9:8] en Address: fid Description: [7:2] DCRM1_I_DCIN[5:0]: dcrm1_i forced value LSB when dcrm1_frz is set else dcrm1 offset computed by the chip. on [1:0] DCRM0_DCIN[9:8]: dcrm0 forced value MSB when dcrm0_frz is set else dcrm0 offset computed by the chip. IQDEM_DCRM_CFG_HL 7 6 C Confidential DCRM1_I_DCIN[5:0] DCRM forced values 5 DCRM forced values 4 3 DCRM1_Q_DCIN[3:0] Address: 0xF432 Type: RW Reset: 0x00 2 1 0 DCRM1_I_DCIN[9:6] Description: [7:4] DCRM1_Q_DCIN[3:0]: dcrm1_q forced value LSB when dcrm1_frz is set else dcrm1 offset computed by the chip. [3:0] DCRM1_I_DCIN[9:6]: dcrm1_i forced value MSB when dcrm1_frz is set else dcrm1 offset computed by the chip. DocID023557 Rev 10 241/604 Information classified Confidential - Do not copy (See last page for obligations) l [7:0] DCRM0_DCIN[7:0]: dcrm0 forced value LSB when dcrm0_frz is set else dcrm0 offset computed by the chip. Front-end registers STiH271EL IQDEM_DCRM_CFG_HH 7 6 DCRM1_FRZ DCRM0_FRZ DCRM forced values 5 4 3 2 1 0 DCRM1_Q_DCIN[9:4] Address: 0xF433 Type: RW Reset: 0x00 Description: ti a l [6] DCRM0_FRZ: 0: Normal mode1: dcrm1 offset forced 7 6 5 4 3 Adjacent IIR filter coefficient 2 1 0 0xF434 Type: RW Reset: 0xE4 on Address: fid ADJIIR_COEFF10[7:0] Description: [7:0] ADJIIR_COEFF10[7:0]: Adjacent Filter Coeff10 LSB (unsigned). C Confidential IQDEM_ADJ_COEFF0 en [5:0] DCRM1_Q_DCIN[9:2]: dcrm1_q forced value MSB when dcrm0_frz is set else dcrm1 offset computed by the chip. IQDEM_ADJ_COEFF1 7 6 Adjacent IIR filter coefficient 5 4 3 2 ADJIIR_COEFF11[5:0] Address: 0xF435 Type: RW Reset: 0xB1 Description: [7:2] ADJIIR_COEFF11[5:0]: Adjacent Filter Coeff11 LSB (unsigned). [1:0] ADJIIR_COEFF10[9:8]: Adjacent Filter Coeff10 MSB (unsigned). 242/604 DocID023557 Rev 10 1 0 ADJIIR_COEFF10[9:8] Information classified Confidential - Do not copy (See last page for obligations) [7] DCRM1_FRZ: 0: Normal mode1: dcrm0 offset forced STiH271EL Front-end registers IQDEM_ADJ_COEFF2 7 6 Adjacent IIR filter coefficient 5 4 3 2 ADJIIR_COEFF12[3:0] Address: 0xF436 Type: RW Reset: 0x05 1 0 ADJIIR_COEFF11[9:6] Description: [7:4] ADJIIR_COEFF12[3:0]: Adjacent Filter Coeff12 LSB (signed). 7 6 5 ti a IQDEM_ADJ_COEFF3 4 3 2 1 0 0xF437 Type: RW Reset: 0xBE fid Address: en ADJIIR_COEFF12[9:4] Description: [7:6] ADJIIR_COEFF20[1:0]: Adjacent Filter Coeff20 LSB (unsigned). IQDEM_ADJ_COEFF4 7 6 Address: 0xF438 Type: RW Reset: 0x79 on [5:0] ADJIIR_COEFF12[9:4]: Adjacent Filter Coeff12 MSB (signed). C Confidential ADJIIR_COEFF20[1:0] Adjacent IIR filter coefficient 5 Adjacent IIR filter coefficient 4 3 2 1 0 ADJIIR_COEFF20[9:2] Description: [7:0] ADJIIR_COEFF20[9:2]: Adjacent Filter Coeff20 MSB (unsigned). DocID023557 Rev 10 243/604 Information classified Confidential - Do not copy (See last page for obligations) l [3:0] ADJIIR_COEFF11[9:6]: Adjacent Filter Coeff11 MSB (unsigned). Front-end registers STiH271EL IQDEM_ADJ_COEFF5 7 Adjacent IIR filter coefficient 6 5 4 3 2 1 0 ADJIIR_COEFF21[7:0] Address: 0xF439 Type: RW Reset: 0x53 Description: 6 5 4 3 Type: RW Reset: 0x37 1 0 ADJIIR_COEFF21[9:8] en 0xF43A 2 fid Description: [7:2] ADJIIR_COEFF22[5:0]: Adjacent Filter Coeff22 LSB (signed). IQDEM_ADJ_COEFF7 7 6 on [1:0] ADJIIR_COEFF21[9:8]: Adjacent Filter Coeff21 MSB (unsigned). 5 Adjacent IIR filter coefficient 4 3 RESERVED 2 Address: 0xF43B Type: RW Reset: 0x03 Description: [7:4] RESERVED [3:0] ADJIIR_COEFF22[9:6]: Adjacent Filter Coeff22 MSB (signed). 244/604 1 ADJIIR_COEFF22[9:6] C Confidential ADJIIR_COEFF22[5:0] Address: ti a 7 Adjacent IIR filter coefficient l IQDEM_ADJ_COEFF6 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [7:0] ADJIIR_COEFF21[7:0]: Adjacent Filter Coeff21 LSB (unsigned). STiH271EL Front-end registers 3 Address: 0xF43C Type: RW Reset: 0x0D 2 ADJ_AGC_EN 0 ti a l Description: 1 [7:4] RESERVED [3] ALLPASSFILT_EN: 0: Allpass filter disabled1: Allpass filter enabled en fid [1] ADJ_COEFF_FRZ: 0: Adjacent filter coefficients sent to demodulator 1: Adjacent filter coefficients frozen [0] ADJ_EN: 0: Adjacent filter disabled1: Adjacent filter enabled 7 on IQDEM_ADJ_AGC_REF 6 5 4 Adjacent AGC reference 3 2 1 0 ADJ_AGC_REF[7:0] C Confidential [2] ADJ_AGC_EN: 0: Adjacent AGC disabled1: Adjacent AGC enabled Address: 0xF43D Type: RW Reset: 0x00 Description: [7:0] ADJ_AGC_REF[7:0]: Adjacent AGC reference. DocID023557 Rev 10 245/604 Information classified Confidential - Do not copy (See last page for obligations) 4 ADJ_EN 5 ALLPASSFILT_EN 6 RESERVED 7 Adjacent IIR filter enable ADJ_COEFF_FRZ IQDEM_ADJ_EN Front-end registers 10.6 STiH271EL QAM all-pass filter registers ALLPASSFILT(1)(2)(3) 7 All pass coefficients 6 5 4 3 2 1 0 ALLPASSFILT_COEFF1[7:0] ALLPASSFILT_COEFF1[15:8] ALLPASSFILT_COEFF1[21:16] Address: 0xF440, 0xF441, 0xF442 Type: RW Reset: 0x6A, 0xF1, 0x2A ti a l Description: [21:0] ALLPASSFILT_COEFF1: Coefficient 1 of the allpass filter. 6 5 4 3 All pass coefficients 2 1 0 ALLPASSFILT_COEFF2[9:2] fid ALLPASSFILT_COEFF2[17:10] ALLPASSFILT_COEFF3[3:0] ALLPASSFILT_COEFF2[21:18] ALLPASSFILT_COEFF3[11:4] 0xF443, 0xF444, 0xF445 Type: RW Reset: 0x2F, 0x36, 0x78, 0x8C on Address: Description: [21:0] ALLPASSFILT_COEFF2: Coefficient 2 of the allpass filter. C Confidential 7 en ALLPASSFILT(4)(5)(6) ALLPASSFILT(7)(8)(9) 7 6 All pass coefficients 5 4 3 2 1 0 ALLPASSFILT_COEFF3[19:12] ALLPASSFILT_COEFF4[5:0] ALLPASSFILT_COEFF4[13:6] Address: 0xF446,0xF447, 0xF448 Type: RW Reset: 0xF6, 0x91, 0x74 Description: [21:0] ALLPASSFILT_COEFF3: Coefficient 3 of the allpass filter. 246/604 DocID023557 Rev 10 ALLPASSFILT_COEFF3[21:20] Information classified Confidential - Do not copy (See last page for obligations) ALLPASSFILT_COEFF2[1:0] STiH271EL Front-end registers ALLPASSFILT(10)(11) 7 6 All pass coefficients 5 4 3 2 1 0 ALLPASSFILT_COEFF4[21:14] Address: 0xF449,0xF44A Type: RW Reset: 0x6C Description: 4 Type: RW Reset: 0x20 en 0xF450 3 2 1 0 fid Address: ti a 5 TRL_AGC_REF[6:0] 6 TRL_AGC_FREEZE on Description: [7] TRL_AGC_FREEZE: Digital AGC factor embedded in the Timing Recovery Loop. 0: Running 1: Frozen; no correction/update on the AGC factor is performed [6:0] TRL_AGC_REF[6:0]: Reference value for digital AGC of TRL block. C Confidential 7 AGC configuration l TRL_AGC_CFG DocID023557 Rev 10 247/604 Information classified Confidential - Do not copy (See last page for obligations) [21:0] ALLPASSFILT_COEFF4: Coefficient 4 of the allpass filter. Front-end registers STiH271EL 3 TRL_SHIFT[1:0] 0xF454 Type: RW Reset: 0x28 1 0 l Address: 2 ti a Description: [7] RESERVED en [6] TRL_NYQPOINT_INV: 0: Initial Nyquist point1: Nyquist point inverted Confidential [5:4] TRL_SHIFT: Number of shifts of the trl tracking coefficient fid [3:2] NYQ_COEFF_SEL[1:0]: 00: 0.12: annex B / 256 QAM01: 0.13: Japan 10: 0.15: DVB-C annex C/Japan 11: 0.18: annex B / 64 QAM [1] TRL_LPF_FREEZE: 0: Loop filter output is not frozen1: Loop filter output is frozen C on [0] TRL_LPF_CRT: 0: TRL criterion for which the discriminant is sign aided 1: TRL criterion for which the discriminant is not sign aided TRL_LPF_ACQ_GAIN 7 6 RESERVED Loop filter acquisition gains 5 TRL_GDIR_ACQ[2:0] Address: 0xF455 Type: RW Reset: 0x44 4 3 RESERVED 2 1 0 TRL_GINT_ACQ[2:0] Description: [7] RESERVED [6:4] TRL_GDIR_ACQ[2:0]: Direct gain of the TRL loop in acquisition mode. The factor applied to the data is computed according to the formula: 2(24+trl_gdir_acq) [3] RESERVED 248/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 4 TRL_LPF_FREEZE 5 NYQ_COEFF_SEL[1:0] 6 TRL_NYQPOINT_INV RESERVED 7 Loop filter configuration TRL_LPF_CRT TRL_LPF_CFG STiH271EL Front-end registers [2:0] TRL_GINT_ACQ[2:0]: Integral gain of the TRL loop in acquisition mode. The factor applied to the data is computed according to the formula: 2(9+trl_gint_acq) TRL_LPF_TRK_GAIN 6 RESERVED 5 4 TRL_GDIR_TRK[2:0] 0xF456 Type: RW Reset: 0x22 2 1 0 TRL_GINT_TRK[2:0] l Address: 3 RESERVED ti a Description: [7] RESERVED en [6:4] TRL_GDIR_TRK[2:0]: Direct gain of the TRL loop in tracking mode. The factor applied to the data is computed according to the formula: 2(24+trl_gdir_trk) fid [2:0] TRL_GINT_TRK[2:0]: Integral gain of the TRL loop in tracking mode. The factor applied to the data is computed according to the formula: 2(9+trl_gint_trk) 7 6 on TRL_LPF_OUT_GAIN 5 4 Loop filter output gain 3 RESERVED Address: 0xF457 Type: RW Reset: 0x03 2 1 0 TRL_GAINOUT[2:0] C Confidential [3] RESERVED Description: [7:3] RESERVED [2:0] TRL_GAINOUT[2:0]: Global gain of the tracking loop. The factor applied to the data is computed according to the formula: 2(16+trl_gain_out) DocID023557 Rev 10 249/604 Information classified Confidential - Do not copy (See last page for obligations) 7 Loop filter tracking gains Front-end registers STiH271EL TRL_LOCKDET_LTH 7 Lock detection low threshold 6 5 4 3 2 RESERVED Address: 0xF458 Type: RW Reset: 0x04 1 0 TRL_LCK_THLO[2:0] Description: ti a l [2:0] TRL_LCK_THLO[2:0]: The threshold applied to the data is computed according to the formula: 2(10+trl_lck_thlo) TRL_LOCKDET_HTH 6 5 4 3 2 1 0 en 7 Lock detection high threshold 0xF459 Type: RW Reset: 0x11 fid Address: Description: on [7:0] TRL_LCK_THHI[7:0]: The threshold applied to the data is computed according to the formula: 2(15+trl_lck_thhi[7]) + 29 trl_lck_thlo[6:0] TRL_LOCKDET_TRGVAL 7 6 C Confidential TRL_LCK_THHI[7:0] Address: 0xF45A Type: RW Reset: 0x20 5 Lock detection trigger value 4 3 TRL_LCK_TRG[7:0] Description: [7:0] TRL_LCK_TRG[7:0]: Sensitivity level of the lock counter. 250/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:3] RESERVED STiH271EL Front-end registers FSM_STATE State machine state 7 6 CRL_DFE DFE_START 5 4 3 2 CTRLG_START[1:0] Address: 0xF460 Type: RW Reset: 0x90 1 0 FSM_FORCESTATE[3:0] Description: ti a l [6] DFE_START: State of DFE active (independent from previous bit). 0: Active from st_eqa1 state1: Active from st_dda state fid en [3:0] FSM_FORCESTATE[3:0]: Encoded state for the master state machine: 0000: st_idle0001: st_agc 0010: st_trl_acq0011: st_trl_trk 0100: st_crl_acq0101: st_crl2 0111: st_eqa21000: st_dda 1010: st_ws_dda1011: st_fec2 1100: st_fec1101: st_ws_fec 1110: st_eqa11111: Unused Address: 0xF461 Type: RW Reset: 0x10 3 2 1 FSM_EQA1_EN FSM_BKP_DIS 0 FSM_FORCE_EN 4 TRL2_EN State machine state control TRL_AHEAD SIT_EN 5 C 6 FEC2_EN 7 on FSM_CTL RESERVED Confidential [5:4] CTRLG_START[1:0]: Low gain of the carrier tracker is used when the FSM state is: 00: st_crl201: st_eqa1 10: st_dda11: st_fec Description: [7] RESERVED [6] FEC2_EN: Enable FEC2 state. 0: No FEC2 state1: FEC2 state enabled [5] SIT_EN: Enable the minimum stay in state for the CRL2 state. 0: Inactive1: Active [4] TRL_AHEAD: Bypass the AGC state. 0: Inactive1: Active DocID023557 Rev 10 251/604 Information classified Confidential - Do not copy (See last page for obligations) [7] CRL_DFE: The DFE is on in CRL mode. 0: Inactive1: Active Front-end registers STiH271EL [3] TRL2_EN: Enable the state TRL2 (TRL tracking). 0: Inactive1: Active [2] FSM_EQA1_EN: Enable the state EQA1 after the state CRL2. 0: eqa1 mode disabled1: eqa1 mode enabled [1] FSM_BKP_DIS: For test purposes only. [0] FSM_FORCE_EN: Force the Master FSM to take the fsm_forcestate as the current state. When this bit is set by I C, the micro interface will generate a pulse, i.e. this bit is auto-reset. 0: Inactive1: Active 6 5 4 3 Type: R Reset: 0x00 ti a 0xF462 2 1 0 FSM_STATUS[3:0] en Address: Description: [7:4] RESERVED FSM_SNR0_HTH 7 6 on fid [3:0] FSM_STATUS[3:0]: Indicates the FSM state: 0000: st_idle0001: st_agc 0010: st_trl_acq0011: st_trl_trk 0100: st_crl_acq0101: st_crl2 0111: st_eqa21000: st_dda 1010: st_ws_dda1011: st_fec2 1100: st_fec1101: st_ws_fec 1110: st_eqa11111: unused C Confidential RESERVED 5 State machine SNR0 high threshold 4 3 SNR0_HTH[7:0] Address: 0xF463 Type: RW Reset: 0x00 Description: [7:0] SNR0_HTH[7:0]: High threshold to move in CRL2 mode. 252/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) 7 State machine status l FSM_STS STiH271EL Front-end registers FSM_SNR1_HTH 7 State machine SNR1 high threshold 6 5 4 3 2 1 0 SNR1_HTH[7:0] Address: 0xF464 Type: RW Reset: 0x00 Description: 6 5 ti a 7 State machine SNR2 high threshold l FSM_SNR2_HTH 4 3 2 1 0 0xF465 Type: RW Reset: 0x00 en Address: fid Description: [7:0] SNR2_HTH[7:0]: High threshold to move from DDA to FEC. 7 6 on FSM_SNR0_LTH 5 Address: 0xF466 Type: RW Reset: 0x00 4 State machine SNR0 low threshold 3 2 1 0 SNR0_LTH[7:0] C Confidential SNR2_HTH[7:0] Description: [7:0] SNR0_LTH[7:0]: Low threshold to unlock in DDA mode. DocID023557 Rev 10 253/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] SNR1_HTH[7:0]: High threshold to move from EQA2 to DDA. Front-end registers STiH271EL FSM_SNR1_LTH State machine SNR1 low threshold 7 6 5 4 3 2 1 0 SNR1_LTH[7:0] Address: 0xF467 Type: RW Reset: 0x00 Description: 6 5 ti a 7 State machine SNR EQA threshold l FSM_RCA_HTH 4 3 0xF468 Type: RW Reset: 0x00 2 1 0 SNR_EQA1_HTH[3:0] en Address: fid Description: [7:4] SNR3_HTH[3:0]: Threshold to move from FEC to FEC2 mode. 5 Address: 0xF469 Type: RW Reset: 0xF432 4 3 2 1 0 SNR_EQA1_HTH[4] 6 C 7 State machine temporization ELT[1:0] FSM_TEMPO WST[2:0] on [3:0] SNR_EQA1_HTH[3:0]: Threshold to move from EQA1 to EQA2 mode. SIT[1:0] Confidential SNR3_HTH[3:0] Description: [7:6] SIT[1:0]: Stay In Timing: Minimum time to stay in CRL2 mode (2^(14+sit): decrease every symbol) [5:3] WST[2:0]: Waiting Stabilization: When unlocked from DDA/FEC mode, we wait a stabilization time to relock or to go back to CRL2. It is a number of SNR_READY. [2:1] ELT[1:0]: Elapsed Time: After this time (2^(18+elt): decrease every symbol), we stop the state CRL2 to go to TRL_ACQ or we stop the state EQA1, EQA2 and DDA to go to CRL2 state [0] SNR_EQA1_HTH[4]: Threshold to move from EQA1 to EQA2 mode. 254/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] SNR1_LTH[7:0]: Low threshold to unlock in FEC mode STiH271EL Front-end registers EQU_I_TESTTAP_L 7 6 I tap test bus 5 4 3 2 1 0 I_TEST_TAP[7:0] Address: 0xF474 Type: R Reset: NA ti a l [7:0] I_TEST_TAP[7:0]: Real part of the equalizer tap's coefficient. The tap can be chosen by the TEST_TAP_SELECT and TEST_FFE_DFE_SEL fields in the EQU_TESTTAP_CFG register. This bus is in two's complement format, and is buffered when the LSB is read. EQU_I_TESTTAP_M 7 6 5 4 3 I tap test bus 2 1 0 Type: R Reset: NA en 0xF475 fid Address: Description: EQU_I_TESTTAP_H 7 6 RESERVED Address: 0xF476 Type: R Reset: NA on [7:0] I_TEST_TAP[15:8]: Real part of the equalizer tap's coefficient. The tap can be chosen by the TEST_TAP_SELECT and TEST_FFE_DFE_SEL fields in the EQU_TESTTAP_CFG register. This bus is in two's complement format, and is buffered when the LSB is read. C Confidential I_TEST_TAP[15:8] 5 I tap test bus 4 3 2 1 0 I_TEST_TAP[20:16] Description: [7:5] RESERVED [4:0] I_TEST_TAP[20:16]: Real part of the equalizer tap's coefficient. The tap can be chosen by the TEST_TAP_SELECT and TEST_FFE_DFE_SEL fields in the EQU_TESTTAP_CFG register. This bus is in two's complement format, and is buffered when the LSB is read. DocID023557 Rev 10 255/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL EQU_TESTTAP_CFG 5 4 3 2 1 0 0xF477 Type: RW Reset: 0x00 ti a l Address: Description: [7] RESERVED en EQU_Q_TESTTAP_L 7 6 5 fid [5:0] TEST_TAP_SELECT: Selection of the tap on the tap test bus. For the DFE only the first 4 bits are valid. 4 Q tap test bus 3 2 1 0 Address: 0xF478 Type: R Reset: NA Description: on Q_TEST_TAP[7:0] C Confidential [6] TEST_FFE_DFE_SEL: Selection of FFE or DFE taps on the tap test bus 0: FFE tap bus 1: DFE tap bus [7:0] Q_TEST_TAP[7:0]: Imaginary part of the tap test bus. The tap can be chosen by the TEST_TAP_SELECT and TEST_FFE_DFE_SEL fields in the EQU_TESTTAP_CFG register. This bus is in two's complement format, and is buffered when the LSB is read. 256/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) TEST_TAP_SELECT[5:0] 6 TEST_FFE_DFE_SEL RESERVED 7 Tap test bus configuration STiH271EL Front-end registers EQU_Q_TESTTAP_M 7 6 Q tap test bus 5 4 3 2 1 0 Q_TEST_TAP[15:8] Address: 0xF479 Type: R Reset: NA ti a l [7:0] Q_TEST_TAP[15:8]: Imaginary part of the tap test bus. The tap can be chosen by the TEST_TAP_SELECT and TEST_FFE_DFE_SEL fields in the EQU_TESTTAP_CFG register. This bus is in two's complement format, and is buffered when the LSB is read. EQU_Q_TESTTAP_H 7 6 5 4 Type: R Reset: NA en 0xF47A 3 2 1 0 Q_TEST_TAP[20:16] fid Address: Description: [7:5] RESERVED Address: 0xF47B Type: RW Reset: 0x06 3 2 1 FFE_TAPMON_EN 0 MTAP_ONLY 4 DFE_TAPMON_EN 5 PRE_FREEZE 6 Tap control MTAP_FRZ 7 C EQU_TAP_CTRL on [4:0] Q_TEST_TAP[20:16]: Imaginary part of the tap test bus. The tap can be chosen by the TEST_TAP_SELECT and TEST_FFE_DFE_SEL fields in the EQU_TESTTAP_CFG register. This bus is in two's complement format, and is buffered when the LSB is read. RESERVED Confidential RESERVED Q tap test bus Description: [7:5] RESERVED [4] MTAP_FRZ: Freeze main tap forced by ffe_maintap_init. [3] PRE_FREEZE: Freeze all the pre-echo related taps. DocID023557 Rev 10 257/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL [2] DFE_TAPMON_EN: DFE tap monitoring enable. [1] FFE_TAPMON_EN: FFE tap monitoring enable (only with the main tap equal to tap 31 or 15). [0] MTAP_ONLY: All taps frozen except the main tap, equalizer pass through. EQU_CTR_CRL_CONTROL_L 7 6 5 Carrier control signal 4 3 2 1 0 0xF47C Type: R Reset: NA ti a l Address: Description: 7 6 5 en fid EQU_CTR_CRL_CONTROL_H 4 Carrier control signal 3 2 1 0 CTR_CRL_CONTROL[15:8] 0xF47D Type: R Reset: NA on Address: Description: [7:0] CTR_CRL_CONTROL[15:8]: This signal is the carrier control bus data. Only MSB (24:9) are read. This bus is buffered when the LSB is read. C Confidential [7:0] CTR_CRL_CONTROL[7:0]: This signal is the carrier control bus data. Only MSB (24:9) are read. This bus is buffered when the LSB is read. 258/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) CTR_CRL_CONTROL[7:0] STiH271EL Front-end registers EQU_CTR_HIPOW_L 7 6 Fractional part extraction of ATAN value 5 4 3 2 1 0 CTR_HIPOW[7:0] Address: 0xF47E Type: R Reset: NA ti a l [7:0] CTR_HIPOW[7:0]: Fractional part extraction of ATAN value (used only for non-square QAMs). If ctr_hipow = 0, values used are: QAM32: ctr_hipow = 69120 QAM128: ctr_hipow = 79488 else (ctr_hipow + 215) is used 6 5 4 3 2 1 0 CTR_HIPOW[15:8] 0xF47F Type: RW Reset: NA fid Address: on Description: [7:0] CTR_HIPOW[15:8]: LSB of fractional part extraction of ATAN value. If ctr_hipow = 0, values used are: QAM32: ctr_hipow = 69120 QAM128: ctr_hipow = 79488 else (ctr_hipow + 215) is used C Confidential 7 Fractional part extraction of ATAN value en EQU_CTR_HIPOW_H EQU_I_EQU_L 7 6 I equalized 5 4 3 2 1 0 I_EQUALIZED[7:0] Address: 0xF480 Type: R Reset: NA Description: [7:0] I_EQUALIZED[7:0]: MSB I value of equalized constellation. The i _equalized value and q_equalized value are buffered when the LSB of i_equalized is read. DocID023557 Rev 10 259/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL EQU_I_EQU_H 7 I equalized 6 5 4 3 2 RESERVED Address: 0xF481 Type: R Reset: NA 1 0 I_EQUALIZED[9:8] Description: [7:2] RESERVED 7 6 5 ti a EQU_Q_EQU_L 4 3 Q equalized 2 1 0 Type: R Reset: NA en 0xF482 fid Address: Description: on [7:0] Q_EQUALIZED[7:0]: MSB Q value of equalized constellation. This value is buffered when the LSB of i_equalized is read. EQU_Q_EQU_H 7 6 Q equalized 5 C Confidential Q_EQUALIZED[7:0] Address: 0xF483 Type: R Reset: NA 4 3 2 RESERVED Description: [7:2] RESERVED [1:0] Q_EQUALIZED[9:8]: LSB Q value of equalized constellation. 260/604 DocID023557 Rev 10 1 0 Q_EQUALIZED[9:8] Information classified Confidential - Do not copy (See last page for obligations) l [1:0] I_EQUALIZED[9:8]: LSB I value of equalized constellation. STiH271EL Front-end registers EQU_MAPPER Equalizer mapper control 7 6 QUAD_AUTO QUAD_INV 5 4 3 2 RESERVED Address: 0xF484 Type: RW Reset: 0x83 1 0 QAM_MODE[2:0] Description: ti a l [6] QUAD_INV: When QUAD_AUTO = 0, this is a RW register to choose the spectrum inversion (`1') or not (`0') When QUAD_AUTO = 1, this is a read only register with the spectrum inversion status 6 5 SNR_PER[1:0] Address: 0xF485 Type: RW Reset: 0x80 Description: on 7 fid EQU_SWEEP_RATE en [2:0] QAM_MODE: 000: Reserved001: QAM16 010: QAM32011: QAM64 100: QAM128101: QAM256 110: Reserved111: Reserved 4 Sweep rate 3 2 1 0 SWEEP_RATE[5:0] C Confidential [5:3] RESERVED [7:6] SNR_PER[1:0]: Integration period to estimate the SNR factor = 2(9+SNR_PER) [5:0] SWEEP_RATE[5:0]: Sweep rate. Ideally, sweep rate = FADC/223 DocID023557 Rev 10 261/604 Information classified Confidential - Do not copy (See last page for obligations) [7] QUAD_AUTO: 0: Quad inversion selected by quad_inv1: Automatic quad selection Front-end registers STiH271EL EQU_SNR_LO 7 SNR value 6 5 4 3 2 1 0 SNR[7:0] Address: 0xF486 Type: R Reset: NA Description: 7 6 5 ti a EQU_SNR_HI 4 3 SNR value 2 1 0 Type: R Reset: NA en 0xF487 fid Address: Description: [7:0] SNR[15:8]: SNR value. 7 on EQU_GAMMA_LO 6 5 Gamma value for error generation 4 3 2 GAMMA[7:0] C Confidential SNR[15:8] Address: 0xF488 Type: RW Reset: 0x00 Description: [7:0] GAMMA[7:0]: Radius of the error generator in the CRL2 state. If gamma = 0 preset values are used, else the register content is used. 262/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) l [7:0] SNR[7:0]: SNR value. The value is buffered when the LSB is read. STiH271EL Front-end registers EQU_GAMMA_HI 7 Gamma value for error generator 6 5 4 3 2 1 0 GAMMA[15:8] Address: 0xF489 Type: RW Reset: 0x00 Description: 7 6 5 4 3 0xF48A Type: RW Reset: 0x36 2 1 CRL2MU[2:0] 0 GAMMA[16] fid Address: Gain for CRL2 and EQA en EQA1MU[2:0] Description: [7] RESERVED [6:4] EQA1MU[2:0]: Gain of the error generator in the EQA state. on [3:1] CRL2MU[2:0]: Gain of the error generator in the CRL2 state. [0] GAMMA[16]: Radius of the error generator in the CRL2 state. If gamma = 0, value depends on the QAM size, else gamma register value is used. (cf. LSB for values). C Confidential RESERVED ti a EQU_ERR_GAIN EQU_RADIUS 7 6 Radius for the EQA in error generator 5 4 3 2 1 0 RADIUS[7:0] Address: 0xF48B Type: RW Reset: 0xAA Description: [7:0] RADIUS[7:0]: Radius of the error generator in the EQA state. DocID023557 Rev 10 263/604 Information classified Confidential - Do not copy (See last page for obligations) l [7:0] GAMMA[15:8]: Radius of the error generator in the CRL2 state. If gamma = 0, value depends on the QAM size, else gamma register value is used. Front-end registers STiH271EL EQU_FFE_MAINTAP 7 FFE main tap initial value 6 5 4 3 2 1 0 FFE_MAINTAP_INIT[7:0] Address: 0xF48C Type: RW Reset: 0x00 Description: 7 6 5 4 3 RW Reset: 0x63 0 PNT2DFE en Type: 1 EQU_OUTSEL fid 0xF48E 2 RESERVED Description: [7:4] LEAK_PER[3:0]: Leak period is 2LEAK_PER [3:2] RESERVED on [1] EQU_OUTSEL: Selection of the normalized data which must be sent to the FEC. 0: Data from the mapper1: Data from the PNT [0] PNT2DFE: Selection of the input of the DFE shift register. 0: Data from the mapper1: Data from the PNT C Confidential LEAK_PER[3:0] Address: Leakage period ti a EQU_LEAKAGE EQU_FFE_MAINTAP_POS 7 6 FFE_LEAK_EN DFE_LEAK_EN Address: 0xF48F Type: RW Reset: 0xDF 5 FFE main tap position value 4 3 FFE_MAINTAP_POS[5:0] Description: [7] FFE_LEAK_EN: FFE taps leakage enable. [6] DFE_LEAK_EN: DFE taps leakage enable. [5:0] FFE_MAINTAP_POS[5:0]: FFE main tap position. 264/604 2 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) l [7:0] FFE_MAINTAP_INIT[7:0]: FFE main tap initial value. 0: Preset values are usedOther values: Register contents are used. STiH271EL Front-end registers EQU_GAIN_WIDE 7 Wide mode gain for error generator 6 5 4 3 2 DFE_GAIN_WIDE[3:0] Address: 0xF490 Type: RW Reset: 0x88 1 0 FFE_GAIN_WIDE[3:0] Description: [7:4] DFE_GAIN_WIDE[3:0]: DFE gain in equalizer wide mode. 7 6 Narrow mode gain for error generator 5 ti a EQU_GAIN_NARROW 4 3 Type: RW Reset: 0x22 1 0 en 0xF491 2 FFE_GAIN_NARROW[3:0] fid Address: Description: [7:4] DFE_GAIN_NARROW[3:0]: DFE gain in equalizer narrow mode. EQU_CTR_LPF_GAIN 7 6 CTR_GTO on [3:0] FFE_GAIN_NARROW[3:0]: FFE gain in equalizer narrow. C Confidential DFE_GAIN_NARROW[3:0] 5 Carrier tracker LPF gain 4 CTR_GDIR[2:0] Address: 0xF492 Type: RW Reset: 0xC1 3 SWEEP_EN 2 1 0 CTR_GINT[2:0] Description: [7] CTR_GTO: Carrier tracker integral gain greater than one. [6:4] CTR_GDIR[2:0]: Carrier tracker LPF direct gain. [3] SWEEP_EN: Sweep mode enable. [2:0] CTR_GINT[2:0]: Carrier tracker LPF integral gain. DocID023557 Rev 10 265/604 Information classified Confidential - Do not copy (See last page for obligations) l [3:0] FFE_GAIN_WIDE[3:0]: FFE gain in equalizer wide mode. Front-end registers STiH271EL EQU_CRL_LPF_GAIN 7 Carrier recovery LPF gain 6 5 CRL_GTO 4 3 CRL_GDIR[2:0] Address: 0xF493 Type: RW Reset: 0xA7 2 SWEEP_DIR 1 0 CRL_GINT[2:0] Description: [7] CRL_GTO: Carrier recovery integral gain greater than one. 7 6 5 4 Address: 0xF494 Type: RW Reset: 0x06 3 2 CTR_INC_GAIN on Description: Carrier global gain 1 0 CTR_FRAC fid CRL_GAIN [7:3] CRL_GAIN: Carrier recovery global gain. If equal to 0, the crl gain depends on QAM size else the register value is used. [2] CTR_INC_GAIN: Carrier tracker global gain incremented. C Confidential EQU_GLOBAL_GAIN en [2:0] CRL_GINT[2:0]: Carrier recovery LPF integral gain. [1:0] CTR_FRAC: Fractional part extraction of ATAN value. 266/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) ti a [3] SWEEP_DIR: Sweep direction: 0: Sweep down1: Sweep up l [6:4] CRL_GDIR[2:0]: Carrier recovery LPF direct gain. STiH271EL Front-end registers 5 3 Address: 0xF495 Type: RW Reset: 0x85 2 1 LIMANEN CTR_GAIN 4 ti a l Description: 0 [7] CTR_BADPOINT_EN: Authorizes the badpoint change in the FSM. [6:4] CTR_GAIN: Carrier tracker global gain. en 3 2 1 0 C on 4 CRL_LD_TFS[1:0] 5 CRL_LD_WST[1:0] 6 CARE_EN 7 Carrier recovery values CRL_LD_PER[1:0] EQU_CRL_LD_VAL fid [2:0] CRL_LD_SEN[2:0]: Carrier recovery lock detect sensitivity. Threshold index for the comparison of the monitored value. CRL_BISTH_LIMIT Confidential [3] LIMANEN: Enables the angle bisector limiter. Address: 0xF496 Type: RW Reset: 0xE2 Description: [7] CRL_BISTH_LIMIT: Enables the threshold bisector limiter. [6] CARE_EN: Enables the care mode in the lock detect of the equalizer. [5:4] CRL_LD_PER[1:0]: CRL lock detect period. [3:2] CRL_LD_WST[1:0]: CRL lock detect waiting success time. It can be set to 5,6,7 or 8 successive stable values. [1:0] CRL_LD_TFS[1:0]: CRL lock detect transfer step: 00: 51201: 1024 10: 204811: 4096 DocID023557 Rev 10 267/604 Information classified Confidential - Do not copy (See last page for obligations) 6 CTR_BADPOINT_EN 7 Carrier recovery lock detect sensitivity CRL_LD_SEN[2:0] EQU_CRL_LD_CFG Front-end registers STiH271EL EQU_CRL_LD_TFR 7 6 Carrier recovery lock detect transfer 5 4 3 2 1 0 CRL_LD_TFR[7:0] Address: 0xF497 Type: RW Reset: 0x23 Description: 6 5 ti a 7 Carrier recovery bisector threshold l EQU_CRL_BISTH_LO Fsymbol / FADC 4 3 2 1 0 0xF498 Type: RW Reset: 0x00 en Address: fid Description: EQU_CRL_BISTH_HI 7 6 on [7:0] CRL_BISTH[7:0]: CRL bisector threshold. When crl_bisth is equal to 0, a default value is selected according to the QAM, else the value is crl_bisth register value. 5 C Confidential CRL_BISTH[7:0] Address: 0xF499 Type: RW Reset: 0x00 Carrier recovery bisector threshold 4 3 CRL_BISTH[15:8] Description: [7:0] CRL_BISTH[15:8]: CRL bisector threshold (see above). 268/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:0] CRL_LD_TFR[7:0]: CRL lock detect transfer ratio = 256 STiH271EL Front-end registers EQU_SWEEP_RANGE_LO 7 6 5 Sweep range 4 3 2 1 0 SWEEP_RANGE[7:0] Address: 0xF49A Type: RW Reset: 0x00 Description: 6 5 ti a 7 Sweep range l EQU_SWEEP_RANGE_HI 4 3 2 1 0 0xF49B Type: RW Reset: 0x00 en Address: fid Description: [7:0] SWEEP_RANGE[15:8]: Sweep start frequency. 7 6 BISECTOR_EN PHEST128_EN on EQU_CRL_LIMITER 5 Address: 0xF49C Type: RW Reset: 0x40 4 CRL limiter 3 2 1 0 CRL_LIMITER[5:0] C Confidential SWEEP_RANGE[15:8] Description: [7] BISECTOR_EN: 0: Bisector disabled (only available in QAM 64, 256 and 1024) 1: Bisector enable [6] PHEST128_EN: 0: Phase estimator 128 disabled1: Phase estimator 128 enabled [5:0] CRL_LIMITER[5:0]: Counter comparator to limit the CRL lock time (4 00, this function is disabled. In read mode, the value of the counter is read. DocID023557 Rev 10 number of ld_per). If 269/604 Information classified Confidential - Do not copy (See last page for obligations) [7:0] SWEEP_RANGE[7:0]: Sweep start frequency = 223 x %Fsymbol / FADC Front-end registers STiH271EL EQU_PNT_CFG0 7 Phase noise tracker configuration 0 6 5 4 3 PNT_DEPTH[2:0] Address: 0xF49D Type: RW Reset: 0x90 2 1 0 MODULUS_CMP[4:0] Description: ti a l [4:0] MODULUS_CMP[4:0]: Threshold of bad data counter. When the threshold is reached, the mapper is the modulus mapper. To go back into the normal mapper the system needs to reach the low threshold which is modulus_errcnt - 4. 5 Type: RW Reset: 0xE7 fid 0xF49E 3 2 on Address: 4 PNT_GAIN[5:0] 6 MODULUSMAP_EN PNT_EN Description: [7] PNT_EN: Enables the phase noise tracker. C Confidential 7 Phase noise tracker configuration 1 en EQU_PNT_CFG1 [6] MODULUSMAP_EN: Enables the modulus_mapper. [5:0] PNT_GAIN[5:0]: Phase noise tracker gain. 270/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:5] PNT_DEPTH: Depth of the PNT average computed. STiH271EL 10.7 Front-end registers QAM FEC A and C registers FEC_AC_CTRL_0 7 Descrambler formatter 6 RESERVED Address: 0xF4A8 Type: RW Reset: 0x16 5 4 3 2 1 0 BE_BYPASS REFRESH47 CT_NBST TEI_ENA DS_ENA TSMF_EN l [7:6] RESERVED en [4] REFRESH47: 1: Inverted MPEG sync bytes are reinverted from 0xB8 back to 0x47. Reset value = 1. Do not set to 0. fid [3] CT_NBST: 0: R/S parity is discarded1: all MPEG/TS bits are output. In TSMF mode this bit must be set high, the TSMF function discarding the R/S parity bits. Reset value = 0 on [2] TEI_ENA: 1: Enables setting of MPEG-2 TEI bit in case of uncorrectable packet error. Reset value = 1. [1] DS_ENA: 1: Descrambling is enabled. RESET / NORMAL VALUE = 1. C Confidential ti a [5] BE_BYPASS: 1: All `back-end' stages, that is - those following symbol-to-byte (deinterleaving, R/S, descrambler) - are by-passed. Reset value = 0 [0] TSMF_EN: 0: TSMF bypassed1: TSMF enabled DocID023557 Rev 10 271/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL FEC_AC_CTRL_1 7 De-interleaver depth 6 5 4 3 2 1 0 DEINT_DEPTH Address: 0xF4A9 Type: R Reset: 0x0B FEC_AC_CTRL_2 7 De-interleaver and descrambler configuration 6 5 4 0xF4AA Type: RW Reset: 0x88 2 DIS_UNLOCK 1 0 DESCR_MODE fid Address: 3 en DEINT_M Description: on [7:3] DEINT_M: Interleaving depth parameter. DEFAULT = 17dec, OK for ITU J83-A&C. To bypass the de-interleaver it is necessary to set deint_depth to 0 and deint_m to 1. [2] DIS_UNLOCK: Disables the capability of the de-interleaver sync detector to switch the descrambler sync detector to unlocked mode. NORMAL VALUE = 0. [1:0] DESCR_MODE: Defines the descrambler sync state machine tracking operation. This machine has two states: 'acquisition' and 'tracking'. The current state conditions the operation of MPEG-TS output pins and is reflected in bit 'syncstate' of Reg.DC (see below). 00: Descrambler sync detector cares only for inverted sync byte. If it is found at the expected time, it goes to tracking, if not it goes to acquisition. 10: "Complete tracking" mode - Descrambler sync detector cares only for inverted sync bytes to lock, but checks all sync bytes (inverted or not) once in tracking state; if one of them is wrong it goes back to acquisition. X1: "Freeze" mode - Once locked, the de-interleaver sync detector will stay in tracking state (=> MPEG output pins stay active) even if there is a missing sync byte. C Confidential ti a l [7:0] DEINT_DEPTH: De-interleaver depth - 1. DEFAULT = 0d11, OK for ITU J83-A&C. Write to 0 and set deint_m (Reg. 0xDA) to 1 to bypass de-interleaver. 272/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL Front-end registers FEC_AC_CTRL_3 7 6 DI_UNLOCK DI_FREEZE De-interleaver sync detector 5 4 3 MISMATCH Address: 0xF4AB Type: RW Reset: 0x02 2 1 ACQ_MODE 0 TRKMODE [7] DI_UNLOCK: 1: Forces the de-interleaver sync detector to unlock. NORMAL VALUE = 0. ti a l [6] DI_FREEZE: 1: Freezes the de-interleaver sync detector in locked mode. NORMAL VALUE = 0. en fid [3:2] ACQ_MODE: Defines the number of states required to declare acquisition: The de-interleaver sync detector will declare an acquisition and enter tracking when it has detected at least "acq_mode+3" successive correct sync bytes out of which one must be the inverted sync byte. Address: 0xF4AC Type: R Reset: 0x00 4 3 2 1 0 RESERVED 5 DESCR_SYNCSTATE 6 C 7 State machine status DEINT_SYNLOST FEC_STATUS_0 DEINT_SYNCSTATE on [1:0] TRKMODE: Defines the number of states (number of successive mismatching sync bytes) required to unlock: trk_mode + 1 incorrect sync bytes will be required. DEINT_SMCNTR Confidential [5:4] MISMATCH: Indicates the number of bit mismatches in a sync byte allowed during tracking state (more erroneous bits and the byte is regarded as mismatching). Description: [7:5] DEINT_SMCNTR: Increase each time the detected sync byte matches, decrease each time it mismatches. Saturates at 0 and ACQ_MODE + 2. [4:3] DEINT_SYNCSTATE: Current state of the de-interleaver state machine. DocID023557 Rev 10 273/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL [2] DEINT_SYNLOST: Goes to 1 when the de-interleaver loses sync (even if it is forced to stay in locked state by bit DI_FREEZE). Cleared in case of relocking. [1] DESCR_SYNCSTATE: Goes to 1 when descrambler is in sync state. [0] RESERVED RS_COUNTER_0 7 Block counter LSB 6 5 4 3 2 1 0 0xF4AE Type: R Reset: 0x00 ti a l Address: Description: en 6 5 Address: 0xF4AF Type: R Reset: 0x00 4 Block counter MSB 3 2 1 0 BK_CT[15:8] on 7 fid RS_COUNTER_1 C Confidential [7:0] BK_CT[7:0]: LSB of the block counter (counting the number of MPEG-TS packets elapsed since the block counters were enabled. Refer to ct_clear bit. The value is buffered when the LSB is read. [7:0] BK_CT[15:8]: MSB of the block counter (counting the number of MPEG-TS packets elapsed since the block counters were enabled. Refer to ct_clear bit. The value is buffered when the LSB is read. RS_COUNTER_2 7 6 Corrected block counter LSB 5 4 3 2 1 0 CORR_CT[7:0] Address: 0xF4B0 Type: R Reset: 0x00 [7:0] CORR_CT[7:0]: LSB of the corrected block counter (counts the number of MPEG-TS packets that were R/S corrected since the block counters were enabled. Refer to ct_clear bit The value is buffered when the LSB is read. 274/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) BK_CT[7:0] STiH271EL Front-end registers RS_COUNTER_3 7 Corrected block counter MSB 6 5 4 3 2 1 0 CORR_CT[15:8] Address: 0xF4B1 Type: R Reset: 0x00 ti a l [7:0] CORR_CT[15:8]: MSB of the corrected block counter (counts the number of MPEG-TS packets that were R/S corrected since the block counters were enabled. Refer to ct_clear bit. The value is buffered when the LSB is read. RS_COUNTER_4 7 Uncorrected block counter LSB 6 5 4 3 2 1 0 Type: R Reset: 0x00 en 0xF4B2 fid Address: Description: on [7:0] UNCORR_CT[7:0]: LSB of the uncorrected block counter (counts packets that were detected as erroneous by the R/S but not correctable). The value is buffered when the LSB is read. RS_COUNTER_5 7 6 C Confidential UNCORR_CT[7:0] Address: 0xF4B3 Type: R Reset: 0x00 5 Uncorrected block counter MSB 4 3 2 1 0 UNCORR_CT[15:8] Description: [7:0] UNCORR_CT[15:8]: MSB of the uncorrected block counter (counts packets that were detected as erroneous by the R/S but not correctable) The value is buffered when the LSB is read. DocID023557 Rev 10 275/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL BERT_0 Descrambler counter control 7 6 5 4 3 RESERVED Address: 0xF4B4 Type: RW Reset: 0x01 2 1 0 RS_NOCORR CT_HOLD CT_CLEAR Description: ti a l [2] RS_NOCORR: 0: The Reed-Solomon block operates normally (default) 1: The Reed-Solomon block does not correct any errors, but all of its other functions operate normally en fid [0] CT_CLEAR: 0: The block counters described in RS_COUNTER_0 through RS_COUNTER_5 are cleared 1: The block counters described in RS_COUNTER_0 through RS_COUNTER_5 are enabled 7 6 RESERVED Address: 0xF4B5 Type: RW Reset: 0x05 on BERT_1 Bert configuration 5 4 3 BERT_ON ERR_SOURCE ERR_MODE 2 1 0 NBYTE C Confidential [1] CT_HOLD: 0 The block counters described in RS_COUNTER_0 through RS_COUNTER_5 can be updated 1: The block counters described in RS_COUNTER_0 through RS_COUNTER_5 are prevented from being updated Description: [7:6] RESERVED [5] BERT_ON: Set to 1 to start counting bit/byte errors (before R/S correction). If err_mode = 0 (see below), `bert_on' will be automatically reset to 0 when the number of data bytes programmed through register `nbyte' (see below) has elapsed. If err_mode = 1 it is not automatically reset. [4] ERR_SOURCE: 0: Count bit errors.1: Count byte errors. [3] ERR_MODE: 0: The internal error counter stops automatically when the number of bytes defined by `nbyte' (see below) has elapsed 1: It will not stop automatically, register nbyte is ignored and bit BERT_ON must be explicitly cleared by the user to stop the error counter 276/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:3] RESERVED STiH271EL Front-end registers [2:0] NBYTE: Defines the number of data BYTES during which bit/byte errors are to be detected as 2(2.nbyte + 12). [Used only if err_mode=0]. (So the count period can range from 4096 to 226 bytes). BERT_2 7 Error counter LSB 6 5 4 3 2 1 0 Address: 0xF4B6 Type: R Reset: 0x00 ti a l Description: 6 5 4 3 2 1 0 fid 7 Error counter MSB BERT_ERRCOUNT[8:15] 0xF4B7 Type: R Reset: 0x00 on Address: Description: [7:0] BERT_ERRCOUNT[8:15]: Internal byte/bit error counter, LSB byte. Note that this result is the raw bit/byte error count and includes any error falling within the R/S redundancy bytes. The value is buffered when the LSB is read. C Confidential BERT_3 en [7:0] BERT_ERRCOUNT[7:0]: Internal byte/bit error counter, LSB byte. Note that this result is the raw bit/byte error count and includes any error falling within the R/S redundancy bytes. The value is buffered when the LSB is read OUTFORMAT_0 7 Output formatter 0 6 CLK_POLARITY 5 4 RESERVED Address: 0xF4B8 Type: RW Reset: 0x02 3 2 SYNC_STRIP TS_SWAP 1 0 OUTPUT_FORMAT Description: [7] CLK_POLARITY: 1: ts_ckout polarity is inverted [6:4] RESERVED DocID023557 Rev 10 277/604 Information classified Confidential - Do not copy (See last page for obligations) BERT_ERRCOUNT[7:0] Front-end registers STiH271EL [3] SYNC_STRIP: 1: TS valid is down during TS sync pulse [2] TS_SWAP: 1: Swap MSB and LSB on TS data output [1:0] OUTPUT_FORMAT: 00: Parallel01: Serial 10: Common interface11: Not used 7 Output formatter 1 6 5 4 3 2 1 0 Address: 0xF4B9 Type: R Reset: 0x22 ti a l CI_DIVRANGE[7:0] en on fid [7:0] CI_DIVRANGE[7:0]: Defines the division ratio "N" between the base clock and the Common Interface clock TS_CKOUT: N = N1 + N2 with N1 = ci_divrange[7:4] and N2 = ci_divrange[3:0]. N1 represents the number of base clock cycles during which TS_CKOUT will be high, N2 is the number of base clock cycles during which TS_CKOUT will be low. Resulting TS_CKOUT frequency = base clock frequency / N. Duty cycle ratio depends on N1/N2 ratio (50% if N1 = N2). TSMF_CTRL_0 7 6 RESERVED 5 TSMF selection 4 C Confidential Description: Address: 0xF4C0 Type: RW Reset: 0x01 3 TS_NUMBER[3:0] Description: [7:5] RESERVED [4:1] TS_NUMBER: Selected TS number. [0] SEL_MODE: Selection mode: 0: Selection by TS_ID1: Selection by TS number. 278/604 2 DocID023557 Rev 10 1 0 SEL_MODE Information classified Confidential - Do not copy (See last page for obligations) OUTFORMAT_1 STiH271EL Front-end registers TSMF_CTRL_1 0xF4C1 Type: RW Reset: 0xC6 1 0 H_MODE l Address: 2 ti a Description: [7] CHECK_ERROR_BIT: When 1, Frame header TS error indicator bit checked [6] CHECK_F_SYNC: When 1, frame_sync bytes of the frame header are checked en [5:4] RESERVED Confidential [3] H_MODE: 0: PID of multiple frame header is overwritten by Null PID 0x1FFF 1: PID of multiple frame header is output as is. fid [2] D_V_MODE: 0: "Data Valid" signal is asserted for all output frames 1: "Data Valid" signal is asserted only for desired output frames. on [1:0] MODE: 00: Force single TS mode01: Force Multiple TS mode 10: Automatic detect mode11: Reserved 7 6 C TS_ON_ID_0 Address: 0xF4C4 Type: RW Reset: 0x00 5 TS identifier 4 3 2 1 0 TS_ID[7:0] Description: [7:0] TS_ID[7:0]: LSB from the selected TS identifier to be provided by the controlling device DocID023557 Rev 10 279/604 Information classified Confidential - Do not copy (See last page for obligations) 3 MODE 4 RESERVED CHECK_F_SYNC 5 D_V_MODE 6 CHECK_ERROR_BIT 7 TSMF control Front-end registers STiH271EL TS_ON_ID_1 7 TS identifier 6 5 4 3 2 1 0 TS_ID[15:8] Address: 0xF4C5 Type: RW Reset: 0x00 Description: 6 5 ti a 7 ON identifier l TS_ON_ID_2 4 3 2 1 0 0xF4C6 Type: RW Reset: 0x00 en Address: fid Description: [7:0] ON_ID[7:0]: LSB from the original Network identifier to be provided by the controlling device. 7 6 on TS_ON_ID_3 5 Address: 0xF4C7 Type: RW Reset: 0x00 ON identifier 4 3 2 1 0 ON_ID[15:8] C Confidential ON_ID[7:0] Description: [7:0] ON_ID[15:8]: MSB from the original Network identifier to be provided by the controlling device. 280/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] TS_ID[15:8]: MSB from the selected TS identifier to be provided by the controlling device. STiH271EL Front-end registers RE_STATUS_0 Receive status 0 7 6 5 4 3 2 1 0 RECEIVE_STATUS[7:0] Address: 0xF4C8 Type: R Reset: 0x00 ti a l [7:0] RECEIVE_STATUS[7:0]: Two bits status per relative_ts_id: Receive status[1:0] for relative_ts_id#1Receive status[3:2] for relative_ts_id#2 Receive status[5:4] for relative_ts_id#3Receive status [7:6] for relative_ts_id#4 RE_STATUS_1 7 6 5 4 3 Receive status 1 2 1 0 Type: R Reset: 0x00 en 0xF4C9 fid Address: Description: on [7:0] RECEIVE_STATUS[15:8]: Two bits status per relative_ts_id: Receive status[9:8] for relative_ts_id#5 Receive status[11:10] for relative_ts_id#6 Receive status[13:12] for relative_ts_id#7 Receive status [15:14] for relative_ts_id#8 C Confidential RECEIVE_STATUS[15:8] RE_STATUS_2 7 6 Receive status 2 5 4 3 2 1 0 RECEIVE_STATUS[23:16] Address: 0xF4CA Type: R Reset: 0x00 Description: [7:0] RECEIVE_STATUS[23:16]: Two bits status per relative_ts_id: Receive status[17:16] for relative_ts_id#9 Receive status[19:18] for relative_ts_id#10 Receive status[21:20] for relative_ts_id#11 Receive status [23:22] for relative_ts_id#12 DocID023557 Rev 10 281/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL RE_STATUS_3 7 Receive status 3 6 5 4 3 RESERVED 2 1 0 RECEIVE_STATUS[29:24] Address: 0xF4CB Type: R Reset: 0x00 Description: ti a l [5:0] RECEIVE_STATUS[29:24]: Two bits status per relative_ts_id: Receive status[26:24] for relative_ts_id#13 Receive status[27:26] for relative_ts_id#14 Receive status[29:28] for relative_ts_id#15 6 5 4 3 TS status 2 1 0 TS_STATUS[7:0] 0xF4CC Type: R Reset: 0x00 fid Address: on Description: [7:0] TS_STATUS[7:0]: One bit status per relative_ts_id: ts_status[0] for relative_ts_id_#1 ... ts_status[7] for relative_ts_id_#8 C Confidential 7 en TS_STATUS_0 TS_STATUS_1 7 6 RESERVED TS status 5 4 3 TS_STATUS[14:8] Address: 0xF4CD Type: R Reset: 0x00 Description: [7] RESERVED [6:0] TS_STATUS[14:8]: One bit status per relative_ts_id: ts_status[8] for relative_ts_id_#9 ... ts_status[14] for relative_ts_id_#15 282/604 DocID023557 Rev 10 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) [7:6] RESERVED STiH271EL Front-end registers TS_STATUS_2 TSMF general status 7 6 5 ERROR EMERGENCY Address: 0xF4CE Type: R Reset: 0x00 4 3 2 CRE_TS 1 VER 0 M_LOCK [7] ERROR: 0: The provided ts_id and on_id are valid and their corresponding ts_status is active 1: The above condition is not met. ti a l [6] EMERGENCY: Emergency indicator. [5:4] CRE_TS: The receive status of the currently selected TS. [3:1] VER: TSMF Version number. en CONTCNT 3 2 1 0 C on 4 TS_IDENTIFIER_SELECT 5 TSMF interrupt RESERVED 6 END_FRAME_HEADER 7 fid TS_STATUS_3 UPDATE_RDY Confidential [0] M_LOCK: 0: Multiple TS unlocked1: Multiple TS locked Address: 0xF4CF Type: R Reset: 0x00 Description: [7] UPDATE_RDY: Receive new header with mask. [6] END_FRAME_HEADER: Receive header with mask. [5] CONTCNT: Receive header with an invalid continuity field mask. [4] RESERVED [3:0] TS_IDENTIFIER_SELECT: Select the ieme identifier. DocID023557 Rev 10 283/604 Information classified Confidential - Do not copy (See last page for obligations) Description: Front-end registers STiH271EL T_O_ID_0 7 TS identifier extracted from header 6 5 4 3 2 1 0 TS_ID_I[7:0] Address: 0xF4D0 Type: R Reset: 0x00 Description: 6 5 ti a 7 TS identifier extracted from header l T_O_ID_1 4 3 2 1 0 0xF4D1 Type: R Reset: 0x00 en Address: fid Description: [7:0] TS_ID_I[15:8]: MSB TS identifier extracted from the header for relative_ts_idi. 7 Original network identifier extracted from header 6 on T_O_ID_2 5 Address: 0xF4D2 Type: R Reset: 0x00 4 3 2 1 0 ON_ID_I[7:0] C Confidential TS_ID_I[15:8] Description: [7:0] ON_ID_I[7:0]: LSB Original Network identifier extracted from the header for relative_ts_id#i. 284/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] TS_ID_I[7:0]: LSB TS identifier extracted from the header for relative_ts_id#i. STiH271EL Front-end registers T_O_ID_3 7 Original network identifier extracted from header 6 5 4 3 2 1 0 ON_ID_I[15:8] Address: 0xF4D3 Type: R Reset: 0x00 Description: C on fid Confidential en ti a l Information classified Confidential - Do not copy (See last page for obligations) [7:0] ON_ID_I[15:8]: MSB Original Network identifier extracted from the header for relative_ts_id#i. DocID023557 Rev 10 285/604 Memory and on-chip peripherals address map 11 STiH271EL Memory and on-chip peripherals address map Figure 36. STiH271EL memory map 0 MB 0x0000 0000 EMI 256M 0x1000 0000 64K 0x1001 0000 128K 256 MB RESERVED ERAM_B 0x1003 0000 256 MB 255.8 M Cannot be accessible by ST40s in 29-bit mode. 512 MB en RESERVED 512M 1024 MB fid 0x4000 0000 Confidential ti a l 0x2000 0000 LMI ST40 32-bit addressing mode on 1024 MB 1024 MB C 0x8000 0000 Reserved 0xFC00 0000 4032 MB 8K 8K Reserved 16376K 3072 MB 0xC000 0000 4048 MB 0xFD00 0000 On-chip peripherals 32 MB MMC 960M 4080 MB 0xFF00 0000 16 MB Reserved 4032 MB 0xFC00 0000 Reg space 64M 0xFFFF FFFF 0xFFFF FFFF 4096 MB 286/604 DocID023557 Rev 10 4096 MB Information classified Confidential - Do not copy (See last page for obligations) Reserved STiH271EL 11.1 Memory and on-chip peripherals address map External memories and on-chip peripherals address map The STiH271EL memory space is populated with non-volatile memories, external peripherals (EMI) at base address 0 (ST40 boots at address 0) and with DDR3-SDRAM devices (LMI). The following table shows the peripheral map of the STiH271EL. For ease of readability, reserved areas are shaded. STiH271EL peripheral address map Start offset End offset Size Description 0x0000000 0xFFFFFFF 256M EMI RESERVED 0x10000000 0x1000FFFF 64K Reserved ERAM_B 0x10010000 0x1002FFFF 128K Tile RAM RESERVED 0x10030000 0x1FFFFFFF 256M Reserved BART 0x14000000 0x17FFFFFF 64M Bart 29-bit alias range RESERVED 0x18000000 0x1FFFFFFF 128M Reserved LMI 0x40000000 0x7FFFFFFF RESERVED 0x40000000 0xBFFFFFFF 2048M Reserved MMC_T3 0xC0000000 0xFBFFFFFF 960M RESERVED 0xFC000000 0xFCFFFFFF 16M Reserved TVOUT_FDMA 0xFD000000 0xFD001FFF 8K TVOUT FDMA (PCMP0, S/PDIF and TTXT) PCMP1 0xFD002000 0xFD002FFF 4K PCM player 1 port and configuration registers PCMP2 0xFD003000 0xFD003FFF 4K PCM player 2 port and configuration registers PCMR0 0xFD004000 0xFD004FFF 4K PCM reader 0 port and configuration registers RESERVED 0xFD005000 0xFD005FFF 4K Reserved RESERVED 0xFD006000 0xFD006FFF 4K Reserved RESERVED 0xFD007000 0xFD007FFF 4K Reserved RESERVED 0xFD008000 0xFD008FFF 4K Reserved RESERVED 0xFD009000 0xFD0FFFFF 988K Reserved FVP3_HQRIE 0xFD100000 0xFD2FFFFF 2M HQ VDP (HQRIE mega cell) RESERVED 0xFD300000 0xFD3FFFFF 1M Reserved RESERVED 0xFD400000 0xFD4FFFFF 1M Reserved SYSCFG_BANK2 0xFD500000 0xFD50FFFF 64K System configuration registers RESERVED 0xFD510000 0xFD51FFFF 64K Reserved RESERVED 0xFD520000 0xFD52FFFF 64K Reserved RESERVED 0xFD530000 0xFD537FFF 32K Reserved TVOUT_CPU 0xFD538000 0xFD53FFFF 32K TVOUT configuration registers RESERVED 0xFD540000 0xFD540FFF 4K Reserved SYSCFG_BANK3 0xFD541000 0xFD541FFF 4K System configuration registers ti a en fid on l EMI C Confidential Region name 2048M LMI MMC T3 DocID023557 Rev 10 287/604 Information classified Confidential - Do not copy (See last page for obligations) Table 56. Memory and on-chip peripherals address map STiH271EL peripheral address map (continued) End offset IRQ_ROUTER_ST40 0xFD542000 0xFD542FFF 4K IRQ router configuration COMMS_LPC 0xFD543000 0xFD543FFF 4K COMMS LPC configuration VDP_AUX 0xFD544000 0xFD544FFF 4K AUX HD display configuration registers COMPO 0xFD545000 0xFD545FFF 4K Compositor configuration registers RESERVED 0xFD546000 0xFD5461FF 0.5K Reserved RESERVED 0xFD546200 0xFD546FFF 3.5K Reserved RESERVED 0xFD547000 0xFD547FFF 4K Reserved RESERVED 0xFD548000 0xFD548FFF 4K Reserved RESERVED 0xFD548000 0xFD54DFFF 24K RESERVED 0xFD54E000 0xFD54E1FF 0.5K Reserved RESERVED 0xFD54E200 0xFD54E3FF 0.5K Reserved RESERVED 0xFD54E400 0xFD54E5FF 0.5K Reserved RESERVED 0xFD54E600 0xFD54E7FF 0.5K Reserved RESERVED 0xFD54E800 0xFD5FFFFF 710K Reserved RESERVED 0xFD600000 0xFD6FFFFF 1M Reserved COMMS 0xFD700000 0xFD7FFFFF 1M Comms configuration registers RESERVED 0xFD800000 0xFD8FFFFF 1M Reserved RESERVED 0xFD900000 0xFD90FFFF 64K RESERVED RESERVED 0xFD910000 0xFD910FFF 4K Reserved RESERVED 0xFD911000 0xFD9BFFFF 700K Reserved RESERVED 0xFD9C0000 0xFD9DFFFF 128K Reserved FDMA1 0xFD9E0000 0xFD9FFFFF 128K FDMA 1 memory and configuration registers FDMA0 0xFDA00000 0xFDA1FFFF 128K FDMA 0 memory and configuration registers RESERVED 0xFDA20000 0xFDA2FFFF 64K Reserved INTC2_ST40L2 0xFDA30000 0xFDA33FFF 16K INTC2 ST40L2 configuration registers ILC3_ST40L2 0xFDA34000 0xFDA37FFF 16K ILC3 ST40L2 configuration registers RESERVED 0xFDA38000 0xFDA3BFFF 16K Reserved RESERVED 0xFDA3C000 0xFDA3FFFF 16K Reserved STFE 0xFDA40000 0xFDA4FFFF 64K STFE configuration registers SYSCFG_BANK1 0xFDA50000 0xFDA5FFFF 64K System configuration registers PIO_BANK1 0xFDA60000 0xFDA6FFFF 64K PIO configuration registers (PIO4 to PIO8) PIO_BANK2 0xFDA70000 0xFDA7FFFF 64K PIO configuration registers (PIO9 to PIO12) RESERVED 0xFDA80000 0xFDA87FFF 32K Reserved ETH 0xFDA88000 0xFDA8FFFF 32K Ethernet configuration registers RESERVED 0xFDA90000 0xFDA9FFFF 64K Reserved 288/604 Size Reserved ti a en fid on Description l Start offset C Confidential Region name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 56. STiH271EL STiH271EL STiH271EL peripheral address map (continued) Start offset End offset Size Description 0xFDAA0000 0xFDAA0FFF 4K Reserved RESERVED 0xFDAA1000 0xFDAA7FFF 28K Reserved EMISS_REG 0xFDAA8000 0xFDAAFFFF 32K EMISS configuration registers (T1 target) RESERVED 0xFDAB0000 0xFDAB3FFF 16K Reserved RESERVED 0xFDAB4000 0xFDAB7FFF 16K Reserved CLKGENA1 0xFDAB8000 0xFDAB8FFF 4K Clock generator A1 (R) RESERVED 0xFDAB9000 0xFDAB9FFF 4K Reserved MMC 0xFDABA000 0xFDABAFFF 4K MMC FDMA_MUX 0xFDABB000 0xFDABBFFF 4K FDMA multiplexer configuration registers RESERVED 0xFDABC000 0xFDABCFFF 4K RESERVED 0xFDABD000 0xFDABDFFF 4K BLITTER 0xFDABE000 0xFDABEFFF 4K MBOX0 0xFDABF000 0xFDABF7FF 2K Mailbox0 configuration registers MBOX1 0xFDABF800 0xFDABFFFF 2K Mailbox1 configuration registers MBOX2 0xFDAC0000 0xFDAC07FF 2K Mailbox2 configuration registers MBOX3 0xFDAC0800 0xFDAC0FFF 2K Mailbox3 configuration registers IRQ_ROUTER_ILC3 0xFDAC1000 0xFDAC17FF 2K IRQ router ILC3 RESERVED 0xFDAC1800 0xFDAC1FFF 2K Reserved RESERVED 0xFDAC2000 0xFDAC2FFF 4K Reserved RESERVED 0xFDAC3000 0xFDAC37FF 2K Reserved RESERVED 0xFDAC3800 0xFDAC39FF 0.5K Reserved RESERVED 0xFDAC3A00 0xFDAC3BFF 0.5K Reserved RESERVED 0xFDAC3C00 0xFDAC3DFF 0.5K Reserved RESERVED 0xFDAC3E00 0xFDAC3FFF 0.5K Reserved RESERVED 0xFDAC4000 0xFDAC41FF 0.5K Reserved RESERVED 0xFDAC4200 0xFDAC4FFF 3K Reserved RESERVED 0xFDAC5000 0xFDAC5FFF 4K Reserved RESERVED 0xFDAC6000 0xFDAC6FFF 4K Reserved RESERVED 0xFDAC7000 0xFDAFFFFF 228K Reserved RESERVED 0xFDB00000 0xFDDFFFFF 3M Reserved DMU 0xFDE00000 0xFDE1FFFF 128K DeltaMu PIO_BANK3 0xFDE20000 0xFDE2FFFF 64K PIO configuration (PIO13 to PIO15) RESERVED 0xFDE30000 0xFDE3FFFF 64K Reserved DDR3SS 0xFDE40000 0xFDE5FFFF 128K DDR subsystem configuration registers RESERVED 0xFDE60000 0xFDE7FFFF 128K Reserved on fid en ti a l RESERVED C Confidential Region name Reserved Reserved Blitter display configuration registers DocID023557 Rev 10 289/604 Information classified Confidential - Do not copy (See last page for obligations) Table 56. Memory and on-chip peripherals address map Memory and on-chip peripherals address map STiH271EL peripheral address map (continued) Start offset End offset Size Description 0xFDE80000 0xFDE8FFFF 64K IRQ IRQ_LXAUD 0xFDE90000 0xFDE97FFF 32K IRQ CLKGENA0 0xFDE98000 0xFDE98FFF 4K Clock generator A0 (L) RESERVED 0xFDE99000 0xFDE99FFF 4K Reserved RESERVED 0xFDE9A000 0xFDE9AFFF 4K Reserved RESERVED 0xFDE9B000 0xFDE9BFFF 4K Reserved RESERVED 0xFDE9C000 0xFDEA37FF 30K Reserved RESERVED 0xFDEA3800 0xFDEA39FF 0.5K Reserved RESERVED 0xFDEA3A00 0xFDEA3BFF 0.5K Reserved RESERVED 0xFDEA3C00 0xFDEA3DFF 0.5K Reserved RESERVED 0xFDEA3E00 0xFDEA3FFF 0.5K Reserved RESERVED 0xFDEA4000 0xFDEA4FFF 4K Reserved RESERVED 0xFDEA5000 0xFDFFFFFF 1388K Reserved USB2_0 0xFE000000 0xFE0FFFFF 1M USB0 2.0 configuration registers USB2_1 0xFE100000 0xFE1FFFFF 1M USB1 2.0 configuration registers RESERVED 0xFE200000 0xFE3FFFFF 2M Reserved SBC 0xFE400000 0xFE5FFFFF 2M Low power monitor peripherals (SSC, UART, CEC, WDT, key scan, and so on) SYSCFG_BANK0 0xFE600000 0xFE60FFFF 64K SBC system configuration bank 0 registers PIO_BANK10 0xFE610000 0xFE61FFFF 64K PIO configuration registers (PIO0 to PIO3); in Always ON domain RESERVED 0xFE620000 0xFE62FFFF 64K Reserved RESERVED 0xFE630000 0xFE630FFF 4K Reserved RESERVED 0xFE631000 0xFE631FFF 4K Reserved RESERVED 0xFE632000 0xFE7FFFFF 1848K Reserved RESERVED 0xFE800000 0xFE8FFFFF 1M Reserved EMI_CFG 0xFE900000 0xFE9FFFFF 1M EMI configuration registers (mapped to T2 target) FEMEM 0xFEA00000 0xFEA07FFF 32K FE Memory RESERVED 0xFEA08000 0xFEA08FFF 4K Reserved RESERVED 0xFEA09000 0xFEAFFFFF 988K Reserved RESERVED 0xFEB00000 0xFEBFFFFF 1M Reserved LXDMU 0xFEC00000 0xFECFFFFF 1M ST231 DeltaMu peripherals LXAUD 0xFED00000 0xFEDFFFFF 1M ST231 audio peripherals RESERVED 0xFEE00000 0xFEEFFFFF 1M Reserved ST40L2_PERIPH 0xFEF00000 0xFEF01FFF ST40L2 (host CPU) peripherals 290/604 on fid ti a en 8K l IRQ_LXVID C Confidential Region name DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 56. STiH271EL STiH271EL Table 56. Memory and on-chip peripherals address map STiH271EL peripheral address map (continued) Region name RESERVED End offset 0xFEF02000 0xFEF03FFF Size Description 8K Reserved 0xFEF04000 0xFEF043FF 1K L2_PERIPH_EXT 0xFEF04400 0xFEF047FF 1K L2 cache prefetch registers through Target 2 port RESERVED 0xFEF04800 0xFEFFFFFF 1006K Reserved RESERVED 0xFF000000 0xFFFFFFFF Reserved LPM address map Start address l Table 57. ti a LPM memory map en 11.1.1 16M Information classified Confidential - Do not copy (See last page for obligations) L2_PERIPH_INT L2 cache configuration registers through Target 1 port. This address is not routed in the interconnect and only ST40L2 can access this region through L2 cache Target 1 port. Region name End address Size Description 0xFE4A0000 0xFE4AFFFF 63K HDMI KEYSCAN 0xFE4B0000 0xFE4B1FFF 8K Keyscan RESERVED 0xFE4B2000 0xFE4B2FFF 4K Not applicable GP TIMER 0xFE4B3000 0xFE4B3FFF 4K General purpose timer MBOX 0xFE4B4000 0xFE4B43FF 1K Mailbox RESERVED 0xFE4B4400 0xFE4B4FFF 2K Reserved RESERVED 0xFE4B5000 0xFE4B50FF 256 Reserved LPM CONFIGURATION 0xFE4B5100 REGISTERS 0xFE4B51FF 256 LPM configuration registers WATCHDOG AND RTC 0xFE4B5200 0xFE4B52FF 256 Watchdog and RTC RESERVED 0xFE4B5300 0xFE4BFFFF 44K Reserved RESERVED 0xFE4C0000 0xFE4CFFFF 64K Reserved RESERVED 0xFE4D0000 0xFE4FFFFF 192K Reserved COMMS 0xFE500000 0xFE5FFFFF 1M Comms (SSC, UART, IRB receiver, PWM, keyscan) SOC RESOURCES 0xFE600000 0xFFFFFFFF 26M - on fid HDMI C Confidential Start offset DocID023557 Rev 10 291/604 Interrupt network 12 STiH271EL Interrupt network The STiH271EL has three interrupt networks. One is associated with the ST40 Applications (ST40 Host); second is associated with the ST231 CPUs; and the third is a general-purpose ILC3 network to support continuity with previous generation devices, and to extend the interrupts visible to the ST231 CPUs. The full interrupt network is summarized in Figure 37. The Table 60, Table 61 and Table 62 show the ILC3 interrupt mapping for all internal and external interrupts. 292/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) C on fid Confidential en ti a l All input interrupts to these two ILC3s are fully programmable (edge/level sensitivity). STiH271EL Interrupt network Figure 37. STiH271EL interrupt network External Internal Interrupt sources Internal IRQ NMI Ethernet External ILC3 ST40 Applications (Host) EXT Mux (300x224) (223:0) INTC2 IRB wakeup interrupt INTC ti a l Information classified Confidential - Do not copy (See last page for obligations) IRL[3:0] Internal External IRQ Mux (300x61) IRQ ST231 (63-4) Audio (3) Confidential en Mailbox #1 fid Internal IRQ IRQ Mux (63-4) (300x61) (3) on External Low power mode UHF data IRB C LPC ST231 Delta Mu Mailbox #2 Internal IRQ Internal Mux ILC3 INT 63:0 Low power wakeup interrupt IRB wakeup interrupt wakeup IR data External External (300x160) ILC3 EXT 95:0 ilc_remote_out[7:4] ilc_remote_out[3:0] IRQ(3:0) Output enable PIO configuration Mailbox #0 Mailbox #1 All three ILC3 see all 6 mailbox interrupts Mailbox #2 DocID023557 Rev 10 293/604 Interrupt network STiH271EL 12.1 ST40 interrupt network 12.1.1 Internal and external interrupts The ST40-300 CPU has two types of interrupts: External interrupts: IRLINT (Interrupt Request Level INTerrupts): four external interrupt sources IRL0 to IRL3, which can be configured as four independent interrupts or encoded to provide 15 external interrupt levels. l NMI (Non-Maskable Interrupt): although normally reserved for an external interrupt source, this is mapped through an ILC3 and so can contain other interrupt sources if required. ti a These interrupts are managed by the INTC interrupt controller integrated into the ST40-300 CPU core. en The four external asynchronous interrupts and the Ethernet PHY interrupts are routed to the ILC3 interrupt controllers before reaching the ST40 and ST231, in order to synchronize and change the polarity if required. Confidential Internal peripheral interrupts: On-chip peripherals interrupt sources fid These interrupts are managed by INTC and INTC2 (which is an expansion of INTC), and an ILC3 which is used to map from the 224 possible sources to the 80 external INTEVT codes supported by the INTC2. on For the ST40 INTEV codes mapping, see Table 59. For the ST40 interrupt mapping, see Table 60. C All interrupts (except NMI) are assigned a priority level between 0 and 15: level 15 is the highest and level 1 is the lowest, while level 0 means that the interrupt is masked. The NMI is defined to have a fixed priority level of 16. INTC controls the following interrupt sources: NMI, IRL[3...0] from external inputs ST40-P130 peripherals interrupts: - UDI (user debug interface) - TMU0,1,2 (timer unit) - WDT (watchdog timer) The INTC2 controls all the on-chip peripherals interrupts, and is connected to the INTC through an interrupt expansion bus. The INTC2 accepts 16 groups of 4 interrupts (64 total). Each group can be assigned a priority by software (INTPRIxx registers). Within each group (of four interrupts), there is a fixed priority, with interrupt 4 having the highest priority. All interrupts are re-synchronized in INTC2. The INTC2 also accepts 15 interrupts to GROUP0, which had reserved functions in previous devices but are free to remap if required in the STiH271EL. 294/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) STiH271EL 12.1.2 Interrupt network Interrupt service routine address Whenever an interrupt occurs, the ST40 CPU branches to the interrupt handling vector address determined by adding the fixed offset 0x600 to the vector base address (VBR) register. Each interrupt type is assigned a code which is stored in the INTEVT (Interrupt Event) register when the interrupt occurs. This enables the interrupt service routine to identify the interrupt source type. The interrupt controller is responsible for mapping each interrupt to its code (INTEVT). ST40-300 ST40-C230 en Interrupt status signals fid INTC IRL [3:0] NMI on ST40-P130 irq UDI TMU WDT Interrupt Expansion Signals: intreq_n intlevel[3:0] INTC2 intevent[8:0] ext_intstb comms.ilc3.ext_out[7:4] STBus T1 C Confidential (CPU core) ti a l Figure 38. ST40 interrupt network async programming Registers 78:0 79 16 groups of 4 interrupts + 12 pins on group0 + 3 legacy (PIO) pins ILC3 Interrupt[223:0] internal and external interrupts DocID023557 Rev 10 The ILC3 is configured with 224 external interrupts that is asynchronous and configurable 295/604 Information classified Confidential - Do not copy (See last page for obligations) The Figure 38 describes the ST40-300 interrupt network, and Table 58 describes the internal interrupts with their INTEVT code. The Table 59 describes the internal interrupts for the on-chip peripherals with their INTEVT code. 12.1.3 Interrupt vectors table Table 58. ST40-300 P130 interrupt table IPR (bit numbers) Interrupt priority (initial value) NMI 0x1C0 - 16 Level encoding 0x200(15) 0x3C0(1) - 1-15 IRL0 0x240 IPRD[15:12] 15-0 (13) IRL1 0x2A0 IPRD[11:8] 15-0 (10) IRL2 0x300 IPRD[7:4] 15-0 (7) IRL3 0x360 IPRD[3:0] 15-0 (4) TMU0 TUNI0 0x400 IPRA[15:12] 15-0 (0) TMU1 TUNI1 0x420 IPRA[11:8] 15-0 (0) TMU2 TUNI2 0x440 IPRA[7:4] 15-0 (0) Reserved TICPI2 0x460 ATI 0x480 PRI 0x4A0 CUI 0x4C0 ERI 0x4E0 RXI 0x500 BRI 0x520 Reserved (SCIF) TXI ITI UDI H-UDI en IPRA[3:0] 15-0 (0) IPRB[7:4] 15-0 (0) 0x560 IPRB[15:12] 15-0 (0) 0x600 IPRC[3:0] 15-0 (0) 0x540 C WDT - fid Reserved (RTC) - on IRL independent encoding 296/604 l INTEVT code ti a Interrupt source IRL Confidential STiH271EL DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Interrupt network STiH271EL Table 59. Interrupt network ST40-300 on-chip peripheral interrupt table ILC3 output number INTEVT code IPR (bit numbers) INTREQ/INTMSK (bit number) 0 0xA00 INTPRI00[3:0] INTREQ00[0] 1 0xA20 2 0xA40 Group (see note) INTREQ00[1] INTREQ00[2] INTPRI00[7:4] 3 0xA60 INTREQ00[3] 4 0xA80 INTREQ00[4] 5 0xB00 INTREQ00[5] 6 0xB20 INTREQ00[6] 7 0xB40 INTREQ00[7] 8 0xB60 9 0xB80 10 0xBA0 11 0xBC0 12 0xC00 INTPRI00[15:12] 13 0xC80 INTPRI00[19:16] 14 0xD00 INTPRI00[23:20] 15 - LOW - 1 0x1060 16 0x1040 INTREQ00[8] INTREQ00[9] fid en INTREQ00[10] INTREQ00[11] INTREQ00[12] PIO 0 INTREQ00[13] PIO 1 INTREQ00[14] PIO 2 INTREQ04[3] INTREQ04[2] 17 0x1020 18 - HIGH - 3 0x1000 19 0x10E0 20 0x10C0 0x10A0 22 0x1080 23 0x1160 24 0x1140 on INTPRI04[3:0] 21 Information classified Confidential - Do not copy (See last page for obligations) l ti a INTPRI00[11:8] C Confidential Group 0 Group 1 INTREQ04[1] INTREQ04[0] INTREQ04[7] INTREQ04[6] INTPRI04[7:4] Group 2 INTREQ04[5] INTREQ04[4] INTREQ04[11] INTREQ04[10] INTPRI04[11:8] Group 3 25 0x1120 INTREQ04[9] 26 0x1100 INTREQ04[8] 27 0x11E0 INTREQ04[15] 28 0x11C0 INTREQ04[14] INTPRI04[15:12] Group 4 29 0x11A0 INTREQ04[13] 30 0x1180 INTREQ04[12] DocID023557 Rev 10 297/604 Interrupt network ST40-300 on-chip peripheral interrupt table (continued) ILC3 output number INTEVT code 31 0x1260 32 0x1240 IPR (bit numbers) INTREQ/INTMSK (bit number) INTREQ04[19] INTREQ04[18] INTPRI04[19:16] Group 5 33 0x1220 INTREQ04[17] 34 0x1200 INTREQ04[16] 35 0x12E0 INTREQ04[23] 36 0x12C0 INTREQ04[22] INTPRI04[23:20] Group 6 0x12A0 INTREQ04[21] 38 0x1280 INTREQ04[20] 39 0x1360 40 0x1340 ti a l 37 INTREQ04[27] INTREQ04[26] 0x1320 42 0x1300 43 0x13E0 44 0x13C0 0x1380 47 0x1460 48 0x1440 on 46 fid INTPRI04[31:28] 0x13A0 INTREQ04[24] INTREQ04[31] INTREQ04[30] Group 8 INTREQ04[29] INTREQ04[28] INTREQ08[3] INTREQ08[2] INTPRI08[3:0] 49 0x1420 50 0x1400 51 0x14E0 52 0x14C0 Group 9 INTREQ08[1] INTREQ08[0] INTREQ08[7] INTREQ08[6] INTPRI08[7:4] Group 10 53 0x14A0 54 0x1480 INTREQ08[4] 55 0x1560 INTREQ08[11] 56 0x1540 INTREQ08[5] INTREQ08[10] INTPRI08[11:8] Group 11 57 0x1520 INTREQ08[9] 58 0x1500 INTREQ08[8] 59 0x15E0 INTREQ08[15] 60 0x15C0 INTREQ08[14] INTPRI08[15:12] Group 12 61 0x15A0 INTREQ08[13] 62 0x1580 INTREQ08[12] 298/604 Group 7 INTREQ04[25] en 41 C Confidential INTPRI04[27:24] 45 Group (see note) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 59. STiH271EL STiH271EL ST40-300 on-chip peripheral interrupt table (continued) ILC3 output number INTEVT code 63 0x1660 64 0x1640 INTREQ/INTMSK (bit number) IPR (bit numbers) INTREQ08[19] INTREQ08[18] INTPRI08[19:16] Group 13 65 0x1620 INTREQ08[17] 66 0x1600 INTREQ08[16] 67 0x16E0 INTREQ08[23] 68 0x16C0 INTREQ08[22] INTPRI08[23:20] Group 14 0x16A0 INTREQ08[21] 70 0x1680 INTREQ08[20] 71 0x1760 72 0x1740 ti a l 69 INTREQ08[27] INTREQ08[26] 0x1720 74 0x1700 75 0x17E0 76 0x17C0 0x1780 79 0x1C0 - INTREQ08[24] INTREQ08[31] INTREQ08[30] Group 16 INTREQ08[29] INTREQ08[28] 16 NMI on 78 fid INTPRI08[31:28] 0x17A0 Group 15 INTREQ08[25] en 73 Note: The group information is not relevant for software (refer to groups/buses of INTC2 signals in hardware). Table 60. ST40 interrupt map Interrupt name EXT_0 C Confidential INTPRI08[27:24] 77 Group (see note) Interrupt controller input Unit generating the interrupt 0 External interrupt 0 EXT_1 1 External interrupt 1 EXT_2 2 External interrupt 2 EXT_3 3 External interrupt 3 ST40_HOST_WDT 4 ST40 host CPU IRB10_INT_OUT 5 IRB interrupt (always on) LPC_WDT 6 Low power controller ANOTHER_NMI 7 Non maskable interrupt (from pad) MAILBOX_0 8 Mailbox 0 (ST40 channel 0) MAILBOX_1 9 Mailbox 0 (ST40 channel 1) MAILBOX_2 10 Mailbox 1 (LX audio channel 0) MAILBOX_3 11 Mailbox 1 (LX audio channel 1) DocID023557 Rev 10 299/604 Information classified Confidential - Do not copy (See last page for obligations) Table 59. Interrupt network Interrupt network MAILBOX_4 12 Mailbox 2 (LX video channel 0) MAILBOX_5 13 Mailbox 2 (LX video channel 1) RESERVED 14 to 15 Reserved IRB10_TIMEOUT 16 IRB timeout (always on) IRB10_THRESHOLD 17 IRB threshold (always on) FDMA_0_GPIO 18 FDMA 0 FDMA_1_GPIO 19 FDMA 1 UHF10_THRESHOLD 20 UHF threshold (always on) ETH_SBD 21 Ethernet SBD ETH_PMT 22 Ethernet PMT ETH_LPI 23 Ethernet LPI UHF10_TIMEOUT 24 UHF timeout (always on) ETH_MDINT 25 UHF10_WAKEUP 26 FDMA_0_MBOX_0 27 FDMA_0_MBOX_1 28 FDMA_1_MBOX_0 29 FDMA_1_MBOX_1 30 CEC_IRQ 31 CEC (always on) REMOTE10_WAKEUP 32 Comms wakeup (always on) SSC0 33 Synchronous serial controller 0 SSC1 34 Synchronous serial controller 1 35 Synchronous serial controller 2 36 Synchronous serial controller 3 SSC10 37 Synchronous serial controller 4 (always on) SSC11 38 Synchronous serial controller 5 (always on) SSC12 39 Synchronous serial controller 6 (always on) ASC0 40 Asynchronous serial controller 0 ASC1 41 Asynchronous serial controller 1 ASC2 42 Asynchronous serial controller 2 ASC10 43 Asynchronous serial controller 3 (always on) ASC11 44 Asynchronous serial controller 4 (always on) IRB0 45 IR blaster IRB0_FIFO_THRES 46 IR blaster IRB0_TIMEOUT 47 IR blaster SSC2 SSC3 300/604 en ti a l Interrupt controller input Unit generating the interrupt on Interrupt name Ethernet MDINT UHF wakeup (always on) fid FDMA 0 FDMA 0 FDMA 1 FDMA 1 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) ST40 interrupt map (continued) C Confidential Table 60. STiH271EL STiH271EL REMOTE0_WAKEUP 48 Comms wakeup KEYSCAN 49 Key scanner (always on) RTC 50 RTC (always on) PWM10 51 PWM (always on) L2CACHE 52 ST40 host L2 cache RESERVED 53 RESERVED RESERVED 54 RESERVED RESERVED 55 RESERVED RESERVED 56 RESERVED RESERVED 57 RESERVED RESERVED 58 RESERVED USB_0_EHCI 59 USB 0 USB_1_EHCI 60 RESERVED 61 USB_0_OHCI 62 USB_1_OHCI 63 MAILBOX10_IRQ 64 RESERVED 65 to 69 PCMPLAYER_1 70 PCM player 1 PCMPLAYER_2 71 PCM player 2 PCMREADER 72 PCM reader STFE_DATA 73 Transport front-end 74 Transport front-end 75 Transport front-end RESERVED 76 Reserved STFE_TP_MBX_0 77 Transport engine RESERVED 78 to 80 Reserved BDISP_AQ_1 81 Blitter display BDISP_AQ_2 82 Blitter display BDISP_AQ_3 83 Blitter display BDISP_AQ_4 84 Blitter display BDISP_CQ_1 85 Blitter display BDISP_CQ_2 86 Blitter display DELTA_MBE 87 Video decoder DELTA_PP 88 Video decoder STFE_ERROR STFE_IDLE en ti a l Interrupt controller input Unit generating the interrupt on Interrupt name Information classified Confidential - Do not copy (See last page for obligations) ST40 interrupt map (continued) C USB 1 Reserved USB 0 fid Confidential Table 60. Interrupt network USB 1 Mailbox (always on) Reserved DocID023557 Rev 10 301/604 Interrupt network Interrupt controller input Unit generating the interrupt COMMS LPC 89 COMMS low power out AUX_VTG_VSYNC 90 Auxiliary VTG AUX_VTG_LINE 91 Auxiliary VTG MAIN_VTG_SYNC 92 Main VTG MAIN_VTG_LINE 93 Main VTG RESERVED 94 to 97 Reserved HDF_AWGSD 98 HD video formatter HDF_AWGHD 99 HD video formatter I2S2SPDIF_0 100 HDMI formatter I2S2SPDIF_1 101 HDMI formatter I2S2SPDIF_2 102 HDMI formatter I2S2SPDIF_3 103 HDMI formatter SPDIFPLAYER 104 PCMPLAYER_0 105 RESERVED 106 HDMI_FORMATTER 107 108 ti a en HDMI formatter HDMI formatter Reserved fid TTXT (1) l Interrupt name HDMI formatter Teletext 109 AUX_VDP_UNF 110 Aux video display COMPO_OVF 111 Video compositor COMPO_TF 112 Video compositor TTXT_DENC_MAIN(2) 113 Dual DENC 114 to 116 Reserved 117 High quality video display DDR_MIXER 118 DDR mixer LPM_XP70_IDLE_REQ 119 XP70 idle (always on) MMC_IRQ 120 MMC controller NAND_IRQ 121 NAND controller RESERVED 122 to 127 Reserved WDT_TIMEOUT 128 Watchdog timeout (always on) PIO_0 129 PIO 0 (always on) PIO_1 130 PIO 1 (always on) PIO_2 131 PIO 2 (always on) PIO_3 132 PIO 3 (always on) PIO_4 133 PIO 4 RESERVED HQVDP_IRQ 302/604 on AUX_VDP_END_PROC Aux video display DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) ST40 interrupt map (continued) C Confidential Table 60. STiH271EL STiH271EL PIO_5 134 PIO 5 PIO_6 135 PIO 6 PIO_7 136 PIO 7 PIO_8 137 PIO 8 PIO_9 138 PIO 9 PIO_10 139 PIO 10 PIO_11 140 PIO 11 PIO_12 141 PIO 12 PIO_13 142 PIO 13 PIO_14 143 PIO 14 PIO_15 144 PIO 15 RESERVED 145 to 156 Reserved STFE_TP_MBX_1 157 RESERVED 158 to 161 SYSCFG_0 162 SYSCFG_1 163 SYSCFG_2 164 SYSCFG_3 165 SYSCFG_4 166 SYSCFG_5 167 SYSCFG_6 168 SYSCFG_7 169 RESERVED en ti a l Interrupt controller input Unit generating the interrupt on Interrupt name Transport engine fid Reserved Software interrupt using the SYSTEM_CONFIG234 register 170 Reserved 171 Clock generator A0 CLKGENA_1_CLKOBS 172 Clock generator A1 RESERVED 173 to 177 Reserved RESERVED 178 RESERVED RESERVED 179 to 180 Reserved RESERVED 181 Reserved RESERVED 181 Reserved RESERVED 182 to 213 Reserved MCRU0 214 MCRU 0 MCRU1 215 MCRU 1 MCRU2 216 MCRU 2 MCRU3 217 MCRU 3 CLKGENA_0_CLKOBS DocID023557 Rev 10 303/604 Information classified Confidential - Do not copy (See last page for obligations) ST40 interrupt map (continued) C Confidential Table 60. Interrupt network Interrupt network Table 60. STiH271EL ST40 interrupt map (continued) Interrupt name Interrupt controller input Unit generating the interrupt GPTIME0 218 Timeout 0 GPTIME1 219 Timeout 1 EXT_4 220 External interrupt 4 EXT_5 221 External interrupt 5 RESERVED 222 to 223 Reserved 12.2 ti a l 2. The control register of the Main DENC of the TTXT block exists at the following address: "HDTVOUT_TOP_GLUE_DENC_MAIN_BASE_ADDRESS + HTO_DENC_MAIN_TTXT_CTRL_ADDRESS or TVOUT_FDMA_BASE_ADDRESS + HDTVOUT_TOP_GLUE_DENC_MAIN_OFFSET + HTO_DENC_MAIN_TTXT_CTRL_ADDRESS or 0xfd000000 + 0x0F00 + 0x30". DeltaMu (video) and audio ST231 interrupt network Confidential en The ST231 accepts 61 external interrupts (from 63 to 3). The interrupts 0 to 2 are reserved to the ST231 internal timers. All the interrupts are maskable but with a single level of priority. Multiple-level priority must be implemented in the software. The interrupts are active high and are resynchronized in the ST231 clk_bus clock domain. fid The Table 61 describes the mapping of the interrupts on the three ST231 interrupt controllers. on When used as an application processor, the ST231 processors receive a subset of the internal interrupts of the ST40 processor. The ST231s also receive the external interrupts through the ILC3 interrupt controller (see ilc_remote_out[7:4] in Figure 37). Through these interrupt lines, any other internal interrupts can be managed by one of the ST231s. 304/604 ST231 interrupt map C Table 61. Software interrupt name Interrupt controller input Unit generating the interrupt ST231_TIMER_0 0 ST231 (timer) ST231_TIMER_1 1 ST231 (timer) ST231_TIMER_2 2 ST231 (timer) AUX_VTG_VSYNC 3 Auxiliary VTG AUX_VTG_LINE 4 Auxiliary VTG MAIN_VTG_SYNC 5 Main VTG MAIN_VTG_LINE 6 Main VTG CEC_IRQ 7 CEC (always on) TTXT_DENC_MAIN 8 Dual DENC RESERVED 9 to 10 Reserved HDF_AWGSD 11 HD video formatter DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 1. The control register of the first DENC of the TTXT block exists at the following address: "HDTVOUT_TOP_GLUE_AUX_BASE_ADDRESS + TTXT_CTRL_ADDRESS or TVOUT_FDMA_BASE_ADDRESS + HDTVOUT_TOP_GLUE_AUX_OFFSET + TTXT_CTRL_ADDRESS or 0xfd000000 + 0x0E00 + 0x30". STiH271EL Interrupt network ST231 interrupt map (continued) Unit generating the interrupt HDF_AWGHD 12 HD video formatter I2S2SPDIF_0 13 HDMI formatter I2S2SPDIF_1 14 HDMI formatter I2S2SPDIF_2 15 HDMI formatter I2S2SPDIF_3 16 HDMI formatter SPDIFPLAYER 17 HDMI formatter PCMPLAYER_0 18 HDMI formatter RESERVED 19 Reserved HDMI_FORMATTER 20 TTXT 21 FDMA_0_MBOX_0 22 FDMA_0_MBOX_1 23 FDMA_1_MBOX_0 24 FDMA_1_MBOX_1 25 RESERVED 26 to 28 ti a en fid MAILBOX_0 HDMI formatter Teletext FDMA 0 FDMA 0 FDMA 1 FDMA 1 Reserved 29 Mailbox 0 (channel 0) 30 Mailbox 1 (channel 0) 31 Mailbox 2 (channel 0) 32 to 33 Reserved 34 Video decoder 35 Video decoder 36 PCM player 1 PCMPLAYER_2 37 PCM player 2 PCMREADER 38 PCM reader STFE_DATA 39 Transport front-end STFE_ERROR 40 Transport front-end STFE_IDLE 41 Transport front-end RESERVED 42 Reserved STFE_TP_MBX_0 43 Transport engine RESERVED 44 Reserved STFE_TP_MBX_1 45 Transport engine RESERVED 46 to 49 Reserved PWM10 50 PWM (always on) RESERVED 51 to 56 Reserved DDR_MIXER 57 DDR mixer MAILBOX_2 RESERVED DELTA_MBE DELTA_PP PCMPLAYER_1 on MAILBOX_4 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Interrupt controller input l Software interrupt name C Confidential Table 61. 305/604 Interrupt network Table 61. STiH271EL ST231 interrupt map (continued) Software interrupt name Interrupt controller input Unit generating the interrupt RESERVED 58 to 59 Reserved EXT_4(1) 60 External interrupt 4 EXT_5 61 External interrupt 5 EXT_6 62 External interrupt 6 EXT_7 63 External interrupt 7 ILC3 interrupt level controller l Comms ILC3 interrupt network ti a 12.3 Confidential en The STiH271EL interrupt network includes a general-purpose ILC3 interrupt level controller in the comms block to support legacy software. This ILC3 accepts 64 synchronous interrupt inputs and 96 asynchronous interrupt inputs. The external interrupts can have up to five programmable triggering conditions (active high, active low, falling edge, rising edge or any edge). fid The ILC3 maps any of these interrupts onto a group of 16 interrupt levels. Bits[3:0] are mapped to external PADS and to the FDMA. Bits[7:4] are mapped to the ST40 IRL inputs, to the ST231 interrupts, and as inputs to the ST40 - ILC3. The ILC3 mapping is described in Table 62. on Wake up by interrupt The ILC3 has also an interrupt output dedicated to the wake-up process. A pulse stretcher receives a transition from the UHF and IR input pins and generates an interrupt connected to one of the external interrupt inputs. C Internal peripheral interrupts The COMMS ILC3 supports 64 internal interrupts which are level sensitive and active HIGH. These are used to allow the ILC3 visibility of all interrupts. External interrupts inputs The four external asynchronous interrupts and the Ethernet PHY interrupts are routed to the ILC3 interrupt controller before reaching the processors, in order to synchronize and change the polarity if needed. External interrupts outputs The ILC3 has the capability to output a subset of the interrupts that are connected to it. Four of these interrupts are software selectable to be output externally for remote devices. Control of the external interrupts direction The direction of the external interrupts is controlled by the PIO configuration registers. 306/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 1. External interrupts 0, 1, 2 and 3 are not used. 12.4 Comms ILC Table 62. Comms ILC3 interrupt map Interrupt controller input Unit generating the interrupt EXT_0 External 0 External interrupt 0 EXT_1 External 1 External interrupt 1 EXT_2 External 2 External interrupt 2 EXT_3 External 3 External interrupt 3 ST40_HOST_WDT External 4 ST40 host CPU IRB10_INT_OUT External 5 IRB interrupt (always on) LPC_WDT External 6 Low power controller ANOTHER_NMI External 7 MAILBOX_0 External 8 MAILBOX_1 External 9 MAILBOX_2 External 10 Mailbox 2 (channel 0) MAILBOX_3 External 11 Mailbox 3 (channel 1) MAILBOX_4 External 12 Mailbox 4 (channel 0) MAILBOX_5 External 13 Mailbox 5 (channel 1) RESERVED External 14 Reserved RESERVED External 15 Reserved IRB10_TIMEOUT External 16 IRB timeout (always on) External 17 IRB threshold (always on) External 18 FDMA 0 External 19 FDMA 1 External 20 UHF threshold (always on) External 21 Ethernet LPI ETH_PMT External 22 Ethernet PMT ETH_SBD External 23 Ethernet SBD UHF10_TIMEOUT External 24 UHF timeout (always on) ETH_MDINT External 25 Ethernet MDINT UHF10_WAKEUP External 26 UHF wakeup (always on) FDMA_0_MBOX_0 External 27 FDMA 0 FDMA_0_MBOX_1 External 28 FDMA 0 FDMA_1_MBOX_0 External 29 FDMA 1 FDMA_1_MBOX_1 External 30 FDMA 1 CEC_IRQ External 31 CEC (always on) REMOTE10_WAKEUP External 32 Comms wakeup (always on) FDMA_0_GPIO FDMA_1_GPIO ETH_LPI ti a en fid on IRB10_THRESHOLD UHF10_THRESHOLD l Interrupt name Information classified Confidential - Do not copy (See last page for obligations) Interrupt network C Confidential STiH271EL DocID023557 Rev 10 Non maskable interrupt (from pad) Mailbox 0 (channel 0) Mailbox 1 (channel 1) 307/604 Interrupt network Interrupt controller input Unit generating the interrupt SSC0 External 33 Synchronous serial controller 0 SSC1 External 34 Synchronous serial controller 1 SSC2 External 35 Synchronous serial controller 2 SSC3 External 36 Synchronous serial controller 3 SSC10 External 37 Synchronous serial controller 4 (always on) SSC11 External 38 Synchronous serial controller 5 (always on) SSC12 External 39 Synchronous serial controller 6 (always on) ASC0 External 40 Asynchronous serial controller 0 ASC1 External 41 ASC2 External 42 ASC10 External 43 ASC11 External 44 IRB0 External 45 IR blaster IRB0_FIFO_THRES External 46 IR blaster IRB0_TIMEOUT External 47 IR blaster REMOTE0_WAKEUP External 48 Comms wakeup KEYSCAN External 49 Key scanner (always on) RTC External 50 RTC (always on) on fid en ti a Asynchronous serial controller 1 PWM10 Asynchronous serial controller 2 Asynchronous serial controller 3 (always on) Asynchronous serial controller 4 (always on) External 51 PWM (always on) External 52 ST40 host L2 cache External 53 RESERVED External 54 RESERVED External 55 RESERVED External 56 RESERVED RESERVED External 57 RESERVED RESERVED External 58 RESERVED USB_0_EHCI External 59 USB 0 USB_1_EHCI External 60 USB 1 WDT_TIMEOUT External 61 Watchdog timeout (always on) USB_0_OHCI External 62 USB 0 USB_1_OHCI External 63 USB 1 MAILBOX10_IRQ External 64 Mailbox (always on) RESERVED External 65 to 69 Reserved PCMPLAYER_1 External 70 PCM player 1 PCMPLAYER_2 External 71 PCM player 2 L2CACHE RESERVED RESERVED RESERVED RESERVED 308/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Interrupt name l Comms ILC3 interrupt map (continued) C Confidential Table 62. STiH271EL STiH271EL Interrupt controller input Unit generating the interrupt PCMREADER External 72 PCM reader STFE_DATA External 73 Transport front-end STFE_ERROR External 74 Transport front-end STFE_IDLE External 75 Transport front-end RESERVED External 76 Reserved STFE_TP_MBX_0 External 77 Transport engine RESERVED External 78 to 80 Reserved BDISP_AQ_1 External 81 Blitter display BDISP_AQ_2 External 82 BDISP_AQ_3 External 83 BDISP_AQ_4 External 84 BDISP_CQ_1 External 85 BDISP_CQ_2 External 86 Blitter display DELTA_MBE External 87 Video decoder DELTA_PP External 88 Video decoder TTXT_DENC_MAIN External 89 Dual DENC AUX_VTG_VSYNC External 90 Auxiliary VTG AUX_VTG_LINE External 91 Auxiliary VTG fid en ti a Blitter display on MAIN_VTG_SYNC Blitter display Blitter display Blitter display External 92 Main VTG External 93 Main VTG External 94 to 95 Reserved Internal 0 to 1 Reserved Internal 2 HD video formatter Internal 3 HD video formatter I2S2SPDIF_0 Internal 4 HDMI formatter I2S2SPDIF_1 Internal 5 HDMI formatter I2S2SPDIF_2 Internal 6 HDMI formatter I2S2SPDIF_3 Internal 7 HDMI formatter SPDIFPLAYER Internal 8 HDMI formatter PCMPLAYER_0 Internal 9 HDMI formatter RESERVED Internal 10 - HDMI_FORMATTER Internal 11 HDMI formatter TTXT Internal 12 Teletext AUX_VDP_END_PROC Internal 13 Aux video display AUX_VDP_UNF Internal 14 Aux video display MAIN_VTG_LINE RESERVED RESERVED HDF_AWGSD HDF_AWGHD Information classified Confidential - Do not copy (See last page for obligations) Interrupt name l Comms ILC3 interrupt map (continued) C Confidential Table 62. Interrupt network DocID023557 Rev 10 309/604 Interrupt network Interrupt controller input Unit generating the interrupt COMPO_OVF Internal 15 Video compositor COMPO_TF Internal 16 Video compositor TTXT_DENC_MAIN Internal 17 Dual DENC CEC_IRQ Internal 18 CEC (always on) RESERVED Internal 19 to 20 Reserved HQVDP_IRQ Internal 21 High quality video display DDR_MIXER Internal 22 DDR mixer RESERVED Internal 23 Reserved MMC_IRQ Internal 24 NAND_IRQ Internal 25 RESERVED Internal 26 RESERVED Internal 27 RESERVED Internal 28 RESERVED Internal 29 RESERVED Internal 30 RESERVED Internal 31 Reserved RESERVED Internal 32 RESERVED PIO_0 Internal 33 PIO 0 on fid en ti a MMC controller PIO_1 NAND controller RESERVED RESERVED RESERVED RESERVED RESERVED Internal 34 PIO 1 Internal 35 PIO 2 Internal 36 PIO 3 Internal 37 PIO 4 Internal 38 PIO 5 Internal 39 PIO 6 PIO_7 Internal 40 PIO 7 PIO_8 Internal 41 PIO 8 PIO_9 Internal 42 PIO 9 PIO_10 Internal 43 PIO 10 PIO_11 Internal 44 PIO 11 PIO_12 Internal 45 PIO 12 PIO_13 Internal 46 PIO 13 PIO_14 Internal 47 PIO 14 PIO_15 Internal 48 PIO 15 RESERVED Internal 49 to 60 Reserved PIO_2 PIO_3 PIO_4 PIO_5 PIO_6 310/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Interrupt name l Comms ILC3 interrupt map (continued) C Confidential Table 62. STiH271EL STiH271EL Table 62. Interrupt network Comms ILC3 interrupt map (continued) Interrupt name Interrupt controller input Unit generating the interrupt STFE_TP_MBX_1 Internal 61 Transport engine RESERVED Internal 62 to 63 Reserved 12.5 CPU mailboxes C on fid Confidential en ti a l Each mailbox has two interrupt output signals; all 6 interrupts connect into the ST40 ILC3s (see Table 62), giving ST40s full visibility during debug and to the two ST231 (see Table 61). DocID023557 Rev 10 311/604 Information classified Confidential - Do not copy (See last page for obligations) The STiH271EL provides three CPU `mailboxes' to facilitate communication between onchip CPUs. Any CPU can access any mailbox using an R/W operation. DMA network 13 STiH271EL DMA network The STiH271EL integrates two multi-channel general-purpose DMA engines. FDMA AUD-VID-RT: audio/video real time FDMA or FDMA0. FDMA GP: general purpose FDMA, application FDMA or FDMA1. ti a l The FDMA supports free-running and paced transfers. The controlling software driver sets up each DMA transfer by writing a linked-list of data structures in main memory. The driver then initializes the transfer by writing the pointer to the first node in the CWI (Control Word Interface) of the FDMA. The FDMA then executes the necessary operations to complete the transfer and informs the driver (through interrupts) when the transfer is complete. Dual-PES parsing channel on same FDMA en Video PES parsing and start-code detection (PES/SCD) for H.264, VC1 and MPEG2 FDMA and driver communications fid 13.1 on Communication with the host is done through dedicated areas of the internal data memory plus two mailbox peripherals. One mailbox is used by the driver to send messages to the FDMA (Mailbox 0, connected to the internal CPU as an external flag). The other mailbox is used by the FDMA to send messages to the driver (Mailbox 1). Mailbox 1 has two request outputs, which are connected to the interrupt network to be visible by all CPUs. C Confidential The FDMA also includes video stream parsing functions: 312/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The FDMA is a general purpose direct memory access controller capable of supporting 16 independent DMA channels. Their purpose is to move data efficiently from memory to memory, memory to peripheral and peripheral to peripheral. The two FDMAs are integrated such that any DMA task can be run on any DMA engine, subject to software partitioning constraints. STiH271EL 13.2 DMA network FDMA requests Figure 39. FDMA request network External I/Os EXTDMA_REQ[2:0] COMMs UART_TX_BUF_HALF_EMPTY<4:0> UART_RX_BUF_HALF_FULL<4:0> DMA_REQ[31:0] 5x UART FDMA 0 SSC_TX_BUF_EMPTY<6:0> 7xSSCs SSC_RX_BUF_FULL<6:0> ti a Audio peripherals PCM reader en S/PDIF player Teletext/HDMI 2 swts req EMI subsystem Serial Flash controller O_COUNTER_REQ on NAND controller FDMA 1 fid Confidential Transport STFE DMA_REQ[31:0] DREQ XBAR FDMA PCM players C The FDMA receives a number of requests where pacing is required for flow control in the system. This signal is a simple high-level sensitive signal used in conjunction with a hold-off counter. The units that emit a request signal are the audio peripherals (PCM players, PCM reader and S/PDIF player), the transport STFE (software stream), the UARTs, the SSCs, the Serial Flash controller, the NAND controller and the external DMA requests. The FDMA accepts up to 32 DMA requests or "events" that are used to drive the paced channels of the FDMA. By connecting their internal timers to requests 0 and 31, software has access to a low-priority timed channel and to a high-priority timed channel. FDMArequest mapping in STiH271EL is fully configurable thanks to the DREQ crossbar router. 13.3 FDMA request table Table 63. FDMA requests Request source Request signal Request index FDMA0 FDMA0_CNTR 1 FDMA1 FDMA1_CNTR 2 DocID023557 Rev 10 Comment 313/604 Information classified Confidential - Do not copy (See last page for obligations) l O_COUNTER_REQ DMA network FDMA requests (continued) SSC0 SSC0_RX 3 SSC1 SSC1_RX 4 SSC2 SSC2_RX 5 SSC3 SSC3_RX 6 SSC0 SSC0_TX 7 SSC1 SSC1_TX 8 SSC2 SSC2_TX 9 SSC3 SSC3_TX 10 UART0 UART0_RX 11 UART1 UART1_RX UART10 UART10_RX UART11 UART11_RX UART0 UART0_TX UART1 UART1_TX UART10 UART10_TX UART11 UART11_TX HDMI HDMI_AVI_TX IRB0 IRB0_RX IRB0 IRB0_TX 21 UHF0 UHF0_RX 22 PCM player0 PCMPLAYER0_TX 23 PCM player1 PCMPLAYER1_TX PCMPLAYER2_TX 25 Comment on fid en 12 13 Always on 14 Always on 15 16 17 Always on 18 Always on 19 20 24 PCM reader0 PCMREADER0_RX 26 S/PDIF player SPDIFPLAYER_TX 27 Transport SWTS0_RX 28 Transport SWTS1_RX 29 IRB10 IRB10_RX 30 Always on UHF10 UHF10_RX 31 Always on Teletext TTXT_RX 32 Teletext main MAIN_TTXT_RX 33 NAND controller NAND_AFM_DATA_RXTX 34 NAND controller NAND_AFM_SEQ_RX 35 Serial Flash controller SPI_AFM_DATA_RXTX 36 Serial Flash controller SPI_AFM_SEQ_RX 37 PCM player2 314/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Request index l Request signal ti a Request source C Confidential Table 63. STiH271EL STiH271EL UART2 UART2_THRES 38 UART2 UART2_TIMEOUT 39 UART2 UART2_RX 40 PIO EXTDMA0_REQ 41 PIO EXTDMA1_REQ 42 UART2 UART2_TX 43 System configuration SYSCONFIG0_REQ 44 System configuration SYSCONFIG1_REQ 45 System configuration SYSCONFIG2_REQ 46 RESERVED RESERVED SSC10 SSC10_RX SSC10 SSC10_TX SSC11 SSC11_RX SSC11 SSC11_TX SSC12 SSC12_RX SSC12 SSC12_TX UART0 UART0_SC_THRES 54 UART0 UART0_SC_TIMEOUT 55 UART1 UART1_SC_THRES 56 UART1 UART1_SC_TIMEOUT 57 UART10 UART10_SC_THRES 58 Always on UART10 UART10_SC_TIMEOUT 59 Always on UART11_SC_THRES 60 Always on Always on ti a fid RESERVED RESERVED 48 Always on 49 Always on 50 Always on 51 Always on 52 Always on 53 Always on UART11 UART11_SC_TIMEOUT 61 UHF0 UHF0_THRES 62 UHF0 UHF0_TIMEOUT 63 UART11 Comment DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Request index l Request signal en Request source on FDMA requests (continued) C Confidential Table 63. DMA network 315/604 Clocking 14 STiH271EL Clocking The STiH271EL includes five clock generator subsystems: Clock generator A0 for the CPUs, EMI and interconnect clocks Clock generator A1 for the Display pipeline, STFE, FDMAs slim and interconnect clocks VID-FS0 for the main display, video output stage and peripheral clocks VID-FS1 for the aux video and aux audio clocks GP-FS2 for the peripheral clocks One alternate system clock input Some internal clocks can also be observed or used as an auxiliary clock. The Figure 40 shows the overall clocking system. SYS_CLKINALT Mode[8] (Alternate clock select) en OSC OSC C SYS_CLKOSC 30 MHz crystal fid on SYS_CLKIN SYS_CLKIN Confidential STiH271EL SYS_CLKIN Figure 40. STiH271EL clocking: block diagram Clock generator A0 Clock generator A1 CPU, HQVDP, EMI, infrastructure DISP, STFE, DMA, infrastructure VID-FS0 Video/audio VID-FS1 Video/audio 0 1 GPFS GP-FS2 See note below Note: 316/604 The STiH271EL implements a clock recovery mechanism to lock some video/audio clocks to the MPEG encoder clock. This mechanism uses digitally controllable frequency synthesizers and an integrated digital clock recovery unit. This can replace the external VCXO functionality and allows the use of a fixed-frequency oscillator. Nevertheless, the external VCXO functionality is still available. When the external VCXO functionality is used, the VCXO oscillator must be connected to the alternate clock input SYS_CLKINALT. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) A 30-MHz oscillator ti a l The clock generators are associated with two external sources: STiH271EL 14.1 Clocking Clock input pins The STiH271EL uses a mode pin to select the reference clock for ClockGenA PLLs either from the 30 MHz system oscillator or from SYS_CLKINALT. The following table shows the mapping between the clock sources and the clock generators. Table 64. STiH271EL clocking network: source and destination table . Clock source Clock generator A0: CPU, and so on YES YES Selection by mode pin [8] (alternate clock select) Clock generator A1: Display pipe, and so on YES YES Selection by mode pin [8] (alternate clock select) VID-FS0 YES YES VID-FS1 YES YES GP-FS2 YES YES ti a Selection by mode pin [8] (alternate clock select) en Clock domains Selection by mode pin [8] (alternate clock select) Selection by mode pin [8] (alternate clock select) fid 14.2 l SYS_CLKINALT The clocking of the functional units integrated in the STiH271EL is described in Table 65. In the table, the clock that rules the interconnect bus plug of each functional unit is called "interface clock". Functional blocks clocking Block Clock signal on Table 65. Clock Max generator frequency source Comment ST40-300 host CLK_SH4L2_ICK A0 650 MHz CPU processing and interface clock Mailbox CLK_IC_REG_LP_ON A0 100 MHz Mailbox interface clock CLK_LX_AUD_CPU A0 650 MHz ST231 processing clock CLK_BLIT_PROC A1 333 MHz Blitter processing clock CLK_IC_BDISP A1 266 MHz Blitter interface clock CLK_SLIM_FDMA_0 A1 400 MHz SLIM processing clock CLK_IC_REG_LP_ON A0 100 MHz FDMA port 0 interface clock CLK_IC_TS_DMA A0 225 MHz FDMA port 1 interface clock Host CPU General purpose CPU ST231_GP Graphic Blitter display DMA FDMA0 DocID023557 Rev 10 317/604 Information classified Confidential - Do not copy (See last page for obligations) Comments SYS_CLKIN C Confidential Clock destination Clocking Table 65. Block FDMA1 STiH271EL Functional blocks clocking (continued) Clock signal Clock Max generator frequency source Comment CLK_SLIM_FDMA_1 A1 400 MHz SLIM processing clock CLK_IC_REG_LP_ON A0 100 MHz FDMA port 0 interface clock CLK_IC_TS_DMA A0 225 MHz FDMA port 1 interface clock A0 366 MHz HD-display pipeline processing clock VCC 148.5 MHz HD-display-to-compositor pixel clock A1 220 MHz HD-display interface clock CLK_IC_IQI A1 200 MHz HD-display IQI clock CLK_VDP_PROC A1 250 MHz SD-display pipeline processing clock CLK_DISP_PIP VCC 13.5 MHz in SD and 74.5 MHz in HD (PIP) SD-display-to-compositor pixel clock Note: This clock can run up to 148.5 MHz if the Aux display is acting as main HD display (that is, feeding the main mixer of the compositor) CLK_IC_COMPO_DISP A1 220 MHz SD-display interface clock A1 220 MHz GDPs pipeline processing clock VCC 148.5 MHz Main mixer (HD) pixel clock VCC 148.5 MHz Capture port (HD) pixel clock VCC 13.5 MHz Aux mixer (SD) pixel clock VCC 13.5 MHz in SD and 74.5 MHz in HD (PIP) Video1 pixel clock (SD or HD) CLK_DISP_HD or CLK_DISP_ID (GDP1_CK = VCC GDP2_CK) 148.5 MHz GDP1 and GDP2 pixel clock (HD or SD) CLK_DISP_HD or CLK_DISP_ID VCC 148.5 MHz GDP3 and GDP4 pixel clock (HD or SD) CLK_IC_COMPO_DISP A1 220 MHz GDPs interface clock CLK_GDP_PROC A0 360 MHz GDPs processor clock VCC 27 MHz DENC processing clock CLK_IC_COMPO_DISP CLK_DISP_HD CLK_DISP_ID on CLK_DISP_HD ti a C CLK_DISP_PIP Compositor Video output stage DENC 318/604 CLK_PIX_SD DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Confidential SD display (VDP aux) en CLK_DISP_HD HD display (HQ-VDP main) CLK_IC_COMPO_DISP fid CLK_HQ_VDP_PROC l Displays composition STiH271EL Functional blocks clocking (continued) Comment CLK_DISP_HD VCC 148.5 MHz HD pixel input clock CLK_PIX_SD VCC 27 MHz SD pixel input clock CLK_PIX_HD VCC 148.5 MHz in HD, 108 MHz in SD Pixel output clock FlexDVO CLK_656 VCC 148.5 MHz HD pixel input clock VTG0 CLK_DISP_HD VCC 148.5 MHz HD display clock VTG1 CLK_DISP_ID VCC 13.5 MHz HD video DAC CLK_PIX_HD VCC 148.5 MHz HD video DAC sampling clock SD video DAC CLK_PIX_SD VCC 27 MHz SD video DAC sampling clock LX- audio (GP) CLK_LX_AUD_CPU A0 PCM player1 (connected to internal audio DACs) CLK_PCM1 GP-FS2 Audio DAC CLK_PCM1 PCM player2 (2-ch digital audio) CLK_PCM2 Interlaced display (ID) clock ST231 processing and interface clock PCM oversampling clock (256 = 192 kHz max) Fs, Fs 50 MHz 50 MHz DAC oversampling clock (256 = 48 kHz max) Fs, Fs GP-FS2 50 MHz PCM oversampling clock (256 = 192 kHz max) Fs, Fs VID-FS1 A0 450 MHz ST231 processing clock CLK_IC_DMU A1 266 MHz DeltaMu interface clock CLK_DMU_PREPROC A0 180 MHz DeltaMu pre-processor clock CLK_FRC0 (CLK_27_0) VID-FS0 27 MHz Free running and programmable counter0 (timestamp) CLK_FRC1 (CLK_27_1) VID-FS1 27 MHZ Free running and programmable counter1 (timestamp) CLK_PACE VID-FS0 27MHz Programmable counter1 CLK_IC_TS_DMA A0 225 MHz STFE interface clock CLK_TP A1 400 MHz TP processing clock CLK_IC_TS_DMA A0 225 MHz TP interface clock CLK_IC_TS_DMA A0 225 MHz SC interface clock on Video decoding fid 650 MHz C Confidential Audio en HD-formatter input l Clock Max generator frequency source ti a Clock signal Block DeltaMu ST231 CLK_LX_DMU_CPU DeltaMu Hw Transport Transport stream preprocessor (STFE) STFE (TP and SC) DocID023557 Rev 10 319/604 Information classified Confidential - Do not copy (See last page for obligations) Table 65. Clocking Clocking Functional blocks clocking (continued) Clock signal Clock Max generator frequency source Comment ETHERNET GMAC CLK_ETHERNET_PHY A1 50 MHz Clock for Ethernet PHY ETHERNET GMAC CLK_IC_GMAC A1 100 MHz Ethernet interface clock USB2.0 Host controller (0-1) CLK_IC_REG_LP_OFF A0 100 MHz USB2.0 Host controller (0-1) interface clock USB2.0 Host controller (0-1) CLOCK60 USB dual PHY 60 MHz From USB PHY PLL USB2.0 Host controller (0-1) CLOCK48 VID-FS1 48 MHz USB0 CLK_UTMI_PHY0_USB USB PHY 60MHz utmi_phy_clock_i USB1 CLK_UTMI_PHY1_USB USB PHY 60MHz utmi_phy_clock_i CLK_DISP_HD VCC 148.5 MHz Pixel clock CLK_TMDS_HDMI en Table 65. STiH271EL HDMI PHY 222.75 MHz TMDS clock is 1.5 12-bit deep color. VCC 148.5 MHz From rejection PLL VID-FS0 50 MHz PCM oversampling clock (256 = 192 kHz Max) GP-FS2 15 MHz S/PDIF clock 256 FS = 256 Block Memory interfaces CLK_EMISS EMISS pixel clock for Fs, Fs 48 kHz l ti a A0 100 MHz EMI subsystem interface clock (clock) CLK_NAND_CTRL A1 200 MHz NAND controller clock CLK_SYS_MMC A1 200 MHz MMC subsystem interface clock (clk_sys_mmc) CLK_CARD_MMC A1 50 MHz MMC card clock CLK_IC_DDRCTRL_0 A1 333 MHz From PLL CLK_LPC FS2 315 kHz Low power clock CLK_DSS FS2 36.864 MHz Smartcard clock MMC DDR SS 0 Used in USB 1.1 mode Comms COMMs 14.3 Clock generator A: CPUs, interconnect and processing clock generation Clock generator A generates the clocks for the CPUs, the interconnect and most of the processing parts of the blocks. 320/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) CLK_SPDIF on CLK_PCM0 fid CLK_PLL_HDMI_PHY HDMI C Confidential Connectivity STiH271EL Clocking The STiH271EL uses two instances of clock generator A, these instances are called A0 and A1. C on fid Confidential en ti a l Information classified Confidential - Do not copy (See last page for obligations) Clock generator A consists of two PLLs (PLL0 1800 and PLL1 1800) attached to a modular array of 18 clock dividers. DocID023557 Rev 10 321/604 Clocking STiH271EL Figure 41. Clock generator A simplified block diagram X6 PLL0 DIV_0 HS HS (1000) PLL0 6 PLL1 DIV_1 HS LS (500) clk_div_hs[5:0] HS (900) LS (450) PLL1 DIV_1 HS clk_osc_a Optional pre dividers (/32) clk_div_hs[9:6] DIV OSC fid clk_osc_c on clk_osc_d X22 PLL0 DIV_0 LS 22 PLL1 DIV_1 LS clk_div_hs[31:10] DIV OSC C Confidential clk_osc Clock op source switch control 4 en clk_osc_b ti a PLL1 l X4 PLL0 DIV_0 LS Observation counter Divider control Clock monitor points Obs Mux0 clk_funcobs T1 target interface STBus interface registers Clock monitor points Obs Mux1 clk_stbus clk_funcobs2 At boot, the PLLs are bypassed and the chip is clocked directly from the oscillator clock. It is up to the boot code to set up the defined PLL settings and the clock configuration by programming the clock dividers with the appropriate value. 322/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) DIV OSC STiH271EL 14.3.1 Clocking Clock generator A functional description Clock generator A has a modular and configurable architecture including: Two PLLs Two clocks out for each PLL 32 independent output clocks A low-power mode based on an optional divide-by-16 oscillator clock A clock observation mechanism PLL0/PLL1 settings 4 MHz <= Fin = Fosc <= 360 MHz D = Loop divider; 5 < D < 256 R = Input divider; 0 < R < 8 600 MHz <= FHS <= 1800 MHz FLS = FHS / 2 en Confidential where: ti a l FHS = Fin x ((2 x D) / R) fid Apart from the PLL powerdown control handled by CLKGNAx_POWER_CFG.POFF_PLL[1:0], all PLL0 and PLL1 settings are managed by the CLKGNAx_PLL0__REGx_CFG and CLKGNAx_PLL1_REGx_CFG registers, respectively. CLKGNAx_PLL0_REG0_CFG/CLKGNAx_PLL1_REG0_CFG.NDIV: loop divider value. CLKGNAx_PLL0_REG1_CFG/CLKGNAx_PLL1_REG1_CFG.IDF: input divider value. CLKGNAx_PLL0_REG0_CFG/CLKGNAx_PLL1_REG0_CFG.ODF: output divider value. CLKGNAx_PLL0_REG2_CFG/CLKGNAx_PLL1_REG2_CFG: for spec spectrum control. CLKGNAx_POWER_CFG.POFF_PLL: PLL power-down control (read only). C on Low-power mode When this mode is entered, CLKGNAx_LOW_POWER_CTRL.CLK_DIV_LP_ENABLE can alter the selection of the clock divider source by forcing to the OSC divider source, which should be preprogrammed with the required divide ratio. An optional 16 predivision can be enabled through the CLKGNAx_LOW_POWER_CFG.LOW_POWER_PREDIV_EN bit. The optional 16 predivision can be enabled at any time through the CLKGNAx_LOW_POWER_CFG.FORCE_OSC_PREDIV bit. 14.3.2 Clock generator A clock observation All clocks of the clock generator Ax can be observed on the PIO12[1:0] pin. The clock selection is done by the CLKGNAx_CLKOBS_MUX1_CFG.CLOCK_OUT_SEL[5:0] bit field. An additional /2 or /4 division, enabled by CLKGNAx_CLKOBS_MUX1_CFG.CLOCKOBS_DIV[1:0] bit field, can be applied to adapt the high frequency clock output to conventional TTL outputs. DocID023557 Rev 10 323/604 Information classified Confidential - Do not copy (See last page for obligations) The PLL0/PLL1 has two outputs: HS and LS, where LS is a divide-by-2 version of HS. The frequencies of these two signals are defined as follows: Clocking 14.3.3 STiH271EL Clock generator A clock observation counter l Clock generator A0: clock signals ti a 14.3.4 The clock generator A0 channel allocation is shown in Table 66 where the frequencies are nominal, and given for information. Each channel can be disabled or slowed down through register programming of ClockGenA or through the low-power signal from the LPC. Channel 1300 Clock name PLL0 HS CLK_DIV_HS[0] CLK_SH4_ICK CLK_DIV_HS[1] fid Divider # en Clock generator A0 clock mapping and nominal frequencies (MHz) 650 1800 900 OSC Recommended PLL0 LS PLL1 HS PLL1 LS - /3 = 600 - - PLL0 HS 1300/2 = 650 MHz CLK_SH4L2_ICK CLK_HQVDP_PROC /3 = 433.33 - /5 = 360 - - PLL1 HS/5 = 360 MHz CLK_DIV_HS[2] CLK_IC_CPU /2 = 650 - /3 = 600 - - PLL0 HS 1300/2 = 650 MHz CLK_DIV_HS[3] CLK_LX_DMU_CPU - - /4 = 450 - - PLL1 HS 1800/4 = 450 MHz CLK_DIV_HS[4] CLK_LX_AUD_CPU /2 = 650 - /4 = 450 - - PLL0 HS 1300/2 = 650 MHz CLK_DIV_HS[5] CLK_TP /3 = 433.33 - /5 = 360 - - PLL1 HS/5 = 360 MHz CLK_DIV_HS[6] CLK_IC_STNOC - /1 = 650 /4 = 450 - - PLL1 HS 1800/4 = 450 MHz CLK_DIV_HS[7] GDP_PROC - - /5 = 360 - - PLL1 HS 1800/5 = 360 MHz CLK_DIV_HS[8] RESERVED - - - - - - CLK_DIV_HS[9] CLK_NAND_CTRL - /3 = 216.6 /9 = 200 - - PLL1 HS 1800/9 = 200 MHz CLK_DIV_LS[10] CLK_IC_REG_LP_O N - /5 = 130 - /9 = 100 - PLL1 LS 900/9 = 100 MHz - - - - - - CLK_DIV_LS[11] RESERVED 324/604 on /2 = 650 C Confidential Table 66. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Additionally, a check can be made of the frequency of the observed clock by means of a software controllable (and observable) counter. Two free-running counters are utilized, one clocked by an oscillator clock, the other (the reference) by the observed clock. The maximum value of the reference counter is programmable (CLKGNAx_CLKOBS_MASTER_MAXCOUNT register). When this reference counter decrements to zero, and reloads max count, then the values of the free-running counter is captured into a readable register (CLKGNAx_CLKOBS_SLAVE0_COUNTER register). This event generates an interrupt. Refer to CLKGENA_0_CLKOBS and CLKGENA_1_CLKOBS in Table 60: ST40 interrupt map. The free running counter can be cleared. The difference between captured value and previous captured or reset value gives an indication of the frequency. STiH271EL Clock generator A0 clock mapping and nominal frequencies (MHz) (continued) 1300 650 PLL0 HS PLL0 LS PLL1 HS PLL1 LS 900 CLK_DIV_LS[12] CLK_IC_TS_DMA - - - CLK_DIV_LS[13] CLK_TSOUT_SRC - /4 = 162.5 140/133 CLK_DIV_LS[14] CLK_IC_REG_LP_OF F CLK_DIV_LS[15] CLK_DMU_PREPRO C Recommended /4 = 225 - PLL1 LS 900/4 = 225 MHz - /6 = 150 - PLL1 LS/6 = 150 MHz /5 = 130 - /9 = 100 - PLL1 LS 900/9 = 100 MHz - /3 = 216.66 - /5 = 180 - PLL1 LS 900/5 = 180 MHz CLK_DIV_LS[16] CLK_THNS - - - - /128 = 0.234 OSC/128 = 234 kHz CLK_DIV_LS[17] RESERVED - - - - - - CLK_DIV_LS[18] CLK_IC_IF - /2 = 325 - /4 = 225 - PLL1 LS 900/4 = 225 MHz CLK_DIV_LS[19] CLK_PMB - - - /9 = 100 - PLL1 LS 900/9 = 100 MHz CLK_DIV_LS[20] RESERVED - - - - - - - - - /9 = 100 - PLL1 LS 900/9 = 100 MHz - - - - - - CLK_DIV_LS[23] CLK_MASTER - - - /18 = 50 - PLL1 LS 900/18 = 50 CLK_DIV_LS[31: RESERVED 24] - - - - - - CLK_DIV_LS[21] CLK_EMISS ti a C 14.3.5 on CLK_DIV_LS[22] RESERVED en Clock name l OSC Divider # Confidential 1800 fid Channel Clock generator A1: clock signals The clock generator A1 channel allocation is shown in Table 67 where the frequencies are nominal, and given for information. Each channel can be disabled or slowed down through register programming of ClockGen A or through the low power signal from the LPC. Table 67. Clock generator A1 clock mapping and nominal frequencies (MHz) Channel 1000 500 1600 800 Recommended Divider# Clock name PLL0 HS PLL0 LS PLL1 HS CLK_DIV_HS[0] CLK_IC_DDR /3 = 333 - /8 = 200 PLL0 HS 1000/3 = 333 MHz CLK_DIV_HS[1] CLK_SLIM_FDMA_0 /3 = 333 - /4 = 400 PLL1 HS 1600/4 = 400 MHz CLK_DIV_HS[2] CLK_SLIM_FDMA_1 /3 = 333 - /4 = 400 PLL1 HS 1600/4 = 400 MHz DocID023557 Rev 10 PLL1 LS 325/604 Information classified Confidential - Do not copy (See last page for obligations) Table 66. Clocking Clocking Clock generator A1 clock mapping and nominal frequencies (MHz) (continued) Channel 1000 500 1600 800 Divider# Clock name PLL0 HS PLL0 LS PLL1 HS CLK_DIV_HS[3] CLK_BDISP_CK (CLK_BLIT_PROC) /3 = 333 - /5 = 320 CLK_DIV_HS[4] RESERVED - - - CLK_DIV_HS[5] CLK_IC_COMPO_DISP /5 = 200 - /5 = 220 PLL0 HS 1000/5 = 200 MHz CLK_DIV_HS[6] CLK_IC_BDISP - /2 = 250 /3 = 266 PLL0 LS 500/2 = 250 MHz CLK_DIV_HS[9:7] RESERVED - - - CLK_DIV_LS[10] ETH_PHY_REF_CLKOUT - CLK_DIV_LS[11] RESERVED - CLK_DIV_LS[12] CLK_IC_DMU - CLK_DIV_LS[13] RESERVED - CLK_DIV_LS[14] CLK_IC_GMAC CLK_DIV_LS[15] CLK_PTP_REF_CLK PLL1 LS PLL0 HS 1000/3 = 333 MHz - fid - - - /16 = 50 PLL1 LS 800/16 = 50 MHz - - - - /4 = 250 - /3 = 266 PLL1 LS 800/3 = 266 - - - - /8 = 100 PLL1 LS 800/8 = 100 MHz ti a en - - l on CLK_DIV_LS[18:16] RESERVED /5 = 100 - - - /4 = 200 PLL1 LS 800/4 = 200 MHz - - - - - - - - /4 = 200 PLL1 LS 800/4 = 200 MHz CLK_DIV_LS[19] CLK_IQI CLK_DIV_LS[20] RESERVED - - - - - CLK_DIV_LS[21] CLK_CARD - - - /16 = 50 PLL1 LS 800/16 = 50 MHz CLK_DIV_LS[22] CLK_VDP_PROC - /2 = 250 - /3 = 266 PLL0 LS 500/2 = 250 MHz CLK_DIV_LS[27:23] RESERVED - - - - - CLK_DIV_LS[28] - /4 = 250 - /4 = 200 PLL1 LS 800/4 = 200 MHz - - - - - C Confidential Recommended CLK_SYS_MMC CLK_DIV_LS[31:29] RESERVED 326/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Table 67. STiH271EL STiH271EL 14.4 Clocking VID-FS0 and VID-FS1: display, video output stage, audio, pace, USB VID-FS0 and VID-FS1 generate the clocks used by the video display pipeline. This includes the following units: SD and HD displays Compositor Video output stage (formatters, HDMI, DENC) HD and SD video DACs Audio (PCM0, PCM2) USB (48 MHz for USB 1.1 mode) STFE (pace0, pace1) ti a l Video clocks are generated in combination of VID-FS0, VID-FS1 and the 16-channel video clock controller. en 14.4.1 Video clock controller fid The video clock controller consists of a central "clock aligner" block which synchronizes several instances of "clock divider," each of which produce a divided clock from either of the four sources from VID-FS0 and VID-FS1. The clock divider consists of three blocks: Clock switch Divider FSM Clock multiplexer on A simplified view of the video clock generator is shown in Figure 42. Note: C Confidential The reference clock can be any of the two sources, selectable by alternate clock select (mode pin [8]) or SYS_CLKIN by default. 1 The current architecture of the video clock controller requires that the ratio between the two source clocks (SD and HD clocks) have not to be greater than 2. This implies that the SD clock generated from VID-FS0 has to be always 108 MHz (even for those scenarios where 27 MHz would be the normal choice). 2 In some simple use cases, the display system needs only one source clock from VID-FS0. The other clock (SD or HD) can be stopped to save power. It is important to switch video clock controller output clocks to the active clock before other clock is stopped. DocID023557 Rev 10 327/604 Information classified Confidential - Do not copy (See last page for obligations) In addition, the two FS also generate clocks for the following units: Clocking STiH271EL Figure 42. Video clock generator simplified block diagram Clock generator VID FS0 / VID FS1 CLK_VID_HD_LOCAL (148.5 MHz Max) Freq. Synth VID#0 CLK_VID_SD_LOCAL (108 MHz Max) SYSCLKIN_ALT B ref ref CLK_27_0 (STFE) (27 MHz) ref CLK_VID_SD_REMOTE l A ti a SYS_CLKIN (Oscillator clock) (108 MHz Max) CLK_PCM2 (256 x Fs Max) CLOCK48 (USB PHY, USB controller) (48 MHz) CLK_27_1 (27 MHz) fid Confidential en Freq. Synth VID#1 on Video clock controller Divider FSM Clock multiplexer CLK_OUT_15 C Clock switch CLK_OUT_0 Clock divider Clock aligner 328/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) CLK_PCM0 (256 x Fs Max) (Selected by mode pin [8]) STiH271EL Clocking Figure 43. Video clock controller detailed diagram tmds_ck ckpxpll HDMI PLL HDMI PHY clockin TRI DAC clk_pix_hd(148.5MHz) 0 clk_hdtvo clk_tmds_hdmi clk_disp_hd (148.5MHz) 1 clk_disp_hd ckpxpll clk_tmds_hdmi(14.5MHz) clk_sdtvo 2 HDTVOut clk_disp_sd(13.5MHz) 3 clk_denc_main(27MHz) ti a l 4 gdp1_ck(148.5MHz) 5 gdp3_ck(148.5MHz) 6 en clk_FS2[4] clk_656(148.5MHz) 7 Video clock divider 8 clk_pix_main fid 9 clk_vid_sd_remote (108 MHz) clk_pix_sd(27MHz) 10 11 on 12 gdp4_ck(148.5MHz) 13 clk_656_0/1 MONO DAC main_ck cap_ck gdp1_ck = gdp2_ck go_mix_vid1_req aux_ck gi_vid1_ycbcr vp2_ck gdp3_ck clk_alp go_mix_vid2_req gi_vid2_ycbcr gdp4_ck vp1_ck gdp_proc_ck st_ck COMPO clk_pip =clk_disp_hd / clk_disp_id 14 compo_r_cr,compo_g_y,compo_b_cb C Confidential clk_vid_hd_local (148.5 MHz) clk_vid_sd_local (108 MHz) clk_denc_main 15 compo_req clk_pix clk_iqi HQVDP Lite o_data[29:0] i_gamma_req clk_pix VDP Aux DocID023557 Rev 10 329/604 Information classified Confidential - Do not copy (See last page for obligations) clk_disp_id Clocking 14.4.2 STiH271EL VID-FS0 and VID-FS1 clock signals The VID-FS clocks with their default and maximum frequencies are listed in Table 68 and Table 69. This clock generator is responsible for clocking the following units: 8-channel PCM player 0 (CLK_PCM1) connected to HDMI or external DACs (stereo) Transport stream clock (FRC0) VID-FS0 clock signals Maximum frequency (MHz) 27 108 148.5 CLK_VID_SD_LOCAL 27 108 148.5 CLK_PCM0 27 50 50 CLK_27_0 27 27 27 SD pixel clock to video clock controller CLK_PCM0 (256 x Fs = 49.15 MHz) Transport stream pre-processor (STFE) pace clock en Note: HD pixel clock to video clock controller ti a CLK_VID_HD_LOCAL Description Default frequency corresponds to a 27 MHz clock input. This clock generator is responsible for clocking the following units: Transport stream clock (FRC1) USB clock 48 VID-FS1 clock signals fid Two-channel PCM player 2 (CLK_PCM2) connected to external DACs on Table 69. Reset frequency (MHz) Clock name Recommended frequency (MHz) Maximum frequency (MHz) Description C Confidential Recommended frequency (MHz) 27 108 108 SD pixel clock to video clock controller remote TV CLK_PCM2 27 50 50 CLK_PCM2 (256 x Fs = 49.15 MHz) CLOCK48 27 48 48 USB clock in 1:1 mode CLK_27_1 27 27 27 Transport stream pre-processor (STFE) second pace clock CLK_VID_SD_REMOTE Table 70. Video clock controller clock signals Channel Default (reset) frequency (MHz) Clock name Recommended frequency (MHz) Description CLK_OUT_0 CLK_PIX_HD 148.5 148.5 HD pixel clock CLK_OUT_1 CLK_DISP_HD 148.5 148.5 HD display clock CLK_OUT_2 RESERVED - - - 330/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Reset frequency (MHz) Clock name l Table 68. STiH271EL Video clock controller clock signals (continued) Default (reset) frequency (MHz) Clock name Recommended frequency (MHz) Description CLK_DISP_SD 148.5 13.5 DISP ID clock (TVOUT) CLK_OUT_4 CLK_DENC_MAIN 148.5 27 New DENC clock CLK_OUT_5 GDP1_CK / GDP1_CK 148.5 148.5 GDP1 clock / GDP2 clock CLK_OUT_6 GDP3_CK 148.5 148.5 GDP3 clock CLK_OUT_7 RESERVED - - - CLK_OUT_8 RESERVED - - - CLK_OUT_9 CLK_PIX_MAIN 148.5 148.5 CLK_OUT_10 CLK_PIX_SD 148.5 CLK_OUT_11 RESERVED - CLK_OUT_12 RESERVED - CLK_OUT_13 GDP4_CK 148.5 CLK_OUT_14 CLK_PIP - CLK_OUT_15 RESERVED - 27 DAC clock - - - - 148.5 GDP4 clock - Aux compositor clock - - fid en ti a Main compositor clock 1 Default frequency corresponding to a 27 MHz clock input on VID-FS0. Also, default source of all generated clocks is the CLK_VID_HD_LOCAL. 2 GDP1 and GDP2 are clocked (in the pixel clock domain) by the same pixel frequency and hence should be connected together either to the Main or Aux mixer. on Note: l CLK_OUT_3 The video clocks must be set up with respect to the display standard in use. The following table gives some programming examples with respect to the targeted application. Main 1080p/60 Hz or 720p/60 Hz (HD) Aux: 480i / 576i (SD) 13.5 148.5 222.75 148.5 GDP1 and 2 on aux 148.5 148.5 27 13.5 148.5 222.75 13.5 Main 1080i/3 0Hz Main (1080i) and or 720p/60 Hz (HD) Aux Aux: 480i / 576i (SD) GDP1 and 2 on main 148.5 74.25 27 13.5 148.5 74.25 74.25 GDP1 and 2 on aux 148.5 74.25 27 13.5 148.5 74.25 13.5 DocID023557 Rev 10 CLK_GDP1/2 27 CLK_656 148.5 CLK_DISP_ID 148.5 CLK_PIX_SD CLK_DISP_HD GDP1 and 2 on main Application Main (1080p) and Aux CLK_TMDS_HDMI Video clock domains by applications CLK_PIX_HD Table 71. C Confidential Channel 331/604 Information classified Confidential - Do not copy (See last page for obligations) Table 70. Clocking Clocking CLK_GDP1/2 CLK_TMDS_HDMI CLK_656 CLK_DISP_ID 27 13.5 54 27 27 GDP1 and 2 on aux 108 27 27 13.5 54 27 13.5 GDP1 and 2 on main 108 (from FS1) 74.25 27 13.5 148.5 74.25 74.25 108 GDP1and 2 (from on aux FS1) 74.25 27 13.5 148.5 74.25 13.5 l 27 General purpose FS This clock generator is responsible for clocking the following units: Stereo PCM player 1 (CLK_PCM1) connected to internal audio DACs Stereo audio DAC (CLK_PCM1) S/PDIF player fid on The reference clock can be any of the two sources, selectable by alternate clock select (mode pin [8]) or SYS_CLKIN by default. The audio clock generator is a quad-frequency synthesizer that generates the various I S serial clock, left-right clock and DAC oversampling clocks. Typical audio sampling frequencies are: 32 kHz, 44.1 kHz, 48 kHz and multiples up to 192 kHz for set-top box applications. The four audio players have independent clock generators. 332/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 14.5 108 C Confidential Main 1080i/30 Hz Main (1080i) and or 720p/60Hz (HD) Aux SCART Aux: 480i / 576i (SD) GDP1 and 2 on main ti a Main 480p/576p (ED) Aux: 480i / 576i (SD) en Main (480p) and Aux CLK_PIX_SD Application CLK_DISP_HD Video clock domains by applications (continued) CLK_PIX_HD Table 71. STiH271EL STiH271EL Clocking Figure 44. Simplified GPFS block diagram 0 CLK_SPDIF (256 Fs) S/PDIF and HDMI 1 CLK_LPM (46.875 kHz) Freq synth SYS_CLKIN 2 GPFS CLK_DSS (36.864 MHz) SYS_CLKINALT 3 Fs) PCM1 player l Reset frequency (MHz) Recommended frequency (MHz) 27 50 CLK_LPC 27 315 kHz CLK_DSS 27 CLK_PCM1 27 Description 50 CLK S/PDIF 315 kHz Low power controller (LPC) clock 36.864 36.864 DSS clock 50 50 CLK_PCM1 (256 Fs = 49.15 MHz) on fid CLK_SPDIF Maximum frequency (MHz) Clock generator USB: USB clocks Clock generator USB generates all clocks required for the USB2 subsystem operation. The reference clock must be a 30 MHz clock SYS_CLKIN. C Confidential Clock name 14.6 ti a GPFS clock signals en Table 72. Clock generator USB can be globally disabled when not used, to decrease the power consumption. 14.7 Clock observation pins Note: Not qualified for uses other than observation purposes. All the clocks of ClockGenA0 and ClockGenA1 can be observed on PIO12[1:0] and PIO10[1:0]. CLKGENA0_CLK0: PIO12[0]. CLKGENA0_CLK1: PIO10[0]. CLKGENA1_CLK0: PIO12[1]. CLKGENA1_CLK1: PIO10[1]. The clock selection is done by the CLKGNAx_CLKOBS_MUX1_CFG configuration register of clockgen A. DocID023557 Rev 10 333/604 Information classified Confidential - Do not copy (See last page for obligations) CLK_PCM1 (256 Mode[8] (Alternate clock select) Clocking STiH271EL All the clocks of the 16-channel video clock controller can be observed on the PIO10[3] pin. The clock selection is done by the SYSTEM_CONFIG462[13:0] bits configuration register. 14.8 MPEG clock recovery The MPEG clock recovery is a mechanism to adjust the locally generated clocks with the encoder clock, referenced in the MPEG program counter reference (PCR), located in the adaptation field of the incoming transport stream. CLK_PIX_SD used for SD video display CLK_PIX_HD used for HD video display CLK_PCM (256 Fs where Fs can take several possible values: 32 kHz, 44.1 kHz, 48 kHz, ...) used for audio output ti a l The clock adjustment can be performed internally by correcting the parameters of the three frequency synthesizers that provide these clocks. Confidential en It is also possible to perform a frequency adjustment by controlling the frequency of an external VCXO. This is done by controlling the voltage reference of the VCXO through an external low-pass filter driven by one of the two PWM modules. fid The MPEG clock recovery mechanism assumes these three clocks are related to each other. on Recovery is performed for the CLK_PIX_SD (generated by the frequency synthesizer FS#1) by comparing the 42-bit PCR value located in the adaptation field of the stream with the local system timer counter (STC) value when a packet arrives. This generates a potential correction that is applied to the CLK_PIX_SD frequency synthesizer. The frequency synthesizer is programmed with new setup values to slow or accelerate the clock. For audio PCM clock recovery, two counters are used. A free-running counter clocked by the PCM audio frequency synthesizer FS#2. C A reference counter clocked by the SD video frequency synthesizer FS#1. The maximum value of this counter is programmable, and defines the time interval between two consecutive resets. This counter is used as a time-base. When the reference counter resets, the values of the free-running counter clocked from CLK_PCM is captured into a readable register. This event generates an interrupt to the CPU (CRU_IRQ). The CPU reads the value and compares it with the previously captured value. The difference between two adjacent values gives an indication of the correction to apply to the PCM audio frequency synthesizer FS#2. The decision to correct the frequency synthesizers setup is under the control of the software. The same principle applies for the recovery of the CLK_PIX_HD. A free-running counter is clocked with the HD video frequency synthesizer FS#0. The same reference counter is used. When this counter resets, the output of the free-running counter clocked at CLK_PIX_HD is captured into a readable register. The Clock Recovery Unit (CRU) block diagram is described in Figure 45. 334/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The STiH271EL integrates a functional block that performs the adjustment for the following three clocks: STiH271EL Clocking Figure 45. Multi clock recovery unit (MCRU) block diagram ZERO_DETECT_IN0 Counter max value Din IRQ Zero detect IRQ Command register Resync ld PCM capture register l Rst free-running HD counter ti a CLK_SLAVE1_0 CLK_SLAVE1_1 CLK_SLAVE1_2 CLK_SLAVE1_3 en Rst free-running PCM counter T1 config port CLK_PROG ld HD capture register fid CLK_SLAVE0_1 CLK_SLAVE0_2 CLK_SLAVE0_3 ZERO_DETECT_OUT Clock generation registers 14.9.1 ClockGen A - CPUs and interconnect clock gen registers on 14.9 Clock generator A consists of two clock generators: C Confidential CLK_SLAVE0_0 Register interface reference counter rst/ld Clock generator A0 for the CPUs, GPU, EMI and interconnect clocks Clock generator A1 for the display pipeline, transport processor, FDMAs slim and interconnect clocks Clock generators A0 and A1 use the same series of registers, called CLKGNAx in this chapter, where x = 0 or 1. Register addresses are provided as one of: ClockGenAxBaseAddress + offset Refer to Section 11.1: External memories and on-chip peripherals address map on page 287 for the base addresses of Clock generator A0 and Clock generator A1. DocID023557 Rev 10 335/604 Information classified Confidential - Do not copy (See last page for obligations) CLK_REF0 CLK_REF1 CLK_REF2 CLK_REF3 Clocking Register name Description Page 0x000 CLKGNAx_PLL0_REG0_CFG PLL0 configuration register 0 on page 338 0x004 CLKGNAx_PLL0_REG1_CFG PLL0 configuration register 1 on page 339 0x008 CLKGNAx_PLL0_REG2_CFG PLL0 configuration register 2 on page 339 0x00C CLKGNAx_PLL1_REG0_CFG PLL1 configuration register 0 on page 340 0x010 CLKGNAx_PLL1_REG1_CFG PLL1 configuration register 1 on page 341 0x014 CLKGNAx_PLL1_REG2_CFG 0x018 CLKGNAx_POWER_CFG 0x01C CLKGNAx_CLKOPSRC_SWITCH_CFG on page 342 0x020 CLKGNAx_CLKOPSRC_SWITCH_CFG2 on page 344 0x024 CLKGNAx_PLL0_ENABLE_FB Clock output source switch control on page and feedback 346 0x028 CLKGNAx_PLL1_ENABLE_FB on page 346 0x02C CLKGNAx_OSC_ENABLE_FB 0x030 CLKGNAx_CLKOBS_MUX0_CFG Observation multiplexer 0 on page 347 0x034 CLKGNAx_CLKOBS_MASTER_MAXCOUNT Clock observation maximum counter on page 348 0x038 CLKGNAx_CLKOBS_CMD Observation command register on page 349 0x03C CLKGNAx_CLKOBS_STATUS Observation status register on page 349 0x040 CLKGNAx_CLKOBS_SLAVE0_COUNTER Observation slave count register on page 350 0x044 CLKGNAx_OSCMUX_DEBUG Selects oscillator source on page 350 0x048 CLKGNAx_CLKOBS_MUX1_CFG Observation multiplexer 1 on page 351 0x04C CLKGNAx_LOW_POWER_CTRL Low power divider control on page 352 336/604 ti a l Offset on page 341 ClockGen A, PLL power control on page 342 on fid en PLL1 configuration register 2 on page 347 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) ClockGenA registers list C Confidential Table 73. STiH271EL STiH271EL Description Page 0x050 CLKGNAx_LOW_POWER_CFG Configuration control register for low power on page 352 0x054 - 0x7FC RESERVED - - 0x800 - 0x87C CLKGNAx_X_DIVn_CFG Oscillator clock dividers for every channel (n = 0 to 31) on page 353 0x880 - 0x8FC RESERVED - - 0x900 - 0x914 CLKGNAx_PLL0HS_DIVn_CFG PLL0 HS dividers (n = 0 to 5) on page 353 0x918 - 0x94C RESERVED - - 0x980 - 0x9A4 CLKGNAx_PLL1HS_DIVn_CFG PLL1 HS dividers (n = 0 to 9) on page 354 0x9A8 - 0xA1C RESERVED - - 0xA20 - 0xA84 CLKGNAx_PLL0LS_DIVn_CFG PLL0 LS dividers (n = 6 to 31) on page 354 0xA80 - 0xAFC RESERVED - - 0xB00 - 0xB54 CLKGNAx_PLL1LS_DIVn_CFG PLL1 LS dividers (n = 10 to 31) on page 355 0xB58 - 0xEFC RESERVED - - 0xF00 - 0xFFC RESERVED - - on en ti a l Register name fid Offset DocID023557 Rev 10 337/604 Information classified Confidential - Do not copy (See last page for obligations) ClockGenA registers list (continued) C Confidential Table 73. Clocking Clocking STiH271EL PLL0 register 0 configuration ClockGenAxBaseAddress + 0x000 Type: R/W Reset: 0x0132 Description: ClockGenAx PLL0 register 0 configuration. 4 3 NDIV[7:0] 5 RW 6 ODF[5:0] 7 RW 8 ti a Address: 9 2 1 0 l RW FRAC_INPUT[15:0] R RW FRAC_CONTROL PD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Confidential en [31] PD: PLL power status. 0: PLL is ON. PLL is fully operational. 1: PLL is powered down. PLL is not functional. Current consumption is only due to leakage. Note: This is a read only bit. The PLL power state is controlled by CLKGNAx_POWER_CFG. fid [30] FRAC_CONTROL: To activate or deactivate the fractional mode (active high). 1: Fractional multiplication is activated. [29:14] FRAC_INPUT[15:0]: Input bits to set the loop division factor (fractional part). [13:8] ODF[5:0]: Input bits to set the output division factor. C on [7:0] NDIV[7:0]: Input bits to set the loop division factor (integer part). 338/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) CLKGNAx_PLL0_REG0_CFG STiH271EL Clocking PLL0 register 1 configuration 8 7 6 5 4 3 2 ClockGenAxBaseAddress + 0x004 Type: R/W Reset: 0x0003 Description: ClockGenAx PLL0 register 1 configuration. IDF[2:0] 0 ti a l Address: 1 RW INC_STEP[14:0] RW LOCK R 9 RW MOD_PERIOD[12:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31] LOCK: PLL lock status. This is a read only bit. en [15:3] MOD_PERIOD[12:0]: Configuration input to set the modulation period and modulation depth (SSCG). PLL0 register 2 configuration Address: ClockGenAxBaseAddress + 0x008 Type: R/W Reset: 0x000 Description: ClockGenAx PLL0 register 2 configuration. SPREAD_CONTROL STRB_BYPASS STRB RW 2 RW 3 RW 4 SSCG_CONTROL 5 RW 6 CP[4:0] 7 RW 8 DIVRESET 9 RW R RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 0 RW DITHER_DISABLE[1:0] CLKGNAx_PLL0_REG2_CFG fid [2:0] IDF[2:0]: Input bits to set the input division factor. C Confidential [30:16] INC_STEP[14:0]: Configuration input to set the modulation depth (SSCG). [31:12] RESERVED [11] DIVRESET: Soft reset control. 0: Allow divide 1: Reset divider Use when changing PLL settings. [10:6] CP[4:0]: Input bits to set the charge pump current. DocID023557 Rev 10 339/604 Information classified Confidential - Do not copy (See last page for obligations) CLKGNAx_PLL0_REG1_CFG Clocking STiH271EL [5] SSCG_CONTROL: To activate or deactivate the SSCG mode (active high). SSCG_CONTROL = H means SSCG is activated. [4] SPREAD_CONTROL: Controls the spread type in SSCG mode: --> center-spread (SPREAD_CONTROL = L). --> down-spread (SPREAD_CONTROL = H). [3] STRB_BYPASS: STRB_BYPASS = H bypasses the STRB signal. [2] STRB: Asynchronous strobe input to the SSCG controller. A rising edge indicates that a new modulation depth and modulation frequency configuration input is to be loaded. PLL1 register 0 configuration ti a l CLKGNAx_PLL1_REG0_CFG ClockGenAxBaseAddress + 0x00C Type: R/W Reset: 0x012D Description: ClockGenAx PLL1 register 0 configuration. 5 4 3 NDIV[7:0] 6 RW 7 ODF[5:0] 8 2 1 0 on fid Address: 9 RW en RW FRAC_INPUT[15:0] R RW FRAC_CONTROL [31] PD: PLL power status. 0: PLL is ON. PLL is fully operational. 1: PLL is powered down. PLL is not functional. Current consumption is only due to leakage. Note: This is a read only bit. The PLL power state is controlled by CLKGNAx_POWER_CFG. C Confidential PD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [30] FRAC_CONTROL: To activate or deactivate the fractional mode (active high). FRAC_CONTROL = H means fractional multiplication is activated. [29:14] FRAC_INPUT[15:0]: Input bits to set the loop division factor (fractional part). [13:8] ODF[5:0]: Input bits to set the output division factor. [7:0] NDIV[7:0]: Input bits to set the loop division factor (integer part). 340/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [1:0] DITHER_DISABLE[1:0]: MSB = 1 disables the rectangular PDF dither input to SDM and LSB = 1 disables the triangular PDF dither input to SDM. STiH271EL Clocking PLL1 register 1 configuration 8 7 6 5 4 3 2 ClockGenAxBaseAddress + 0x010 Type: R/W Reset: 0x0003 Description: ClockGenAx PLL1 register 1 configuration. IDF[2:0] 0 ti a l Address: 1 RW INC_STEP[14:0] RW LOCK R 9 RW MOD_PERIOD[12:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31] LOCK: PLL lock status. This is a read only bit. en [15:3] MOD_PERIOD[12:0]: Configuration input to set the modulation period and modulation depth (SSCG). PLL1 register 2 configuration Address: ClockGenAxBaseAddress + 0x014 Type: R/W Reset: 0x000 Description: ClockGenAx PLL1 register 2 configuration. SPREAD_CONTROL STRB_BYPASS STRB RW 2 RW 3 RW 4 SSCG_CONTROL 5 RW 6 CP[4:0] 7 RW 8 DIVRESET 9 RW R RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 0 RW DITHER_DISABLE[1:0] CLKGNAx_PLL1_REG2_CFG fid [2:0] IDF[2:0]: Input bits to set the input division factor. C Confidential [30:16] INC_STEP[14:0]: Configuration input to set the modulation depth (SSCG). [31:12] RESERVED [11] DIVRESET: Soft reset control. 0: Allow divide 1: Reset divider Use when changing PLL settings. [10:6] CP[4:0]: Input bits to set the charge pump current. DocID023557 Rev 10 341/604 Information classified Confidential - Do not copy (See last page for obligations) CLKGNAx_PLL1_REG1_CFG Clocking STiH271EL [5] SSCG_CONTROL: To activate or deactivate the SSCG mode (active high). SSCG_CONTROL = H means SSCG is activated. [4] SPREAD_CONTROL: Controls the spread type in SSCG mode: - Center-spread (SPREAD_CONTROL = L). - Down-spread (SPREAD_CONTROL = H). [3] STRB_BYPASS: STRB_BYPASS = H bypasses the STRB signal. [2] STRB: Asynchronous strobe input to the SSCG controller. A rising edge indicates that a new modulation depth and modulation frequency configuration input is to be loaded. ClockGenAx PLL power configuration ti a l CLKGNAx_POWER_CFG 8 7 6 5 4 3 2 1 en ClockGenAxBaseAddress + 0x018 Type: R/W Reset: 0x00 Description: ClockGenAx PLL power control. 0 POFF_PLL[1:0] 9 [31:2] RESERVED on fid Address: C [1:0] POFF_PLL[1:0]: PLL Power-down control: (CLKGNAx_POWER_CFG[0] = POFF[0] = PLL0) 0: PLL is ON 1: PLL is powered down Shadowed by read-only. CLKGNAx_PLL[2:0]_CFG.POFF bits. Switch control and feedback 342/604 DocID023557 Rev 10 6 5 4 3 2 1 0 CLK0_SRC_SEL 7 CLK1_SRC_SEL 8 CLK2_SRC_SEL 9 CLK3_SRC_SEL CLK5_SRC_SEL CLK6_SRC_SEL CLK7_SRC_SEL CLK8_SRC_SEL CLK9_SRC_SEL CLK10_SRC_SEL CLK11_SRC_SEL CLK12_SRC_SEL CLK13_SRC_SEL CLK14_SRC_SEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLK4_SRC_SEL CLKGNAx_CLKOPSRC_SWITCH_CFG CLK15_SRC_SEL Confidential RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Information classified Confidential - Do not copy (See last page for obligations) [1:0] DITHER_DISABLE[1:0]: MSB = 1 disables the rectangular PDF dither input to SDM and LSB = 1 disables the triangular PDF dither input to SDM. STiH271EL Clocking Address: ClockGenAxBaseAddress + 0x01C Type: R/W Reset: 0x0000 Description: Clock output source switch control and feedback. [31:30] CLK15_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1LS11: STOP Information classified Confidential - Do not copy (See last page for obligations) [29:28] CLK14_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1LS11: STOP ti a l [27:26] CLK13_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1LS11: STOP en fid [23:22] CLK11_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1LS11: STOP [21:20] CLK10_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1LS11: STOP on [19:18] CLK9_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1HS11: STOP [17:16] CLK8_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1HS11: STOP C Confidential [25:24] CLK12_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1LS11: STOP [15:14] CLK7_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1HS11: STOP [13:12] CLK6_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0LS 10: PLL1HS11: STOP [11:10] CLK5_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0HS 10: PLL1HS11: STOP [9:8] CLK4_SRC_SEL: Selection of divider source output. 00: OSC 01: PLL0HS 10: PLL1HS11: STOP [7:6] CLK3_SRC_SEL: Selection of divider source output. 00: OSC01: PLL0HS 10: PLL1HS11: STOP DocID023557 Rev 10 343/604 Clocking STiH271EL [5:4] CLK2_SRC_SEL: Selection of divider source output. 00: OSC01: PLL0HS 10: PLL1HS11: STOP [3:2] CLK1_SRC_SEL: Selection of divider source output. 00: OSC01: PLL0HS 10: PLL1HS11: STOP [1:0] CLK0_SRC_SEL: Selection of divider source output. 00: OSC01: PLL0HS 10: PLL1HS11: STOP Type: R/W Reset: 0x0000 Description: Divider source output selection. on [31:30] CLK31_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [29:28] CLK30_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [27:26] CLK29_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [25:24] CLK28_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [23:22] CLK27_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [21:20] CLK26_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [19:18] CLK25_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP 344/604 DocID023557 Rev 10 6 5 4 3 2 1 0 CLK16_SRC_SEL 7 CLK17_SRC_SEL 8 CLK18_SRC_SEL 9 CLK19_SRC_SEL l fid ClockGenAxBaseAddress + 0x020 CLK21_SRC_SEL CLK22_SRC_SEL CLK23_SRC_SEL ti a CLK24_SRC_SEL en CLK25_SRC_SEL CLK26_SRC_SEL CLK27_SRC_SEL CLK28_SRC_SEL CLK29_SRC_SEL CLK30_SRC_SEL Address: C Confidential CLK31_SRC_SEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Information classified Confidential - Do not copy (See last page for obligations) Divider source output selection CLK20_SRC_SEL CLKGNAx_CLKOPSRC_SWITCH_CFG2 STiH271EL Clocking [17:16] CLK24_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [15:14] CLK23_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP [13:12] CLK22_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP Information classified Confidential - Do not copy (See last page for obligations) [11:10] CLK21_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP ti a l [9:8] CLK20_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP en [5:4] CLK18_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP fid [3:2] CLK17_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP on [1:0] CLK16_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP C Confidential [7:6] CLK19_SRC_SEL: Selection of divider source output 00: OSC01: PLL0LS 10: PLL1LS11: STOP DocID023557 Rev 10 345/604 Clocking STiH271EL CLKGNAx_PLL0_ENABLE_FB PLL0 enable feedback 9 8 7 6 5 4 3 2 1 0 ClockGenAxBaseAddress + 0x024 Type: R Reset: 0x0000 Description: PLL0 enable feedback. ti a l Address: en fid [5:0] PLL0HS_ENABLE_CLOCK_FB: PLL0HS feedback on stop status. Bit 0 of HS is for divider 0. 0: Stopped1: Running CLKGNAx_PLL1_ENABLE_FB on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PLL1LS_ENABLE_CLOCK_FB Address: ClockGenAxBaseAddress + 0x028 Type: R Reset: 0x0000 Description: PLL1 enable feedback. PLL1 enable 9 8 7 6 5 4 3 2 1 0 PLL1HS_ENABLE_CLOCK_FB C Confidential [31:6] PLL0LS_ENABLE_CLOCK_FB: PLL0LS feedback on stop status. Bit 8 of LS is for divider 8. 0: Stopped1: Running [31:10] PLL1LS_ENABLE_CLOCK_FB: PLL1LS feedback on stop status. Bit 8 of LS is for divider 8. 0: Stopped1: Running [9:0] PLL1HS_ENABLE_CLOCK_FB: PLL1HS feedback on stop status. Bit 0 of HS is for divider 0. 0: Stopped1: Running 346/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) PLL0LS_ENABLE_CLOCK_FB PLL0HS_ENABLE_CLOCK_FB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STiH271EL Clocking CLKGNAx_OSC_ENABLE_FB Clock oscillator enable 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address: ClockGenAxBaseAddress + 0x02C Type: R Reset: 0XFFFFFFFF Description: Clock oscillator enable feedback. 7 ClockGenAxBaseAddress + 0x030 Type: R/W Reset: 0x180 Description: Observation multiplexer 0. 5 4 3 2 1 0 on Address: 6 CLOCK_OUT_SEL[5:0] en 8 fid RESERVED 9 Note: Clockgen A observation signals are available on PIO10[1:0]. C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Observation multiplexer0 CLOCKOBS_DIV[1:0] CLKGNAx_CLKOBS_MUX0_CFG CLOCKOBS_DIV[2] ti a l [31:0] OSC_ENABLE_CLOCK_FB: Feedback on stop status. Bit 0 is divider 0. 0: Stopped1: Running [31:9] RESERVED [8] CLOCKOBS_DIV[2]: 0: clk_funcobs = OBS_MUX0 output 1: clk_funcobs = OBS_MUX1 output Note: The clk_funcobs port is finally connected on the PAD interface for observing the clocks on the oscilloscope. This feature enables observation multiplexer output clocks to reach the PADs. [7:6] CLOCKOBS_DIV[1:0]: Selects divide ratio for externally-observed clock. 00: Divide by 201: Divide by 4 1X: No divide DocID023557 Rev 10 347/604 Information classified Confidential - Do not copy (See last page for obligations) OSC_ENABLE_CLOCK_FB STiH271EL ti a l [5:0] CLOCK_OUT_SEL[5:0]: Source selection for external observation clock. 0x00: CLK_DIV_HS[0]0x01: CLK_DIV_HS[1] 0x02: CLK_DIV_HS[2]0x03: CLK_DIV_HS[3] 0x04: CLK_DIV_HS[4]0x05: CLK_DIV_HS[5] 0x06: CLK_DIV_HS[6]0x07: CLK_DIV_HS[7] 0x08: CLK_DIV_HS[8]0x09: CLK_DIV_HS[9] 0x0A: CLK_DIV_LS[10]0x0B: CLK_DIV_LS[11] 0x0C: CLK_DIV_LS[12]0x0D: CLK_DIV_LS[13] 0x0E: CLK_DIV_LS[14]0x0F: CLK_DIV_LS[15] 0x10: CLK_DIV_LS[16]0x11: CLK_DIV_LS[17] 0x12: CLK_DIV_LS[18]0x13: CLK_DIV_LS[19] 0x14: CLK_DIV_LS[20]0x15: CLK_DIV_LS[21] 0x16: CLK_DIV_LS[22]0x17: CLK_DIV_LS[23] 0x18: CLK_DIV_LS[24]0x19: CLK_DIV_LS[25] 0x1A: CLK_DIV_LS[26]0x1B: CLK_DIV_LS[27] 0x1C: CLK_DIV_LS[28]0x1D: CLK_DIV_LS[29] 0x1E: CLK_DIV_LS[30]0x1F: CLK_DIV_LS[31] en CLKGNAx_CLKOBS_MASTER_MAXCOUNT CLK observation max counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ClockGenAxBaseAddress + 0x034 Type: R/W Reset: 0x0000 Description: CLK observation max counter. on fid Address: [31:0] CLKOBS_MASTER_MAXCOUNT: Clock observation master reference maximum count load value. It is read when CLKGNAx_CLKOBS_CMD.COUNT_LD is 1 or count = 0. C Confidential CLKOBS_MASTER_MAXCOUNT 348/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Clocking STiH271EL Clocking Observation command register 8 7 6 5 4 3 2 1 RESERVED ClockGenAxBaseAddress + 0x038 Type: R/W Reset: 0x0001 Description: Observation command register. l Address: 0 ti a [31:2] RESERVED: 0 for Reserved [1] IRQ_CLEAR: Clears interrupt IRQ. When this value is `1' it must return to `0' to allow correct operation. Reset value is 0x0. Observation status register RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address: ClockGenAxBaseAddress + 0x03C Type: R Reset: 0x0000 Description: Observation status register. 9 8 7 6 5 4 3 2 1 0 O_DCO_IRQ en fid CLKGNAx_CLKOBS_STATUS C Confidential [0] COUNT_LD: Reset value is 0x1. 0: Allows counting. 1: Loads REF Master counter with maxcount, and loads the slave counter with zero. [31:1] RESERVED: 0 for Reserved [0] O_DCO_IRQ: Interrupt status. 0: No interrupt1: Indicated interrupt DocID023557 Rev 10 349/604 Information classified Confidential - Do not copy (See last page for obligations) 9 IRQ_CLEAR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COUNT_LD CLKGNAx_CLKOBS_CMD Clocking STiH271EL CLKGNAx_CLKOBS_SLAVE0_COUNTER Observation slave count register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKOBS_SLAVE0_COUNTER Address: ClockGenAxBaseAddress + 0x040 Type: R Reset: 0x0000 Description: Observation slave count register. en ClockGenAxBaseAddress + 0x044 Type: R/W Reset: 0x0 Description: ClockGenAx oscillator multiplexer debug control. [31:2] RESERVED on fid Address: [1:0] OSCMUX_DEBUG: Oscillator multiplexer debug control. 00: clk_osc_a 01: clk_osc_b 10: clk_osc_c 11: clk_osc_d C Confidential RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 350/604 DocID023557 Rev 10 9 8 7 6 5 4 3 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) OSC multiplexer debug control OSCMUX_DEBUG CLKGNAx_OSCMUX_DEBUG ti a l [31:0] CLKOBS_SLAVE0_COUNTER: SLAVE0_COUNT value when IRQ = 1. STiH271EL Clocking Observation multiplexer1 8 7 6 RESERVED ClockGenAxBaseAddress + 0x048 Type: R/W Reset: 0x00E9 Description: Observation multiplexer 1. 4 3 2 1 0 ti a l Address: 5 Information classified Confidential - Do not copy (See last page for obligations) 9 CLOCKOBS_DIV[1:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLOCK_OUT_SEL[5:0] CLKGNAx_CLKOBS_MUX1_CFG Note: Clockgen A observation signals are available on PIO10[1:0]. en [7:6] CLOCKOBS_DIV[1:0]: Selects divide ratio for externally-observed clock. 00: Divide by 201: Divide by 4 1X: No divide on fid [5:0] CLOCK_OUT_SEL[5:0]: Source selection for external observation clock: 0x00: CLK_OSC_OTH 0x01: CLK_PLL_0_INFOUT 0x02: CLK_PLL_0_REFOUT0x03: NA 0x04: NA0x05: CLK_PLL_1_INFOUT 0x06: CLK_PLL_1_REFOUT0x07: NA 0x08: NA0x09: clk_osc_a 0x0A: CLK_OSC_B0x0B: CLK_OSC_C 0x0C: CLK_OSC_D0x0D: PLL0.FVCO 0x0E: PLL0.PHI0x0F: PLL1.FVCO 0x10: PLL1.PHI0x11: RESERVED 0x12: RESERVED0x13: RESERVED 0x14: RESERVED0x15: RESERVED 0x16: RESERVED0x17: RESERVED 0x18: RESERVED C Confidential [31:8] RESERVED Note: Software must program the register to the required value before using this feature. DocID023557 Rev 10 351/604 Clocking STiH271EL CLKGNAx_LOW_POWER_CTRL Low power control 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address: ClockGenAxBaseAddress + 0x04C Type: RW Reset: 0x0000 Description: Low power divider control. 8 7 6 5 4 3 RESERVED fid en 9 ClockGenAxBaseAddress + 0x050 Type: RW Reset: 0x0000 Description: Configuration control register for low power. on Address: C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Low power configuration [31:2] RESERVED [1] FORCE_OSC_PREDIV: Enable divide by 16 on OSC input at any time. [0] LOW_POWER_PREDIV_EN: Enable extra pre-divider (by 16) on OSC input when low_power_in=1 352/604 DocID023557 Rev 10 2 1 0 FORCE_OSC_PREDIV CLKGNAx_LOW_POWER_CFG LOW_POWER_PREDIV_EN ti a l [31:0] CLK_DIV_LP_ENABLE: Select low power override function. 0: No action 1: Change to OSC divide when LOW_POWER_IN = 1 Information classified Confidential - Do not copy (See last page for obligations) CLK_DIV_LP_ENABLE STiH271EL Clocking CLKGNAx_X_DIVn_CFG ClockGenAx PLL division configuration 8 7 6 5 4 3 1 0 ClockGenAxBaseAddress + 0x800 + n * 0x04 (where n = 0 to 31) Type: R/W Reset: 0x10000 Description: ClockGenAx PLL division configuration. Oscillator clock dividers for every channel. ti a l Address: [31] UPDATE_FB: This bit is read only. Cross-clock update information. 1: Register will not accept new data. en [30:5] RESERVED ClockGenAx PLL division configuration fid CLKGNAx_PLL0HS_DIVn_CFG 8 7 6 RESERVED on R 9 5 4 3 2 1 0 MAX_COUNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 UPDATE_FB R/W Address: ClockGenAxBaseAddress + 0x900 + n * 0x04 (where n = 0 to 5) Type: R/W Reset: 0x10000 Description: ClockGenAx PLL division configuration. C Confidential [4:0] MAX_COUNT: Maximum count (N) - 1. [31] UPDATE_FB: This bit is read only. Cross-clock update information 1: Register will not accept new data. [30:5] RESERVED [4:0] MAX_COUNT: Maximum count (N)-1 DocID023557 Rev 10 353/604 Information classified Confidential - Do not copy (See last page for obligations) R R 2 RW MAX_COUNT 9 RESERVED UPDATE_FB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Clocking STiH271EL CLKGNAx_PLL1HS_DIVn_CFG ClockGenAx PLL division configuration 8 7 6 5 4 3 1 0 R/W ClockGenAxBaseAddress + 0x980 + n * 0x04 (where n = 0 to 9) Type: R/W Reset: 0x10000 Description: ClockGenAx PLL division configuration. ti a l Address: [31] UPDATE_FB: This bit is read only. Cross-clock update information 1: Register will not accept new data. en [30:5] RESERVED ClockGenAx PLL division configuration fid CLKGNAx_PLL0LS_DIVn_CFG 8 7 6 5 RESERVED on R 9 R/W ClockGenAxBaseAddress + 0xA20 + (n - 6)* 0x04 (where n = 6 to 31) Type: R/W Reset: 0x10000 Description: ClockGenAx PLL division configuration. C Address: [31] UPDATE_FB: This bit is read only. Cross clock update information. 1: Register will not accept new data. [30:5] RESERVED [4:0] MAX_COUNT: Maximum count (N)-1 354/604 4 3 2 MAX_COUNT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 UPDATE_FB Confidential [4:0] MAX_COUNT: Maximum count (N)-1 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) R 2 MAX_COUNT 9 RESERVED UPDATE_FB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 STiH271EL Clocking CLKGNAx_PLL1LS_DIVn_CFG ClockGenAx PLL division configuration 8 7 6 5 4 2 1 0 R/W ClockGenAxBaseAddress + 0xB00 + (n - 10) * 0x04 (where n = 10 to 31) Type: R/W Reset: 0x10000 Description: ClockGenAx PLL division configuration. ti a l Address: Information classified Confidential - Do not copy (See last page for obligations) R 3 MAX_COUNT 9 RESERVED UPDATE_FB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31] UPDATE_FB: This bit is read only. Cross-clock update info. 1: Register will not accept new data. en [30:5] RESERVED C on fid Confidential [4:0] MAX_COUNT: Maximum count (N)-1 DocID023557 Rev 10 355/604 Power-on and system reset STiH271EL 15 Power-on and system reset 15.1 Reset sources The different reset sources to be considered are: Watchdog reset generated by the ST40 internal watchdog timer (WDT) - UDI reset sent through the ST40 debug port - Software POR reset - Software MANUAL reset Software reset from the ST40 to the ST231 CPUs ti a Watchdog reset generated by the comms LPC watchdog timer Front-panel reset generated by checking an alternate input for approximately 4-second on-time Low voltage detector reset Power supply setting (SOC_VOLT_OK) en fid POR reset (cold reset) versus system reset (warm reset) Note: on The complete reset sequence (refer to Figure 46 on page 357) is executed only during a power-on-reset sequence (Cold reset). In that sequence everything is reset including the clock generators, the captured mode pins values, and the comms LPC watchdog timer. The minimum duration of the reset pulse to apply on the SYS_NOTRESETIN pad is 66 ns When the reset source is one of the ST40 reset outputs and this is unmasked (refer to Figure 46 on page 357), then a system reset sequence is executed (Warm reset). In that sequence everything is reset except the clock generators, the captured mode pins values and the comms LPC watchdog timer. The cold reset is allowed through the reset inputs under software control. C Confidential - 15.2 ST40 reset output that is associated with four possible reset sources: The SYSTEM_CONFIG458[5] register is used to control the cold or warm reset for LPC watchdog. Note: 356/604 The reset value of this system configuration bit selects the warm reset. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Power-on reset signal, which is applied on the SYS_NOTRESETIN pad (with glitch suppression using a Schmitt type pad) l STiH271EL Power-on and system reset Figure 46. STiH271EL reset scheme FP_RESET (alt function) COMMS.LPC SYS CONFIG POR FP_RESET RST.LPC.WDT SYS CONFIG ST40 HOST MAN SYS_NOTRESETIN FP.RESET.ENABLE RESETOUT.MASK WDT.RESET.ENABLE AND ST40 RESET OUT COLD RESET RST_ST40 HOST SYS_AONOTWDOGRSTOUT fid WARM RESET RST_PERIPHERALS (Peripherals, ST231s) An unmasked reset output (ResetOut mask = 0) from the ST40 always resets all the other processors (ST231s). Note: The FP_RESET (Front Panel) includes programmable inversion of pad input and reset flag as well as mask/enable of the fp.reset and comms.lpc.wdt. on Note: C Confidential ti a RST_MODEPIN en RST_CLKGEN DocID023557 Rev 10 357/604 Information classified Confidential - Do not copy (See last page for obligations) COMMS.WDT.MASK l LP Reset gen Boot modes 16 STiH271EL Boot modes The STiH271EL can boot from Serial NOR Flash, NAND Flash (selection done by means of Mode[6:2] pins mapped on EMI_ADD[5:1]. The ST40 acts as a boot master. All the ST231 CPUs act as slave CPUs. The boot addresses of the slave processors must be first defined in the system configuration registers before their reset is released by the boot master ST40. 2. The reset of the slave processors must be released by the boot master ST40 by writing in the dedicated CPU soft reset system configuration registers. 16.1 ti a l 1. Boot modes system configuration registers en All the CPU (ST40 and ST231) soft reset configuration bits are active low; that is, the CPU is held in reset when this bit is at `0'. Table 74. ST40 and ST231 boot modes system configuration registers System configuration register fid Note: Reset value ST40 boot vector SYSTEM_CONFIG173[28:1] on ST40 registers Configuration 0x0 To be programmed by CPU when the ST40 is slave 0x0 Reset deasserted by the boot master ST40 AUD ST231 power reset SYSTEM_CONFIG460[26] 0x0 Reset deasserted by the boot master ST40 VID ST231 boot vector SYSTEM_CONFIG175[31:6] 0x0 To be programmed by the boot master ST40 AUD ST231 boot vector SYSTEM_CONFIG176[31:6] 0x0 To be programmed by the boot master ST40 ST231 registers VID ST231 power reset SYSTEM_CONFIG460[27] C Confidential This section provides an overview of the registers needed to control the boot vector and soft reset of the slave processors. 358/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) At power-on the slave CPUs (ST231 slaves) are all halted (kept under reset). It is up to the ST40 software to control the boot sequence of the slave processors. This implies: STiH271EL 16.2 Boot modes ST40 reset outputs The ST40 processor outputs four reset signals associated with four possible reset sources: Watchdog reset generated by the ST40 internal watchdog timer (WDT) UDI reset sent through the ST40 debug port Software POR reset Software MANUAL reset After the boot sequence, the host processor can disable/enable (by using mask configuration registers, see below) these reset outputs using dedicated system configuration bits. ti a l SYSTEM_CONFIG498[5]: Resetout mask for the ST40 Host en When the WDT reset output from an ST40 is masked, it can still be detected through the interrupt controllers (that is, the WDT reset output is routed to the interrupt controller). This allows the host to detect and fix a problem in the slave processor without causing a full system reset. SYSTEM_CONFIG499[0]: power soft reset for the ST40 host. SYSTEM_CONFIG475[2]: manual reset for the ST40 host. fid 16.2.1 on If it is not possible for the ST40 core to fix the system then eventually a watchdog reset is generated by the low power controller block inside the COMMS. This performs a system reset cycle, which includes the ST40 processor. This reset does not cause the initial startup (that is, perform only a warm reset) sequence if the comms.wdt.mask (SYSTEM_CONFIG498[4]) is activated. Masked ST40 reset outputs A masked reset output (ResetOut mask = 1) from of the ST40 can eventually reset the rest of the system (if not masked, see below). For each case, two different masks are provided: C Confidential System configuration bits can be used to force either a manual or power-on-reset to ST40. 1. The wdt.mask for the POR, MAN and WDT reset outputs 2. The udi.mask for the UDI reset output The following registers perform the ST40 mask function: 1. SYSTEM_CONFIG498[0]: masks MAN reset output of ST40 Host towards the system 2. SYSTEM_CONFIG498[1]: masks UDI reset output of ST40 Host towards the system 3. SYSTEM_CONFIG498[2]: mask POR reset output of ST40 Host towards the system 4. SYSTEM_CONFIG498[3]: mask WDT reset output of ST40 Host towards the system 5. SYSTEM_CONFIG498[4]: mask LPC_WDT reset output towards the system 6. SYSTEM_CONFIG498[5]: mask PWR_SW reset output towards the system DocID023557 Rev 10 359/604 Information classified Confidential - Do not copy (See last page for obligations) These reset outputs can be configured eventually to reset the ST231s and system peripherals (warm reset). Reset configuration (mode pins) 17 STiH271EL Reset configuration (mode pins) The STiH271EL has static configuration pins (called mode pins). These pins are shared with the EMI_ADD[8:1] balls and are valid only during the power-on-reset sequence. External pull-up or pull-down resistors must be applied to define the desired configuration. The values of these mode pins are captured by the rising edge of an internal, stretched (by 1.4 ms), version of the power-on reset signal, applied on the SYS_NOTRESETIN pad during the reset phase. These mode pin values are made available to the system to define operating modes, such as the boot mode configuration. ti a Mode[2] => EMI_ADD[1] Mode[3] => EMI_ADD[2] Mode[4] => EMI_ADD[3] Mode[5] => EMI_ADD[4] Mode[6] => EMI_ADD[5] Mode[7] Reserved. Must be set to `0'. EMI_ADD[6] Mode[8] Alternate clock select 0: oscillator 1: Alternate clock EMI_ADD[7] Mode[9] Reserved. Must be set to `0'. fid Boot device selection (refer to Table 76) EMI_ADD[8] Mode[1] and Mode[0] do not exist. Table 76. Mode[6:2] 360/604 Controlling pad Mode[6:2] on Note: Description C Confidential Bit field Mode pins mapping en Table 75. l The following table shows the mapping of the mode pins. Boot device selection encoding Boot device 00000 Reserved 00001 8-bit NAND, 2K page, 4 address cycles, error free (BCH controller) 00010 8-bit NAND, 2K page, 4 address cycles, 18 bits error prone (BCH controller) 00011 8-bit NAND, 2K page, 4 address cycles, 30 bits error prone (BCH controller) 00100 8-bit NAND, 2K page, 5 address cycles, error free (BCH controller) 00101 8-bit NAND, 2K page, 5 address cycles, 18 bits error prone (BCH controller) 00110 8-bit NAND, 2K page, 5 address cycles, 30 bits error prone (BCH controller) 00111 Reserved 01000 8-bit NAND, 4K page, 5 address cycles, error free (BCH controller) 01001 8-bit NAND, 4K page, 5 address cycles, 18 bits error prone (BCH controller) 01010 8-bit NAND, 4K page, 5 address cycles, 30 bits error prone (BCH controller) DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The captured values are also recorded in a readable register SYSTEM_STATUS42. STiH271EL Reset configuration (mode pins) Boot device selection encoding (continued) Boot device 01011 Reserved 01100 8-bit NAND, 8K page, 5 address cycles, error free (BCH controller) 01101 8-bit NAND, 8K page, 5 address cycles, 18 bits error prone (BCH controller) 01110 8-bit NAND, 8K page, 5 address cycles, 30 bits error prone (BCH controller) 01111 Reserved 10000 Reserved 10001 8-bit NAND, 0.5 K page, 3 address cycles (Hamming controller) 10010 8-bit NAND, 0.5 K page, 4 address cycles (Hamming controller) 10011 8-bit NAND, 2 K page, 4 address cycles (Hamming controller) 10100 8-bit NAND, 2 K page, 5 address cycles (Hamming controller) 10101 Reserved 10110 Reserved 10111 Reserved 11000 Reserved 11001 Reserved 11010 SPI NOR 11011 Reserved 11100 Reserved 11101 Reserved 11110 Reserved 11111 Reserved on fid en ti a l Information classified Confidential - Do not copy (See last page for obligations) Mode[6:2] C Confidential Table 76. DocID023557 Rev 10 361/604 Standby controller 18 STiH271EL Standby controller The STiH271EL SoC infrastructure integrates an autonomous standby controller (SBC) block, to support the controller passive standby mode, which reduces energy consumption in the SoC. l The SBC is a CPU-based logic and peripheral IP (low power manager-LPM). It is integrated as an independent always ON power domain partition associated with its always ON padring. C on fid Confidential en ti a Further details are explained in a dedicated application note. For access to this internal document, please contact your local STMicroelectronics representative. 362/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) In the controller passive standby mode, the whole part of the chip (including core and padring) is not powered except the SBC power partition and its padring and DDR padrings (to support retention mode). In this mode, the wake-up triggers are detected by the SBC block itself. STiH271EL 19 System configuration registers System configuration registers The following table gives the global view of the four system configuration banks (SYSCFG_BANK0 to SYSCFG_BANK3). Each bank has a unique base address, of the form SYSCFG_BANK0BaseAddress, which can be found in Chapter 11: Memory and onchip peripherals address map. System configuration registers banks summary SYSCFG_BAN K3: Section 19.5: Bank 3 registers descriptions AGC bist, SBC reset, SBC voltage regulator, compensation, Ethernet PHY, front-panel, mode pins status and device ID SYSTEM_STATUS27 to SYSTEM_STATUS42 ti a l SYSTEM_CONFIG0 to SYSTEM_CONFIG23 Configuration of PIO4 to PIO 12, retime configuration of PIO4 to PIO12, comms configuration, temperature sensor, compensation, DDR3SS3, ST40 boot address, ST231 boot address Temperature sensor, compensation status, cache L2 power down status, DDR3SS status, ClockGenA1, PLL lock status SYSTEM_CONFIG100 to SYSTEM_CONFIG144 and SYSTEM_CONFIG168 to SYSTEM_CONFIG176 SYSTEM_STATUS148 to SYSTEM_STATUS160 Configuration registers for PIO 13 to 15, retime configuration registers for PIO 13 to 15, SYSTEM_CONFIG200 to compensation, system interrupt bank, system SYSTEM_CONFIG212, SYSTEM_CONFIG234, DREQ bank, comms configuration, MMC boot SYSTEM_CONFIG235, SYSTEM_CONFIG239 and configuration Compensation status SYSTEM_STATUS227 Power down control, frequency synthesizer 0, 1 and 2 configuration, ADAC controller, audio configuration, video DAC, reset generator control, VCC configuration, video clock divider, CPU soft reset, HDMI PLL configuration, USB PHY control, compensation control and EMI_DVBCIREG selection SYSTEM_CONFIG401 to SYSTEM_CONFIG422, SYSTEM_CONFIG424 to SYSTEM_CONFIG465, SYSTEM_CONFIG468, SYSTEM_CONFIG475, SYSTEM_CONFIG478 to SYSTEM_CONFIG503 and SYSTEM_CONFIG509 Power down status, HDMI PLL, reset generator, compensation status, HDMI PHY sink current SYSTEM_STATUS423, SYSTEM_STATUS466, SYSTEM_STATUS467, SYSTEM_STATUS470, SYSTEM_STATUS472, SYSTEM_STATUS504 and SYSTEM_STATUS510 DocID023557 Rev 10 363/604 Information classified Confidential - Do not copy (See last page for obligations) SYSCFG_BAN K2: Section 19.4: Bank 2 registers descriptions Configuration registers for PIO 0 to 3, retime configuration registers for PIO 0 to 3, Standby controller configuration, Ethernet PHY configuration, Compensation configuration, front-panel reset configuration en SYSCFG_BAN K1: Section 19.3: Bank 1 registers descriptions Registers of this bank fid Confidential SYSCFG_BAN K0: Section 19.2: Bank 0 register descriptions Functions controlled in this bank on Bank name C Table 77. System configuration registers STiH271EL 19.1 Registers summary table Table 78. Registers list Offset Register name Description Page Alternate function output control for PIO0 page 371 0x00000004 SYSTEM_CONFIG1 Alternate function output control for PIO1 page 372 0x00000008 SYSTEM_CONFIG2 Alternate function output control for PIO2 page 373 0x0000000C SYSTEM_CONFIG3 Alternate function output control for PIO3 page 374 0x00000010 SYSTEM_CONFIG4 Output enable pad control for all PIO alternate functions page 376 0x00000014 SYSTEM_CONFIG5 Pull up pad control for all PIO alternate functions l page 377 0x00000018 SYSTEM_CONFIG6 Open drain pad control for all PIO alternate functions page 378 0x0000001C SYSTEM_CONFIG7 PIO0 retime configuration register 0 page 380 0x00000020 SYSTEM_CONFIG8 PIO0 retime configuration register 1 page 380 0x00000024 SYSTEM_CONFIG9 PIO1 retime configuration register 0 page 381 0x00000028 SYSTEM_CONFIG10 PIO1 retime configuration register 1 page 381 0x0000002C SYSTEM_CONFIG11 PIO2 retime configuration register 0 page 382 0x00000030 SYSTEM_CONFIG12 0x00000034 SYSTEM_CONFIG13 0x00000038 SYSTEM_CONFIG14 0x0000003C en PIO3 retime configuration register 0 page 383 PIO3 retime configuration register 1 page 383 SYSTEM_CONFIG15 StandBy controller configuration register page 384 0x00000040 RESERVED RESERVED - 0x00000044 SYSTEM_CONFIG17 StandBy controller peripheral reset configuration page 384 0x00000048 SYSTEM_CONFIG18 StandBy controller voltage regulator configuration page 385 0x0000004C SYSTEM_CONFIG19 Low power monitor configuration page 386 0x00000050 SYSTEM_CONFIG20 Cross trigger PIO not system configuration page 387 0x00000054 SYSTEM_CONFIG21 Front panel reset control configuration page 387 0x00000058 SYSTEM_CONFIG22 Compensation digital 1 configuration page 388 0x0000005C SYSTEM_CONFIG23 Ethernet configuration register page 389 0x00000060 to 0x00000068 RESERVED RESERVED - 0x0000006C SYSTEM_STATUS27 StandBy controller ACG glue bist status register page 390 0x00000070 SYSTEM_STATUS28 StandBy controller reset observation status page 390 0x00000074 SYSTEM_STATUS29 StandBy controller voltage regulator status page 390 0x00000078 SYSTEM_STATUS30 ACG status register page 391 0x0000007C SYSTEM_STATUS31 Front panel reset control status page 392 0x00000080 SYSTEM_STATUS32 Compensation digital 1 status page 392 364/604 fid page 382 on PIO2 retime configuration register 1 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG0 ti a 0x00000000 C Confidential Bank 0 (Sapphire) STiH271EL Registers list (continued) Register name Description Page 0x00000084 SYSTEM_STATUS33 Ethernet status page 393 0x00000088 SYSTEM_STATUS34 SoC voltage control OK page 393 0x0000008C to 0x00000090 RESERVED RESERVED - 0x00000094 SYSTEM_CONFIG37 32 kHz oscillator configuration page 394 0x00000098 SYSTEM_CONFIG38 Voltage regulator DLVDPDLV page 394 0x0000009C RESERVED RESERVED - 0x000000A0 SYSTEM_STATUS40 Mode pins status page 395 0x000000A4 SYSTEM_STATUS41 Device ID page 395 0x000000A8 SYSTEM_STATUS42 Mode pins captured at power-on-reset page 396 0x00000000 SYSTEM_CONFIG100 Alternate function output control for PIO4 page 396 0x00000004 SYSTEM_CONFIG101 Alternate function output control for PIO5 page 397 0x00000008 SYSTEM_CONFIG102 Alternate function output control for PIO6 page 398 0x0000000C SYSTEM_CONFIG103 Alternate function output control for PIO7 page 399 0x00000010 SYSTEM_CONFIG104 0x00000014 SYSTEM_CONFIG105 0x00000018 SYSTEM_CONFIG106 0x0000001C ti a en Bank 1 (Coral) Alternate function output control for PIO9 page 402 Alternate function output control for PIO10 page 403 SYSTEM_CONFIG107 Alternate function output control for PIO11 page 404 0x00000020 SYSTEM_CONFIG108 Alternate function output control for PIO12 page 406 0x00000024 SYSTEM_CONFIG109 Output enable pad control for all PIO alternate functions page 407 0x00000028 SYSTEM_CONFIG110 Output enable pad control for all PIO alternate functions page 408 0x0000002C SYSTEM_CONFIG111 Output enable pad control for all PIO alternate functions page 410 0x00000030 SYSTEM_CONFIG112 Pull up pad control for all PIO alternate functions page 411 0x00000034 SYSTEM_CONFIG113 Pull up pad control for all PIO alternate functions page 412 0x00000038 SYSTEM_CONFIG114 Pull up pad control for all PIO alternate functions page 413 0x0000003C SYSTEM_CONFIG115 Open drain pad control for all PIO alternate functions page 414 0x00000040 SYSTEM_CONFIG116 Open drain pad control for all PIO alternate functions page 415 0x00000044 SYSTEM_CONFIG117 Open drain pad control for all PIO alternate functions page 416 0x00000048 SYSTEM_CONFIG118 PIO4 retime configuration register 0 page 417 0x0000004C SYSTEM_CONFIG119 PIO4 retime configuration register 1 page 417 0x00000050 SYSTEM_CONFIG120 PIO5 retime configuration register 0 page 418 0x00000054 SYSTEM_CONFIG121 PIO5 retime configuration register 1 page 419 0x00000058 SYSTEM_CONFIG122 PIO6 retime configuration register 0 page 419 0x0000005C SYSTEM_CONFIG123 PIO6 retime configuration register 1 page 420 fid page 400 on Alternate function output control for PIO8 C Confidential l Offset DocID023557 Rev 10 365/604 Information classified Confidential - Do not copy (See last page for obligations) Table 78. System configuration registers System configuration registers Description Page 0x00000060 SYSTEM_CONFIG124 PIO7 retime configuration register 0 page 420 0x00000064 SYSTEM_CONFIG125 PIO7 retime configuration register 1 page 421 0x00000068 SYSTEM_CONFIG126 PIO8 retime configuration register 0 page 421 0x0000006C SYSTEM_CONFIG127 PIO8 retime configuration register 1 page 422 0x00000070 SYSTEM_CONFIG128 PIO9 retime configuration register 0 page 422 0x00000074 SYSTEM_CONFIG129 PIO9 retime configuration register 1 page 423 0x00000078 SYSTEM_CONFIG130 PIO10 retime configuration register 0 page 423 0x0000007C SYSTEM_CONFIG131 PIO10 retime configuration register 1 page 424 0x00000080 SYSTEM_CONFIG132 PIO11 retime configuration register 0 0x00000084 SYSTEM_CONFIG133 PIO11 retime configuration register 1 page 425 0x00000088 SYSTEM_CONFIG134 PIO12 retime configuration register 0 page 425 0x0000008C SYSTEM_CONFIG135 PIO12 retime configuration register 1 page 426 0x00000090 SYSTEM_CONFIG136 Comms configuration page 426 0x00000094 0x0000009C RESERVED - - 0x000000A0 SYSTEM_CONFIG140 Temperature sensor 0 configuration page 427 0x000000A4 SYSTEM_CONFIG141 Compensation digital 2 configuration page 428 0x000000A8 0x000000AC RESERVED - - 0x000000B0 SYSTEM_CONFIG144 TSIN3 byte clock select page 429 0x000000B4 0x000000BC RESERVED - - 0x000000C0 SYSTEM_STATUS148 Temperature sensor 0 status page 429 0x000000C4 SYSTEM_STATUS149 Compensation digital 2 and 3 status page 430 0x000000C8 0x000000CC RESERVED - - 0x000000D0 SYSTEM_STATUS152 Cache L2 power down status page 430 0x000000D4 RESERVED - - 0x000000D8 SYSTEM_STATUS154 DDR3SS status register 0 page 431 0x000000DC 0x000000EC RESERVED - - 0x000000F0 SYSTEM_STATUS160 ClockGenA1 PLL0-1 lock status page 432 0x000000F4 0x0000010C RESERVED - - 0x00000110 SYSTEM_CONFIG168 Cache L2 power down control page 432 0x00000114 SYSTEM_CONFIG169 DDR3SS configuration register 0 page 433 366/604 fid en ti a l Register name on Offset DocID023557 Rev 10 page 424 Information classified Confidential - Do not copy (See last page for obligations) Registers list (continued) C Confidential Table 78. STiH271EL STiH271EL Registers list (continued) Offset Register name Description Page 0x000000118 0x00000120 RESERVED - - 0x00000124 SYSTEM_CONFIG173 ST40 boot address page 434 0x00000128 RESERVED - - 0x0000012C SYSTEM_CONFIG175 ST231 DMU boot address page 434 0x00000130 SYSTEM_CONFIG176 ST231 audio boot address page 435 0x00000134 0x00000150 RESERVED - - 0x00000000 SYSTEM_CONFIG200 Alternate function output control for PIO13 page 435 0x00000004 SYSTEM_CONFIG201 Alternate function output control for PIO14 page 437 0x00000008 SYSTEM_CONFIG202 Alternate function output control for PIO15 page 437 0x0000000C SYSTEM_CONFIG203 Output enable pad control for all PIO alternate functions page 440 0x00000010 SYSTEM_CONFIG204 Pull up pad control for all PIO alternate functions page 441 0x00000014 SYSTEM_CONFIG205 Open drain pad control for all PIO alternate functions page 442 0x00000018 SYSTEM_CONFIG206 PIO13 retime configuration register 0 page 443 0x0000001C SYSTEM_CONFIG207 0x00000020 SYSTEM_CONFIG208 0x00000024 SYSTEM_CONFIG209 0x00000028 ti a en fid page 444 PIO14 retime configuration register 0 page 444 PIO14 retime configuration register 1 page 445 SYSTEM_CONFIG210 PIO15 retime configuration register 0 page 445 0x0000002C SYSTEM_CONFIG211 PIO15 retime configuration register 1 page 446 0x00000030 SYSTEM_CONFIG212 Compensation digital 0 configuration register page 446 0x00000034 0x00000068 RESERVED - - 0x0000006C SYSTEM_STATUS227 Compensation status register 0 page 447 0x00000070 0x00000084 RESERVED - - 0x00000088 SYSTEM_CONFIG234 System configuration interrupts bank page 447 0x0000008C SYSTEM_CONFIG235 System configuration DREQ bank page 448 0x00000090 0x00000098 RESERVED - - 0x0000009C SYSTEM_CONFIG239 Comms configuration page 449 0x000000B0 0x000000BC RESERVED - - RESERVED - - on PIO13 retime configuration register 1 C Confidential l Bank 2 (Pearl) Bank 3 (Opal) 0x00000000 DocID023557 Rev 10 367/604 Information classified Confidential - Do not copy (See last page for obligations) Table 78. System configuration registers System configuration registers Description Page 0x00000004 SYSTEM_CONFIG401 Power down requests control page 449 0x00000008 0x00000014 RESERVED - - 0x00000018 SYSTEM_CONFIG406 Global parameters of frequency synthesizer 0 (GP) page 450 0x0000001C SYSTEM_CONFIG407 Frequency synthesizer 2 (GP) channel 0 coarse selection page 450 0x00000020 SYSTEM_CONFIG408 Frequency synthesizer 2 (GP) channel 0 fine selection page 451 0x00000024 SYSTEM_CONFIG409 Frequency synthesizer 2 (GP) channel 0 output divider page 451 0x00000028 SYSTEM_CONFIG410 Frequency synthesizer 2 (GP) channel 0 program enable page 452 0x0000002C SYSTEM_CONFIG411 Frequency synthesizer 2 (GP) channel 1 coarse selection page 452 0x00000030 SYSTEM_CONFIG412 Frequency synthesizer 2 (GP) channel 1 fine selection page 453 0x00000034 SYSTEM_CONFIG413 Frequency synthesizer 2 (GP) channel 1 output divider page 453 0x00000038 SYSTEM_CONFIG414 Frequency synthesizer 2 (GP) channel 1 program enable page 454 0x0000003C SYSTEM_CONFIG415 Frequency synthesizer 2 (GP) channel 2 coarse selection page 454 0x00000040 SYSTEM_CONFIG416 Frequency synthesizer 2 (GP) channel 2 fine selection page 455 0x00000044 SYSTEM_CONFIG417 Frequency synthesizer 2 (GP) channel 2 output divider page 455 0x00000048 SYSTEM_CONFIG418 Frequency synthesizer 2 (GP) channel 2 program enable page 456 0x0000004C SYSTEM_CONFIG419 Frequency synthesizer 2 (GP) channel 3 coarse selection page 456 0x00000050 SYSTEM_CONFIG420 Frequency synthesizer 2 (GP) channel 3 fine selection page 457 0x00000054 SYSTEM_CONFIG421 Frequency synthesizer 2 (GP) channel 3 output divider page 457 0x00000058 SYSTEM_CONFIG422 Frequency synthesizer 2 (GP) channel 3 program enable page 458 0x0000005C SYSTEM_STATUS423 Power down ACK monitor page 458 0x00000060 SYSTEM_CONFIG424 Global parameters of frequency synthesizer 0 (VID0) page 459 0x00000064 SYSTEM_CONFIG425 Frequency synthesizer 0 (VID0) channel 0 coarse selection page 459 0x00000068 SYSTEM_CONFIG426 Frequency synthesizer 0 (VID0) channel 0 fine selection page 460 0x0000006C SYSTEM_CONFIG427 Frequency synthesizer 0 (VID0) channel 0 output divider page 460 0x00000070 SYSTEM_CONFIG428 Frequency synthesizer 0 (VID0) channel 0 program enable page 461 0x00000074 SYSTEM_CONFIG429 Frequency synthesizer 0 (VID0) channel 1 coarse selection page 461 0x00000078 SYSTEM_CONFIG430 Frequency synthesizer 0 (VID0) channel 1 fine selection page 462 0x0000007C SYSTEM_CONFIG431 Frequency synthesizer 0 (VID0) channel 1 output divider page 462 0x00000080 SYSTEM_CONFIG432 Frequency synthesizer 0 (VID0) channel 1 program enable page 463 0x00000084 SYSTEM_CONFIG433 Frequency synthesizer 0 (VID0) channel 2 coarse selection page 463 0x00000088 SYSTEM_CONFIG434 Frequency synthesizer 0 (VID0) channel 2 fine selection page 464 0x0000008C SYSTEM_CONFIG435 Frequency synthesizer 0 (VID0) channel 2 output divider page 464 368/604 fid en ti a l Register name on Offset DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Registers list (continued) C Confidential Table 78. STiH271EL STiH271EL Registers list (continued) Description Page 0x00000090 SYSTEM_CONFIG436 Frequency synthesizer 0 (VID0) channel 2 program enable page 465 0x00000094 SYSTEM_CONFIG437 Frequency synthesizer 0 (VID0) channel 3 coarse selection page 465 0x00000098 SYSTEM_CONFIG438 Frequency synthesizer 0 (VID0) channel 3 fine selection page 466 0x0000009C SYSTEM_CONFIG439 Frequency synthesizer 0 (VID0) channel 3 output divider page 466 0x000000A0 SYSTEM_CONFIG440 Frequency synthesizer 0 (VID0) channel 3 program enable page 467 0x000000A4 SYSTEM_CONFIG441 AUD_ADAC_CTRL page 467 0x000000A8 SYSTEM_CONFIG442 AUD_IO_CTRL page 468 0x000000AC SYSTEM_CONFIG443 Audio glue configuration page 468 0x000000B0 RESERVED - 0x000000B8 RESERVED - 0x000000C4 SYSTEM_CONFIG449 Power down requests control 0x000000C8 SYSTEM_CONFIG450 Video DACs configuration page 470 0x000000CC 0x000000E4 RESERVED - - 0x000000E8 SYSTEM_CONFIG458 Reset generator control 2 0x000000EC SYSTEM_CONFIG459 0x000000F0 SYSTEM_CONFIG460 0x000000F4 SYSTEM_CONFIG461 0x000000F8 ti a en fid page 470 page 471 page 472 Reset generator control 0 page 472 Reset generator control 1 page 473 SYSTEM_CONFIG462 Video control and debug configuration register 1 page 473 0x000000FC SYSTEM_CONFIG463 Video clock divider 0 setting 0 page 475 0x00000100 SYSTEM_CONFIG464 Video clock divider 0 setting 1 page 476 0x00000104 SYSTEM_CONFIG465 Video clock divider 0 setting 2 page 476 0x00000114 RESERVED - - 0x00000118 SYSTEM_STATUS470 HDMI rejection PLL status register page 476 0x0000011C RESERVED - - 0x00000120 SYSTEM_STATUS472 Reset generator status register page 477 0x00000124 0x00000128 RESERVED - - 0x0000012C SYSTEM_CONFIG475 CPUs soft reset page 478 0x00000130 0x00000134 RESERVED - - 0x00000138 SYSTEM_CONFIG478 Global parameters of frequency synthesizer 1 (VID1) page 478 0x0000013C SYSTEM_CONFIG479 Frequency synthesizer 1 (VID1) channel 0 coarse selection page 479 0x00000140 SYSTEM_CONFIG480 Frequency synthesizer 1 (VID1) channel 0 fine selection page 479 on Reset generator control 3 DocID023557 Rev 10 369/604 Information classified Confidential - Do not copy (See last page for obligations) Register name l Offset C Confidential Table 78. System configuration registers System configuration registers Description Page 0x00000144 SYSTEM_CONFIG481 Frequency synthesizer 1 (VID1) channel 0 output divider page 480 0x00000148 SYSTEM_CONFIG482 Frequency synthesizer 1 (VID1) channel 0 program enable page 480 0x0000014C SYSTEM_CONFIG483 Frequency synthesizer 1 (VID1) channel 1 coarse selection page 481 0x00000150 SYSTEM_CONFIG484 Frequency synthesizer 1 (VID1) channel 1 fine selection page 481 0x00000154 SYSTEM_CONFIG485 Frequency synthesizer 1 (VID1) channel 1 output divider page 482 0x00000158 SYSTEM_CONFIG486 Frequency synthesizer 1 (VID1) channel 1 program enable page 482 0x0000015C SYSTEM_CONFIG487 Frequency synthesizer 1 (VID1) channel 2 coarse selection 0x00000160 SYSTEM_CONFIG488 Frequency synthesizer 1 (VID1) channel 2 fine selection page 483 0x00000164 SYSTEM_CONFIG489 Frequency synthesizer 1 (VID1) channel 2 output divider page 484 0x00000168 SYSTEM_CONFIG490 Frequency synthesizer 1 (VID1) channel 2 program enable page 484 0x0000016C SYSTEM_CONFIG491 Frequency synthesizer 1 (VID1) channel 3 coarse selection page 485 0x00000170 SYSTEM_CONFIG492 Frequency synthesizer 1 (VID1) channel 3 fine selection page 485 0x00000174 SYSTEM_CONFIG493 Frequency synthesizer 1 (VID1) channel 3 output divider page 486 0x00000178 SYSTEM_CONFIG494 Frequency synthesizer 1 (VID1) channel 3 program enable page 486 0x0000017C SYSTEM_CONFIG495 0x00000180 SYSTEM_CONFIG496 0x00000184 en fid page 483 page 487 HDMI PLL configuration register 2 page 487 SYSTEM_CONFIG497 HDMI PLL configuration register 3 page 488 0x00000188 SYSTEM_CONFIG498 ST40 CPU mask register page 489 0x0000018C SYSTEM_CONFIG499 ST40 power soft reset n page 490 0x00000190 RESERVED - - 0x00000194 SYSTEM_CONFIG501 USB PHY control register 0 page 490 0x00000198 SYSTEM_CONFIG502 USB PHY control register 1 page 492 0x0000019C SYSTEM_CONFIG503 Compensation digital 5 configuration register page 494 0x000001A0 SYSTEM_STATUS504 Compensation status register 5 page 495 0x000001A4 0x000001B0 RESERVED - - 0x000001B4 SYSTEM_CONFIG509 EMI_DVBCIREG selection register page 495 0x000001B8 SYSTEM_STATUS510 HDMI PHY transmitter sink current correction page 496 370/604 on HDMI PLL configuration register 1 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Register name ti a Offset l Registers list (continued) C Confidential Table 78. STiH271EL STiH271EL Bank 0 register descriptions SYSTEM_CONFIG0 Alternate function output control for PIO0 RESERVED PIO0_3_SELECTOR RESERVED PIO0_2_SELECTOR RESERVED PIO0_1_SELECTOR RESERVED PIO0_0_SELECTOR 1 PIO0_4_SELECTOR 2 RESERVED 3 PIO0_5_SELECTOR 4 RESERVED 5 PIO0_6_SELECTOR 6 RESERVED 7 PIO0_7_SELECTOR 8 R RW R RW R RW R RW R RW R RW R RW R RW SYSCFG_BANK0BaseAddress + 0x00000000 Type: RW Reset: 0x0000 0000 Description: PIO0 alternate function output configuration. 0 en ti a l Address: [31] RESERVED fid [30:28] PIO0_7_SELECTOR: PIO0[7] bit selection according to the PIO0_7_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 [27] RESERVED [23] RESERVED on [26:24] PIO0_6_SELECTOR: PIO0[6] bit selection according to the PIO0_6_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 [22:20] PIO0_5_SELECTOR: PIO0[5] bit selection according to the PIO0_5_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [19] RESERVED [18:16] PIO0_4_SELECTOR: PIO0[4] bit selection according to the PIO0_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 101: Alternate function 5 [15] RESERVED [14:12] PIO0_3_SELECTOR: PIO0[3] bit selection according to the PIO0_3_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 [11] RESERVED [10:8] PIO0_2_SELECTOR: PIO0[2] bit selection according to the PIO0_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 [7] RESERVED DocID023557 Rev 10 371/604 Information classified Confidential - Do not copy (See last page for obligations) 19.2 System configuration registers System configuration registers STiH271EL [6:4] PIO0_1_SELECTOR: PIO0[1] bit selection according to the PIO0_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 [3] RESERVED [2:0] PIO0_0_SELECTOR: PIO0[0] bit selection according to the PIO0_0_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 Alternate function output control for PIO1 RW SYSCFG_BANK0BaseAddress + 0x00000004 Type: RW Reset: 0x0000 0000 Description: PIO1 alternate function output configuration. 2 1 R RW R RW R RW fid en Address: 3 PIO1_0_SELECTOR RESERVED R 4 RESERVED PIO1_4_SELECTOR RW 5 PIO1_1_SELECTOR RESERVED R 6 RESERVED PIO1_5_SELECTOR RW 7 PIO1_2_SELECTOR RESERVED R l PIO1_6_SELECTOR RW 8 RESERVED RESERVED R PIO1_3_SELECTOR PIO1_7_SELECTOR RW ti a RESERVED R 9 [31] RESERVED [27] RESERVED on [30:28] PIO1_7_SELECTOR: PIO1[7] bit selection according to the PIO1_7_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [26:24] PIO1_6_SELECTOR: PIO1[6] bit selection according to the PIO1_6_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 [23] RESERVED [22:20] PIO1_5_SELECTOR: PIO1[5] bit selection according to the PIO1_5_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 [19] RESERVED [18:16] PIO1_4_SELECTOR: PIO1[4] bit selection according to the PIO1_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 [15] RESERVED [14:12] PIO1_3_SELECTOR: PIO1[3] bit selection according to the PIO1_3_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 [11] RESERVED 372/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG1 STiH271EL System configuration registers [10:8] PIO1_2_SELECTOR: PIO1[2] bit selection according to the PIO1_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4101: Alternate function 5 [7] RESERVED [6:4] PIO1_1_SELECTOR: PIO1[1] bit selection according to the PIO1_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 l [2:0] PIO1_0_SELECTOR: PIO1[0] bit selection according to the PIO1_0_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 Alternate function output control for PIO2 ti a SYSTEM_CONFIG2 2 1 PIO2_0_SELECTOR 3 RW R RW R RW R RW SYSCFG_BANK0BaseAddress + 0x00000008 Type: RW Reset: 0x0000 3000 Description: PIO2 alternate function output configuration. 0 C on Address: [31] RESERVED 4 RESERVED R 5 PIO2_1_SELECTOR RW 6 RESERVED R 7 PIO2_2_SELECTOR RESERVED RW 8 RESERVED PIO2_5_SELECTOR R 9 PIO2_3_SELECTOR RESERVED RW RESERVED PIO2_6_SELECTOR R PIO2_4_SELECTOR RESERVED RW en PIO2_7_SELECTOR R fid RESERVED Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [30:28] PIO2_7_SELECTOR: PIO2[7] bit selection according to the PIO2_7_SELECTOR[2:0] value. 000: PIO general-purpose function 010: Alternate function 2 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [27] RESERVED [26:24] PIO2_6_SELECTOR: PIO2[6] bit selection according to the PIO2_6_SELECTOR[2:0] value. 000: PIO general-purpose function 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 [23] RESERVED [22:20] PIO2_5_SELECTOR: PIO2[5] bit selection according to the PIO2_5_SELECTOR[2:0] value. 000: PIO general-purpose function 010: Alternate function 2 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [19] RESERVED DocID023557 Rev 10 373/604 Information classified Confidential - Do not copy (See last page for obligations) [3] RESERVED System configuration registers STiH271EL [18:16] PIO2_4_SELECTOR: PIO2[4] bit selection according to the PIO2_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 [15] RESERVED [14:12] PIO2_3_SELECTOR: PIO2[3] bit selection according to the PIO2_3_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 l [10:8] PIO2_2_SELECTOR: PIO2[2] bit selection according to the PIO2_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 101: Alternate function 5 ti a [7] RESERVED en [3] RESERVED fid [2:0] PIO2_0_SELECTOR: PIO2[0] bit selection according to the PIO2_0_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 on SYSTEM_CONFIG3 Alternate function output control for PIO3 RESERVED PIO3_0_SELECTOR 1 PIO3_1_SELECTOR 2 RESERVED 3 PIO3_2_SELECTOR 4 RESERVED 5 PIO3_3_SELECTOR 6 RESERVED R 7 PIO3_4_SELECTOR RW 8 RESERVED R 9 PIO3_5_SELECTOR PIO3_6_SELECTOR RW RESERVED RESERVED R C PIO3_7_SELECTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Confidential [6:4] PIO2_1_SELECTOR: PIO2[1] bit selection according to the PIO2_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 RW R RW R RW R RW R RW R RW Address: SYSCFG_BANK0BaseAddress + 0x0000000C Type: RW Reset: 0x0000 0000 Description: PIO3 alternate function output configuration. [31] RESERVED [30:28] PIO3_7_SELECTOR: PIO3[7] bit selection according to the PIO3_7_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 374/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [11] RESERVED STiH271EL System configuration registers [27] RESERVED [26:24] PIO3_6_SELECTOR: PIO3[6] bit selection according to the PIO3_6_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 101: Alternate function 5110: Alternate function 6 [23] RESERVED [19] RESERVED ti a l [18:16] PIO3_4_SELECTOR: PIO3[4] bit selection according to the PIO3_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 en [14:12] PIO3_3_SELECTOR: PIO3[3] bit selection according to the PIO3_3_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5110: Alternate function 6 fid [11] RESERVED [7] RESERVED on [10:8] PIO3_2_SELECTOR: PIO3[2] bit selection according to the PIO3_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 [6:4] PIO3_1_SELECTOR: PIO3[1] bit selection according to the PIO3_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 C Confidential [15] RESERVED [3] RESERVED [2:0] PIO3_0_SELECTOR: PIO3[0] bit selection according to the PIO3_0_SELECTOR[2:0] value. 000: Adaptive Voltage Scaling feedback 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 DocID023557 Rev 10 375/604 Information classified Confidential - Do not copy (See last page for obligations) [22:20] PIO3_5_SELECTOR: PIO3[5] bit selection according to the PIO3_5_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 System configuration registers STiH271EL 8 7 6 5 4 3 2 1 0 SYSCFG_PIO0_6_OE SYSCFG_PIO0_5_OE SYSCFG_PIO0_4_OE SYSCFG_PIO0_3_OE SYSCFG_PIO0_2_OE SYSCFG_PIO0_1_OE SYSCFG_PIO0_0_OE SYSCFG_BANK0BaseAddress + 0x00000010 Type: RW Reset: 0x2008 0000 Description: Output enable pad control for all PIO alternate functions. ti a l Address: en [31] SYSCFG_PIO3_7_OE: PIO3[7] output enable control, active high. [30] SYSCFG_PIO3_6_OE: PIO3[6] output enable control, active high. Confidential [29] SYSCFG_PIO3_5_OE: PIO3[5] output enable control, active high. [28] SYSCFG_PIO3_4_OE: PIO3[4] output enable control, active high. fid [27] SYSCFG_PIO3_3_OE: PIO3[3] output enable control, active high. [26] SYSCFG_PIO3_2_OE: PIO3[2] output enable control, active high. [25] SYSCFG_PIO3_1_OE: PIO3[1] output enable control, active high. on [24] SYSCFG_PIO3_0_OE: PIO3[0] output enable control, active high. [23] SYSCFG_PIO2_7_OE: PIO2[7] output enable control, active high. [22] SYSCFG_PIO2_6_OE: PIO2[6] output enable control, active high. C [21] SYSCFG_PIO2_5_OE: PIO2[5] output enable control, active high. [20] SYSCFG_PIO2_4_OE: PIO2[4] output enable control, active high. [19] SYSCFG_PIO2_3_OE: PIO2[3] output enable control, active high. [18] SYSCFG_PIO2_2_OE: PIO2[2] output enable control, active high. [17] SYSCFG_PIO2_1_OE: PIO2[1] output enable control, active high. [16] SYSCFG_PIO2_0_OE: PIO2[0] output enable control, active high. [15] SYSCFG_PIO1_7_OE: PIO1[7] output enable control, active high. [14] SYSCFG_PIO1_6_OE: PIO1[6] output enable control, active high. [13] SYSCFG_PIO1_5_OE: PIO1[5] output enable control, active high. [12] SYSCFG_PIO1_4_OE: PIO1[4] output enable control, active high. [11] SYSCFG_PIO1_3_OE: PIO1[3] output enable control, active high. [10] SYSCFG_PIO1_2_OE: PIO1[2] output enable control, active high. [9] SYSCFG_PIO1_1_OE: PIO1[1] output enable control, active high. [8] SYSCFG_PIO1_0_OE: PIO1[0] output enable control, active high. 376/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 9 SYSCFG_PIO0_7_OE SYSCFG_PIO1_2_OE SYSCFG_PIO1_3_OE SYSCFG_PIO1_4_OE SYSCFG_PIO1_5_OE SYSCFG_PIO1_6_OE SYSCFG_PIO1_7_OE SYSCFG_PIO2_0_OE SYSCFG_PIO2_1_OE SYSCFG_PIO2_2_OE SYSCFG_PIO2_3_OE SYSCFG_PIO2_4_OE SYSCFG_PIO2_5_OE SYSCFG_PIO2_6_OE SYSCFG_PIO2_7_OE SYSCFG_PIO3_0_OE SYSCFG_PIO3_1_OE SYSCFG_PIO3_2_OE SYSCFG_PIO3_3_OE SYSCFG_PIO3_4_OE SYSCFG_PIO3_5_OE SYSCFG_PIO3_6_OE SYSCFG_PIO3_7_OE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO1_0_OE Output enable pad control for all PIO alternate functions SYSCFG_PIO1_1_OE SYSTEM_CONFIG4 STiH271EL System configuration registers [7] SYSCFG_PIO0_7_OE: PIO0[7] output enable control, active high. [6] SYSCFG_PIO0_6_OE: PIO0[6] output enable control, active high. [5] SYSCFG_PIO0_5_OE: PIO0[5] output enable control, active high. [4] SYSCFG_PIO0_4_OE: PIO0[4] output enable control, active high. [3] SYSCFG_PIO0_3_OE: PIO0[3] output enable control, active high. [2] SYSCFG_PIO0_2_OE: PIO0[2] output enable control, active high. [1] SYSCFG_PIO0_1_OE: PIO0[1] output enable control, active high. Type: RW Reset: 0x0000 0000 Description: Pull up pad control for all PIO alternate functions. 6 5 4 3 2 SYSCFG_PIO1_0_PU SYSCFG_PIO0_7_PU SYSCFG_PIO0_6_PU SYSCFG_PIO0_5_PU SYSCFG_PIO0_4_PU SYSCFG_PIO0_3_PU SYSCFG_PIO0_2_PU 1 0 SYSCFG_PIO0_0_PU 7 SYSCFG_PIO0_1_PU 8 on fid SYSCFG_BANK0BaseAddress + 0x00000014 SYSCFG_PIO1_2_PU SYSCFG_PIO1_3_PU SYSCFG_PIO1_4_PU ti a SYSCFG_PIO1_5_PU SYSCFG_PIO1_6_PU SYSCFG_PIO1_7_PU SYSCFG_PIO2_0_PU SYSCFG_PIO2_1_PU en SYSCFG_PIO2_2_PU SYSCFG_PIO2_3_PU SYSCFG_PIO2_4_PU SYSCFG_PIO2_5_PU SYSCFG_PIO2_6_PU SYSCFG_PIO2_7_PU SYSCFG_PIO3_0_PU SYSCFG_PIO3_1_PU SYSCFG_PIO3_2_PU SYSCFG_PIO3_3_PU SYSCFG_PIO3_4_PU SYSCFG_PIO3_5_PU SYSCFG_PIO3_6_PU Address: 9 [31] SYSCFG_PIO3_7_PU: PIO3[7] pull up control, active high. [30] SYSCFG_PIO3_6_PU: PIO3[6] pull up control, active high. [29] SYSCFG_PIO3_5_PU: PIO3[5] pull up control, active high. C Confidential SYSCFG_PIO3_7_PU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO1_1_PU Pull up pad control for all PIO alternate functions l SYSTEM_CONFIG5 [28] SYSCFG_PIO3_4_PU: PIO3[4] pull up control, active high. [27] SYSCFG_PIO3_3_PU: PIO3[3] pull up control, active high. [26] SYSCFG_PIO3_2_PU: PIO3[2] pull up control, active high. [25] SYSCFG_PIO3_1_PU: PIO3[1] pull up control, active high. [24] SYSCFG_PIO3_0_PU: PIO3[0] pull up control, active high. [23] SYSCFG_PIO2_7_PU: PIO2[7] pull up control, active high. [22] SYSCFG_PIO2_6_PU: PIO2[6] pull up control, active high. [21] SYSCFG_PIO2_5_PU: PIO2[5] pull up control, active high. [20] SYSCFG_PIO2_4_PU: PIO2[4] pull up control, active high. [19] SYSCFG_PIO2_3_PU: PIO2[3] pull up control, active high. [18] SYSCFG_PIO2_2_PU: PIO2[2] pull up control, active high. [17] SYSCFG_PIO2_1_PU: PIO2[1] pull up control, active high. [16] SYSCFG_PIO2_0_PU: PIO2[0] pull up control, active high. DocID023557 Rev 10 377/604 Information classified Confidential - Do not copy (See last page for obligations) [0] SYSCFG_PIO0_0_OE: PIO0[0] output enable control, active high. System configuration registers STiH271EL [15] SYSCFG_PIO1_7_PU: PIO1[7] pull up control, active high. [14] SYSCFG_PIO1_6_PU: PIO1[6] pull up control, active high. [13] SYSCFG_PIO1_5_PU: PIO1[5] pull up control, active high. [12] SYSCFG_PIO1_4_PU: PIO1[4] pull up control, active high. [11] SYSCFG_PIO1_3_PU: PIO1[3] pull up control, active high. [10] SYSCFG_PIO1_2_PU: PIO1[2] pull up control, active high. [9] SYSCFG_PIO1_1_PU: PIO1[1] pull up control, active high. [8] SYSCFG_PIO1_0_PU: PIO1[0] pull up control, active high. l [6] SYSCFG_PIO0_6_PU: PIO0[6] pull up control, active high. ti a [5] SYSCFG_PIO0_5_PU: PIO0[5] pull up control, active high. [4] SYSCFG_PIO0_4_PU: PIO0[4] pull up control, active high. [3] SYSCFG_PIO0_3_PU: PIO0[3] pull up control, active high. en [2] SYSCFG_PIO0_2_PU: PIO0[2] pull up control, active high. Address: SYSCFG_BANK0BaseAddress + 0x00000018 Type: RW Reset: 0x0000 0000 Description: Open drain pad control for all PIO alternate functions. 9 8 7 6 5 4 3 2 1 0 SYSCFG_PIO0_7_OD SYSCFG_PIO0_6_OD SYSCFG_PIO0_5_OD SYSCFG_PIO0_4_OD SYSCFG_PIO0_3_OD SYSCFG_PIO0_2_OD SYSCFG_PIO0_1_OD SYSCFG_PIO0_0_OD SYSCFG_PIO1_2_OD SYSCFG_PIO1_3_OD SYSCFG_PIO1_4_OD SYSCFG_PIO1_5_OD SYSCFG_PIO1_6_OD SYSCFG_PIO1_7_OD SYSCFG_PIO2_0_OD SYSCFG_PIO2_1_OD SYSCFG_PIO2_2_OD SYSCFG_PIO2_3_OD SYSCFG_PIO2_4_OD on SYSCFG_PIO2_5_OD SYSCFG_PIO2_6_OD SYSCFG_PIO2_7_OD SYSCFG_PIO3_0_OD C SYSCFG_PIO3_1_OD SYSCFG_PIO3_2_OD SYSCFG_PIO3_3_OD SYSCFG_PIO3_4_OD SYSCFG_PIO3_5_OD SYSCFG_PIO3_6_OD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO1_0_OD Open drain pad control for all PIO alternate functions SYSCFG_PIO1_1_OD SYSTEM_CONFIG6 fid [0] SYSCFG_PIO0_0_PU: PIO0[0] pull up control, active high. SYSCFG_PIO3_7_OD Confidential [1] SYSCFG_PIO0_1_PU: PIO0[1] pull up control, active high. [31] SYSCFG_PIO3_7_OD: PIO3[7] open drain control, active high. [30] SYSCFG_PIO3_6_OD: PIO3[6] open drain control, active high. [29] SYSCFG_PIO3_5_OD: PIO3[5] open drain control, active high. [28] SYSCFG_PIO3_4_OD: PIO3[4] open drain control, active high. [27] SYSCFG_PIO3_3_OD: PIO3[3] open drain control, active high. [26] SYSCFG_PIO3_2_OD: PIO3[2] open drain control, active high. [25] SYSCFG_PIO3_1_OD: PIO3[1] open drain control, active high. 378/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7] SYSCFG_PIO0_7_PU: PIO0[7] pull up control, active high. STiH271EL System configuration registers [24] SYSCFG_PIO3_0_OD: PIO3[0] open drain control, active high. [23] SYSCFG_PIO2_7_OD: PIO2[7] open drain control, active high. [22] SYSCFG_PIO2_6_OD: PIO2[6] open drain control, active high. [21] SYSCFG_PIO2_5_OD: PIO2[5] open drain control, active high. [20] SYSCFG_PIO2_4_OD: PIO2[4] open drain control, active high. [19] SYSCFG_PIO2_3_OD: PIO2[3] open drain control, active high. [18] SYSCFG_PIO2_2_OD: PIO2[2] open drain control, active high. [17] SYSCFG_PIO2_1_OD: PIO2[1] open drain control, active high. [16] SYSCFG_PIO2_0_OD: PIO2[0] open drain control, active high. l Information classified Confidential - Do not copy (See last page for obligations) [15] SYSCFG_PIO1_7_OD: PIO1[7] open drain control, active high. ti a [14] SYSCFG_PIO1_6_OD: PIO1[6] open drain control, active high. [13] SYSCFG_PIO1_5_OD: PIO1[5] open drain control, active high. [12] SYSCFG_PIO1_4_OD: PIO1[4] open drain control, active high. en [11] SYSCFG_PIO1_3_OD: PIO1[3] open drain control, active high. [9] SYSCFG_PIO1_1_OD: PIO1[1] open drain control, active high. fid [8] SYSCFG_PIO1_0_OD: PIO1[0] open drain control, active high. [7] SYSCFG_PIO0_7_OD: PIO0[7] open drain control, active high. [6] SYSCFG_PIO0_6_OD: PIO0[6] open drain control, active high. on [5] SYSCFG_PIO0_5_OD: PIO0[5] open drain control, active high. [4] SYSCFG_PIO0_4_OD: PIO0[4] open drain control, active high. [3] SYSCFG_PIO0_3_OD: PIO0[3] open drain control, active high. [2] SYSCFG_PIO0_2_OD: PIO0[2] open drain control, active high. [1] SYSCFG_PIO0_1_OD: PIO0[1] open drain control, active high. C Confidential [10] SYSCFG_PIO1_2_OD: PIO1[2] open drain control, active high. [0] SYSCFG_PIO0_0_OD: PIO0[0] open drain control, active high. DocID023557 Rev 10 379/604 System configuration registers STiH271EL PIO0 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO0_CFG_DELAY_1 PIO0_CFG_DELAY_0 RESERVED PIO0_CFG_CLK1NOTCLK0 RW RW R RW Address: SYSCFG_BANK0BaseAddress + 0x0000001C Type: RW Reset: 0x0000 0000 Description: PIO0 retime configuration register 0. 0 ti a l [31:24] PIO0_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns en [15:8] RESERVED fid [7:0] PIO0_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] on SYSTEM_CONFIG8 PIO0 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO0_CFG_DOUBLE_EDGE PIO0_CFG_CLKNOTDATA PIO0_CFG_RETIME Address: SYSCFG_BANK0BaseAddress + 0x00000020 Type: RW Reset: 0x0000 0000 Description: PIO0 retime configuration register 1. 9 8 7 6 5 4 [31:24] PIO0_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge [23:16] PIO0_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO0_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed [7:0] PIO0_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted 380/604 DocID023557 Rev 10 3 2 1 PIO0_CFG_INVERTCLK C Confidential [23:16] PIO0_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG7 STiH271EL System configuration registers PIO1 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO1_CFG_DELAY_1 PIO1_CFG_DELAY_0 RESERVED PIO1_CFG_CLK1NOTCLK0 RW RW R RW Address: SYSCFG_BANK0BaseAddress + 0x00000024 Type: RW Reset: 0x0000 0000 Description: PIO1 retime configuration register 0. 0 ti a l [31:24] PIO1_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns en [15:8] RESERVED fid [7:0] PIO1_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] on SYSTEM_CONFIG10 PIO1 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO1_CFG_DOUBLE_EDGE PIO1_CFG_CLKNOTDATA PIO1_CFG_RETIME Address: SYSCFG_BANK0BaseAddress + 0x00000028 Type: RW Reset: 0x0000 0000 Description: PIO1 retime configuration register 1. 9 8 7 6 5 4 3 2 1 0 PIO1_CFG_INVERTCLK C Confidential [23:16] PIO1_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [31:24] PIO1_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge [23:16] PIO1_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO1_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed [7:0] PIO1_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted DocID023557 Rev 10 381/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG9 System configuration registers STiH271EL PIO2 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO2_CFG_DELAY_1 PIO2_CFG_DELAY_0 RESERVED PIO2_CFG_CLK1NOTCLK0 RW RW R RW Address: SYSCFG_BANK0BaseAddress + 0x0000002C Type: RW Reset: 0x0000 0000 Description: PIO2 retime configuration register 0. 0 ti a l [31:24] PIO2_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns en [15:8] RESERVED fid [7:0] PIO2_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] on SYSTEM_CONFIG12 PIO2 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO2_CFG_DOUBLE_EDGE PIO2_CFG_CLKNOTDATA PIO2_CFG_RETIME Address: SYSCFG_BANK0BaseAddress + 0x00000030 Type: RW Reset: 0x0000 0000 Description: PIO2 retime configuration register 1. 9 8 7 6 5 4 [31:24] PIO2_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge [23:16] PIO2_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO2_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed [7:0] PIO2_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted 382/604 DocID023557 Rev 10 3 2 1 PIO2_CFG_INVERTCLK C Confidential [23:16] PIO2_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG11 STiH271EL System configuration registers PIO3 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO3_CFG_DELAY_1 PIO3_CFG_DELAY_0 9 8 7 RESERVED Address: SYSCFG_BANK0BaseAddress + 0x00000034 Type: RW Reset: 0x0000 0000 Description: PIO3 retime configuration register 0. 6 5 4 3 2 1 0 PIO3_CFG_CLK1NOTCLK0 ti a l [31:24] PIO3_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns en [23:16] PIO3_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns fid [7:0] PIO3_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] SYSTEM_CONFIG14 PIO3 retime configuration register 1 on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO3_CFG_DOUBLE_EDGE PIO3_CFG_CLKNOTDATA PIO3_CFG_RETIME Address: SYSCFG_BANK0BaseAddress + 0x00000038 Type: RW Reset: 0x0000 0000 Description: PIO3 retime configuration register 1. 9 8 7 6 5 4 3 2 1 0 PIO3_CFG_INVERTCLK C Confidential [15:8] RESERVED [31:24] PIO3_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge [23:16] PIO3_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO3_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed [7:0] PIO3_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted DocID023557 Rev 10 383/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG13 System configuration registers STiH271EL StandBy controller configuration 2 1 0 SBC_SW_RST_N 3 SBC_LVD_RST_MASK 4 SBC_SEL_CLK_OSC_FOR_RST 5 SBC_RST_LEVEL1_0_MASK 6 RESERVED 7 SBC_LEVEL1_WARM_COLDN 8 R RW R R W R W R W R W SYSCFG_BANK0BaseAddress + 0x0000003C Type: RW Reset: 0x0000 FE0B Description: StandBy controller configuration register. en ti a l Address: Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:17] RESERVED fid [16:8] SBC_LEVEL1_WARM_COLDN: 0: Cold reset on SBC level1 reset inputs1: Warm reset on SBC level1 reset inputs [3] SBC_RST_LEVEL1_0_MASK: Masks the reset input connected on SBC reset generator rst_level1_n[0]. on [2] SBC_SEL_CLK_OSC_FOR_RST: 0: ACG clock1: External clock [1] SBC_LVD_RST_MASK: Mask low voltage detector reset input. C [0] SBC_SW_RST_N: SBC software reset. SYSTEM_CONFIG17 StandBy controller peripheral reset configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 SBC_RESET_PER_CONF0 Address: SYSCFG_BANK0BaseAddress + 0x00000044 Type: RW Reset: 0xFFFF FFFF Description: Lower 32 peripheral resets control. [31:0] SBC_RESET_PER_CONF0: Soft reset for reset peripherals <31:0>. Bit[0]: Interconnect (always on)Bit[1]: Retime padlogic (always on) Bit[2]: LPM (always on)Bit[3]: Reserved Bit[4]: Ethernet (hard reset)Bit[31:5]: Reserved 384/604 DocID023557 Rev 10 6 5 4 3 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG15 STiH271EL System configuration registers StandBy controller voltage regulator configuration R W R W R W 6 5 R W R W R W SYSCFG_BANK0BaseAddress + 0x00000048 Type: RW Reset: 0x0000 0400 Description: StandBy controller voltage regulator configuration register. 3 R W R W 2 1 0 R W R W R W ti a l Address: 4 [31:13] RESERVED en [11] VREG_REGPDLV: Active high power down for regulator. [10] VREG_PORPULV: Active high POR enable control. fid [9:6] RESERVED [5] VREG_ILVDMPDLV: Active high, power-down for VPLUSM input supply LVD. [4:1] RESERVED on [0] VREG_BGPDLV: Active high, power-down for voltage reference. C Confidential [12] VREG_MLVDPDLV: Active high power down for 3.3 V input supply Low Voltage Detector (LVD). DocID023557 Rev 10 385/604 Information classified Confidential - Do not copy (See last page for obligations) VREG_PORPULV R W 7 VREG_BGPDLV VREG_REGPDLV R W 8 RESERVED VREG_MLVDPDLV R 9 VREG_ILVDMPDLV RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SYSTEM_CONFIG18 System configuration registers STiH271EL Low power monitor configuration register 2 1 0 R W R W R W R W R W R W l LPM_XP70_RUNNING 3 SBC_LPM_SW_RST_N_MASK 4 XP70_DMA_TRANSFER_PRIORITY 5 XP70_IDLE_ACK 6 ISOLATION_DISABLE 7 MISSION_PS_ENABLE 8 R SYSCFG_BANK0BaseAddress + 0x0000004C Type: RW Reset: 0x0000 0030 Description: Low power monitor configuration register. en ti a Address: Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:6] RESERVED fid [5] MISSION_PS_ENABLE: 0: Regulator is turned off 1: Regulator is enabled and SoC powered. on [4] ISOLATION_DISABLE: 0: Isolation enable 1: Isolation disable [3] XP70_IDLE_ACK: Acknowledge signal for IDLE request generated by the XP70. C [2] XP70_DMA_TRANSFER_PRIORITY: This signal is used by the XP70 to give a higher priority to the DMA transfer over XP70 memory accesses. 0: Higher priority will be given to access by XP70 1: Higher priority is given to the DMA transfer [1] LPM_XP70_RUNNING: Low power monitor CPU XP70 is running. [0] SBC_LPM_SW_RST_N_MASK: Low power monitor software reset mask. 386/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG19 STiH271EL System configuration registers Cross trigger PIO not system configuration 7 6 5 4 3 2 1 0 CROSS_TRIGGER_PIO_NSTAC 8 RESERVED 9 R R W SYSCFG_BANK0BaseAddress + 0x00000050 Type: RW Reset: 0x0000 0000 Description: Cross trigger PIO not system configuration. en ti a l Address: [31:1] RESERVED fid [0] CROSS_TRIGGER_PIO_NSTAC: 0: Reserved 1: LPM-XP70 trigger_in/trigger_out are connected to PIOs on SYSTEM_CONFIG21 Front panel reset control configuration 6 5 4 3 2 1 0 FP_RESET_CTRL_SENSE 7 FP_RESET_CTRL_ENABLE 8 FP_RESET_CTRL_CLEAR_FLAG 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W R W R W Address: SYSCFG_BANK0BaseAddress + 0x00000054 Type: RW Reset: 0x0000 0001 Description: Front panel reset control configuration register. [31:3] RESERVED [2] FP_RESET_CTRL_CLEAR_FLAG: Front panel reset clear flag control. DocID023557 Rev 10 387/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG20 System configuration registers STiH271EL [1] FP_RESET_CTRL_ENABLE: Front panel reset enable control. [0] FP_RESET_CTRL_SENSE: Front panel reset sense control. Compensation digital 1 configuration COMP_DIG1_FREEZE COMP_DIG1_COMPTQ COMP_DIG1_COMPEN R W R W R W R W R W R W R W R W R W R W ti a l COMP_DIG1_RASRC0 0 COMP_DIG1_RASRC1 1 COMP_DIG1_RASRC2 2 COMP_DIG1_RASRC3 3 R W Type: RW Reset: 0x0000 0000 Description: Compensation digital 1 configuration register. en SYSCFG_BANK0BaseAddress + 0x00000058 fid [31:11] RESERVED [10] COMP_DIG1_TQ: 0: Normal mode 1: To enable IDDQ mode on [9] COMP_DIG1_RASRC6: Seventh bit of the digital input code. [8] COMP_DIG1_RASRC5: Sixth bit of the digital input code. [7] COMP_DIG1_RASRC4: Fifth bit of the digital input code. [6] COMP_DIG1_RASRC3: Fourth bit of the digital input code. C [5] COMP_DIG1_RASRC2: Third bit of the digital input code. [4] COMP_DIG1_RASRC1: Second bit of the digital input code. [3] COMP_DIG1_RASRC0: First bit of the digital input code. [2] COMP_DIG1_FREEZE: To enable freeze mode. [1] COMP_DIG1_COMPTQ: To select operation mode. Use this bit with bit[0]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode [0] COMP_DIG1_COMPEN: To select operation mode. Use this bit with bit[1]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode 388/604 4 COMP_DIG1_RASRC4 5 COMP_DIG1_RASRC5 6 COMP_DIG1_RASRC6 7 COMP_DIG1_TQ 8 R Address: Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG22 STiH271EL System configuration registers Ethernet configuration register RW Reset: 0x0000 0040 Description: Ethernet configuration register. RESERVED ETH_POWERDOWN_REQ 0 ETH_MII_PHY_SEL 1 ETH_ENMII 2 RESERVED 3 R W R W R W R W R W RW R R W on [9] ETH_GMAC_EN: 0: Soft reset 1: GMAC_EN 4 fid [31:10] RESERVED 5 [8] ETH_SEL_TX_RETIMING_CLK: Selection of the clock used to retime TX data. 0: Clock selected by ETH_SEL_TXCLK_NOT_CLK125 bit 1: Clock fed to or provided by ETH_PHYCLK depending on the ETH_SEL_INTERNAL_NOTEXT_PHYCLK bit setting [7] ETH_SEL_INTERNAL_NOTEXT_PHYCLK: Selection of internal clock or external clock from ETH_PHYCLK for retiming in the RMII mode. 0: External clock (beware that ETH1_SEL_TX_RETIMING_CLK bit must also be programmed). 1: Internal clock (from ClockGenA) [6] RESERVED [5] ETH_ENMII: 0: Reverse MII mode 1: MII mode [4:2] ETH_MII_PHY_SEL: 000: MII (default) 001: Reserved 010: Reserved 100: RMII [1] RESERVED [0] ETH_POWERDOWN_REQ: Ethernet power down request. DocID023557 Rev 10 389/604 Information classified Confidential - Do not copy (See last page for obligations) Type: 6 ETH_SEL_INTERNAL_NOTEXT_PHYCLK ti a SYSCFG_BANK0BaseAddress + 0x0000005C 7 en Address: 8 C Confidential R 9 ETH_GMAC_EN l RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ETH_SEL_TX_RETIMING_CLK SYSTEM_CONFIG23 System configuration registers STiH271EL SYSTEM_STATUS27 StandBy controller acg_glue_bist status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED 5 4 3 2 1 0 ACG_BIST_COUNT Address: SYSCFG_BANK0BaseAddress + 0x0000006C Type: R Reset: 0x0000 0000 Description: Status of ACG PLL BIST. ti a l [7:0] ACG_BIST_COUNT: ACG bist counter result. SYSTEM_STATUS28 StandBy controller reset observation status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en SYSCFG_BANK0BaseAddress + 0x00000070 Type: R Reset: 0x0000 0000 Description: StandBy controller reset status. fid Address: Address: SYSCFG_BANK0BaseAddress + 0x00000074 Type: R Reset: 0x0000 0000 Description: StandBy controller voltage regulator status register. 3 2 [31:9] RESERVED [8] XP70_OCE_GPO: This bit is set to 1 when the STxP70 core is in the debug mode. [7] XP70_IDLE_REQ: 0: XP70 is not in the idle mode. 1: XP70 is in the idle mode. 390/604 DocID023557 Rev 10 1 0 RESERVED 4 VREG_DLVDBOKLV 5 VREG_ILVDMOKLV 6 VREG_POR2LV 7 VREG_PUPLV_N 8 RESERVED 9 XP70_HREST_NO RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 XP70_IDLE_REQ StandBy controller voltage regulator status XP70_OCE_GPO SYSTEM_STATUS29 on [31:0] SBC_RESET_STATUS: Observation of internal reset sources. C Confidential SBC_RESET_STATUS Information classified Confidential - Do not copy (See last page for obligations) [31:8] RESERVED STiH271EL System configuration registers [6] XP70_HREST_NO: Reset out signal from XP70. This indicates that XP70 is out of reset and is ready to execute code. [5] RESERVED [4] VREG_POR2LV: Active high signal, indicating that ILVDMOKLV, ILVDBOKLV, DLVDMOKLV, and DLVDBOKLV outputs are high. [3] VREG_PUPLV_N: Active high signal, indicates that both input and output are up. [2] VREG_ILVDMOKLV: Active high, indicates that the VPLUSM supply has stabilized. [1] RESERVED ACG status register SYSCFG_BANK0BaseAddress + 0x00000078 Type: R Reset: 0x0000 0000 Description: ACG status register. 1 0 ACG_ADJ_MIN 2 ACG_ADJ_MAX R 3 ACG_OSC_LOCK R 4 ACG_CALIBRATE 5 SPEC_EXCEED 6 R R R R R on [31:25] RESERVED 7 fid Address: 8 THERM_CODE BINARY_CODE R ti a OSCIOK_32KHZ R en RESERVED R 9 [24] OSCIOK_32KHZ: 32 kHz oscillator status. Oscillator OK signal. 0: Oscillations not yet stable. 1: Oscillator has stabilized and clock is available on ZI. C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ACG_LOCK_RAW l SYSTEM_STATUS30 [23:14] BINARY_CODE: 10 bit bus from which binary code [9:0] can be read. [13:6] THERM_CODE: 8 bit bus from which thermup_code can be read. [5] SPEC_EXCEED: When high, indicates the oscillator clock has exceeded the accuracy specification. [4] ACG_CALIBRATE: 0: The calibration cycle starts and the oscillator produces calibrated frequency after the calibration has been achieved. 1: The oscillator gives default (free running frequency output). [3] ACG_LOCK_RAW: 1: Oscillator free running frequency is within the specified range. [2] ACG_OSC_LOCK: ACG lock signal. [1] ACG_ADJ_MIN: ACG adjust minimum. [0] ACG_ADJ_MAX: ACG adjust maximum. DocID023557 Rev 10 391/604 Information classified Confidential - Do not copy (See last page for obligations) [0] VREG_DLVDBOKLV: Active high, indicates that the VDDB output is stabilized. System configuration registers STiH271EL Front panel reset control status register 9 8 7 6 5 4 3 2 1 0 RESERVED FP_RESET_CTRL_FLAG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_BANK0BaseAddress + 0x0000007C Type: R Reset: 0x0000 0000 Description: Front panel reset control status register. ti a l Address: [31:1] RESERVED Compensation digital 1 status 8 7 RESERVED on Address: SYSCFG_BANK0BaseAddress + 0x00000080 Type: R Reset: 0x0000 0000 Description: Compensation digital 1 status register. [31:8] RESERVED [7] COMP_DIG1_COMP_OK: Compensation OK for digital section 1. [6:0] COMP_DIG1_NASRC: Compensation NASRC for digital section 1. 392/604 DocID023557 Rev 10 6 5 4 3 COMP_DIG1_NASRC 9 fid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMP_DIG1_COMP_OK en SYSTEM_STATUS32 C Confidential [0] FP_RESET_CTRL_FLAG: Front panel reset flag control. 2 1 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_STATUS31 STiH271EL System configuration registers Ethernet status 5 4 3 2 1 0 ETH_MAC_SPEED 6 ETH_POWERDOWN_ACK 7 ETH_SBD_PWR_DOWN_ACK 8 R R R R SYSCFG_BANK0BaseAddress + 0x00000084 Type: R Reset: 0x0000 0000 Description: Ethernet status register. en ti a l Address: [31:4] RESERVED [3] ETH_SBD_PWR_DOWN_ACK: Acknowledge to indicate start of power down sequence. fid [2] ETH_POWERDOWN_ACK: Power down acknowledge. SoC voltage control OK 9 8 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address: SYSCFG_BANK0BaseAddress + 0x00000088 Type: R Reset: 0x0000 0000 Description: SoC voltage control OK. 7 6 5 4 3 2 1 0 NRST1_DATA_IN SYSTEM_STATUS34 on [1:0] ETH_MAC_SPEED: Indicates the operating speed. 10: 10 Mbit/s 11: 100 Mbit/s C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:1] RESERVED [0] NRST1_DATA_IN: Status of the POR for the switch able SoC area DocID023557 Rev 10 393/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_STATUS33 System configuration registers STiH271EL Oscillator 32 kHz configuration 7 6 5 4 3 2 1 0 OSCI32KHZ_ENABLE 8 R R W SYSCFG_BANK0BaseAddress + 0x00000094 Type: RW Reset: 0x0000 0001 Description: 32 kHz oscillator configuration. en ti a l Address: [31:1] RESERVED [0] OSCI32KHZ_ENABLE: 0: 32 kHz oscillator core is disabled 1: 32 kHz oscillator core is enabled fid SYSTEM_CONFIG38 Voltage regulator DLVDPDLV 8 6 5 4 3 2 1 0 R R W Address: SYSCFG_BANK0BaseAddress + 0x00000098 Type: RW Reset: 0x0000 0000 Description: Voltage regulator. [31:1] RESERVED [0] VREG_DLVDPDLV: Power down for 1.1 V output LVD, active high. 394/604 7 VREG_DLVDPDLV 9 RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG37 STiH271EL System configuration registers SYSTEM_STATUS40 Mode pins status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RESERVED 6 5 4 3 2 1 0 MODEPINS_STATUS Address: SYSCFG_BANK0BaseAddress + 0x000000A0 Type: R Reset: 0x0000 0000 Description: Value of mode pins. DEVICE_ID en 9 8 7 6 5 4 3 2 1 0 fid GROUP_ID VERSION SYSCFG_BANK0BaseAddress + 0x000000A4 Type: R Reset: 0x0000 0000 Description: JTAG device ID. on Address: [31:28] VERSION: STiH271EL device ID. C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Device ID JTAG_BIT SYSTEM_STATUS41 MANUFACTURER_ID ti a l [9:0] MODEPINS_STATUS: Value of mode pins. [27:22] GROUP_ID: STiH271EL device ID. [21:12] DEVICE_ID: STiH271EL device ID. [11:1] MANUFACTURER_ID: STiH271EL device ID. [0] JTAG_BIT: STiH271EL device ID. DocID023557 Rev 10 395/604 Information classified Confidential - Do not copy (See last page for obligations) [31:10] RESERVED System configuration registers STiH271EL SYSTEM_STATUS42 Mode pin captured at POR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODEPINS_VALUE Address: SYSCFG_BANK0BaseAddress + 0x000000A8 Type: R Reset: 0x0000 0000 Description: Mode pin captured at Power-on-reset. SYSTEM_CONFIG100 Alternate function output control for PIO4 1 R W R R W R R W R RW R R W SYSCFG_BANK1BaseAddress + 0x00000000 Type: RW Reset: 0x0000 0000 Description: PIO4 alternate function output configuration. C on Address: [31:29] RESERVED [28] PIO4_7_SELECTOR: PIO4[7] bit selection according to the PIO4_7_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 [27:25] RESERVED [24] PIO4_6_SELECTOR: PIO4[6] bit selection according to the PIO4_6_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 [23:22] RESERVED [21:20] PIO4_5_SELECTOR: PIO4[5] bit selection according to the PIO4_5_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 10: Alternate function 2 [19:17] RESERVED [16] PIO4_4_SELECTOR: PIO4[4] bit selection according to the PIO4_4_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 396/604 0 PIO4_0_SELECTOR 2 RESERVED 3 PIO4_1_SELECTOR 4 RESERVED 5 PIO4_2_SELECTOR R 6 RESERVED RW 7 PIO4_3_SELECTOR PIO4_5_SELECTOR R 8 RESERVED RESERVED R W en PIO4_6_SELECTOR R 9 PIO4_4_SELECTOR RESERVED R W RESERVED PIO4_7_SELECTOR R fid RESERVED Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Bank 1 registers descriptions ti a 19.3 l [31:0] MODEPINS_VALUE: Mode pins value captured at power-on-reset. STiH271EL System configuration registers [15:13] RESERVED [12] PIO4_3_SELECTOR: PIO4[3] bit selection according to the PIO4_3_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 [11:9] RESERVED [8] PIO4_2_SELECTOR: PIO4[2] bit selection according to the PIO4_2_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 [7:6] RESERVED [3:1] RESERVED ti a l [0] PIO4_0_SELECTOR: PIO4[0] bit selection according to the PIO4_0_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 Alternate function output control for PIO5 en SYSTEM_CONFIG101 1 PIO5_0_SELECTOR 2 RESERVED 3 PIO5_1_SELECTOR 4 RESERVED R 5 PIO5_2_SELECTOR RW 6 RESERVED PIO5_5_SELECTOR R 7 PIO5_3_SELECTOR RESERVED RW 8 RESERVED PIO5_6_SELECTOR R 9 PIO5_4_SELECTOR RESERVED RW RESERVED PIO5_7_SELECTOR R RW R RW R RW R RW R RW fid RESERVED SYSCFG_BANK1BaseAddress + 0x00000004 Type: RW Reset: 0x0000 0000 Description: PIO5 alternate function output configuration. on Address: 0 C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31] RESERVED [30:28] PIO5_7_SELECTOR: PIO5[7] bit selection according to the PIO5_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 [27] RESERVED [26:24] PIO5_6_SELECTOR: PIO5[6] bit selection according to the PIO5_6_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 [23] RESERVED [22:20] PIO5_5_SELECTOR: PIO5[5] bit selection according to the PIO5_5_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 [19] RESERVED DocID023557 Rev 10 397/604 Information classified Confidential - Do not copy (See last page for obligations) [5:4] PIO4_1_SELECTOR: PIO4[1] bit selection according to the PIO4_1_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 10: Alternate function 2 System configuration registers STiH271EL [18:16] PIO5_4_SELECTOR: PIO5[4] bit selection according to the PIO5_4_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [15] RESERVED [14:12] PIO5_3_SELECTOR: PIO5[3] bit selection according to the PIO5_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [11] RESERVED l [7] RESERVED ti a [6:4] PIO5_1_SELECTOR: PIO5[1] bit selection according to the PIO5_1_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 SYSTEM_CONFIG102 fid en [2:0] PIO5_0_SELECTOR: PIO5[0] bit selection according to the PIO5_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 Alternate function output control for PIO6 RESERVED PIO6_0_SELECTOR 1 PIO6_1_SELECTOR 2 RESERVED 3 PIO6_2_SELECTOR 4 RESERVED 5 PIO6_3_SELECTOR RW 6 RESERVED R 7 PIO6_4_SELECTOR RW 8 RESERVED RESERVED R PIO6_5_SELECTOR PIO6_6_SELECTOR RW on RESERVED R 9 R RW R RW R RW R RW R RW C PIO6_7_SELECTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Confidential [3] RESERVED Address: SYSCFG_BANK1BaseAddress + 0x00000008 Type: RW Reset: 0x0000 0000 Description: PIO6 alternate function output configuration. [31] RESERVED [30:28] PIO6_7_SELECTOR: PIO6[7] bit selection according to the PIO6_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 [27] RESERVED [26:24] PIO6_6_SELECTOR: PIO6[6] bit selection according to the PIO6_6_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 [23] RESERVED 398/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [10:8] PIO5_2_SELECTOR: PIO5[2] bit selection according to the PIO5_2_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 STiH271EL System configuration registers [22:20] PIO6_5_SELECTOR: PIO6[5] bit selection according to the PIO6_5_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 [19] RESERVED [18:16] PIO6_4_SELECTOR: PIO6[4] bit selection according to the PIO6_4_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 [15] RESERVED l [11] RESERVED ti a [10:8] PIO6_2_SELECTOR: PIO6[2] bit selection according to the PIO6_2_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 en [5:4] PIO6_1_SELECTOR: PIO6[1] bit selection according to the PIO6_1_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 10: Alternate function 2 fid [3] RESERVED SYSTEM_CONFIG103 on [2:0] PIO6_0_SELECTOR: PIO6[0] bit selection according to the PIO6_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 Alternate function output control for PIO7 RESERVED PIO7_0_SELECTOR 1 PIO7_1_SELECTOR 2 RESERVED 3 PIO7_2_SELECTOR 4 RESERVED 5 PIO7_3_SELECTOR 6 RESERVED R 7 PIO7_4_SELECTOR RW 8 RESERVED R 9 PIO7_5_SELECTOR PIO7_6_SELECTOR RW RESERVED RESERVED R C PIO7_7_SELECTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Confidential [7:6] RESERVED RW R RW R RW R RW R RW R RW Address: SYSCFG_BANK1BaseAddress + 0x0000000C Type: RW Reset: 0x0000 0000 Description: PIO7 alternate function output configuration. 0 [31] RESERVED [30:28] PIO7_7_SELECTOR: PIO7[7] bit selection according to the PIO7_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 DocID023557 Rev 10 399/604 Information classified Confidential - Do not copy (See last page for obligations) [14:12] PIO6_3_SELECTOR: PIO6[3] bit selection according to the PIO6_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 System configuration registers STiH271EL [27] RESERVED [26:24] PIO7_6_SELECTOR: PIO7[6] bit selection according to the PIO7_6_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 [23] RESERVED [22:20] PIO7_5_SELECTOR: PIO7[5] bit selection according to the PIO7_5_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 ti a l [17:16] PIO7_4_SELECTOR: PIO7[4] bit selection according to the PIO7_4_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 11: Alternate function 3 [15] RESERVED en [14:12] PIO7_3_SELECTOR: PIO7[3] bit selection according to the PIO7_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 Confidential [11] RESERVED fid [10:8] PIO7_2_SELECTOR: PIO7[2] bit selection according to the PIO7_2_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 [7] RESERVED [3] RESERVED on [6:4] PIO7_1_SELECTOR: PIO7[1] bit selection according to the PIO7_1_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 C [2:0] PIO7_0_SELECTOR: PIO7[0] bit selection according to the PIO7_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 SYSTEM_CONFIG104 Alternate function output control for PIO8 PIO8_3_SELECTOR RESERVED PIO8_2_SELECTOR RESERVED PIO8_1_SELECTOR RESERVED PIO8_0_SELECTOR 1 RESERVED 2 PIO8_4_SELECTOR 3 RESERVED 4 PIO8_5_SELECTOR 5 RESERVED 6 PIO8_6_SELECTOR 7 RESERVED 8 PIO8_7_SELECTOR 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R RW R RW R RW R RW R RW R RW R RW R RW Address: SYSCFG_BANK1BaseAddress + 0x00000010 Type: RW Reset: 0x3333 0333 400/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [19:18] RESERVED STiH271EL Description: System configuration registers PIO8 alternate function output configuration. [31] RESERVED [30:28] PIO8_7_SELECTOR: PIO8[7] bit selection according to the PIO8_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 [26:24] PIO8_6_SELECTOR: PIO8[6] bit selection according to the PIO8_6_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 ti a l [23] RESERVED en [22:20] PIO8_5_SELECTOR: PIO8[5] bit selection according to the PIO8_5_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 101: Alternate function 5 fid [17:16] PIO8_4_SELECTOR: PIO8[4] bit selection according to the PIO8_4_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 11: Alternate function 3 [15] RESERVED [11:10] RESERVED on [14:12] PIO8_3_SELECTOR: PIO8[3] bit selection according to the PIO8_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 [9:8] PIO8_2_SELECTOR: PIO8[2] bit selection according to the PIO8_2_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 11: Alternate function 3 C Confidential [19:18] RESERVED [7:6] RESERVED [5:4] PIO8_1_SELECTOR: PIO8[1] bit selection according to the PIO8_1_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 11: Alternate function 3 [3] RESERVED [2:0] PIO8_0_SELECTOR: PIO8[0] bit selection according to the PIO8_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 DocID023557 Rev 10 401/604 Information classified Confidential - Do not copy (See last page for obligations) [27] RESERVED System configuration registers STiH271EL Alternate function output control for PIO9 PIO9_3_SELECTOR RESERVED PIO9_2_SELECTOR RESERVED PIO9_1_SELECTOR RESERVED PIO9_0_SELECTOR 1 RESERVED 2 PIO9_4_SELECTOR 3 RESERVED 4 PIO9_5_SELECTOR 5 RESERVED 6 PIO9_6_SELECTOR 7 RESERVED 8 PIO9_7_SELECTOR 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R RW R RW R RW R RW R RW R RW R RW R RW SYSCFG_BANK1BaseAddress + 0x00000014 Type: RW Reset: 0x0000 3330 Description: PIO9 alternate function output configuration. ti a l Address: [31:30] RESERVED en Confidential [29:28] PIO9_7_SELECTOR: PIO9[7] bit selection according to the PIO9_7_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 10: Alternate function 2 [27:26] RESERVED fid [25:24] PIO9_6_SELECTOR: PIO9[6] bit selection according to the PIO9_6_SELECTOR[1:0] value 00: PIO general-purpose function 01: Alternate function 1 10: Alternate function 2 on [23] RESERVED [22:20] PIO9_5_SELECTOR: PIO9[5] bit selection according to the PIO9_5_SELECTOR[2:0] value 000: PIO general-purpose function 010: Alternate function 2 100: Alternate function 4 C [19] RESERVED [18:16] PIO9_4_SELECTOR: PIO9[4] bit selection according to the PIO9_4_SELECTOR[2:0] value 000: PIO general-purpose function 010: Alternate function 2 100: Alternate function 4 [15] RESERVED [14:12] PIO9_3_SELECTOR: PIO9[3] bit selection according to the PIO9_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 [11] RESERVED [10:8] PIO9_2_SELECTOR: PIO9[2] bit selection according to the PIO9_2_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 [7] RESERVED 402/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG105 STiH271EL System configuration registers [6:4] PIO9_1_SELECTOR: PIO9[1] bit selection according to the PIO9_1_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 [3] RESERVED [2:0] PIO9_0_SELECTOR: PIO9[0] bit selection according to the PIO9_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 Alternate function output control for PIO10 SYSCFG_BANK1BaseAddress + 0x00000018 Type: RW Reset: 0x3300 0000 Description: PIO10 alternate function output configuration. 1 R RW R RW R RW 0 on [31] RESERVED 2 fid Address: 3 PIO10_0_SELECTOR RW 4 RESERVED RESERVED R 5 PIO10_1_SELECTOR PIO10_4_SELECTOR RW 6 RESERVED RESERVED R 7 PIO10_2_SELECTOR PIO10_5_SELECTOR RW l RESERVED R 8 RESERVED PIO10_6_SELECTOR RW PIO10_3_SELECTOR RESERVED R ti a PIO10_7_SELECTOR RW en RESERVED R 9 [30:28] PIO10_7_SELECTOR: PIO10[7] bit selection according to the PIO10_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [27] RESERVED [26:24] PIO10_6_SELECTOR: PIO10[6] bit selection according to the PIO10_6_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 [23] RESERVED [22:20] PIO10_5_SELECTOR: PIO10[5] bit selection according to the PIO10_5_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [19] RESERVED [18:16] PIO10_4_SELECTOR: PIO10[4] bit selection according to the PIO10_4_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 100: Alternate function 4 [15] RESERVED DocID023557 Rev 10 403/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG106 System configuration registers STiH271EL [14:12] PIO10_3_SELECTOR: PIO10[3] bit selection according to the PIO10_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 [11] RESERVED [10:8] PIO10_2_SELECTOR: PIO10[2] bit selection according to the PIO10_2_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 ti a l [6:4] PIO10_1_SELECTOR: PIO10[1] bit selection according to the PIO10_1_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 [3] RESERVED en Alternate function output control for PIO11 fid SYSTEM_CONFIG107 RESERVED PIO11_0_SELECTOR 1 PIO11_1_SELECTOR 2 RESERVED 3 PIO11_2_SELECTOR 4 RESERVED 5 PIO11_3_SELECTOR RW 6 RESERVED R 7 PIO11_4_SELECTOR RW 8 RESERVED RESERVED R PIO11_5_SELECTOR PIO11_6_SELECTOR RW on RESERVED R 9 R RW R RW R RW R RW R RW C PIO11_7_SELECTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Confidential [2:0] PIO10_0_SELECTOR: PIO10[0] bit selection according to the PIO10_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 101: Alternate function 5 Address: SYSCFG_BANK1BaseAddress + 0x0000001C Type: RW Reset: 0x0000 0000 Description: PIO11 alternate function output configuration. [31] RESERVED [30:28] PIO11_7_SELECTOR: PIO11[7] bit selection according to the PIO11_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 101: Alternate function 5 110: Alternate function 6 [27] RESERVED [26:24] PIO11_6_SELECTOR: PIO11[6] bit selection according to the PIO11_6_SELECTOR[2:0] value 000: PIO general-purpose function 101: Alternate function 5 110: Alternate function 6 404/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [7] RESERVED STiH271EL System configuration registers [23] RESERVED [22:20] PIO11_5_SELECTOR: PIO11[5] bit selection according to the PIO11_5_SELECTOR[2:0] value 000: PIO general-purpose function 101: Alternate function 5 110: Alternate function 6 [19] RESERVED [18:16] PIO11_4_SELECTOR: PIO11[4] bit selection according to the PIO11_4_SELECTOR[2:0] value 000: PIO general-purpose function 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 ti a l [14:12] PIO11_3_SELECTOR: PIO11[3] bit selection according to the PIO11_3_SELECTOR[2:0] value 000: PIO general-purpose function 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 en [10:8] PIO11_2_SELECTOR: PIO11[2] bit selection according to the PIO11_2_SELECTOR[2:0] value 000: PIO general-purpose function 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 fid [7] RESERVED [3] RESERVED on [6:4] PIO11_1_SELECTOR: PIO11[1] bit selection according to the PIO11_1_SELECTOR[2:0] value 000: PIO general-purpose function 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [2:0] PIO11_0_SELECTOR: PIO11[0] bit selection according to the PIO11_0_SELECTOR[2:0] value 000: PIO general-purpose function 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 C Confidential [11] RESERVED DocID023557 Rev 10 405/604 Information classified Confidential - Do not copy (See last page for obligations) [15] RESERVED System configuration registers STiH271EL Alternate function output control for PIO12 PIO12_3_SELECTOR RESERVED PIO12_2_SELECTOR RESERVED PIO12_1_SELECTOR RESERVED PIO12_0_SELECTOR 1 RESERVED 2 PIO12_4_SELECTOR 3 RESERVED 4 PIO12_5_SELECTOR 5 RESERVED 6 PIO12_6_SELECTOR 7 RESERVED 8 PIO12_7_SELECTOR 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R RW R RW R RW R RW R RW R R W R RW R RW SYSCFG_BANK1BaseAddress + 0x00000020 Type: RW Reset: 0x1111 1100 Description: PIO12 alternate function output configuration. ti a l Address: 0 en [31] RESERVED fid Confidential [30:28] PIO12_7_SELECTOR: PIO12[7] bit selection according to the PIO12_7_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [27] RESERVED [23] RESERVED on [26:24] PIO12_6_SELECTOR: PIO12[6] bit selection according to the PIO12_6_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 C [22:20] PIO12_5_SELECTOR: PIO12[5] bit selection according to the PIO12_5_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [19] RESERVED [18:16] PIO12_4_SELECTOR: PIO12[4] bit selection according to the PIO12_4_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [15] RESERVED [14:12] PIO12_3_SELECTOR: PIO12[3] bit selection according to the PIO12_3_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 100: Alternate function 4 [11:9] RESERVED [8] PIO12_2_SELECTOR: PIO12[2] bit selection according to the PIO12_2_SELECTOR[0] value 0: PIO general-purpose function 1: Alternate function 1 [7] RESERVED 406/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG108 STiH271EL System configuration registers [6:4] PIO12_1_SELECTOR: PIO12[1] bit selection according to the PIO12_1_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 110: Alternate function 6 [3] RESERVED 6 5 4 3 2 SYSCFG_PIO4_7_OE SYSCFG_PIO4_6_OE SYSCFG_PIO4_5_OE SYSCFG_PIO4_4_OE SYSCFG_PIO4_3_OE SYSCFG_PIO4_2_OE SYSCFG_BANK1BaseAddress + 0x00000024 Type: RW Reset: 0x0000 0010 Description: Output enable pad control for all PIO alternate functions. 0 on fid Address: 1 SYSCFG_PIO4_0_OE 7 SYSCFG_PIO4_1_OE 8 SYSCFG_PIO5_0_OE SYSCFG_PIO5_2_OE SYSCFG_PIO5_3_OE SYSCFG_PIO5_4_OE ti a SYSCFG_PIO5_5_OE SYSCFG_PIO5_6_OE SYSCFG_PIO5_7_OE SYSCFG_PIO6_0_OE SYSCFG_PIO6_1_OE en SYSCFG_PIO6_2_OE SYSCFG_PIO6_3_OE SYSCFG_PIO6_4_OE SYSCFG_PIO6_5_OE SYSCFG_PIO6_6_OE SYSCFG_PIO6_7_OE SYSCFG_PIO7_0_OE SYSCFG_PIO7_1_OE SYSCFG_PIO7_2_OE SYSCFG_PIO7_3_OE SYSCFG_PIO7_4_OE SYSCFG_PIO7_5_OE SYSCFG_PIO7_6_OE 9 [31] SYSCFG_PIO7_7_OE: PIO7[7] output enable control, active high. [30] SYSCFG_PIO7_6_OE: PIO7[6] output enable control, active high. [29] SYSCFG_PIO7_5_OE: PIO7[5] output enable control, active high. C Confidential SYSCFG_PIO7_7_OE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO5_1_OE Output enable pad control for all PIO alternate functions l SYSTEM_CONFIG109 [28] SYSCFG_PIO7_4_OE: PIO7[4] output enable control, active high. [27] SYSCFG_PIO7_3_OE: PIO7[3] output enable control, active high. [26] SYSCFG_PIO7_2_OE: PIO7[2] output enable control, active high. [25] SYSCFG_PIO7_1_OE: PIO7[1] output enable control, active high. [24] SYSCFG_PIO7_0_OE: PIO7[0] output enable control, active high. [23] SYSCFG_PIO6_7_OE: PIO6[7] output enable control, active high. [22] SYSCFG_PIO6_6_OE: PIO6[6] output enable control, active high. [21] SYSCFG_PIO6_5_OE: PIO6[5] output enable control, active high. [20] SYSCFG_PIO6_4_OE: PIO6[4] output enable control, active high. [19] SYSCFG_PIO6_3_OE: PIO6[3] output enable control, active high. [18] SYSCFG_PIO6_2_OE: PIO6[2] output enable control, active high. [17] SYSCFG_PIO6_1_OE: PIO6[1] output enable control, active high. [16] SYSCFG_PIO6_0_OE: PIO6[0] output enable control, active high. DocID023557 Rev 10 407/604 Information classified Confidential - Do not copy (See last page for obligations) [2:0] PIO12_0_SELECTOR: PIO12[0] bit selection according to the PIO12_0_SELECTOR[2:0] value 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 110: Alternate function 6 System configuration registers STiH271EL [15] SYSCFG_PIO5_7_OE: PIO5[7] output enable control, active high. [14] SYSCFG_PIO5_6_OE: PIO5[6] output enable control, active high. [13] SYSCFG_PIO5_5_OE: PIO5[5] output enable control, active high. [12] SYSCFG_PIO5_4_OE: PIO5[4] output enable control, active high. [11] SYSCFG_PIO5_3_OE: PIO5[3] output enable control, active high. [10] SYSCFG_PIO5_2_OE: PIO5[2] output enable control, active high. [9] SYSCFG_PIO5_1_OE: PIO5[1] output enable control, active high. [8] SYSCFG_PIO5_0_OE: PIO5[0] output enable control, active high. l [6] SYSCFG_PIO4_6_OE: PIO4[6] output enable control, active high. ti a [5] SYSCFG_PIO4_5_OE: PIO4[5] output enable control, active high. [4] SYSCFG_PIO4_4_OE: PIO4[4] output enable control, active high. [3] SYSCFG_PIO4_3_OE: PIO4[3] output enable control, active high. en [2] SYSCFG_PIO4_2_OE: PIO4[2] output enable control, active high. [0] SYSCFG_PIO4_0_OE: PIO4[0] output enable control, active high. 9 8 7 6 5 4 3 2 1 0 SYSCFG_PIO9_0_OE SYSCFG_PIO8_7_OE SYSCFG_PIO8_6_OE SYSCFG_PIO8_5_OE SYSCFG_PIO8_4_OE SYSCFG_PIO8_3_OE SYSCFG_PIO8_2_OE SYSCFG_PIO8_1_OE SYSCFG_PIO8_0_OE SYSCFG_PIO9_2_OE SYSCFG_PIO9_3_OE SYSCFG_PIO9_4_OE SYSCFG_PIO9_5_OE SYSCFG_PIO9_6_OE SYSCFG_PIO9_7_OE SYSCFG_PIO10_0_OE SYSCFG_PIO10_1_OE SYSCFG_PIO10_2_OE SYSCFG_PIO10_3_OE SYSCFG_PIO10_4_OE on SYSCFG_PIO10_5_OE SYSCFG_PIO10_6_OE SYSCFG_PIO11_0_OE SYSCFG_PIO10_7_OE C SYSCFG_PIO11_1_OE SYSCFG_PIO11_2_OE SYSCFG_PIO11_3_OE SYSCFG_PIO11_4_OE SYSCFG_PIO11_5_OE SYSCFG_PIO11_6_OE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO9_1_OE Output enable pad control for all PIO alternate functions fid SYSTEM_CONFIG110 SYSCFG_PIO11_7_OE Confidential [1] SYSCFG_PIO4_1_OE: PIO4[1] output enable control, active high. Address: SYSCFG_BANK1BaseAddress + 0x00000028 Type: RW Reset: 0x0000 0200 Description: Output enable pad control for all PIO alternate functions. [31] SYSCFG_PIO11_7_OE: PIO11[7] output enable control, active high. [30] SYSCFG_PIO11_6_OE: PIO11[6] output enable control, active high. [29] SYSCFG_PIO11_5_OE: PIO11[5] output enable control, active high. [28] SYSCFG_PIO11_4_OE: PIO11[4] output enable control, active high. [27] SYSCFG_PIO11_3_OE: PIO11[3] output enable control, active high. [26] SYSCFG_PIO11_2_OE: PIO11[2] output enable control, active high. [25] SYSCFG_PIO11_1_OE: PIO11[1] output enable control, active high. 408/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7] SYSCFG_PIO4_7_OE: PIO4[7] output enable control, active high. STiH271EL System configuration registers [24] SYSCFG_PIO11_0_OE: PIO11[0] output enable control, active high. [23] SYSCFG_PIO10_7_OE: PIO10[7] output enable control, active high. [22] SYSCFG_PIO10_6_OE: PIO10[6] output enable control, active high. [21] SYSCFG_PIO10_5_OE: PIO10[5] output enable control, active high. [20] SYSCFG_PIO10_4_OE: PIO10[4] output enable control, active high. [19] SYSCFG_PIO10_3_OE: PIO10[3] output enable control, active high. [18] SYSCFG_PIO10_2_OE: PIO10[2] output enable control, active high. [17] SYSCFG_PIO10_1_OE: PIO10[1] output enable control, active high. [16] SYSCFG_PIO10_0_OE: PIO10[0] output enable control, active high. l Information classified Confidential - Do not copy (See last page for obligations) [15] SYSCFG_PIO9_7_OE: PIO9[7] output enable control, active high. ti a [14] SYSCFG_PIO9_6_OE: PIO9[6] output enable control, active high. [13] SYSCFG_PIO9_5_OE: PIO9[5] output enable control, active high. [12] SYSCFG_PIO9_4_OE: PIO9[4] output enable control, active high. en [11] SYSCFG_PIO9_3_OE: PIO9[3] output enable control, active high. [9] SYSCFG_PIO9_1_OE: PIO9[1] output enable control, active high. fid [8] SYSCFG_PIO9_0_OE: PIO9[0] output enable control, active high. [7] SYSCFG_PIO8_7_OE: PIO8[7] output enable control, active high. [6] SYSCFG_PIO8_6_OE: PIO8[6] output enable control, active high. on [5] SYSCFG_PIO8_5_OE: PIO8[5] output enable control, active high. [4] SYSCFG_PIO8_4_OE: PIO8[4] output enable control, active high. [3] SYSCFG_PIO8_3_OE: PIO8[3] output enable control, active high. [2] SYSCFG_PIO8_2_OE: PIO8[2] output enable control, active high. [1] SYSCFG_PIO8_1_OE: PIO8[1] output enable control, active high. C Confidential [10] SYSCFG_PIO9_2_OE: PIO9[2] output enable control, active high. [0] SYSCFG_PIO8_0_OE: PIO8[0] output enable control, active high. DocID023557 Rev 10 409/604 System configuration registers STiH271EL Output enable pad control for all PIO alternate functions SYSCFG_PIO12_0_OE 0 SYSCFG_PIO12_1_OE 1 SYSCFG_PIO12_2_OE 2 SYSCFG_PIO12_3_OE 3 SYSCFG_PIO12_4_OE 4 SYSCFG_PIO12_5_OE 5 R W R W R W R W R W R W R W R W Type: RW Reset: 0x0000 000F Description: Output enable pad control for all PIO alternate functions. en ti a l SYSCFG_BANK1BaseAddress + 0x0000002C [31:8] RESERVED [7] SYSCFG_PIO12_7_OE: PIO12[7] output enable control, active high. fid [6] SYSCFG_PIO12_6_OE: PIO12[6] output enable control, active high. [5] SYSCFG_PIO12_5_OE: PIO12[5] output enable control, active high. [4] SYSCFG_PIO12_4_OE: PIO12[4] output enable control, active high. on [3] SYSCFG_PIO12_3_OE: PIO12[3] output enable control, active high. [2] SYSCFG_PIO12_2_OE: PIO12[2] output enable control, active high. [1] SYSCFG_PIO12_1_OE: PIO12[1] output enable control, active high. C [0] SYSCFG_PIO12_0_OE: PIO12[0] output enable control, active high. 410/604 6 SYSCFG_PIO12_6_OE 7 R Address: Confidential 8 SYSCFG_PIO12_7_OE 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG111 STiH271EL System configuration registers Type: RW Reset: 0x0000 0000 Description: Pull up pad control for all PIO alternate functions. 6 5 4 3 2 SYSCFG_PIO4_7_PU SYSCFG_PIO4_6_PU SYSCFG_PIO4_5_PU SYSCFG_PIO4_4_PU SYSCFG_PIO4_3_PU SYSCFG_PIO4_2_PU 1 0 SYSCFG_PIO4_0_PU 7 SYSCFG_PIO4_1_PU 8 Information classified Confidential - Do not copy (See last page for obligations) SYSCFG_BANK1BaseAddress + 0x00000030 9 ti a l Address: SYSCFG_PIO5_2_PU SYSCFG_PIO5_3_PU SYSCFG_PIO5_4_PU SYSCFG_PIO5_5_PU SYSCFG_PIO5_6_PU SYSCFG_PIO5_7_PU SYSCFG_PIO6_0_PU SYSCFG_PIO6_1_PU SYSCFG_PIO6_2_PU SYSCFG_PIO6_3_PU SYSCFG_PIO6_4_PU SYSCFG_PIO6_5_PU SYSCFG_PIO6_6_PU SYSCFG_PIO6_7_PU SYSCFG_PIO7_0_PU SYSCFG_PIO7_1_PU SYSCFG_PIO7_2_PU SYSCFG_PIO7_3_PU SYSCFG_PIO7_4_PU SYSCFG_PIO7_5_PU SYSCFG_PIO7_6_PU SYSCFG_PIO7_7_PU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO5_0_PU Pull up pad control for all PIO alternate functions SYSCFG_PIO5_1_PU SYSTEM_CONFIG112 [31] SYSCFG_PIO7_7_PU: PIO7[7] pull up control, active high. en [30] SYSCFG_PIO7_6_PU: PIO7[6] pull up control, active high. [28] SYSCFG_PIO7_4_PU: PIO7[4] pull up control, active high. [27] SYSCFG_PIO7_3_PU: PIO7[3] pull up control, active high. fid [26] SYSCFG_PIO7_2_PU: PIO7[2] pull up control, active high. [25] SYSCFG_PIO7_1_PU: PIO7[1] pull up control, active high. [24] SYSCFG_PIO7_0_PU: PIO7[0] pull up control, active high. on [23] SYSCFG_PIO6_7_PU: PIO6[7] pull up control, active high. [22] SYSCFG_PIO6_6_PU: PIO6[6] pull up control, active high. [21] SYSCFG_PIO6_5_PU: PIO6[5] pull up control, active high. [20] SYSCFG_PIO6_4_PU: PIO6[4] pull up control, active high. C Confidential [29] SYSCFG_PIO7_5_PU: PIO7[5] pull up control, active high. [19] SYSCFG_PIO6_3_PU: PIO6[3] pull up control, active high. [18] SYSCFG_PIO6_2_PU: PIO6[2] pull up control, active high. [17] SYSCFG_PIO6_1_PU: PIO6[1] pull up control, active high. [16] SYSCFG_PIO6_0_PU: PIO6[0] pull up control, active high. [15] SYSCFG_PIO5_7_PU: PIO5[7] pull up control, active high. [14] SYSCFG_PIO5_6_PU: PIO5[6] pull up control, active high. [13] SYSCFG_PIO5_5_PU: PIO5[5] pull up control, active high. [12] SYSCFG_PIO5_4_PU: PIO5[4] pull up control, active high. [11] SYSCFG_PIO5_3_PU: PIO5[3] pull up control, active high. [10] SYSCFG_PIO5_2_PU: PIO5[2] pull up control, active high. [9] SYSCFG_PIO5_1_PU: PIO5[1] pull up control, active high. [8] SYSCFG_PIO5_0_PU: PIO5[0] pull up control, active high. [7] SYSCFG_PIO4_7_PU: PIO4[7] pull up control, active high. DocID023557 Rev 10 411/604 System configuration registers STiH271EL [6] SYSCFG_PIO4_6_PU: PIO4[6] pull up control, active high. [5] SYSCFG_PIO4_5_PU: PIO4[5] pull up control, active high. [4] SYSCFG_PIO4_4_PU: PIO4[4] pull up control, active high. [3] SYSCFG_PIO4_3_PU: PIO4[3] pull up control, active high. [2] SYSCFG_PIO4_2_PU: PIO4[2] pull up control, active high. [1] SYSCFG_PIO4_1_PU: PIO4[1] pull up control, active high. [0] SYSCFG_PIO4_0_PU: PIO4[0] pull up control, active high. RW Reset: 0x0000 0000 Description: Pull up pad control for all PIO alternate functions. 7 6 5 4 3 2 1 0 SYSCFG_PIO8_7_PU SYSCFG_PIO8_6_PU SYSCFG_PIO8_5_PU SYSCFG_PIO8_4_PU SYSCFG_PIO8_3_PU SYSCFG_PIO8_2_PU SYSCFG_PIO8_1_PU SYSCFG_PIO8_0_PU on [31] SYSCFG_PIO11_7_PU: PIO11[7] pull up control, active high. [30] SYSCFG_PIO11_6_PU: PIO11[6] pull up control, active high. [29] SYSCFG_PIO11_5_PU: PIO11[5] pull up control, active high. [28] SYSCFG_PIO11_4_PU: PIO11[4] pull up control, active high. [27] SYSCFG_PIO11_3_PU: PIO11[3] pull up control, active high. [26] SYSCFG_PIO11_2_PU: PIO11[2] pull up control, active high. [25] SYSCFG_PIO11_1_PU: PIO11[1] pull up control, active high. [24] SYSCFG_PIO11_0_PU: PIO11[0] pull up control, active high. [23] SYSCFG_PIO10_7_PU: PIO10[7] pull up control, active high. [22] SYSCFG_PIO10_6_PU: PIO10[6] pull up control, active high. [21] SYSCFG_PIO10_5_PU: PIO10[5] pull up control, active high. [20] SYSCFG_PIO10_4_PU: PIO10[4] pull up control, active high. [19] SYSCFG_PIO10_3_PU: PIO10[3] pull up control, active high. [18] SYSCFG_PIO10_2_PU: PIO10[2] pull up control, active high. [17] SYSCFG_PIO10_1_PU: PIO10[1] pull up control, active high. [16] SYSCFG_PIO10_0_PU: PIO10[0] pull up control, active high. [15] SYSCFG_PIO9_7_PU: PIO9[7] pull up control, active high. 412/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Type: 8 fid SYSCFG_BANK1BaseAddress + 0x00000034 SYSCFG_PIO9_2_PU l SYSCFG_PIO9_3_PU SYSCFG_PIO9_4_PU ti a SYSCFG_PIO9_5_PU SYSCFG_PIO9_6_PU SYSCFG_PIO9_7_PU SYSCFG_PIO10_0_PU SYSCFG_PIO10_1_PU en SYSCFG_PIO10_2_PU SYSCFG_PIO10_3_PU SYSCFG_PIO10_4_PU SYSCFG_PIO10_5_PU SYSCFG_PIO10_6_PU SYSCFG_PIO11_0_PU SYSCFG_PIO10_7_PU SYSCFG_PIO11_1_PU SYSCFG_PIO11_2_PU SYSCFG_PIO11_3_PU SYSCFG_PIO11_4_PU SYSCFG_PIO11_5_PU SYSCFG_PIO11_6_PU Address: 9 C Confidential SYSCFG_PIO11_7_PU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO9_0_PU Pull up pad control for all PIO alternate functions SYSCFG_PIO9_1_PU SYSTEM_CONFIG113 STiH271EL System configuration registers [14] SYSCFG_PIO9_6_PU: PIO9[6] pull up control, active high. [13] SYSCFG_PIO9_5_PU: PIO9[5] pull up control, active high. [12] SYSCFG_PIO9_4_PU: PIO9[4] pull up control, active high. [11] SYSCFG_PIO9_3_PU: PIO9[3] pull up control, active high. [10] SYSCFG_PIO9_2_PU: PIO9[2] pull up control, active high. [9] SYSCFG_PIO9_1_PU: PIO9[1] pull up control, active high. [8] SYSCFG_PIO9_0_PU: PIO9[0] pull up control, active high. [7] SYSCFG_PIO8_7_PU: PIO8[7] pull up control, active high. l [5] SYSCFG_PIO8_5_PU: PIO8[5] pull up control, active high. ti a [4] SYSCFG_PIO8_4_PU: PIO8[4] pull up control, active high. [3] SYSCFG_PIO8_3_PU: PIO8[3] pull up control, active high. [2] SYSCFG_PIO8_2_PU: PIO8[2] pull up control, active high. en [1] SYSCFG_PIO8_1_PU: PIO8[1] pull up control, active high. Pull up pad control for all PIO alternate functions fid SYSTEM_CONFIG114 1 0 R R W R W R W R W R W R W R W R W on SYSCFG_PIO12_0_PU 2 SYSCFG_PIO12_1_PU 3 SYSCFG_PIO12_2_PU 4 SYSCFG_PIO12_3_PU 5 SYSCFG_PIO12_4_PU 6 SYSCFG_PIO12_5_PU 7 SYSCFG_PIO12_6_PU 8 SYSCFG_PIO12_7_PU 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential [0] SYSCFG_PIO8_0_PU: PIO8[0] pull up control, active high. Address: SYSCFG_BANK1BaseAddress + 0x00000038 Type: RW Reset: 0x0000 0000 Description: Pull up pad control for all PIO alternate functions. [31:8] RESERVED [7] SYSCFG_PIO12_7_PU: PIO12[7] pull up control, active high. [6] SYSCFG_PIO12_6_PU: PIO12[6] pull up control, active high. [5] SYSCFG_PIO12_5_PU: PIO12[5] pull up control, active high. [4] SYSCFG_PIO12_4_PU: PIO12[4] pull up control, active high. [3] SYSCFG_PIO12_3_PU: PIO12[3] pull up control, active high. [2] SYSCFG_PIO12_2_PU: PIO12[2] pull up control, active high. DocID023557 Rev 10 413/604 Information classified Confidential - Do not copy (See last page for obligations) [6] SYSCFG_PIO8_6_PU: PIO8[6] pull up control, active high. System configuration registers STiH271EL [1] SYSCFG_PIO12_1_PU: PIO12[1] pull up control, active high. [0] SYSCFG_PIO12_0_PU: PIO12[0] pull up control, active high. 6 5 4 3 2 1 0 SYSCFG_BANK1BaseAddress + 0x0000003C Type: RW Reset: 0x0000 0000 Description: Open drain pad control for all PIO alternate functions. SYSCFG_PIO4_6_OD SYSCFG_PIO4_5_OD SYSCFG_PIO4_4_OD SYSCFG_PIO4_3_OD SYSCFG_PIO4_2_OD SYSCFG_PIO4_1_OD SYSCFG_PIO4_0_OD en [31] SYSCFG_PIO7_7_OD: PIO7[7] open drain control, active high. fid [30] SYSCFG_PIO7_6_OD: PIO7[6] open drain control, active high. [29] SYSCFG_PIO7_5_OD: PIO7[5] open drain control, active high. [28] SYSCFG_PIO7_4_OD: PIO7[4] open drain control, active high. on [27] SYSCFG_PIO7_3_OD: PIO7[3] open drain control, active high. [26] SYSCFG_PIO7_2_OD: PIO7[2] open drain control, active high. [25] SYSCFG_PIO7_1_OD: PIO7[1] open drain control, active high. C [24] SYSCFG_PIO7_0_OD: PIO7[0] open drain control, active high. [23] SYSCFG_PIO6_7_OD: PIO6[7] open drain control, active high. [22] SYSCFG_PIO6_6_OD: PIO6[6] open drain control, active high. [21] SYSCFG_PIO6_5_OD: PIO6[5] open drain control, active high. [20] SYSCFG_PIO6_4_OD: PIO6[4] open drain control, active high. [19] SYSCFG_PIO6_3_OD: PIO6[3] open drain control, active high. [18] SYSCFG_PIO6_2_OD: PIO6[2] open drain control, active high. [17] SYSCFG_PIO6_1_OD: PIO6[1] open drain control, active high. [16] SYSCFG_PIO6_0_OD: PIO6[0] open drain control, active high. [15] SYSCFG_PIO5_7_OD: PIO5[7] open drain control, active high. [14] SYSCFG_PIO5_6_OD: PIO5[6] open drain control, active high. [13] SYSCFG_PIO5_5_OD: PIO5[5] open drain control, active high. [12] SYSCFG_PIO5_4_OD: PIO5[4] open drain control, active high. [11] SYSCFG_PIO5_3_OD: PIO5[3] open drain control, active high. 414/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 7 SYSCFG_PIO4_7_OD SYSCFG_PIO5_2_OD SYSCFG_PIO5_3_OD SYSCFG_PIO5_4_OD 8 ti a Address: Confidential 9 l SYSCFG_PIO5_5_OD SYSCFG_PIO5_6_OD SYSCFG_PIO5_7_OD SYSCFG_PIO6_0_OD SYSCFG_PIO6_1_OD SYSCFG_PIO6_2_OD SYSCFG_PIO6_3_OD SYSCFG_PIO6_4_OD SYSCFG_PIO6_5_OD SYSCFG_PIO6_6_OD SYSCFG_PIO6_7_OD SYSCFG_PIO7_0_OD SYSCFG_PIO7_1_OD SYSCFG_PIO7_2_OD SYSCFG_PIO7_3_OD SYSCFG_PIO7_4_OD SYSCFG_PIO7_5_OD SYSCFG_PIO7_6_OD SYSCFG_PIO7_7_OD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO5_0_OD Open drain pad control for all PIO alternate functions SYSCFG_PIO5_1_OD SYSTEM_CONFIG115 STiH271EL System configuration registers [10] SYSCFG_PIO5_2_OD: PIO5[2] open drain control, active high. [9] SYSCFG_PIO5_1_OD: PIO5[1] open drain control, active high. [8] SYSCFG_PIO5_0_OD: PIO5[0] open drain control, active high. [7] SYSCFG_PIO4_7_OD: PIO4[7] open drain control, active high. [6] SYSCFG_PIO4_6_OD: PIO4[6] open drain control, active high. [5] SYSCFG_PIO4_5_OD: PIO4[5] open drain control, active high. [4] SYSCFG_PIO4_4_OD: PIO4[4] open drain control, active high. [3] SYSCFG_PIO4_3_OD: PIO4[3] open drain control, active high. l [1] SYSCFG_PIO4_1_OD: PIO4[1] open drain control, active high. ti a [0] SYSCFG_PIO4_0_OD: PIO4[0] open drain control, active high. SYSCFG_BANK1BaseAddress + 0x00000040 Type: RW Reset: 0x0000 0000 Description: Open drain pad control for all PIO alternate functions. 6 5 4 3 2 SYSCFG_PIO8_7_OD SYSCFG_PIO8_6_OD SYSCFG_PIO8_5_OD SYSCFG_PIO8_4_OD SYSCFG_PIO8_3_OD SYSCFG_PIO8_2_OD 1 0 SYSCFG_PIO8_0_OD 7 SYSCFG_PIO8_1_OD 8 C on Address: 9 SYSCFG_PIO9_0_OD SYSCFG_PIO9_2_OD SYSCFG_PIO9_3_OD SYSCFG_PIO9_4_OD SYSCFG_PIO9_5_OD SYSCFG_PIO9_6_OD SYSCFG_PIO9_7_OD SYSCFG_PIO10_0_OD SYSCFG_PIO10_1_OD SYSCFG_PIO10_2_OD SYSCFG_PIO10_3_OD fid SYSCFG_PIO10_4_OD SYSCFG_PIO10_5_OD SYSCFG_PIO10_6_OD SYSCFG_PIO11_0_OD SYSCFG_PIO10_7_OD SYSCFG_PIO11_1_OD SYSCFG_PIO11_2_OD SYSCFG_PIO11_3_OD SYSCFG_PIO11_4_OD SYSCFG_PIO11_5_OD SYSCFG_PIO11_6_OD SYSCFG_PIO11_7_OD Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYSCFG_PIO9_1_OD Open drain pad control for all PIO alternate functions en SYSTEM_CONFIG116 [31] SYSCFG_PIO11_7_OD: PIO11[7] open drain control, active high. [30] SYSCFG_PIO11_6_OD: PIO11[6] open drain control, active high. [29] SYSCFG_PIO11_5_OD: PIO11[5] open drain control, active high. [28] SYSCFG_PIO11_4_OD: PIO11[4] open drain control, active high. [27] SYSCFG_PIO11_3_OD: PIO11[3] open drain control, active high. [26] SYSCFG_PIO11_2_OD: PIO11[2] open drain control, active high. [25] SYSCFG_PIO11_1_OD: PIO11[1] open drain control, active high. [24] SYSCFG_PIO11_0_OD: PIO11[0] open drain control, active high. [23] SYSCFG_PIO10_7_OD: PIO10[7] open drain control, active high. [22] SYSCFG_PIO10_6_OD: PIO10[6] open drain control, active high. [21] SYSCFG_PIO10_5_OD: PIO10[5] open drain control, active high. [20] SYSCFG_PIO10_4_OD: PIO10[4] open drain control, active high. DocID023557 Rev 10 415/604 Information classified Confidential - Do not copy (See last page for obligations) [2] SYSCFG_PIO4_2_OD: PIO4[2] open drain control, active high. System configuration registers STiH271EL [19] SYSCFG_PIO10_3_OD: PIO10[3] open drain control, active high. [18] SYSCFG_PIO10_2_OD: PIO10[2] open drain control, active high. [17] SYSCFG_PIO10_1_OD: PIO10[1] open drain control, active high. [16] SYSCFG_PIO10_0_OD: PIO10[0] open drain control, active high. [15] SYSCFG_PIO9_7_OD: PIO9[7] open drain control, active high. [14] SYSCFG_PIO9_6_OD: PIO9[6] open drain control, active high. [13] SYSCFG_PIO9_5_OD: PIO9[5] open drain control, active high. [12] SYSCFG_PIO9_4_OD: PIO9[4] open drain control, active high. l [10] SYSCFG_PIO9_2_OD: PIO9[2] open drain control, active high. ti a [9] SYSCFG_PIO9_1_OD: PIO9[1] open drain control, active high. [8] SYSCFG_PIO9_0_OD: PIO9[0] open drain control, active high. [7] SYSCFG_PIO8_7_OD: PIO8[7] open drain control, active high. en [6] SYSCFG_PIO8_6_OD: PIO8[6] open drain control, active high. [4] SYSCFG_PIO8_4_OD: PIO8[4] open drain control, active high. fid [3] SYSCFG_PIO8_3_OD: PIO8[3] open drain control, active high. [2] SYSCFG_PIO8_2_OD: PIO8[2] open drain control, active high. [1] SYSCFG_PIO8_1_OD: PIO8[1] open drain control, active high. SYSTEM_CONFIG117 on [0] SYSCFG_PIO8_0_OD: PIO8[0] open drain control, active high. Open drain pad control for all PIO alternate functions 0 SYSCFG_PIO12_0_OD 1 SYSCFG_PIO12_1_OD 2 SYSCFG_PIO12_2_OD 3 SYSCFG_PIO12_3_OD 4 SYSCFG_PIO12_4_OD 5 SYSCFG_PIO12_5_OD 6 R R W R W R W R W R W R W R W R W Address: SYSCFG_BANK1BaseAddress + 0x00000044 Type: RW Reset: 0x0000 0000 Description: Open drain pad control for all PIO alternate functions. [31:8] RESERVED [7] SYSCFG_PIO12_7_OD: PIO12[7] open drain control, active high. 416/604 7 SYSCFG_PIO12_6_OD 8 SYSCFG_PIO12_7_OD 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential [5] SYSCFG_PIO8_5_OD: PIO8[5] open drain control, active high. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [11] SYSCFG_PIO9_3_OD: PIO9[3] open drain control, active high. STiH271EL System configuration registers [6] SYSCFG_PIO12_6_OD: PIO12[6] open drain control, active high. [5] SYSCFG_PIO12_5_OD: PIO12[5] open drain control, active high. [4] SYSCFG_PIO12_4_OD: PIO12[4] open drain control, active high. [3] SYSCFG_PIO12_3_OD: PIO12[3] open drain control, active high. [2] SYSCFG_PIO12_2_OD: PIO12[2] open drain control, active high. [1] SYSCFG_PIO12_1_OD: PIO12[1] open drain control, active high. [0] SYSCFG_PIO12_0_OD: PIO12[0] open drain control, active high. PIO4 retime configuration register 0 9 8 7 6 5 4 3 2 1 PIO4_CFG_DELAY_0 RESERVED PIO4_CFG_CLK1NOTCLK0 RW RW R RW ti a l PIO4_CFG_DELAY_1 SYSCFG_BANK1BaseAddress + 0x00000048 Type: RW Reset: 0x0000 0000 Description: PIO4 retime configuration register 0. en Address: 0 on fid [31:24] PIO4_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO4_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [7:0] PIO4_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] SYSTEM_CONFIG119 PIO4 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO4_CFG_DOUBLE_EDGE PIO4_CFG_CLKNOTDATA PIO4_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x0000004C Type: RW Reset: 0x0000 0000 Description: PIO4 retime configuration register 1. DocID023557 Rev 10 9 8 7 6 5 4 3 2 1 0 PIO4_CFG_INVERTCLK 417/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG118 System configuration registers STiH271EL [31:24] PIO4_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge [23:16] PIO4_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO4_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed [7:0] PIO4_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted PIO5 retime configuration register 0 RW RW l PIO5_CFG_DELAY_0 9 8 7 6 5 4 3 2 1 RESERVED PIO5_CFG_CLK1NOTCLK0 R RW ti a PIO5_CFG_DELAY_1 SYSCFG_BANK1BaseAddress + 0x00000050 Type: RW Reset: 0x0000 0000 Description: PIO5 retime configuration register 0. 0 fid en Address: on [31:24] PIO5_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO5_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [15:8] RESERVED [7:0] PIO5_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] 418/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG120 STiH271EL System configuration registers PIO5 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO5_CFG_DOUBLE_EDGE PIO5_CFG_CLKNOTDATA 9 8 7 PIO5_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x00000054 Type: RW Reset: 0x0000 0000 Description: PIO5 retime configuration register 1. 6 5 4 3 2 1 0 PIO5_CFG_INVERTCLK l [31:24] PIO5_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge ti a [23:16] PIO5_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO5_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en fid SYSTEM_CONFIG122 PIO6 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO6_CFG_DELAY_1 PIO6_CFG_DELAY_0 RESERVED SYSCFG_BANK1BaseAddress + 0x00000058 Type: RW Reset: 0x0000 0000 Description: PIO6 retime configuration register 0. 8 7 6 5 4 3 2 1 0 PIO6_CFG_CLK1NOTCLK0 on Address: 9 C Confidential [7:0] PIO5_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO6_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO6_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO6_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] DocID023557 Rev 10 419/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG121 System configuration registers STiH271EL PIO6 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO6_CFG_DOUBLE_EDGE PIO6_CFG_CLKNOTDATA PIO6_CFG_RETIME PIO6_CFG_INVERTCLK RW RW RW RW Address: SYSCFG_BANK1BaseAddress + 0x0000005C Type: RW Reset: 0x0000 0000 Description: PIO6 retime configuration register 1. 0 ti a l [31:24] PIO6_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge [23:16] PIO6_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock en [7:0] PIO6_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted fid SYSTEM_CONFIG124 PIO7 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO7_CFG_DELAY_0 RESERVED PIO7_CFG_CLK1NOTCLK0 RW RW R RW 0 on PIO7_CFG_DELAY_1 Address: SYSCFG_BANK1BaseAddress + 0x00000060 Type: RW Reset: 0x0000 0000 Description: PIO7 retime configuration register 0. C Confidential [15:8] PIO6_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed [31:24] PIO7_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO7_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO7_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] 420/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG123 STiH271EL System configuration registers PIO7 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO7_CFG_DOUBLE_EDGE PIO7_CFG_CLKNOTDATA 9 8 7 PIO7_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x00000064 Type: RW Reset: 0x0000 0000 Description: PIO7 retime configuration register 1. 6 5 4 3 2 1 0 PIO7_CFG_INVERTCLK l [31:24] PIO7_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge1: Double edge ti a [23:16] PIO7_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO7_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en fid SYSTEM_CONFIG126 PIO8 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO8_CFG_DELAY_1 PIO8_CFG_DELAY_0 RESERVED PIO8_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK1BaseAddress + 0x00000068 Type: RW Reset: 0x0000 0000 Description: PIO8 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO7_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted1: Input and output clock are inverted [31:24] PIO8_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO8_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO8_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] DocID023557 Rev 10 421/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG125 System configuration registers STiH271EL PIO8 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO8_CFG_DOUBLE_EDGE PIO8_CFG_CLKNOTDATA 9 8 7 PIO8_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x0000006C Type: RW Reset: 0x0000 0000 Description: PIO8 retime configuration register 1. 6 5 4 3 2 1 0 PIO8_CFG_INVERTCLK l [31:24] PIO8_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge ti a [23:16] PIO8_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO8_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en fid SYSTEM_CONFIG128 PIO9 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO9_CFG_DELAY_1 PIO9_CFG_DELAY_0 RESERVED PIO9_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK1BaseAddress + 0x00000070 Type: RW Reset: 0x0000 0000 Description: PIO9 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO8_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO9_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO9_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO9_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] 422/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG127 STiH271EL System configuration registers PIO9 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO9_CFG_DOUBLE_EDGE PIO9_CFG_CLKNOTDATA 9 8 7 PIO9_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x00000074 Type: RW Reset: 0x0000 0000 Description: PIO9 retime configuration register 1. 6 5 4 3 2 1 0 PIO9_CFG_INVERTCLK l [31:24] PIO9_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge ti a [23:16] PIO9_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO9_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en PIO10 retime configuration register 0 fid SYSTEM_CONFIG130 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO10_CFG_DELAY_1 PIO10_CFG_DELAY_0 RESERVED PIO10_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK1BaseAddress + 0x00000078 Type: RW Reset: 0x0000 0000 Description: PIO10 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO9_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO10_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO10_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO10_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] DocID023557 Rev 10 423/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG129 System configuration registers STiH271EL PIO10 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO10_CFG_DOUBLE_EDGE PIO10_CFG_CLKNOTDATA 9 8 7 PIO10_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x0000007C Type: RW Reset: 0x0000 0000 Description: PIO10 retime configuration register 1. 6 5 4 3 2 1 0 PIO10_CFG_INVERTCLK l [31:24] PIO10_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge ti a [23:16] PIO10_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO10_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en fid SYSTEM_CONFIG132 PIO11 retime configuration register 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO11_CFG_DELAY_1 PIO11_CFG_DELAY_0 RESERVED PIO11_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK1BaseAddress + 0x00000080 Type: RW Reset: 0x0000 0000 Description: PIO11 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO10_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO11_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO11_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO11_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] 424/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG131 STiH271EL System configuration registers PIO11 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO11_CFG_DOUBLE_EDGE PIO11_CFG_CLKNOTDATA 9 8 7 PIO11_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x00000084 Type: RW Reset: 0x0000 0000 Description: PIO11 retime configuration register 1. 6 5 4 3 2 1 0 PIO11_CFG_INVERTCLK l [31:24] PIO11_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge 1: Double edge ti a [23:16] PIO11_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO11_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en PIO12 retime configuration register 0 fid SYSTEM_CONFIG134 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO12_CFG_DELAY_1 PIO12_CFG_DELAY_0 RESERVED PIO12_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK1BaseAddress + 0x00000088 Type: RW Reset: 0x0000 0000 Description: PIO12 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO11_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO12_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO12_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO12_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] DocID023557 Rev 10 425/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG133 System configuration registers STiH271EL PIO12 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO12_CFG_DOUBLE_EDGE PIO12_CFG_CLKNOTDATA 9 8 7 PIO12_CFG_RETIME Address: SYSCFG_BANK1BaseAddress + 0x0000008C Type: RW Reset: 0x0000 0000 Description: PIO12 retime configuration register 1. 6 5 4 3 2 1 0 PIO12_CFG_INVERTCLK l [31:24] PIO12_CFG_DOUBLE_EDGE: Configure double edge 0: Single edge1: Double edge ti a [23:16] PIO12_CFG_CLKNOTDATA: Configure data/clock 0: Output retimed data 1: Output clock [15:8] PIO12_CFG_RETIME: Configure data retime 0: Input and output data are not retimed 1: Input and output data are retimed en Comms configuration register SC0_RESET_CFG SC0_DETECT_POL SC0_COND_VCC_ENABLE SEL_CLK_DSS_SC1 R W RW R W R W R W R W Address: SYSCFG_BANK1BaseAddress + 0x00000090 Type: RW Reset: 0x0000 0000 Description: Comms control. 7 6 5 4 3 RESERVED RESERVED R W 8 SEL_SCCLK0_NOT_CLKDSS SC1_COND_VCC_ENABLE R W 9 SEL_CLK_DSS_SC0 SC1_DETECT_POL on C R SC1_RESET_CFG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SEL_SCCLK1_NOT_CLKDSS fid SYSTEM_CONFIG136 RESERVED Confidential [7:0] PIO12_CFG_INVERTCLK: Configure clock inversion 0: Input and output clock are not inverted 1: Input and output clock are inverted R W R W R W RW 2 1 0 [31:19] RESERVED [18] SC1_RESET_CFG [17] SC1_DETECT_POL: Selection of polarity of input signal sc_detect for smartcard1 [16] SC1_COND_VCC_ENABLE: Enable control of smartcard1 VCC upon detection of smartcard removal or insertion [15:14] RESERVED 426/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG135 STiH271EL System configuration registers [13] SC0_RESET_CFG: Reset configuration for sc0_reset_cfg for smartcard0 [12] SC0_DETECT_POL: Selection of polarity of input signal sc_detect for smartcard0 [11] SC0_COND_VCC_ENABLE: Enable control of smartcard0 VCC upon detection of smartcard removal or insertion [10] SEL_CLK_DSS_SC1: Smartcard1 input clock selection to SC1 clockgen [9] SEL_CLK_DSS_SC0: Smartcard0 input clock selection to SC0 clockgen [8] SEL_SCCLK1_NOT_CLKDSS: Smartcard1 clock multiplexing selection [7] SEL_SCCLK0_NOT_CLKDSS: Smartcard0 clock multiplexing selection Temperature sensor 0 configuration Type: RW Reset: 0x0000 0008 Description: Temperature sensor control. 5 4 3 2 1 0 on [31:10] RESERVED 6 RESERVED THSENS0_PDN SYSCFG_BANK1BaseAddress + 0x000000A0 7 fid Address: 8 THSENS0_DCORRECT RESERVED ti a 9 en 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [9] THSENS0_PDN: Power down. 0: Power down mode 1: Normal mode asynchronous C Confidential l SYSTEM_CONFIG140 [8:4] THSENS0_DCORRECT: Digital code to correct systematic offset by addition to the digital output [3:0] RESERVED DocID023557 Rev 10 427/604 Information classified Confidential - Do not copy (See last page for obligations) [6:0] RESERVED System configuration registers STiH271EL Compensation digital 2 configuration COMP_DIG2_RASRC0 COMP_DIG2_FREEZE COMP_DIG2_COMPTQ COMP_DIG2_COMPEN 0 COMP_DIG2_RASRC1 1 COMP_DIG2_RASRC2 2 R W R W R W R W R W R W R W R W R W R W R W Type: RW Reset: 0x0000 0000 Description: Compensation digital 2 configuration. ti a l SYSCFG_BANK1BaseAddress + 0x000000A4 en [31:11] RESERVED [10] COMP_DIG2_TQ: 0: Normal mode 1: To enable IDDQ mode Confidential 3 R Address: fid [9] COMP_DIG2_RASRC6: Seventh bit of the digital input code. [8] COMP_DIG2_RASRC5: Sixth bit of the digital input code. [7] COMP_DIG2_RASRC4: Fifth bit of the digital input code. on [6] COMP_DIG2_RASRC3: Fourth bit of the digital input code. [5] COMP_DIG2_RASRC2: Third bit of the digital input code. [4] COMP_DIG2_RASRC1: Second bit of the digital input code. [3] COMP_DIG2_RASRC0: First bit of the digital input code. C [2] COMP_DIG2_FREEZE: To enable freeze mode. [1] COMP_DIG2_COMPTQ: To select operation mode. Use this bit with bit[0]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode [0] COMP_DIG2_COMPEN: To select operation mode. Use this bit with bit[1]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode 428/604 4 COMP_DIG2_RASRC3 5 COMP_DIG2_RASRC4 6 COMP_DIG2_RASRC5 7 COMP_DIG2_RASRC6 8 COMP_DIG2_TQ 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG141 STiH271EL System configuration registers SYSTEM_CONFIG144 TSIN3 byte clock select 9 8 7 6 5 4 3 2 1 0 SYSCFG_BANK1BaseAddress + 0x000000C0 Type: R Reset: 0x0000 0000 Description: Allows TSIN3 byte clock selection. ti a l Address: en THSENS0_VOBS on THSENS0_DATA 9 fid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 THSENS0_OVERFLOW Temperature sensor 0 status THSENS0_DATAREADY SYSTEM_STATUS148 RESERVED Address: SYSCFG_BANK1BaseAddress + 0x000000C0 Type: R Reset: 0x0000 0000 Description: Allows to read temperature values. 8 7 6 5 4 3 2 1 0 C Confidential [0] TSIN3_BYTECLK_SEL: 0: PIO9[0] 1: PIO6[0] RESERVED [31:1] RESERVED [31:20] RESERVED [19] THSENS0_VOBS [18:11] THSENS0_DATA: Output data [10] THSENS0_DATAREADY: Set to 1 every 32 clock cycles when conversion is over. Valid for 1 clock period, held at 0 as long as the bandgap has not started [9] THSENS0_OVERFLOW: Overflow of digital adder, corresponds to the upper limit of the temperature range after calibration [8:0] RESERVED DocID023557 Rev 10 429/604 Information classified Confidential - Do not copy (See last page for obligations) RESERVED TSIN3_BYTECLK_SEL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 System configuration registers STiH271EL Compensation digital 2 and 3 status 9 8 7 6 5 4 SYSCFG_BANK1BaseAddress + 0x000000C4 Type: R Reset: 0x0000 0000 Description: Compensation status register 2 and 3. 2 1 0 ti a l Address: 3 COMP_DIG2_NASRC RESERVED COMP_DIG2_COMP_OK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:8] RESERVED en [7] COMP_DIG2_COMP_OK: Compensation OK for digital section 2 Cache L2 power down status RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address: SYSCFG_BANK1BaseAddress + 0x000000D0 Type: R Reset: 0x0000 0000 Description: Cache L2 power down grant detection. [31:1] RESERVED [0] L2CACHE_IDLE_MOD: Cache L2 power down grant 430/604 DocID023557 Rev 10 9 8 7 6 5 4 3 2 1 0 L2CACHE_IDLE_MOD fid SYSTEM_STATUS152 C Confidential [6:0] COMP_DIG2_NASRC: Compensation NASRC for digital section 2 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_STATUS149 DDR3SS status register 0 9 8 7 6 5 4 2 RESERVED SYSCFG_BANK1BaseAddress + 0x000000D8 Type: R Reset: 0x0000 0000 Description: DDR3SS status register 0. 0 en ti a l Address: 1 [31:3] RESERVED [2] DDR3SS_PWRDWN_LMI_ONLY_ACK: Power down acknowledge, active low. fid [1] DDR3SS_PCTL_C_ACTIVE: Clock active, active high. on [0] DDR3SS_LPSRCREGF_RESET_END: Reset of the low priority source register file. 0: Normal mode 1: Start reset. A sequence of 0 to 1 will initiate the reset of the low priority source register file. C Confidential 3 DDR3SS_PWRDWN_LMI_ONLY_ACK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 431/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_STATUS154 DDR3SS_PCTL_C_ACTIVE System configuration registers DDR3SS_LPSRCREGF_RESET_END STiH271EL System configuration registers STiH271EL ClockGenA1 PLL0-1 lock status 8 7 6 5 4 3 2 RESERVED SYSCFG_BANK1BaseAddress + 0x000000F0 Type: R Reset: 0x0000 0000 Description: ClockGenA1 lock status register. 0 en ti a l Address: [31:2] RESERVED fid [1] CLKGENA1_PLL1_LOCK_STATUS: ClockGen A1, PLL1 lock status bit. 1: PLL is locked. Cache L2 power down control RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address: SYSCFG_BANK1BaseAddress + 0x00000110 Type: RW Reset: 0x0000 0000 Description: Cache L2 power down request. [31:1] RESERVED [0] L2CACHE_IDLE_REQ: Cache L2 power down request 432/604 DocID023557 Rev 10 9 8 7 6 5 4 3 2 1 0 L2CACHE_IDLE_REQ SYSTEM_CONFIG168 on [0] CLKGENA1_PLL0_LOCK_STATUS: ClockGen A1, PLL0 lock status bit. 1: PLL is locked. C Confidential 1 Information classified Confidential - Do not copy (See last page for obligations) 9 CLKGENA1_PLL1_LOCK_STATUS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLKGENA1_PLL0_LOCK_STATUS SYSTEM_STATUS160 STiH271EL System configuration registers 5 4 3 2 ti a 0 en 1 SYSCFG_BANK1BaseAddress + 0x00000114 Type: RW Reset: 0x0000 0005 Description: DDR3SS configuration register 0. on [2] DDR3SS_PWRDWN_LMI_ONLY_REQ: LMI power-down request, active loq. [1] DDR3SS_MIXER_R_PKT_SIZE_REDUCTION_IF_ERROR_EN: Allows truncation of response packet in case of error on low priority port. 0: Truncation disable 1: Truncation enable [0] DDR3SS_MIXER_BYPASS_HW_EN: Allow the mixer bypass feature. 0: Normal mode 1: Mixer is bypassed DocID023557 Rev 10 433/604 Information classified Confidential - Do not copy (See last page for obligations) 6 DDR3SS_MIXER_BYPASS_HW_EN 7 l 8 fid Address: [31:3] RESERVED 9 C Confidential DDR3SS_CONFIG_REGISTER_0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DDR3SS_MIXER_R_PKT_SIZE_REDUCTION_IF_ERROR_EN DDR3SS configuration register 0 DDR3SS_PWRDWN_LMI_ONLY_REQ SYSTEM_CONFIG169 System configuration registers STiH271EL ST40 boot address 7 6 5 4 3 2 1 0 RESERVED 8 ST40_BOOT_ADDR 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R RW R SYSCFG_BANK1BaseAddress + 0x00000124 Type: RW Reset: 0x0000 0000 Description: ST40 boot address. ti a l Address: [31:29] RESERVED en [28:1] ST40_BOOT_ADDR: ST40 boot address fid SYSTEM_CONFIG175 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 RESERVED RW R SYSCFG_BANK1BaseAddress + 0x0000012C Type: RW Reset: 0x0000 0000 Description: ST231 DMU boot address. on Address: [31:6] ST231_DMU_BOOT_ADDR: ST231 DMU boot address [5:0] RESERVED 434/604 ST231 DMU boot address ST231_DMU_BOOT_ADDR C Confidential [0] RESERVED DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG173 STiH271EL System configuration registers SYSTEM_CONFIG176 ST231 audio boot address 9 8 7 6 5 4 3 2 1 ST231_AUD_BOOT_ADDR RESERVED RW R Address: SYSCFG_BANK1BaseAddress + 0x00000130 Type: RW Reset: 0x0000 0000 Description: ST231 audio boot address. 0 l [31:6] ST231_AUD_BOOT_ADDR: ST231 audio boot address ti a [5:0] RESERVED Bank 2 registers descriptions en 19.4 Alternate function output control for PIO13 1 PIO13_0_SELECTOR 2 RESERVED 3 PIO13_1_SELECTOR 4 RESERVED 5 PIO13_2_SELECTOR 6 RESERVED R 7 PIO13_3_SELECTOR RW 8 RESERVED R 9 PIO13_4_SELECTOR RW RESERVED RESERVED R RW R RW R RW R RW R RW fid PIO13_6_SELECTOR RW PIO13_5_SELECTOR RESERVED R on PIO13_7_SELECTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Address: SYSCFG_BANK2BaseAddress + 0x00000000 Type: RW Reset: 0x1111 1111 Description: PIO13 alternate function output configuration. 0 C Confidential SYSTEM_CONFIG200 [31] RESERVED [30:28] PIO13_7_SELECTOR: PIO13[7] bit selection according to the PIO13_7_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [27] RESERVED [26:24] PIO13_6_SELECTOR: PIO13[6] bit selection according to the PIO13_6_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 DocID023557 Rev 10 435/604 Information classified Confidential - Do not copy (See last page for obligations) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 System configuration registers STiH271EL [23] RESERVED [22:20] PIO13_5_SELECTOR: PIO13[5] bit selection according to the PIO13_5_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 [19] RESERVED l [15] RESERVED en ti a [14:12] PIO13_3_SELECTOR: PIO13[3] bit selection according to the PIO13_3_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 Confidential [11] RESERVED fid [10:8] PIO13_2_SELECTOR: PIO13[2] bit selection according to the PIO13_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [7] RESERVED C on [6:4] PIO13_1_SELECTOR: PIO13[1] bit selection according to the PIO13_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [3] RESERVED [2:0] PIO13_0_SELECTOR: PIO13[0] bit selection according to the PIO13_0_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 436/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [18:16] PIO13_4_SELECTOR: PIO13[4] bit selection according to the PIO13_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 STiH271EL System configuration registers Alternate function output control for PIO14 RESERVED PIO14_3_SELECTOR RESERVED PIO14_2_SELECTOR RESERVED PIO14_1_SELECTOR RESERVED PIO14_0_SELECTOR 1 PIO14_4_SELECTOR 2 RESERVED 3 PIO14_5_SELECTOR 4 RESERVED 5 PIO14_6_SELECTOR 6 RESERVED 7 PIO14_7_SELECTOR 8 R RW R RW R RW R RW R RW R RW R RW R RW SYSCFG_BANK2BaseAddress + 0x00000004 Type: RW Reset: 0x0111 1111 Description: PIO14 alternate function output configuration. 0 ti a l Address: [31] RESERVED en [30:28] PIO14_7_SELECTOR: PIO14[7] bit selection according to the PIO14_7_SELECTOR[2:0] value. 000: PIO general-purpose function 011: Alternate function 3 101: Alternate function 5 fid [27] RESERVED [23] RESERVED on [26:24] PIO14_6_SELECTOR: PIO14[6] bit selection according to the PIO14_6_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 [22:20] PIO14_5_SELECTOR: PIO14[5] bit selection according to the PIO14_5_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [19] RESERVED [18:16] PIO14_4_SELECTOR: PIO14[4] bit selection according to the PIO14_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [15] RESERVED [14:12] PIO14_3_SELECTOR: PIO14[3] bit selection according to the PIO14_3_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 [11] RESERVED DocID023557 Rev 10 437/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG201 System configuration registers STiH271EL [10:8] PIO14_2_SELECTOR: PIO14[2] bit selection according to the PIO14_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3101: Alternate function 5 110: Alternate function 6 [7] RESERVED [6:4] PIO14_1_SELECTOR: PIO14[1] bit selection according to the PIO14_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 ti a l [2:0] PIO14_0_SELECTOR: PIO14[0] bit selection according to the PIO14_0_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 101: Alternate function 5 110: Alternate function 6 en Alternate function output control for PIO15 1 PIO15_0_SELECTOR 2 RESERVED 3 PIO15_1_SELECTOR 4 RESERVED 5 PIO15_2_SELECTOR 6 RESERVED R 7 PIO15_3_SELECTOR RW 8 RESERVED R 9 PIO15_4_SELECTOR RW RESERVED RESERVED R RW R RW R RW R RW R RW fid PIO15_6_SELECTOR RW PIO15_5_SELECTOR RESERVED R on PIO15_7_SELECTOR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Address: SYSCFG_BANK2BaseAddress + 0x00000008 Type: RW Reset: 0x0000 0000 Description: PIO15 alternate function output configuration. C Confidential SYSTEM_CONFIG202 [31] RESERVED [30:28] PIO15_7_SELECTOR: PIO15[7] bit selection according to the PIO15_7_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 [27] RESERVED 438/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [3] RESERVED STiH271EL System configuration registers [26:24] PIO15_6_SELECTOR: PIO15[6] bit selection according to the PIO15_6_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 [22:20] PIO15_5_SELECTOR: PIO15[5] bit selection according to the PIO15_5_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 ti a l [19] RESERVED en [18:16] PIO15_4_SELECTOR: PIO15[4] bit selection according to the PIO15_4_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 110: Alternate function 6 fid [14:12] PIO15_3_SELECTOR: PIO15[3] bit selection according to the PIO15_3_SELECTOR[2:0] value. 000: PIO general-purpose function 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 [11] RESERVED [7] RESERVED on [10:8] PIO15_2_SELECTOR: PIO15[2] bit selection according to the PIO15_2_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 C Confidential [15] RESERVED [6:4] PIO15_1_SELECTOR: PIO15[1] bit selection according to the PIO15_1_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 [3] RESERVED [2:0] PIO15_0_SELECTOR: PIO15[0] bit selection according to the PIO15_0_SELECTOR[2:0] value. 000: PIO general-purpose function 001: Alternate function 1 010: Alternate function 2 011: Alternate function 3 100: Alternate function 4 101: Alternate function 5 DocID023557 Rev 10 439/604 Information classified Confidential - Do not copy (See last page for obligations) [23] RESERVED System configuration registers STiH271EL Output enable pad control for all PIO alternate functions SYSCFG_PIO15_0_OE SYSCFG_PIO14_7_OE SYSCFG_PIO14_6_OE SYSCFG_PIO14_5_OE SYSCFG_PIO14_4_OE SYSCFG_PIO14_3_OE SYSCFG_PIO14_2_OE SYSCFG_PIO14_1_OE SYSCFG_PIO14_0_OE SYSCFG_PIO13_7_OE SYSCFG_PIO13_6_OE SYSCFG_PIO13_5_OE SYSCFG_PIO13_4_OE SYSCFG_PIO13_3_OE SYSCFG_PIO13_2_OE SYSCFG_PIO13_1_OE SYSCFG_PIO13_0_OE 0 SYSCFG_PIO15_1_OE 1 SYSCFG_PIO15_2_OE 2 SYSCFG_PIO15_3_OE 3 SYSCFG_PIO15_4_OE 4 SYSCFG_PIO15_5_OE 5 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Type: RW Reset: 0x0000 2200 Description: Output enable pad control for all PIO alternate functions. en ti a l SYSCFG_BANK2BaseAddress + 0x0000000C [31:24] RESERVED [23] SYSCFG_PIO15_7_OE: PIO15[7] output enable control, active high. fid [22] SYSCFG_PIO15_6_OE: PIO15[6] output enable control, active high. [21] SYSCFG_PIO15_5_OE: PIO15[5] output enable control, active high. [20] SYSCFG_PIO15_4_OE: PIO15[4] output enable control, active high. on [19] SYSCFG_PIO15_3_OE: PIO15[3] output enable control, active high. [18] SYSCFG_PIO15_2_OE: PIO15[2] output enable control, active high. [17] SYSCFG_PIO15_1_OE: PIO15[1] output enable control, active high. [16] SYSCFG_PIO15_0_OE: PIO15[0] output enable control, active high. C [15] SYSCFG_PIO14_7_OE: PIO14[7] output enable control, active high. [14] SYSCFG_PIO14_6_OE: PIO14[6] output enable control, active high. [13] SYSCFG_PIO14_5_OE: PIO14[5] output enable control, active high. [12] SYSCFG_PIO14_4_OE: PIO14[4] output enable control, active high. [11] SYSCFG_PIO14_3_OE: PIO14[3] output enable control, active high. [10] SYSCFG_PIO14_2_OE: PIO14[2] output enable control, active high. [9] SYSCFG_PIO14_1_OE: PIO14[1] output enable control, active high. [8] SYSCFG_PIO14_0_OE: PIO14[0] output enable control, active high. [7] SYSCFG_PIO13_7_OE: PIO13[7] output enable control, active high. [6] SYSCFG_PIO13_6_OE: PIO13[6] output enable control, active high. [5] SYSCFG_PIO13_5_OE: PIO13[5] output enable control, active high. [4] SYSCFG_PIO13_4_OE: PIO13[4] output enable control, active high. [3] SYSCFG_PIO13_3_OE: PIO13[3] output enable control, active high. 440/604 6 SYSCFG_PIO15_6_OE 7 R Address: Confidential 8 SYSCFG_PIO15_7_OE 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG203 STiH271EL System configuration registers [2] SYSCFG_PIO13_2_OE: PIO13[2] output enable control, active high. [1] SYSCFG_PIO13_1_OE: PIO13[1] output enable control, active high. [0] SYSCFG_PIO13_0_OE: PIO13[0] output enable control, active high. Pull up pad control for all PIO alternate functions SYSCFG_BANK2BaseAddress + 0x00000010 Type: RW Reset: 0x0000 0000 Description: Pull up pad control for all PIO alternate functions. R W R W R W R W R W R W R W R W R W R W R W fid en Address: SYSCFG_PIO13_0_PU R W SYSCFG_PIO13_1_PU SYSCFG_PIO14_4_PU R W 0 SYSCFG_PIO13_2_PU SYSCFG_PIO14_5_PU R W 1 SYSCFG_PIO13_3_PU SYSCFG_PIO14_6_PU R W 2 SYSCFG_PIO13_4_PU SYSCFG_PIO14_7_PU R W 3 SYSCFG_PIO13_5_PU SYSCFG_PIO15_0_PU R W 4 SYSCFG_PIO13_6_PU SYSCFG_PIO15_1_PU R W 5 SYSCFG_PIO13_7_PU SYSCFG_PIO15_2_PU R W 6 SYSCFG_PIO14_0_PU SYSCFG_PIO15_3_PU R W 7 SYSCFG_PIO14_1_PU SYSCFG_PIO15_4_PU R W 8 SYSCFG_PIO14_2_PU SYSCFG_PIO15_5_PU R W SYSCFG_PIO14_3_PU SYSCFG_PIO15_6_PU R W l SYSCFG_PIO15_7_PU R W ti a RESERVED R 9 [31:24] RESERVED [23] SYSCFG_PIO15_7_PU: PIO15[7] pull up control, active high. on [22] SYSCFG_PIO15_6_PU: PIO15[6] pull up control, active high. [21] SYSCFG_PIO15_5_PU: PIO15[5] pull up control, active high. [20] SYSCFG_PIO15_4_PU: PIO15[4] pull up control, active high. [19] SYSCFG_PIO15_3_PU: PIO15[3] pull up control, active high. [18] SYSCFG_PIO15_2_PU: PIO15[2] pull up control, active high. C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [17] SYSCFG_PIO15_1_PU: PIO15[1] pull up control, active high. [16] SYSCFG_PIO15_0_PU: PIO15[0] pull up control, active high. [15] SYSCFG_PIO14_7_PU: PIO14[7] pull up control, active high. [14] SYSCFG_PIO14_6_PU: PIO14[6] pull up control, active high. [13] SYSCFG_PIO14_5_PU: PIO14[5] pull up control, active high. [12] SYSCFG_PIO14_4_PU: PIO14[4] pull up control, active high. [11] SYSCFG_PIO14_3_PU: PIO14[3] pull up control, active high. [10] SYSCFG_PIO14_2_PU: PIO14[2] pull up control, active high. [9] SYSCFG_PIO14_1_PU: PIO14[1] pull up control, active high. [8] SYSCFG_PIO14_0_PU: PIO14[0] pull up control, active high. [7] SYSCFG_PIO13_7_PU: PIO13[7] pull up control, active high. [6] SYSCFG_PIO13_6_PU: PIO13[6] pull up control, active high. DocID023557 Rev 10 441/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG204 System configuration registers STiH271EL [5] SYSCFG_PIO13_5_PU: PIO13[5] pull up control, active high. [4] SYSCFG_PIO13_4_PU: PIO13[4] pull up control, active high. [3] SYSCFG_PIO13_3_PU: PIO13[3] pull up control, active high. [2] SYSCFG_PIO13_2_PU: PIO13[2] pull up control, active high. [1] SYSCFG_PIO13_1_PU: PIO13[1] pull up control, active high. [0] SYSCFG_PIO13_0_PU: PIO13[0] pull up control, active high. Open drain pad control for all PIO alternate functions SYSCFG_PIO14_0_OD SYSCFG_PIO13_7_OD SYSCFG_PIO13_6_OD SYSCFG_PIO13_5_OD SYSCFG_PIO13_4_OD SYSCFG_PIO13_3_OD SYSCFG_PIO13_2_OD SYSCFG_PIO13_1_OD SYSCFG_PIO13_0_OD 0 SYSCFG_PIO14_1_OD 1 SYSCFG_PIO14_2_OD 2 R W R W R W R W R W R W R W R W R W R W R W R W R W Type: RW Reset: 0x0000 0000 Description: Open drain pad control for all PIO alternate functions. on fid SYSCFG_BANK2BaseAddress + 0x00000014 [23] SYSCFG_PIO15_7_OD: PIO15[7] open drain control, active high. [22] SYSCFG_PIO15_6_OD: PIO15[6] open drain control, active high. [21] SYSCFG_PIO15_5_OD: PIO15[5] open drain control, active high. [20] SYSCFG_PIO15_4_OD: PIO15[4] open drain control, active high. [19] SYSCFG_PIO15_3_OD: PIO15[3] open drain control, active high. [18] SYSCFG_PIO15_2_OD: PIO15[2] open drain control, active high. [17] SYSCFG_PIO15_1_OD: PIO15[1] open drain control, active high. [16] SYSCFG_PIO15_0_OD: PIO15[0] open drain control, active high. [15] SYSCFG_PIO14_7_OD: PIO14[7] open drain control, active high. [14] SYSCFG_PIO14_6_OD: PIO14[6] open drain control, active high. [13] SYSCFG_PIO14_5_OD: PIO14[5] open drain control, active high. [12] SYSCFG_PIO14_4_OD: PIO14[4] open drain control, active high. [11] SYSCFG_PIO14_3_OD: PIO14[3] open drain control, active high. [10] SYSCFG_PIO14_2_OD: PIO14[2] open drain control, active high. [9] SYSCFG_PIO14_1_OD: PIO14[1] open drain control, active high. 442/604 3 R W Address: [31:24] RESERVED 4 R W l R W 5 SYSCFG_PIO14_3_OD R W 6 SYSCFG_PIO14_4_OD R W ti a SYSCFG_PIO15_2_OD R W 7 SYSCFG_PIO14_5_OD SYSCFG_PIO15_3_OD R W 8 SYSCFG_PIO14_6_OD SYSCFG_PIO15_4_OD R W SYSCFG_PIO14_7_OD SYSCFG_PIO15_5_OD R W SYSCFG_PIO15_0_OD SYSCFG_PIO15_6_OD R W SYSCFG_PIO15_1_OD SYSCFG_PIO15_7_OD R W en RESERVED R 9 C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG205 STiH271EL System configuration registers [8] SYSCFG_PIO14_0_OD: PIO14[0] open drain control, active high. [7] SYSCFG_PIO13_7_OD: PIO13[7] open drain control, active high. [6] SYSCFG_PIO13_6_OD: PIO13[6] open drain control, active high. [5] SYSCFG_PIO13_5_OD: PIO13[5] open drain control, active high. [4] SYSCFG_PIO13_4_OD: PIO13[4] open drain control, active high. [3] SYSCFG_PIO13_3_OD: PIO13[3] open drain control, active high. [2] SYSCFG_PIO13_2_OD: PIO13[2] open drain control, active high. [1] SYSCFG_PIO13_1_OD: PIO13[1] open drain control, active high. PIO13 retime configuration register 0 ti a l SYSTEM_CONFIG206 PIO13_CFG_DELAY_1 PIO13_CFG_DELAY_0 RW RW 9 8 7 6 5 4 3 2 1 RESERVED PIO13_CFG_CLK1NOTCLK0 R RW SYSCFG_BANK2BaseAddress + 0x00000018 Type: RW Reset: 0x0000 0000 Description: PIO13 retime configuration register 0. fid en Address: 0 on [31:24] PIO13_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO13_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [15:8] RESERVED [7:0] PIO13_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] DocID023557 Rev 10 443/604 Information classified Confidential - Do not copy (See last page for obligations) [0] SYSCFG_PIO13_0_OD: PIO13[0] open drain control, active high. System configuration registers STiH271EL PIO13 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO13_CFG_DOUBLE_EDGE PIO13_CFG_CLKNOTDATA 9 8 7 PIO13_CFG_RETIME Address: SYSCFG_BANK2BaseAddress + 0x0000001C Type: RW Reset: 0x0000 0000 Description: PIO13 retime configuration register 1. 6 5 4 3 2 1 0 PIO13_CFG_INVERTCLK l [31:24] PIO13_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge ti a [23:16] PIO13_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO13_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed en PIO14 retime configuration register 0 fid SYSTEM_CONFIG208 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO14_CFG_DELAY_1 PIO14_CFG_DELAY_0 RESERVED PIO14_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK2BaseAddress + 0x00000020 Type: RW Reset: 0x0000 0000 Description: PIO14 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO13_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO14_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO14_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO14_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] 444/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG207 STiH271EL System configuration registers PIO14 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO14_CFG_DOUBLE_EDGE PIO14_CFG_CLKNOTDATA 9 8 7 PIO14_CFG_RETIME Address: SYSCFG_BANK2BaseAddress + 0x00000024 Type: RW Reset: 0x0000 0000 Description: PIO14 retime configuration register 1. 6 5 4 3 2 1 0 PIO14_CFG_INVERTCLK l [31:24] PIO14_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge ti a [23:16] PIO14_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO14_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed en PIO15 retime configuration register 0 fid SYSTEM_CONFIG210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIO15_CFG_DELAY_1 PIO15_CFG_DELAY_0 RESERVED PIO15_CFG_CLK1NOTCLK0 RW RW R RW SYSCFG_BANK2BaseAddress + 0x00000028 Type: RW Reset: 0x0000 0000 Description: PIO15 retime configuration register 0. on Address: 0 C Confidential [7:0] PIO14_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted [31:24] PIO15_CFG_DELAY_1: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [23:16] PIO15_CFG_DELAY_0: Configure delay on input and output data related to worst case prior to retiming. 00: No delay 01: Delay input by 0.5 ns and output by 1 ns 10: Delay input by 1 ns and output by 2 ns 11: Delay input by 1.5 ns and output by 3 ns [15:8] RESERVED [7:0] PIO15_CFG_CLK1NOTCLK0: Configure which clock to retime output/input data to. 0: Retime output data to CLKOUT[0] and input data on CLKIN[0] 1: Retime output data to CLKOUT[1] and input data on CLKIN[1] DocID023557 Rev 10 445/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG209 System configuration registers STiH271EL PIO15 retime configuration register 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PIO15_CFG_DOUBLE_EDGE PIO15_CFG_CLKNOTDATA 9 8 7 PIO15_CFG_RETIME Address: SYSCFG_BANK2BaseAddress + 0x0000002C Type: RW Reset: 0x0000 0000 Description: PIO15 retime configuration register 1. 6 5 4 3 2 1 0 PIO15_CFG_INVERTCLK l [31:24] PIO15_CFG_DOUBLE_EDGE: Configure double edge. 0: Single edge 1: Double edge ti a [23:16] PIO15_CFG_CLKNOTDATA: Configure data/clock. 0: Output retimed data 1: Output clock [15:8] PIO15_CFG_RETIME: Configure data retime. 0: Input and output data are not retimed 1: Input and output data are retimed en Compensation digital 0 configuration register fid SYSTEM_CONFIG212 Address: SYSCFG_BANK2BaseAddress + 0x00000030 Type: RW Reset: 0x0000 0000 Description: Compensation digital 0 configuration register. COMP_DIG0_FREEZE COMP_DIG0_COMPTQ COMP_DIG0_COMPEN 0 COMP_DIG0_RASRC0 1 COMP_DIG0_RASRC1 2 COMP_DIG0_RASRC2 3 COMP_DIG0_RASRC3 4 COMP_DIG0_RASRC4 5 COMP_DIG0_RASRC5 6 R W R W R W R W R W R W R W R W R W R W [10] COMP_DIG0_TQ: 0: Normal mode 1: To enable IDDQ mode [9] COMP_DIG0_RASRC6: Seventh bit of the digital input code. [8] COMP_DIG0_RASRC5: Sixth bit of the digital input code. [7] COMP_DIG0_RASRC4: Fifth bit of the digital input code. [6] COMP_DIG0_RASRC3: Fourth bit of the digital input code. DocID023557 Rev 10 7 R W [31:11] RESERVED 446/604 8 COMP_DIG0_RASRC6 R 9 COMP_DIG0_TQ on RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential [7:0] PIO15_CFG_INVERTCLK: Configure clock inversion. 0: Input and output clock are not inverted 1: Input and output clock are inverted Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG211 STiH271EL System configuration registers [5] COMP_DIG0_RASRC2: Third bit of the digital input code. [4] COMP_DIG0_RASRC1: Second bit of the digital input code. [3] COMP_DIG0_RASRC0: First bit of the digital input code. [2] COMP_DIG0_FREEZE: To enable freeze mode. [1] COMP_DIG0_COMPTQ: To select operation mode. Use this bit with bit[0]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode Compensation status register 7 6 5 4 2 1 0 COMP_DIG0_NASRC 3 fid en RESERVED 8 SYSCFG_BANK2BaseAddress + 0x0000006C Type: R Reset: 0x0000 0000 Description: Compensation status register. on Address: [31:8] RESERVED 9 C [7] COMP_DIG0_COMP_OK: Compensation OK for digital section 0. [6:0] COMP_DIG0_NASRC: Compensation NASRC for digital section 0. Address: SYSCFG_BANK2BaseAddress + 0x00000088 Type: RW Reset: 0x0000 0000 Description: System configuration interrupts bank. DocID023557 Rev 10 5 4 3 2 SYS_CONF_IRQ2 1 0 SYS_CONF_IRQ0 6 SYS_CONF_IRQ1 7 SYS_CONF_IRQ3 8 SYS_CONF_IRQ4 9 SYS_CONF_IRQ5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYS_CONF_IRQ6 System configuration interrupts bank SYS_CONF_IRQ7 SYSTEM_CONFIG234 RESERVED Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 COMP_DIG0_COMP_OK ti a l SYSTEM_STATUS227 447/604 Information classified Confidential - Do not copy (See last page for obligations) [0] COMP_DIG0_COMPEN: To select operation mode. Use this bit with bit[1]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode System configuration registers STiH271EL [31:8] RESERVED [7] SYS_CONF_IRQ7: IRQ from system config registers. Mapped to IRQ router [169]. [6] SYS_CONF_IRQ6: IRQ from system config registers. Mapped to IRQ router [168]. [5] SYS_CONF_IRQ5: IRQ from system config registers. Mapped to IRQ router [167]. [4] SYS_CONF_IRQ4: IRQ from system config registers. Mapped to IRQ router [166]. [3] SYS_CONF_IRQ3: IRQ from system config registers. Mapped to IRQ router [165]. [2] SYS_CONF_IRQ2: IRQ from system config registers. Mapped to IRQ router [164]. l [0] SYS_CONF_IRQ0: IRQ from system config registers. Mapped to IRQ router [162]. Type: RW Reset: 0x0000 0000 Description: System configuration DREQ bank. on [31:3] RESERVED [2] SYS_CONF_DREQ2: System configuration DREQ 2. [1] SYS_CONF_DREQ1: System configuration DREQ 1. [0] SYS_CONF_DREQ0: System configuration DREQ 0. 448/604 DocID023557 Rev 10 8 7 6 5 4 3 2 1 0 SYS_CONF_DREQ0 9 SYS_CONF_DREQ1 RESERVED en SYSCFG_BANK2BaseAddress + 0x0000008C fid Address: C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SYS_CONF_DREQ2 System configuration DREQ bank ti a SYSTEM_CONFIG235 Information classified Confidential - Do not copy (See last page for obligations) [1] SYS_CONF_IRQ1: IRQ from system config registers. Mapped to IRQ router [163]. STiH271EL System configuration registers Comms configuration 6 5 4 3 2 1 0 RESERVED 7 GLOBAL_POWERDOWN 8 R R W R W SYSCFG_BANK2BaseAddress + 0x0000009C Type: RW Reset: 0x0000 0001 Description: Comms configuration. ti a l Address: en [31:2] RESERVED [1] GLOBAL_POWERDOWN: It replace the LPC method to enter/exit in/from the low power mode. Bank 3 registers descriptions 9 8 7 6 5 4 3 2 1 R W R W R W RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NAND_PWRDWN_REQ Power-down requests control GLOBAL_PWRDWN_REQ SYSTEM_CONFIG401 on 19.5 fid [0] RESERVED C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R Address: SYSCFG_BANK3BaseAddress + 0x00000004 Type: RW Reset: 0x0000 0000 Description: EMI power-down requests control. 0 [31:2] RESERVED [1] NAND_PWRDWN_REQ: NAND power-down request. [0] GLOBAL_PWRDWN_REQ: EMI subsystem power-down request. DocID023557 Rev 10 449/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG239 System configuration registers Global parameters of frequency synthesizer 2 (GP) 4 3 2 1 0 GP_RSTN 5 RESERVED 6 GP_NSB R W 7 GP_NPDA F_0X0 RW 8 F_0X0 GP_BW_SEL R 9 GP_NDIV0 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R W R W R W RW R R W SYSCFG_BANK3BaseAddress + 0x00000018 Type: RW Reset: 0x0000 0000 Description: Global parameters of frequency synthesizer 2 (GP). ti a l Address: [31:20] RESERVED [19:18] GP_BW_SEL: Frequency synthesizer reference clock filter. en [16] F_0X0: Frequency synthesizer reference clock frequency NDIV1. [15] GP_NDIV0: Frequency synthesizer reference clock frequency NDIV0. fid [14] GP_NPDA: Frequency synthesizer analog power-down mode - active low. [13:10] GP_NSB: Frequency synthesizer digital part standby mode - active low. [9:1] RESERVED SYSTEM_CONFIG407 on [0] GP_RSTN: Frequency synthesizer reset - active low. C Confidential [17] F_0X0: Frequency synthesizer reference clock frequency NDIV2. Frequency synthesizer 2 (GP) channel 0 coarse selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED GP_MD0 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000001C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 0 coarse selection. 0 [31:5] RESERVED [4:0] GP_MD0: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 0. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). 450/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG406 STiH271EL STiH271EL System configuration registers Frequency synthesizer 2 (GP) channel 0 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED GP_PE0 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000020 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 0 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] GP_PE0: Defines the PE parameter (fine selection) for the frequency synthesizer channel 0. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 2 (GP) channel 0 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 GP_SDIV0 R RW fid RESERVED SYSCFG_BANK3BaseAddress + 0x00000024 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 0 output divider. 0 on Address: [31:4] RESERVED 8 C Confidential SYSTEM_CONFIG409 [3:0] GP_SDIV0: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 0. The SDIV parameter can take the values up to 28. DocID023557 Rev 10 451/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG408 System configuration registers Frequency synthesizer 2 (GP) channel 0 program enable 4 3 2 1 0 GP_NSDIV0 5 GP_PROG_EN0 6 GP_NSDIV1 7 GP_NSDIV2 8 GP_NSDIV3 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W R W R W R W R W SYSCFG_BANK3BaseAddress + 0x00000028 Type: RW Reset: 0x0000 001E Description: Frequency synthesizer 2 (GP) channel 0 program enable. ti a l Address: en [31:5] RESERVED fid [0] GP_PROG_EN0: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 0. This parameter must be set to 1 to take into account a new configuration. SYSTEM_CONFIG411 Frequency synthesizer 2 (GP) channel 1 coarse selection on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED GP_MD1 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000002C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 1 coarse selection. 0 C Confidential [4:1] GP_NSDIV[3:0]: Output divider control NSDIV. [31:5] RESERVED [4:0] GP_MD1: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 1. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). 452/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG410 STiH271EL STiH271EL System configuration registers Frequency synthesizer 2 (GP) channel 1 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED GP_PE1 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000030 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 1 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] GP_PE1: Defines the PE parameter (fine selection) for the frequency synthesizer channel 1. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 2 (GP) channel 1 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 GP_SDIV1 R RW fid RESERVED SYSCFG_BANK3BaseAddress + 0x00000034 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 1 output divider. 0 on Address: [31:4] RESERVED 8 C Confidential SYSTEM_CONFIG413 [3:0] GP_SDIV1: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 1. The SDIV parameter can take the values up to 28. DocID023557 Rev 10 453/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG412 System configuration registers Frequency synthesizer 2 (GP) channel 1 program enable 7 6 5 4 3 2 1 0 GP_PROG_EN1 8 R R W SYSCFG_BANK3BaseAddress + 0x00000038 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 1 program enable. ti a l Address: en [31:1] RESERVED [0] GP_PROG_EN1: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 1. This parameter must be set to 1 to take into account a new configuration. Frequency synthesizer 2 (GP) channel 2 coarse selection fid SYSTEM_CONFIG415 on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED GP_MD2 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000003C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 2 coarse selection. 0 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:5] RESERVED [4:0] GP_MD2: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 2. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). 454/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG414 STiH271EL STiH271EL System configuration registers Frequency synthesizer 2 (GP) channel 2 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED GP_PE2 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000040 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 2 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] GP_PE2: Defines the PE parameter (fine selection) for the frequency synthesizer channel 2. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 2 (GP) channel 2 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 GP_SDIV2 R RW fid RESERVED SYSCFG_BANK3BaseAddress + 0x00000044 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 2 output divider. 0 on Address: [31:4] RESERVED 8 C Confidential SYSTEM_CONFIG417 [3:0] GP_SDIV2: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 2. The SDIV parameter can take the values up to 28. DocID023557 Rev 10 455/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG416 System configuration registers Frequency synthesizer 2 (GP) channel 1 program enable 7 6 5 4 3 2 1 0 GP_PROG_EN2 8 R R W SYSCFG_BANK3BaseAddress + 0x00000048 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 1 program enable. ti a l Address: en [31:1] RESERVED [0] GP_PROG_EN2: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 2. This parameter must be set to 1 to take into account a new configuration. Frequency synthesizer 2 (GP) channel 3 coarse selection fid SYSTEM_CONFIG419 on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED GP_MD3 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000004C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 3 coarse selection. 0 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:5] RESERVED [4:0] GP_MD3: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 3. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). 456/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG418 STiH271EL STiH271EL System configuration registers Frequency synthesizer 2 (GP) channel 3 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED GP_PE3 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000050 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 3 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] GP_PE3: Defines the PE parameter (fine selection) for the frequency synthesizer channel 3. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 2 (GP) channel 3 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 GP_SDIV3 R RW fid RESERVED SYSCFG_BANK3BaseAddress + 0x00000054 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 3 output divider. 0 on Address: [31:4] RESERVED 8 C Confidential SYSTEM_CONFIG421 [3:0] GP_SDIV3: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 3. The SDIV parameter can take the values up to 28. DocID023557 Rev 10 457/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG420 System configuration registers Frequency synthesizer 2 (GP) channel 3 program enable 7 6 5 4 3 2 1 0 GP_PROG_EN3 8 R R W SYSCFG_BANK3BaseAddress + 0x00000058 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 2 (GP) channel 3 program enable. ti a l Address: en [31:1] RESERVED [0] GP_PROG_EN3: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 3. This parameter must be set to 1 to take into account a new configuration. 6 Address: SYSCFG_BANK3BaseAddress + 0x0000005C Type: R Reset: 0x0000 0000 Description: EMI/USB power down ACK monitor. [31:5] RESERVED [4] POWERDOWN_ACK_USB1: Power down ACK USB1. [3] POWERDOWN_ACK_USB0: Power down ACK USB0. [2] RESERVED [1] NAND_PWRDWN_GRANT: NAND power own ACK. [0] EMISS_GLOBAL_PWRDWN_ACK: EMI subsystem power down ACK. 458/604 DocID023557 Rev 10 5 4 3 2 1 0 NAND_PWRDWN_GRANT 7 EMISS_GLOBAL_PWRDWN_ACK 8 RESERVED 9 RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 POWERDOWN_ACK_USB0 Power down ACK monitor POWERDOWN_ACK_USB1 fid SYSTEM_STATUS423 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG422 STiH271EL STiH271EL System configuration registers Global parameters of frequency synthesizer 0 (VID0) 1 0 VID_RSTN 2 RESERVED 3 VID_NSB 4 VID_NPDA 5 VID_NDIV0 6 VID_NDIV1 7 VID_NDIV2 8 VID_BW_SEL 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R RW R W R W R W R W RW R R W SYSCFG_BANK3BaseAddress + 0x00000060 Type: RW Reset: 0x0000 0000 Description: Global parameters of frequency synthesizer 0 (VID0). ti a l Address: [31:20] RESERVED en [19:18] VID_BW_SEL: Frequency synthesizer reference clock filter. Confidential [17] VID_NDIV2: Frequency synthesizer reference clock frequency NDIV2. [16] VID_NDIV1: Frequency synthesizer reference clock frequency NDIV1. fid [15] VID_NDIV0: Frequency synthesizer reference clock frequency NDIV0. [14] VID_NPDA: Frequency synthesizer analog power down mode - active low. [13:10] VID_NSB: Frequency synthesizer digital part standby mode - active low. on [9:1] RESERVED [0] VID_RSTN: Frequency synthesizer reset - active low. C SYSTEM_CONFIG425 Frequency synthesizer 0 (VID0) channel 0 coarse selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID_MD0 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000064 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 0 coarse selection. 0 [31:5] RESERVED [4:0] VID_MD0: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 0. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). DocID023557 Rev 10 459/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG424 System configuration registers Frequency synthesizer 0 (VID0) channel 0 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED VID_PE0 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000068 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 0 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] VID_PE0: Defines the PE parameter (fine selection) for the frequency synthesizer channel 0. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 0 (VID0) channel 0 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 RW fid VID_SDIV0 R SYSCFG_BANK3BaseAddress + 0x0000006C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 0 output divider. 0 on Address: [31:4] RESERVED 7 RESERVED C Confidential SYSTEM_CONFIG427 [3:0] VID_SDIV0: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 0. The SDIV parameter can take the values up to 28. 460/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG426 STiH271EL STiH271EL System configuration registers Frequency synthesizer 0 (VID0) channel 0 program enable 4 3 2 1 0 VID_NSDIV0 5 VID_PROG_EN0 6 VID_NSDIV1 7 VID_NSDIV2 8 VID_NSDIV3 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W R W R W R W R W SYSCFG_BANK3BaseAddress + 0x00000070 Type: RW Reset: 0x0000 001E Description: Frequency synthesizer 0 (VID0) channel 0 program enable. ti a l Address: en [31:5] RESERVED fid [0] VID_PROG_EN0: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 0. This parameter must be set to 1 to take into account a new configuration. Frequency synthesizer 0 (VID0) channel 1 coarse selection on SYSTEM_CONFIG429 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID_MD1 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000074 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 1 coarse selection. 0 C Confidential [4:1] VID_NSDIV[3:0]: Output divider control NSDIV. [31:5] RESERVED [4:0] VID_MD1: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 1. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). DocID023557 Rev 10 461/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG428 System configuration registers Frequency synthesizer 0 (VID0) channel 1 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED VID_PE1 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000078 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 1 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] VID_PE1: Defines the PE parameter (fine selection) for the frequency synthesizer channel 1. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 0 (VID0) channel 1 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 RW fid VID_SDIV1 R SYSCFG_BANK3BaseAddress + 0x0000007C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 1 output divider. 0 on Address: [31:4] RESERVED 7 RESERVED C Confidential SYSTEM_CONFIG431 [3:0] VID_SDIV1: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 1. The SDIV parameter can take the values up to 28. 462/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG430 STiH271EL STiH271EL System configuration registers Frequency synthesizer 0 (VID0) channel 1 program enable 7 6 5 4 3 2 1 0 VID_PROG_EN1 8 R R W SYSCFG_BANK3BaseAddress + 0x00000080 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 1 program enable. ti a l Address: en [31:1] RESERVED [0] VID_PROG_EN1: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 1. This parameter must be set to 1 to take into account a new configuration. Frequency synthesizer 0 (VID0) channel 2 coarse selection fid SYSTEM_CONFIG433 on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID_MD2 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000084 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 2 coarse selection. 0 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:5] RESERVED [4:0] VID_MD2: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 2. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). DocID023557 Rev 10 463/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG432 System configuration registers Frequency synthesizer 0 (VID0) channel 2 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED VID_PE2 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000088 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 2 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] VID_PE2: Defines the PE parameter (fine selection) for the frequency synthesizer channel 2. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 0 (VID0) channel 2 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 RW fid VID_SDIV2 R SYSCFG_BANK3BaseAddress + 0x0000008C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 2 output divider. 0 on Address: [31:4] RESERVED 7 RESERVED C Confidential SYSTEM_CONFIG435 [3:0] VID_SDIV2: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 2. The SDIV parameter can take the values up to 28. 464/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG434 STiH271EL STiH271EL System configuration registers Frequency synthesizer 0 (VID0) channel 2 program enable 7 6 5 4 3 2 1 0 VID_PROG_EN2 8 R R W SYSCFG_BANK3BaseAddress + 0x00000090 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 2 program enable. ti a l Address: en [31:1] RESERVED [0] VID_PROG_EN2: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 2. This parameter must be set to 1 to take into account a new configuration. Frequency synthesizer 0 (VID0) channel 3 coarse selection fid SYSTEM_CONFIG437 on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID_MD3 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000094 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 3 coarse selection 0 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:5] RESERVED [4:0] VID_MD3: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 3. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). DocID023557 Rev 10 465/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG436 System configuration registers Frequency synthesizer 0 (VID0) channel 3 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 RESERVED VID_PE3 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000098 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 3 fine selection. 4 3 2 1 0 ti a l [31:15] RESERVED 5 [14:0] VID_PE3: Defines the PE parameter (fine selection) for the frequency synthesizer channel 3. The PE parameter is defined in the range from 0 to 215 - 1. en Frequency synthesizer 0 (VID0) channel 3 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 RW fid VID_SDIV3 R SYSCFG_BANK3BaseAddress + 0x0000009C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 3 output divider. 0 on Address: [31:4] RESERVED 7 RESERVED C Confidential SYSTEM_CONFIG439 [3:0] VID_SDIV3: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 3. The SDIV parameter can take the values up to 28. 466/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG438 STiH271EL STiH271EL System configuration registers Frequency synthesizer 0 (VID0) channel 3 program enable 7 6 5 4 3 2 1 0 VID_PROG_EN3 8 R R W SYSCFG_BANK3BaseAddress + 0x000000A0 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 0 (VID0) channel 3 program enable. ti a l Address: en [31:1] RESERVED [0] VID_PROG_EN3: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 3. This parameter must be set to 1 to take into account a new configuration. fid SYSTEM_CONFIG441 Audio DAC control 5 4 3 2 1 0 AUDIO_DAC_NRST 6 RESERVED 7 SOFTMUTE 8 ADAC_NPDA 9 RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W R W R R W Address: SYSCFG_BANK3BaseAddress + 0x000000A4 Type: RW Reset: 0x0000 0000 Description: Audio DAC control. [31:6] RESERVED [5] ADAC_NPDA: DAC standby mode - active high. [4] SOFTMUTE: DAC soft mute - active high. [3:1] RESERVED [0] AUDIO_DAC_NRST: DAC reset - active low. DocID023557 Rev 10 467/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG440 System configuration registers STiH271EL Audio source and output controls 4 3 2 RESERVED 5 ADAC_VALID 6 RESERVED 7 CLKREC_SEL 8 R RW R R W R SYSCFG_BANK3BaseAddress + 0x000000A8 Type: RW Reset: 0x0000 0000 Description: Audio source and output controls. en [8:7] RESERVED 0 ti a [10:9] CLKREC_SEL: Audio clock to recover 1 l Address: [31:11] RESERVED [6] ADAC_VALID: Audio DAC validation path SYSTEM_CONFIG443 fid [5:0] RESERVED Audio glue configuration Address: SYSCFG_BANK3BaseAddress + 0x000000AC Type: RW Reset: 0x0000 0040 Description: Audio glue configuration. [31:12] RESERVED 468/604 DocID023557 Rev 10 7 6 5 4 3 2 1 0 PCMP_VALID_SEL 8 RESERVED R 9 PCM_CLK_SEL on RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RW r RW Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG442 STiH271EL System configuration registers [11:8] PCM_CLK_SEL: Selects the frequency synthesizer clock or the external PCM clock for each channel. Bit[8] is PCM player 0 clock from FS or external pad. 0: External clock from PIO15[1] and 1: FS clock. Bit[9] is PCM player 1 clock from FS or external pad. 0: External clock from PIO15[1] and 1: FS clock. Bit[10] is S/PDIF clock from FS or external pad. 0: External clock from PIO15[1] and 1: FS clock. Bit[11] is PCM player 2 clock from FS or external pad. 0: External clock from PIO15[1] and 1: FS clock. [7:2] RESERVED C on fid Confidential en ti a l Information classified Confidential - Do not copy (See last page for obligations) [1:0] PCMP_VALID_SEL: PCM player to pad selection. 00: PCM player 0 to pads 01: PCM player 1 to pads 10: PCM player 2 to pads 11: Not applicable DocID023557 Rev 10 469/604 System configuration registers STiH271EL Power down requests control 7 6 5 4 3 2 SYSCFG_BANK3BaseAddress + 0x000000C4 Type: RW Reset: 0x0000 0006 Description: USB power down requests control. 0 R W R W en ti a l Address: [31:2] RESERVED [1] USB_1_POWERDOWN_REQ: USB1 power down request. Address: SYSCFG_BANK3BaseAddress + 0x000000C8 Type: RW Reset: 0x0000 0000 Description: Video DACs control. 8 7 6 5 4 3 2 RESERVED 9 DAC_HD_HZVX RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DAC_HD_HZUVW Video DACs configuration DAC_HD_CMDS SYSTEM_CONFIG450 DAC_HD_CMDR fid [0] USB_0_POWERDOWN_REQ: USB0 power down request. C Confidential R 1 [31:10] RESERVED [9] DAC_HD_CMDR: Functions with CMDR signals. Can be used to force DAC HD output. [8] DAC_HD_CMDS: Functions with CMDS signal. Can be used to force DAC HD output. 470/604 DocID023557 Rev 10 1 0 Information classified Confidential - Do not copy (See last page for obligations) 8 USB_0_POWERDOWN_REQ 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 USB_1_POWERDOWN_REQ SYSTEM_CONFIG449 STiH271EL System configuration registers [7] DAC_HD_HZUVW: Disables the tri-channel (UVW) DAC output current and puts the output in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [6] DAC_HD_HZVX: Disables the mono-channel (X) DAC output current and puts the output in high impedance mode, but leaves the reference circuitry powered for fast recovery to active mode. [5:0] RESERVED Reset generator control 2 RW Reset: 0x0000 01FE Description: Reset generator: warm or cold reset control. [31:6] RESERVED 1 0 RESERVED 2 LEVEL1_1_WARM_COLDN 3 LEVEL1_2_WARM_COLDN 4 LEVEL1_3_WARM_COLDN 5 R W R W R W R W R W R on l 6 [5] LEVEL1_5_WARM_COLDN: LPC watchdog. 0: Cold reset 1: Warm reset [4] LEVEL1_4_WARM_COLDN: ST40 watchdog. 0: Cold reset 1: Warm reset [3] LEVEL1_3_WARM_COLDN: ST40 power. 0: Cold reset 1: Warm reset [2] LEVEL1_2_WARM_COLDN: ST40 UDI. 0: Cold reset 1: Warm reset [1] LEVEL1_1_WARM_COLDN: ST40 manual. 0: Cold reset 1: Warm reset [0] RESERVED DocID023557 Rev 10 471/604 Information classified Confidential - Do not copy (See last page for obligations) Type: 7 LEVEL1_4_WARM_COLDN ti a en SYSCFG_BANK3BaseAddress + 0x000000E8 8 fid Address: 9 C Confidential R l RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LEVEL1_5_WARM_COLDN SYSTEM_CONFIG458 System configuration registers STiH271EL SYSTEM_CONFIG459 Reset generator control 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address: SYSCFG_BANK3BaseAddress + 0x000000EC Type: RW Reset: 0x0052 65C0 Description: Reset generator: period of Resetout. l [31:0] NOTRESETOUT_TEMPO: Period of reset out in 30 MHz cycles. This defines the NOT_RESETOUT length. ti a SYSTEM_CONFIG460 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reset generator control 0 9 8 7 6 5 4 3 2 1 0 SYSCFG_BANK3BaseAddress + 0x000000F0 Type: RW Reset: 0xF3FF FFFF Description: Reset generator. Soft reset for first 32 reset peripherals. fid en Address: on [31:0] RESETGEN_SOFT_0: Soft reset for <31:0> reset peripherals. Bit[0]: EMI subsystem, FDMA multiplexer, interrupt controller, PIOs, PCM player, PCM reader, mailboxes, interrupt multiplexer Bit[1]: FDMA0, DDR Bit[2]: FDMA1, DeltaMU Bit[4:3]: Reserved Bit[5]: HDTVout, compositor Bit[6]: STFE Bit[7]: Comms Bit[8]: GPFS0 Bit[9] USB0 Bit[10]: Blitter Bit[11]: Reserved Bit[12]: HQVDP, NRSTSCAN_HDMIPHY Bit[13]: ERAM, PRBSC0_HDMIPHY Bit[14]: PRBSC1_HDMIPHY Bit[15]: PRBSC2_HDMIPHY Bit[16]: Interconnect Bit[17]: VID FS0 Bit[18]: Reserved Bit[19]: USB1 Bit[20]: VID FS1 Bit[21]: HDMI PHY (nreset) Bit[22]: Thermal sensorBit[23]: VCC Bit[24]: VDP Aux Bit[25]: RESERVED Bit[26]: LX audio Bit[27]: LX DMU Bit[31:28]: Reserved C Confidential RESETGEN_SOFT_0 472/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) NOTRESETOUT_TEMPO STiH271EL System configuration registers SYSTEM_CONFIG461 Reset generator control 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address: SYSCFG_BANK3BaseAddress + 0x000000F4 Type: RW Reset: 0xFFFF FFFF Description: Reset generator. Soft reset for upper 32 reset peripherals. ti a l [31:0] RESETGEN_SOFT_1: Soft reset for <63:32> reset peripherals. Bit[0]: RESERVED Bit[1]: MMC Bit[2]: RESERVED Bit[3]: RESERVED Bit[4]: Reserved Bit[5]: MCRU Bit[31:6]: Reserved SYSCFG_BANK3BaseAddress + 0x000000F8 Type: RW Reset: 0x0000 0000 Description: Video control and debug configuration register. 5 4 3 2 1 0 VTG_PIP 6 RESERVED 7 SPDIFOUT_SEL 8 on Address: VVC_CLKOUT fid RESERVED 9 C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MAIN_INVERTED_VTG Video control and debug configuration register en SYSTEM_CONFIG462 DocID023557 Rev 10 473/604 Information classified Confidential - Do not copy (See last page for obligations) RESETGEN_SOFT_1 System configuration registers STiH271EL ti a l [13:8] VCC_CLKOUT: VCC clockout on CLK_obs_to_pad Bit[8]: Must be kept 1 to enable VCC outputs[7:4] to pad, selection is with bits [13:12] Bit[9]: 0: to enable VCC outputs[3:0] to pad, selection is with bit [11:10] 1: to enable VCC outputs [7:4] to pad, selection is with bit[13:12] Bit[11:10]: 00: VCC output[0] to pad 01: VCC output[1] to pad 10: VCC output[2] to pad 11: VCC output[3] to pad Bit[13:12]: 00: VCC output[4] to pad 01: VCC output[5] to pad 10: VCC output[6] to pad 11: VCC output[7] to pad Confidential en [7:6] SPDIFOUT_SEL: S/PDIF out selection. 00: o_spdif_out[0] for spdif_out on PIO4[1] 01: o_spdif_out[1] for spdif_out on PIO4[1] 10: o_spdif_out[2] for spdif_out on PIO4[1] 11: o_spdif_out[3] for spdif_out on PIO4[1] fid [1] MAIN_INVERTED_VTG: Main/inverted main VTG on PIO. 0: Main VTG on PIO 1: inverted Main VTG on PIO Clock observation C Table 79. on [0] VTG_PIP: 0: VTG PIP for AUX VDP from Aux VTG 1: VTG PIP from Main VTG Register setting Observation clock SYSTEM_CONFIG462 [8] [9] [10] [11] [12] [13] Channel 0 1 0 0 0 0 0 Channel 1 1 0 1 0 0 0 Channel 2 1 0 0 1 0 0 Channel 3 1 0 1 1 0 0 Channel 4 1 1 0 0 0 0 Channel 5 1 1 0 0 1 0 Channel 6 1 1 0 0 0 1 Channel 7 1 1 0 0 1 1 474/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [31:14] RESERVED STiH271EL System configuration registers Figure 47. Clock observation 0 clk_vidclkctrl_0 0 clk_vidclkctrl_1 1 clk_vidclkctrl_2 2 0 0 Clock observation 3 clk_vidclkctrl_3 SYSTEM_CONFIG462[10] SYSTEM_CONFIG462[11] clk_vidclkctrl_5 1 SYSTEM_CONFIG462[8] 2 clk_vidclkctrl_7 3 en clk_vidclkctrl_6 SYSTEM_CONFIG462[9] SYSTEM_CONFIG462[12] fid SYSTEM_CONFIG462[13] on SYSTEM_CONFIG463 Video clock divider 0 setting 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED 9 8 7 6 5 4 3 2 1 0 VCD0_STOP_CLK Address: SYSCFG_BANK3BaseAddress + 0x000000FC Type: RW Reset: 0x0000 0000 Description: Video clock divider setting. C Confidential 1 [31:16] RESERVED [15:0] VCD0_STOP_CLK: Clock enable. 0: Disable the clock. 1: Enable the clock. DocID023557 Rev 10 475/604 Information classified Confidential - Do not copy (See last page for obligations) 0 ti a clk_vidclkctrl_4 l 1 System configuration registers STiH271EL SYSTEM_CONFIG464 Video clock divider 0 setting 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSCFG_BANK3BaseAddress + 0x00000100 Type: RW Reset: 0x0000 0000 Description: Video clock divider setting. ti a [31:0] VCD0_SEL_CLK: Clock source selection. 00: Input 1 01: Input 2 10: Input 3 11: Input 4 Channel 0: Bit[1:0] Channel 1: Bit[3:2] Channel 2: Bit[5:4] ................................ Channel 16: Bit[31:30] en Video clock divider 0 setting 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VCD0_DIV_MODE SYSCFG_BANK3BaseAddress + 0x00000104 Type: RW Reset: 0x0000 0000 Description: Video clock divider setting. on fid Address: [31:0] VCD0_DIV_MODE: Clock division selection. 00: Divide by 1 01: Divide by 2 10: Divide by 411: Divide by 8 Channel 0: Bit[1:0] Channel 1: Bit[3:2] Channel 2: Bit[5:4] ................................ Channel 16: Bit[31:30] C HDMI rejection PLL status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address: SYSCFG_BANK3BaseAddress + 0x00000118 Type: R 476/604 DocID023557 Rev 10 9 8 7 6 5 4 3 2 1 0 HDMI_REJ_PLL_LOCK SYSTEM_STATUS470 RESERVED Confidential SYSTEM_CONFIG465 l Address: Information classified Confidential - Do not copy (See last page for obligations) VCD0_SEL_CLK STiH271EL System configuration registers Reset: 0x0000 0000 Description: HDMI rejection PLL status register. [31:1] RESERVED [0] HDMI_REJ_PLL_LOCK: It is used to check lock condition of the HDMI rejection PLL. SYSTEM_STATUS472 Reset generator status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSCFG_BANK3BaseAddress + 0x00000120 Type: R Reset: 0x0000 0000 Description: Reset generator status register. en ti a l Address: Information classified Confidential - Do not copy (See last page for obligations) RESET_STATUS C on fid Confidential [31:0] RESET_STATUS: Internal reset sources. DocID023557 Rev 10 477/604 System configuration registers STiH271EL CPUs soft reset 6 5 4 3 2 1 0 RESERVED 7 ST40_MAN_SOFT_RST 8 R R W R SYSCFG_BANK3BaseAddress + 0x0000012C Type: RW Reset: 0x0000 000C Description: ST40 core soft reset. ti a l Address: en [31:3] RESERVED [2] ST40_MAN_SOFT_RST: ST40 manual soft reset. fid [1:0] RESERVED SYSTEM_CONFIG478 Global parameters of frequency synthesizer 1 (VID1) 1 0 VID1_RSTN 2 RESERVED 3 RW R W R W R W R W RW R R W Address: SYSCFG_BANK3BaseAddress + 0x00000138 Type: RW Reset: 0x0000 0000 Description: Global parameters of frequency synthesizer 1 (VID1). [31:20] RESERVED [19:18] VID1_BW_SEL: Frequency synthesizer reference clock filter. [17] VID1_NDIV2: Frequency synthesizer reference clock frequency NDIV2. [16] VID1_NDIV1: Frequency synthesizer reference clock frequency NDIV1. [15] VID1_NDIV0: Frequency synthesizer reference clock frequency NDIV0. [14] VID1_NPDA: Frequency synthesizer analog power down mode - active low. 478/604 4 VID1_NSB 5 VID1_NPDA 6 VID1_NDIV0 7 VID1_NDIV1 8 VID1_NDIV2 C R 9 VID1_BW_SEL on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG475 STiH271EL System configuration registers [13:10] VID1_NSB: Frequency synthesizer digital part standby mode - active low. [9:1] RESERVED [0] VID1_RSTN: Frequency synthesizer reset - active low. Frequency synthesizer 1 (VID1) channel 0 coarse selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 VID1_MD0 R RW SYSCFG_BANK3BaseAddress + 0x0000013C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 0 coarse selection. 0 ti a l Address: en [31:5] RESERVED [4:0] VID1_MD0: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 0. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). Frequency synthesizer 1 (VID1) channel 0 fine selection fid SYSTEM_CONFIG480 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R 9 on RESERVED 8 7 6 5 4 3 2 1 0 VID1_PE0 RW Address: SYSCFG_BANK3BaseAddress + 0x00000140 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 0 fine selection. C Confidential 9 RESERVED [31:15] RESERVED [14:0] VID1_PE0: Defines the PE parameter (fine selection) for the frequency synthesizer channel 0. The PE parameter is defined in the range from 0 to 215 - 1. DocID023557 Rev 10 479/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG479 System configuration registers Frequency synthesizer 1 (VID1) channel 0 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VID1_SDIV0 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000144 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 0 output divider. ti a l [31:4] RESERVED [3:0] VID1_SDIV0: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 0. The SDIV parameter can take the values up to 28. Address: SYSCFG_BANK3BaseAddress + 0x00000148 Type: RW Reset: 0x0000 001E Description: Frequency synthesizer 1 (VID1) channel 0 program enable. 5 4 3 2 1 0 VID1_NSDIV0 6 VID1_PROG_EN0 on R 7 VID1_NSDIV1 8 VID1_NSDIV2 9 fid RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VID1_NSDIV3 en Frequency synthesizer 1 (VID1) channel 0 program enable R W R W R W R W R W C Confidential SYSTEM_CONFIG482 [31:5] RESERVED [4] VID1_NSDIV3: Output divider control NSDIV. [3] VID1_NSDIV2: Output divider control NSDIV. [2] VID1_NSDIV1: Output divider control NSDIV. [1] VID1_NSDIV0: Output divider control NSDIV. [0] VID1_PROG_EN0: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 0. This parameter must be set to 1 to take into account a new configuration. 480/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG481 STiH271EL STiH271EL System configuration registers Frequency synthesizer 1 (VID1) channel 1 coarse selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID1_MD1 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000014C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 1 coarse selection. ti a l [31:5] RESERVED 0 [4:0] VID1_MD1: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 1. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). en Frequency synthesizer 1 (VID1) channel 1 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED fid R 9 SYSCFG_BANK3BaseAddress + 0x00000150 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 1 fine selection. [31:15] RESERVED 7 6 5 4 3 2 1 0 VID1_PE1 RW on Address: 8 C Confidential SYSTEM_CONFIG484 [14:0] VID1_PE1: Defines the PE parameter (fine selection) for the frequency synthesizer channel 1. The PE parameter is defined in the range from 0 to 215 - 1. DocID023557 Rev 10 481/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG483 System configuration registers Frequency synthesizer 1 (VID1) channel 1 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VID1_SDIV1 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000154 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 1 output divider. ti a l [31:4] RESERVED [3:0] VID1_SDIV1: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 1. The SDIV parameter can take the values up to 28. en Frequency synthesizer 1 (VID1) channel 1 program enable 8 7 6 5 4 3 2 1 0 VID1_PROG_EN1 9 RESERVED on fid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W Address: SYSCFG_BANK3BaseAddress + 0x00000158 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 1 program enable. C Confidential SYSTEM_CONFIG486 [31:1] RESERVED [0] VID1_PROG_EN1: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 1. This parameter must be set to 1 to take into account a new configuration. 482/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG485 STiH271EL STiH271EL System configuration registers Frequency synthesizer 1 (VID1) channel 2 coarse selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID1_MD2 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000015C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 2 coarse selection. ti a l [31:5] RESERVED 0 [4:0] VID1_MD2: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 2. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). en Frequency synthesizer 1 (VID1) channel 2 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED fid R 9 SYSCFG_BANK3BaseAddress + 0x00000160 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 2 fine selection. [31:15] RESERVED 7 6 5 4 3 2 1 0 VID1_PE2 RW on Address: 8 C Confidential SYSTEM_CONFIG488 [14:0] VID1_PE2: Defines the PE parameter (fine selection) for the frequency synthesizer channel 2. The PE parameter is defined in the range from 0 to 215 - 1. DocID023557 Rev 10 483/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG487 System configuration registers Frequency synthesizer 1 (VID1) channel 2 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VID1_SDIV2 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000164 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 2 output divider. ti a l [31:4] RESERVED [3:0] VID1_SDIV2: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 2. The SDIV parameter can take the values up to 28. en Frequency synthesizer 1 (VID1) channel 2 program enable 8 7 6 5 4 3 2 1 0 VID1_PROG_EN2 9 RESERVED on fid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W Address: SYSCFG_BANK3BaseAddress + 0x00000168 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 2 program enable. C Confidential SYSTEM_CONFIG490 [31:1] RESERVED [0] VID1_PROG_EN2: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 2. This parameter must be set to 1 to take into account a new configuration. 484/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG489 STiH271EL STiH271EL System configuration registers Frequency synthesizer 1 (VID1) channel 3 coarse selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED VID1_MD3 R RW Address: SYSCFG_BANK3BaseAddress + 0x0000016C Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 3 coarse selection. ti a l [31:5] RESERVED 0 [4:0] VID1_MD3: Defines the MD parameter (coarse selection) for the frequency synthesizer channel 3. The MD parameter is defined in the range from -1 to -16 (0x1F to 0x0F). en Frequency synthesizer 1 (VID1) channel 3 fine selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED fid R 9 SYSCFG_BANK3BaseAddress + 0x00000170 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 3 fine selection. [31:15] RESERVED 7 6 5 4 3 2 1 0 VID1_PE3 RW on Address: 8 C Confidential SYSTEM_CONFIG492 [14:0] VID1_PE3: Defines the PE parameter (fine selection) for the frequency synthesizer channel 3. The PE parameter is defined in the range from 0 to 215 - 1. DocID023557 Rev 10 485/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG491 System configuration registers Frequency synthesizer 1 (VID1) channel 3 output divider 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED VID1_SDIV3 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000174 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 3 output divider. ti a l [31:4] RESERVED [3:0] VID1_SDIV3: Defines the SDIV parameter (output divider control) for the frequency synthesizer channel 3. The SDIV parameter can take the values up to 28. en Frequency synthesizer 1 (VID1) channel 3 program enable 8 7 6 5 4 3 2 1 0 VID1_PROG_EN3 9 RESERVED on fid 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W Address: SYSCFG_BANK3BaseAddress + 0x00000178 Type: RW Reset: 0x0000 0000 Description: Frequency synthesizer 1 (VID1) channel 3 program enable. C Confidential SYSTEM_CONFIG494 [31:1] RESERVED [0] VID1_PROG_EN3: Defines the PROG_EN parameter (programming enable) for the frequency synthesizer channel 3. This parameter must be set to 1 to take into account a new configuration. 486/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG493 STiH271EL STiH271EL System configuration registers HDMI PLL configuration register 1 9 8 7 6 5 4 SYSCFG_BANK3BaseAddress + 0x0000017C Type: RW Reset: 0x0000 0000 Description: HDMI PLL configuration register 1. 2 1 0 ti a l Address: 3 en [30] HDMI_FRAC_CONTROL: To activate or deactivate the fractional mode (active high). FRAC_CONTROL = H means fractional multiplication is activated. fid [29:14] HDMI_FRAC_INPUT: Input bits to set the loop division factor (fraction part). [13:8] HDMI_ODF: Input bits to set the output division factor. HDMI PLL configuration register 2 R RW Address: SYSCFG_BANK3BaseAddress + 0x00000180 Type: RW Reset: 0x0000 0000 Description: HDMI PLL configuration register 2. 9 8 7 6 5 4 3 2 1 HDMI_IDF C HDMI_INC_STEP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 HDMI_MODE_PERIOD SYSTEM_CONFIG496 on [7:0] HDMI_NDIV: Input bits to set the loop division factor (integer part). RESERVED Confidential [31] HDMI_PD: PLL power status. 0: PLL is ON, PLL is fully operational. 1: PLL is powered down. PLL is not functional. Current consumption is only due to leakage. RW RW 0 [31] RESERVED DocID023557 Rev 10 487/604 Information classified Confidential - Do not copy (See last page for obligations) HDMI_ODF HDMI_FRAC_INPUT HDMI_PD HDMI_FRAC_CONTROL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 HDMI_NDIV SYSTEM_CONFIG495 System configuration registers STiH271EL [30:16] HDMI_INC_STEP: Configuration input to set the modulation depth (SSCG). [15:3] HDMI_MODE_PERIOD: Configuration input to set the modulation period and modulation depth (SSCG). [2:0] HDMI_IDF: Input bits to set the input division factor. HDMI PLL configuration register 3 RW Reset: 0x0000 0000 Description: HDMI PLL configuration register3. 1 0 RW R W R W R W R W RW fid [31:11] RESERVED on [10:6] HDMI_CP: Input bits to set the charge pump current. [5] HDMI_SSCG_CONTROL: To activate or deactivate the SSCG mode (active high). 1: SSCG is activated. [4] HDMI_SPREAD_CONTROL: Controls the spread type in SSCG mode. 0: Centre-spread 1: Down-spread [3] HDMI_STRB_BYPASS: 1: Bypasses the STRB signal. [2] HDMI_STRB: Asynchronous strobe input to the SSCG controller; a rising edge indicates that a new modulation depth and modulation frequency configuration input is to be loaded. [1:0] HDMI_DITHER_DISABLE: MSB = 1 disables the rectangular PDF dither input to SDM. LSB = 1 disables the triangular PDF dither input to SDM. 488/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Type: 2 HDMI_DITHER_DISABLE ti a SYSCFG_BANK3BaseAddress + 0x00000184 3 en Address: 4 C Confidential R 5 HDMI_STRB 6 HDMI_STRB_BYPASS 7 HDMI_SPREAD_CONTROL 8 HDMI_SSCG_CONTROL 9 l RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 HDMI_CP SYSTEM_CONFIG497 STiH271EL System configuration registers ST40 CPU mask SYSCFG_BANK3BaseAddress + 0x00000188 Type: RW Reset: 0x0000 03FF Description: ST40 CPU mask register. 1 0 R W R W R W R W R W en ti a l Address: 2 Information classified Confidential - Do not copy (See last page for obligations) R W 3 ST40_RST_UDI_OUT_MASK R 4 ST40_RST_MAN_OUT_MASK 5 ST40_RST_PWR_OUT_MASK 6 LPC_WDT_OUT_MASK 7 ST40_PWR_SW_RST_MASK 8 RESERVED 9 [31:6] RESERVED fid [5] ST40_PWR_SW_RST_MASK: ST40 soft reset mask bit. 1: Masked. [4] LPC_WDT_OUT_MASK: LPC watchdog reset mask. 1: Masked. on [3] ST40_RST_WDT_OUT_MASK: ST40 watchdog reset mask. 1: Masked. [2] ST40_RST_PWR_OUT_MASK: ST40 power reset mask. 1: Masked. [1] ST40_RST_UDI_OUT_MASK: ST40 user debug reset mask. 1: Masked. C Confidential 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ST40_RST_WDT_OUT_MASK SYSTEM_CONFIG498 [0] ST40_RST_MAN_OUT_MASK: ST40 manual reset mas. 1: Masked. DocID023557 Rev 10 489/604 System configuration registers STiH271EL ST40 power soft reset n 7 6 5 4 3 2 1 0 ST40_PWR_SOFT_RST_N 8 R R W SYSCFG_BANK3BaseAddress + 0x0000018C Type: RW Reset: 0x0000 0000 Description: ST40 power soft reset n. en ti a l Address: [31:1] RESERVED SYSTEM_CONFIG501 fid [0] ST40_PWR_SOFT_RST_N: ST40 power reset by software, active low. USB PHY control register 0 0 USB_PHY_COMMONONN 1 USB_PHY_COMPDISTUNE0_BIT 2 USB_PHY_COMPDISTUNE1_BIT 3 USB_PHY_OTGDISABLE0_BIT 4 RW RW R W R W RW R W RW RW R W Address: SYSCFG_BANK3BaseAddress + 0x00000194 Type: RW Reset: 0x0000 0080 Description: USB PHY control register 0. 490/604 5 USB_PHY_OTGTUNE0_BIT RW 6 USB_PHY_SLEEPM0_BIT R W 7 USB_PHY_SLEEPM1_BIT R W 8 USB_PHY_SQRXTUNE0_BIT USB_PHY_TXPREEMPHASISTUNE0_BIT R W 9 USB_PHY_SQRXTUNE1_BIT USB_PHY_TXPREEMPHASISTUNE1_BIT R W on USB_PHY_TXRISETUNE0_BIT RW USB_PHY_TXFSLSTUNE0_BIT USB_PHY_TXRISETUNE1_BIT R C USB_PHY_TXVREFTUNE0_BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Confidential 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG499 STiH271EL System configuration registers [31] RESERVED ti a l [26] USB_PHY_TXRISETUNE1_BIT: Port 1 HS transmitter rise/fall time adjustment. This bus adjusts the rise/fall times of the high-speed waveform. 0: Design default 1: -8% en [24] USB_PHY_TXPREEMPHASISTUNE1_BIT: Port 1 HS transmitter pre-emphasis enable. This signal controls the pre-emphasis for a J-K or K-J state transition in HS mode. 0: Design default. The HS transmitter pre-emphasis is disabled. 1: The HS transmitter pre-emphasis is enabled. fid [23] USB_PHY_TXPREEMPHASISTUNE0_BIT: Port 0 HS transmitter pre-emphasis enable. This signal controls the pre-emphasis for a J-K or K-J state transition in HS mode. 0: Design default. The HS transmitter pre-emphasis is disabled. 1: The HS transmitter pre-emphasis is enabled. on [22:19] USB_PHY_TXFSLSTUNE0_BIT: Port 0 FS/LS Source Impedance Adjustment. This bus adjusts the low- and full-speed single-ended source impedance while driving high. The following adjustment values are based on nominal process, voltage, and temperature. 0000: +5% 0001: +2.5% 0011: Design default 0111: -2.5% 1111: -5% C Confidential [25] USB_PHY_TXRISETUNE0_BIT: Port 0 HS transmitter rise/fall time adjustment. This bus adjusts the rise/fall times of the high-speed waveform. 0: Design default 1: -8% [18:16] USB_PHY_SQRXTUNE1_BIT: Port 1 squelch threshold adjustment. This bus adjusts the voltage level for the threshold used to detect valid high-speed data. 000: +15% 001: +10% 010: +5% 011: Design default 100: -5% 101: -10% 110: -15% 111: -20% [15:13] USB_PHY_SQRXTUNE0_BIT: Port 0 squelch threshold adjustment. This bus adjusts the voltage level for the threshold used to detect valid high-speed data. 000: +15% 001: +10% 010: +5% 011: Design default 100: -5% 101: -10% 110: -15% 111: -20% [12] USB_PHY_SLEEPM1_BIT: Port 1 sleep assertion. 0: Sleep mode 1: Normal operation [11] USB_PHY_SLEEPM0_BIT: Port 0 sleep assertion. 0: Sleep mode 1: Normal operation DocID023557 Rev 10 491/604 Information classified Confidential - Do not copy (See last page for obligations) [30:27] USB_PHY_TXVREFTUNE0_BIT: Port 0 HS DC voltage level adjustment. This bus adjusts the high-speed DC level voltage. 0000: -10% 0001: -8.75% 0010: -7.5% 0011: -6.25% 0100: -5% 0101: -3.75% 0110: -2.5% 0111: -1.25% 1000: Design default 1001: +1.25% 1010: +2.5% 1011: +3.75% 1100: +5% 1101: +6.25% 1110: +7.5% 1111: +8.75% System configuration registers STiH271EL [10:8] USB_PHY_OTGTUNE0_BIT: VBUS valid threshold adjustment. This bus adjusts the voltage level for the VBUS valid threshold. 000: -12% 001: -9% 010: -6% 011: -3% 100: Design default 101: +3% 110: +6% 111: +9% l [6:4] USB_PHY_COMPDISTUNE1_BIT: Port 1 disconnect threshold adjustment. This bus adjusts the voltage level for the threshold used to detect a disconnect event at the host. 000: -6% 001: -4.5% 010: -3% 011: -1.5% 100: Design default 101: +1.5% 110: +3% 111: +4.5% en fid [0] USB_PHY_COMMONONN: Common block power down control. 0: In suspend mode, the XO, bias, and PLL blocks remain powered in suspend mode. In sleep mode, if the reference clock is a crystal, the XO block remains powered. 1: In suspend mode, the XO, bias, and PLL blocks are powered down. In sleep mode, the bias and PLL blocks are powered down. on SYSTEM_CONFIG502 USB PHY control register 1 4 3 2 1 USB_PHY_TXVREFTUNE1_BIT 5 USB_PHY_TXFSLSTUNE1_BIT 6 USB_PHY_TXHSXVTUNE0_BIT 7 USB_PHY_TXHSXVTUNE1_BIT 8 R RW RW RW RW Address: SYSCFG_BANK3BaseAddress + 0x00000198 Type: RW Reset: 0x0000 0000 Description: USB PHY control register 1. 492/604 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C Confidential ti a [3:1] USB_PHY_COMPDISTUNE0_BIT: Port 0 disconnect threshold adjustment. This bus adjusts the voltage level for the threshold used to detect a disconnect event at the host. 000: -6% 001: -4.5% 010: -3% 011: -1.5% 100: Design default 101: +1.5% 110: +3% 111: +4.5% DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) [7] USB_PHY_OTGDISABLE0_BIT: OTG block disable. 0: OTG block is powered up 1: OTG block is power down STiH271EL System configuration registers [31:12] RESERVED [11:10] USB_PHY_TXHSXVTUNE1_BIT: Port 1 transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode. 00: Reserved 01: -15 mV 10: +15 mV 11: Default setting on fid en [3:0] USB_PHY_TXVREFTUNE1_BIT: Port 1 HS DC voltage level adjustment. This bus adjusts the high-speed DC level voltage. 0000: -10% 0001: -8.75% 0010: -7.5% 0011: -6.25% 0100: -5% 0101: -3.75% 0110: -2.5% 0111: -1.25% 1000: Design default 1001: +1.25% 1010: +2.5% 1011: +3.75% 1100: +5% 1101: +6.25% 1110: +7.5% 1111: +8.75% C Confidential ti a l [7:4] USB_PHY_TXFSLSTUNE1_BIT: Port 1 FS/LS source impedance adjustment. This bus adjusts the low- and full-speed single-ended source impedance while driving high. The following adjustment values are based on nominal process, voltage, and temperature. 0000: +5% 0001: +2.5% 0011: Design default 0111: -2.5% 1111: -5% DocID023557 Rev 10 493/604 Information classified Confidential - Do not copy (See last page for obligations) [9:8] USB_PHY_TXHSXVTUNE0_BIT: Port 0 transmitter high-speed crossover adjustment. This bus adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode. 00: Reserved 01: -15 mV 10: +15 mV 11: Default setting System configuration registers STiH271EL Compensation digital 5 configuration COMP_DIG5_RASRC0 COMP_DIG5_FREEZE COMP_DIG5_COMPTQ COMP_DIG5_COMPEN 0 COMP_DIG5_RASRC1 1 COMP_DIG5_RASRC2 2 R W R W R W R W R W R W R W R W R W R W R W Type: RW Reset: 0x0000 0000 Description: Compensation digital 5 configuration register. ti a l SYSCFG_BANK3BaseAddress + 0x0000019C en [31:11] RESERVED [10] COMP_DIG5_TQ: 0: Normal mode 1: To enable IDDQ mode Confidential 3 R Address: fid [9] COMP_DIG5_RASRC6: Seventh bit of the digital input code. [8] COMP_DIG5_RASRC5: Sixth bit of the digital input code. [7] COMP_DIG5_RASRC4: Fifth bit of the digital input code. on [6] COMP_DIG5_RASRC3: Fourth bit of the digital input code. [5] COMP_DIG5_RASRC2: Third bit of the digital input code. [4] COMP_DIG5_RASRC1: Second bit of the digital input code. [3] COMP_DIG5_RASRC0: First bit of the digital input code. C [2] COMP_DIG5_FREEZE: To enable freeze mode. [1] COMP_DIG5_COMPTQ: To select operation mode. Use this bit with bit[0]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode [0] COMP_DIG5_COMPEN: To select operation mode. Use this bit with bit[1]. 00: Normal mode 01: High impedance mode 10: Fixed code mode 11: Read mode 494/604 4 COMP_DIG5_RASRC3 5 COMP_DIG5_RASRC4 6 COMP_DIG5_RASRC5 7 COMP_DIG5_RASRC6 8 COMP_DIG5_TQ 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG503 STiH271EL System configuration registers Compensation status register 5 9 8 7 6 5 4 SYSCFG_BANK3BaseAddress + 0x000001A0 Type: R Reset: 0x0000 0000 Description: Compensation status register 5. 2 1 0 [31:8] RESERVED ti a l Address: 3 COMP_DIG5_NASRC RESERVED COMP_DIG5_COMP_OK 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 en [7] COMP_DIG5_COMP_OK: Compensation OK for digital. fid SYSTEM_CONFIG509 EMI_DVBCIREG selection register 8 7 6 5 4 3 2 1 0 DVBCI_REG 9 RESERVED on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R R W Address: SYSCFG_BANK3BaseAddress + 0x000001B4 Type: RW Reset: 0x0000 0000 Description: EMI_DVBCIREG selection on EMI_DVBCIREG_PAD. Write 1 for EMI_DVBCIREG. C Confidential [6:0] COMP_DIG5_NASRC: Compensation NASRC for digital. [31:1] RESERVED [0] DVBCI_REG: 1: This bit is used for DVBCI_REG DocID023557 Rev 10 495/604 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_STATUS504 System configuration registers STiH271EL HDMI PHY transmitter sink current correction 3 2 1 0 HDMIPHY_ISNKCRCNCH0 4 HDMIPHY_ISNKCRCNCHCK 5 HDMIPHY_ISNKCRCNCH1 6 HDMIPHY_ISNKCRCNCH2 7 RW RW RW RW Type: RW Reset: 0x0000 0000 Description: HDMI PHY transmitter sink current correction. [31:8] RESERVED [7:6] HDMIPHY_ISNKCRCNCH2: 00: No correction01: +5% 10: -5%11: -10% fid en ti a l SYSCFG_BANK3BaseAddress + 0x000001B8 Confidential 8 R Address: [5:4] HDMIPHY_ISNKCRCNCH1: 00: No correction01: +5% 10: -5%11: -10% on [3:2] HDMIPHY_ISNKCRCNCHCK: 00: No correction01: +5% 10: -5%11: -10% C [1:0] HDMIPHY_ISNKCRCNCH0: 00: No correction01: +5% 10: -5%11: -10% 496/604 9 RESERVED 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SYSTEM_CONFIG510 STiH271EL External circuitry recommendations 20 External circuitry recommendations 20.1 Power supplies 20.1.1 Decoupling recommendations Power supply sequencing l 20.1.2 20.2 ti a There are no specific power supply sequence operations to be followed for the STiH271EL. System en The system oscillator recommended external circuitry is shown in Table 48. Confidential Figure 48. Oscillators recommended external circuitry fid CL2 on GND 20.3 STiH271EL SYS_CLKOSC Rs C CL1 SYS_CLKIN On-chip voltage sensing feedback The CORESENSE_DVDD1V1 signal is used to provide loopback information on the on-die core supply voltage to an external voltage regulator. The CORESENSE_DGND1V1 signal is used to monitor noise on ground for the debug purpose only. The LMIVSENSE_VDD1V5 signal is used to provide loopback information on the on-die LMI supply voltage to an external voltage regulator. DocID023557 Rev 10 497/604 Information classified Confidential - Do not copy (See last page for obligations) The decoupling capacitor values must be carefully considered and fully simulated prior to the board design cycle. All *DECAP* balls are dedicated for decoupling capacitance. They are internally connected to the specified supply so that there is no need to connect them to the specified supply at the board level. External circuitry recommendations 20.4 STiH271EL JTAG The JTAG external recommended connections are shown in Figure 49. Figure 49. JTAG recommended connections VDD3V3 10k l 47 ti a NOT_RST SYS_AONOTRESETIN 10k en Board power-on reset If there is a lot of noise on the clock line, a capacitor in the range 10 pF to 100 pF can be fitted between TCK and ground near the target STiH271EL, however this may limit the maximum TAP clock rate. 20.5 Video analog output interface on fid Note: There is a one quad video DAC for HD and SD output. It is a high-performance 10-bit digital to analog converter, and consist of four 10-bit DAC modules joined together. A reference circuit controlled by one external resistor sets the full-scale output for each DAC set. Each DAC is able to drive 35 mA. C Confidential STiH271EL JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK JTAG_NOTTRST SYS_NOTASEBRK 47 TDI TDO TMS TCK NOT_TRST NOTASEBRK The blocks require an external precision resistor (Rref) to be connected between VDAC_REXTP and VDAC_REXTN to provide a band-gap reference. The block's analog current sources provide a voltage output range of 1.4 V with an optimum linearity through an external precision resistor (Rload) connected between all outputs and the analog ground. Output level may be calculated as: VOUT = [DIN] x 0.0625 x [(VDAC_REXTP - VDAC_REXTN)/Rref] x Rload Where, VDAC_REXTP - VDAC_REXTN = VbandGap = 1.202 V DIN = Code value in decimal Rref = reference resistor Rload = load resistor 498/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Host device STiH271EL External circuitry recommendations Table 80. Voltage output range parameters Parameter 20.6 Value Rref Optimum value 2.05 k 1% Rload Optimum value 37.5 1%. HDMI interface l Audio analog interface ti a 20.7 The audio DAC provides voltage outputs for each channel. The following figure describes a typical audio output gain stage for the STiH271EL. en 3n3 C7 fid R5 AUD_L+ C2 AUD_R+ C3 3 IN1+ 1 OUT1 on R4 16 K 43 K U79 ADAC_VCM 2 1 F IN1C5 4.7 F 16 V AUD_LEFT 5 R3 16 K C Confidential Figure 50. VRMS external audio analog schematic with +9V power supply IN2+ 7 OUT2 6 1 F IN2- +9V_ADAC_VCC C6 +9V_ADAC_VCC 8 4.7 F 16 V VCC+ 4 VCC- C8 100 nF AUD_RIGHT TSH72CD +9V_ADAC_VCC R6 43 K C4 3n3 R2 47 K ADAC_VCM C1 R1 10 F 47 K DocID023557 Rev 10 499/604 Information classified Confidential - Do not copy (See last page for obligations) For PCB design guidelines, refer to the `HDMI PCB design guidelines' document. For access to this internal document please contact your local ST representative. External circuitry recommendations 20.8 STiH271EL USB interface The USB external recommended connections are shown in Figure 51. Figure 51. USB 2.0 application circuit +5 V Power switch Input EN1 EN2 GND STiH271EL USB POWER EN OUT1 NOC1 OUT2 NOC2 ti a USB VBUS 400 mV (High speed), 3.3 V (Low speed and full speed) fid 43.2 DP GND SHIELD SHIELD Shield 20.9 on Please contact your local ST representative to access application notes describing USB PCB design guidelines. Ethernet PHY The following sub-sections give the connection diagrams for each of the Ethernet modes. Refer to Section 8.13.2 for detailed information about the relevant PIO and ball locations. C Confidential DM 400 mV (High speed), 3.3 V (Low speed and full speed) en USB_DM USB_DP USB_TXRTUNE Please contact your local ST representative to access application note describing crystal specifications (DM00055355: Single port 10/100 MII/RMII/TP fast Ethernet transceiver). 500/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) l USB OVRCUR DET STiH271EL 20.9.1 External circuitry recommendations MII mode MII mode is used for the internal connection between the ethernet MAC and the internal ethernet PHY. This internal connection is also available externally to be used to connect to an external PHY as an alternative (not in addition to) the internal PHY. Note: If the internal PHY is being used the GPIOs/alternate functions associated with the MII interface (see Table 20) are not available to be used in the application. Figure 52. Ethernet MII mode (drv_clk_ethernet) l phy_tx_clk SYSTEM_CONFIG23.ETH_ENMII = 1 25 MHz crystal A 1 2 TX_clk tx_clk RX_clk rx_clk fid phy_rx_clk mdc MDC mdc PHY (external) Table 81. on 1. Ethernet PHY-clock PIO is PIO2[3] for GMAC. MII and MII overdrive (TMII) configuration Clock source and rate (MHz) Mode C Confidential C ti a en GMAC phy_rmii_clk Ext. osc. B CLK_ETHERNET CLK_ETHERNET Ext Osc Routing (c = closed) Ethernet PHY A B C D drv_clk_ethernet MII external clock - - 25 c - - - no MII internal clock 25 - - - - c - yes MII overdrive external clock - 25-50 - - c c - no MII overdrive internal clock 25-50 - - - - c - yes DocID023557 Rev 10 501/604 Information classified Confidential - Do not copy (See last page for obligations) PIO o/e (1) External circuitry recommendations 20.9.2 STiH271EL RMII (reduced MII) mode The Ethernet controller subsystem also supports an RMII protocol to interface to an external RMII-based PHY. The RMII specification has been optimized for use in high port density interconnect devices, which require independent treatment of the data paths. A single synchronous reference clock for transmit, receive, and control is used. Alternatively, the clock reference could be sourced from an external device. Each PHY provides a clock reference input. However, only one input is required for multiple PHYs on a single IC. ti a (drv_clk_ethernet) mac_speed en clk_ethernet Confidential A 1 2 N/C tx_clk N/C phy_rx_clk on C sclk phy_tx_clk SYSTEM_CONFIG23.ETH_ENMII = 0" Ext. osc. 25 MHz crystal fid phy_rmii_clk D 50 MHz 25 / 2.5 MHz /2 /20 GMAC B rx_clk mdc mdc MDC PHY (external) 1. Ethernet PHY-clock PIO is PIO2[3] for GMAC. Table 82. C 2. sclk is ETHPHY_RXCLK if the PHY is the RMII reference clock source. sclk is ETHPHY_TXCLK if CLK_ETHERNET is the RMII reference clock source. RMII configuration Clock source and rate (MHz) Mode CLK_ETHERNET Ext Osc Ethernet PHY RMII external clock - 50 - RMII internal clock 50 - - 502/604 DocID023557 Rev 10 Routing (c = closed) A B c C D drv_clk_ethernet c no c yes Information classified Confidential - Do not copy (See last page for obligations) PIO o/e (1) l Figure 53. Ethernet RMII mode STiH271EL Electrical specifications 21 Electrical specifications 21.1 Absolute maximum ratings Absolute maximum ratings Parameter Min Typ Max Units VDD3V3 Digital 3.3 V operating voltage -0.5 - 3.9 V VDD2V5 Analog 2.5 V operating voltage -0.5 - 3.9 V VDD1V5 Digital 1.5 V operating voltage -0.5 - 3.9 V VDD1V2 Digital 1.2 V operating voltage -0.5 - 1.9 V VDD1V1 Digital 1.1 V operating voltage - 1.5 V ti a l Symbol / pin name Electrostatic discharge voltage VESD_RCDM Electrostatic discharge voltage (RCDM)(1) Class 1C Class II en VESD_HBM -0.5 (HBM)(1) These AMR values are applicable to all pins powered to the given voltage. 2 These are maximum limits. Exceeding them may result in permanent damage to the device. Operation at these limits is not intended. 21.2 fid 1 Operating conditions on Note: Adaptive voltage scaling (AVS) makes it possible to control power consumption by reducing very significantly the core power supply voltage. The core voltage (VDD1V1) is the main contributor to power consumption. Using AVS, the core voltage is controlled and adjusted by a PWM signal. The AVS adjustment is dependent upon silicon process, and is used to optimize the performance : consumption ratio. C Confidential 1. For a definition of the ESD classes, refer the relevant JEDEC standards, or contact STMicroelectronics customer support. For more details on AVS implementation, refer to the application note: Adaptive voltage scaling on Liege family products (DM00070070). Table 84. Operating conditions Symbol / pin name Parameter Min Typ Max Units VDD3V3 Digital 3.3 V operating voltage 3.00 3.30 3.60 V VDD2V5 Analog 2.5 V operating voltage 2.25 2.50 2.60 V VDD1V5 Digital 1.5 V operating voltage 1.425 1.50 1.575 V Digital 1.1 V operating voltage(1) 1.05 1.10 1.15 V VDD1V1 with AVS Digital 1.1 V operating voltage(1) 1.00 1.05 1.10 V VDD1V2 1.2 V operating voltage 1.14 1.20 1.26 V I3V3 Digital 3.3 V current - 0.07 0.10 A I2V5 Analog 2.5 V current - 0.28 0.29 A VDD1V1 without AVS DocID023557 Rev 10 503/604 Information classified Confidential - Do not copy (See last page for obligations) Table 83. Electrical specifications Symbol / pin name Parameter Min Typ Max Units I1V5 Digital 1.5 V current - 0.18 0.20 A I1V1 without AVS Digital 1.1 V core current without AVS - 1.17 1.47 A I1V2-DVBC (IF) Digital 1.2 V current - 0.04 0.05 A I1V2-DVBT (IF) Digital 1.2 V current - 0.10 0.12 A (2) P3V3 Digital 3.3 V power consumption - 0.24 0.36 W P2V5 Analog 2.5 V power consumption - 0.69 0.75 W P1V5 Digital 1.5 core power consumption - 0.27 0.32 W P1V1 without AVS Digital 1.1 core power consumption - 1.29 1.69 W - - 1.26 W Digital 1.1 core power P1V2-DVBC Digital 1.2 core power consumption - l 0.05 0.06 W P1V2-DVBT Digital 1.2 core power consumption - 0.12 0.14 W PD-DVBC (IF) without AVS Full power consumption without AVS - 2.54 3.18 W PD-DVBT (IF) without AVS Full power consumption without AVS - 2.61 3.26 W PD-DVBC (IF) with AVS Full power consumption with AVS - - 2.75 W PD-DVBT (IF) with AVS Full power consumption with AVS - - 2.83 W RthJA Junction-to-ambient thermal resistance (mounted on recommended PCB)(3) - 17.00 - C/W TA Operating ambient temperature 0 - 70 C - 125(4) C fid TJUNCTION ti a P1V1 with AVS en consumption(2) Operating temperature (junction) - on 1. The value of the power supply voltage connected to circuits inside the STiH271EL (the Vcore voltage) is not the same as the power voltage connected to the external pins of the STiH271EL. This is because there are resistive losses in the power supply connections. To compensate for these losses and to check that the Vcore voltage matches the conditions under which the STiH271EL has been characterized, you must use the two pins CORESENSE_DVDD1V1 (ball C32) and CORESENSE_DGND1V1 (ball D30). CORESENSE_DVDD1V1 is connected to the lowest value of on-chip VDD; CORESENSE_DGND1V1 is connected to the highest value of on-chip GND. The voltage difference between these two pins must reflect the range of values shown in the table. 2. The power consumption depends on chip activity and silicon temperature. Silicon temperature depends on the PCB layout. The values in this table are measured in the ST application environment and may vary from one application to another. - Typical values correspond to the power consumption for standard parts with typical operating conditions. - Maximum values correspond to worse-case process/voltage/temperature. 3. The reported RthJA has been measured using an FR4 board and must be considered only as an approximate indication. The thermal performance of the electronic package can vary significantly depending on board design, size, thickness, material and other physical factors. 4. Maximum value in worse-case conditions with AVS. 504/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Operating conditions (continued) C Confidential Table 84. STiH271EL STiH271EL Electrical specifications 21.3 Audio DAC 21.3.1 Operating conditions Table 85. Pin name Parameter Min Typ Max Units ADAC_VDD3V3 Analog power supply 3.00 3.30 3.60 V Min Typ Max Units - - 730 - 1.45 - V 100 pF Specifications Table 86. Specifications of audio DAC Analog RMS output(1) Analog output common mode Cmax en Output load ti a l Parameter k 10 1. Analog output RMS depends on external load resistance. Quad DAC Table 87. Static electrical performance Rref = 2.05 k; Rload = 37.5 on 21.4 fid Output voltage = (0.73 x RL)/(RL + 500) Vrms Symbol Iout Rref = 2.05 k Parameter DAC output current Min Typ Max Unit 36.98 - 38.0 mA C Confidential Rmin mVrms 21.5 DDR electrical characteristics 21.5.1 Limiting values Table 88. Symbol VDDE DDR limiting values Parameter 1.5 V pad supply voltage Conditions DDR III mode DocID023557 Rev 10 Min Typ Max Unit - 1.5 - V 505/604 Information classified Confidential - Do not copy (See last page for obligations) 21.3.2 Operating conditions Electrical specifications 21.5.2 STiH271EL General electrical specifications Table 89. General electrical specifications Symbol Rref 21.6 Parameter Min Typ Max Unit External reference resistor (from refers pin to the VDD_PLL pin) -1% 487 +1% Ohm External memory interface (EMI) Parameter Min Typical Max Units Notes 2.0 - VDD3V3 + 0.5 V - -0.5 - 0.8 V - VDD3V3 0.2 - - V (1) - - 0.2 V (2) VIL Input logic 0 voltage VOH Output logic 1 voltage VOL Output logic 0 voltage RPU Equivalent pull-up resistance - 50 - k - RPD Equivalent pull-down resistance - 50 - k - IIN Input leakage current (input pin) - - 4 A (3) CIN Input capacitance - - 10 pF - C 1. IOUT = -8 mA en Input logic 1 voltage fid VIH on Confidential Symbol 2. IOUT = 8 mA 3. 0 Vin VDD3V3 506/604 l TTL-mode 3V3 EMI pads DC specifications ti a Table 90. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The EMI pads are TTL dual-mode. TTL electrical specifications are shown in Table 90. STiH271EL USB USB operating conditions Symbol / pin name Min Typ Max Unit 3.0 3.3 3.6 V USB_VDD2V5 Analog supply voltage 2.3 2.5 2.7 V VLFS-cm Low and full speed mode input common mode level 800 - 2500 mV VHS-cm High speed mode input common mode level -50 200 500 mV Vchirp-cm Chirp mode input common mode level -50 - 600 mV Vdiff Differential input signal amplitude 100 400 1100 mV Min Typ Max Unit Notes 3V3 IO pads Table 92. l Analog supply voltage ti a USB_VDD3V3 3V3 electrical specifications Parameter fid Symbol High level input voltage 2 - - V - VIL Low level input voltage - - 0.8 V - VHYST Input hysteresis voltage 300 - - mV - VOH High level output voltage VDDE3V3 - 0.3 - - V (1) VOL Low level output voltage - - 0.3 V (2) IPU Pull-up current (conditions Vi = 0 V) 39 66 101 A - Ipd Pull-down current (conditions Vi=VDDE3V3) 33 66 120 A - RPU Equivalent pull-up resistance (conditions Vi = 0 V) 36 50 76 k - RPD Equivalent pull-down resistance (conditions Vi = VDDE3V3) 30 50 90 k - on VIH C Confidential 21.8 Parameter 1. IOUT = -6mA 2. IOUT = 6mA DocID023557 Rev 10 507/604 Information classified Confidential - Do not copy (See last page for obligations) Table 91. en 21.7 Electrical specifications Timing specifications STiH271EL 22 Timing specifications 22.1 JTAG interfaces AC specification Input clocks: TCK (rising edge) Inputs: TDI, TMS Figure 54. JTAG interfaces waveforms tTAPHCLK Inputs en Confidential tTAPSCLK Table 93. Min Max Units tTAPCLK TCK period 20 - ns tTAPSCLK Input setup to TCK rising edge 5 - ns Input hold from TCK rising edge 5 - ns TDO output delay from TCK falling edge - 15 ns C on Parameter tPTAPCLK 508/604 JTAG input/output port timings Symbol tTAPHCLK tPTAPCLK fid TDO ti a l TCK DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) tTAPCLK STiH271EL Timing specifications 22.2 Transport stream 22.2.1 Serial input AC specification Transport timing can be against either rising or falling clock edge. Input clocks: TSINBYTECLK Inputs: TSINBYTECLKVALID, TSINERROR, TSINPACKETCLK, TSINDATA Figure 55. Transport stream serial input waveforms ti a l TSINBYTECLK Inputs tTSSCLK Transport input serial ports AC timings Parameter Min Max Units tTSINBYTECLK TSINBYTECLK period 10.0 - ns tTSSCLK Input setup to TSINBYTECLK 2.0 - ns tTSHCLK Input hold from TSINBYTECLK 1.5 - ns fid Symbol on 22.2.2 en Table 94. Parallel input AC specification Transport timing can be against either rising or falling clock edge. C Confidential tTSHCLK Input clock: TSINBYTECLK Inputs: TSINBYTECLKVALID, TSINERROR, TSINPACKETCLK, TSINDATA[7:0] Figure 56. Transport stream parallel input waveforms tTSINBYTECLK TSINBYTECLK tTSSCLK Inputs tTSHCLK DocID023557 Rev 10 509/604 Information classified Confidential - Do not copy (See last page for obligations) tTSINBYTECLK Timing specifications STiH271EL Table 95. 22.2.3 Transport input parallel ports AC timings Symbol Parameter Min Max Units tTSINBYTECLK TSINBYTECLK period 37.0 - ns tTSSCLK Input setup to TSINBYTECLK 5.0 - ns tTSHCLK Input hold from TSINBYTECLK 5.0 - ns Serial output AC specification Transport timing can be against either rising or falling clock edge. l Outputs: TSOUTBYTECLKVALID, TSOUTERROR, TSOUTPACKETCLK, TSOUTDATA ti a Figure 57. Transport stream output waveforms tTSOUTBYTECLK Confidential en TSOUTBYTECLK tTSSCLK Transport stream output timings Parameter Min Max Units tTSOUTBYTECLK TSOUTBYTECLK clock period 10 - ns tTSSCLK Output setup to TSOUTBYTECLK 2 - ns Output hold from TSOUTBYTECLK 1.5 - ns C Symbol tTSHCLK 22.2.4 tTSHCLK on Table 96. fid Outputs Parallel output AC specification Transport timing can be against either rising or falling clock edge. Output clock: TSOUTBYTECLK Outputs: TSOUTBYTECLKVALID, TSOUTERROR, TSOUTPACKETCLK, TSOUTDATA[7:0] 510/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Output clock: TSOUTBYTECLK STiH271EL Timing specifications Figure 58. Transport stream output waveforms tTSOUTBYTECLK TSOUTBYTECLK tTSSCLK Outputs tTSHCLK Min Max Units tTSOUTBYTECLK TSOUTBYTECLK clock period 37 - ns tTSSCLK Output setup to TSOUTBYTECLK 5 - ns tTSHCLK Output hold from TSOUTBYTECLK 5 - ns en HDMI AC specification PIO output AC specification Reference clock in this case means the last transition of any PIO signal. on 22.4 fid Please refer to the HDMI v1.2 specification. Figure 59. PIO output waveforms PIO reference clock tPCHPOV PIOOUT tPCHWDZ PIOOUT Table 98. PIO SSC output AC timings Symbol Parameter Min Max Units tPCHPOV PIO_REFCLOCK high to PIO output valid -20.0 0.0 ns tPCHWDZ PIO tristate after PIO_REFCLOCK high -20.0 5.0 ns tPIOr Output rise time 3.0 30.0 ns tPIOf Output fall time 3.0 30.0 ns DocID023557 Rev 10 511/604 Information classified Confidential - Do not copy (See last page for obligations) Parameter ti a Symbol C Confidential 22.3 Transport stream output timings l Table 97. Timing specifications Table 99. PIO other outputs AC timings Symbol Parameter Min Max Units tPCHPOV PIO_REFCLOCK high to PIO output valid -6.0 0.0 ns tPCHWDZ PIO tristate after PIO_REFCLOCK high -6.0 5.0 ns tPIOr Output rise time 1.0 7.0 ns tPIOf Output fall time 1.0 7.0 ns LMI DDR3-SDRAM timings PCM audio 22.6.1 Input en 22.6 ti a l For DDR3 SDRAM, refer to the JESD79-3F of July 2012, specifically sections 12 and 13 regarding electrical characteristics and AC timing. fid Confidential The audio inputs are characterized with respect to the AUDSCLKIN input clock (rising edge). They are clocked on the rising edge of this clock. Data is generated on the falling edge of AUDSCLKIN. Figure 60. Audio input AC waveforms on AUDSCLKIN tDTSSTR C AUDDATAIN tDTHSTR tLRSSTR AUDLRCLKIN tLRHSTR Table 100. Audio input port timings 512/604 Symbol Parameter Min Max Units tDTHSTR AUDDATAIN setup to AUDSCLKIN rising edge 5 - ns tDTSSTR AUDDATAIN hold from AUDSCLKIN rising edge 5 - ns tLRHSTR AUDLRCLKIN setup to AUDSCLKIN rising edge 5 - ns tLRSSTR AUDLRCLKIN hold from AUDSCLKIN rising edge 5 - ns DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) 22.5 STiH271EL STiH271EL 22.6.2 Timing specifications Output specification Output clock: AUDPCMCLKOUT Outputs: AUDPCMOUT[1:0], AUDLRCLKOUT Figure 61. Audio output waveforms tPCMCLK AUDPCMCLKOUT Max Units tPCMCLK AUDPCMCLKOUT clock period 66 - ns tPCMSCLK Output delay from AUDPCMCLKOUT rising edge - 5 ns tSCLKPCM Output delay to AUDPCMCLKOUT rising edge - 5 ns en Min fid Parameter Ethernet interface AC specification on 22.7 Symbol MII (standard 25 MHz Ethernet 10/100 Mbit/s) complies with IEEE802.3 standard, section 2, clause 22. RMII (reduced MII) complies with RMII specification, v1.2 (March 20, 1998) released by the RMII consortium. 22.8 C Confidential Table 101. Audio output port timings ti a l Outputs USB AC specification The USB interface is compliant to the USB 2.0 specifications. DocID023557 Rev 10 513/604 Information classified Confidential - Do not copy (See last page for obligations) tPCMSCLK tSCLKPCM Timing specifications STiH271EL 22.9 Serial Flash controller interface 22.9.1 Input Input clocks: SPI_CLK (rising edge) Inputs: SPI_DI, SPI_DO, SPI_HOLD, SPI_WRPROTECT Figure 62. Serial Flash controller Flash input waveforms tSPICLK tSPIHCLK ti a l tSPISCLK Inputs Table 102. Serial Flash controller input ports AC timings en SPI CLK period tSPISCLK Input setup to SPI CLK rising edge tSPIHCLK Input hold from SPI CLK rising edge fid tSPICLK Output Min Max Units 20.0 - ns 2.0 - ns 5.0 - ns on 22.9.2 Parameter Output clocks: SPI_CLK (rising edge) Outputs: SPI_DI, SPI_DO, SPI_HOLD, SPI_WRPROTECT, SPI_NOTCS Figure 63. Serial Flash controller output waveforms C Confidential Symbol tSPICLK SPI CLK tSPISCLK tSPIHCLK Outputs Table 103. Serial Flash controller output ports AC timings Symbol 514/604 Parameter Min Max Units tSPICLK SPI CLK period 20.0 - ns tSPISCLK Output setup to SPI CLK rising edge 2.0 - ns tSPIHCLK Output hold from SPI CLK rising edge 5.0 - ns DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) SPI CLK STiH271EL Timing specifications 22.10 MMC interface 22.10.1 Input Conforms to SD-card Part 1 Physical layer specification v2.0. Input clocks: MMC_CLK Inputs: MMC_DATA[7:0], MMC_CMD Figure 64. MMC input waveforms tMMC_CLK ti a tMMC_HCLK tMMC_SCLK Inputs MMC_CLK period tMMC_SCLK tMMC_HCLK Output Max Units 20.0 - ns Input setup to MMC_CLK rising edge 6.0 - ns Input hold from MMC_CLK rising edge 2.0 - ns fid tMMC_CLK Min on 22.11 Parameter Output clocks: MMC_CLK Outputs: MMC_DATA[7:0], MMC_CMD C Confidential Symbol en Table 104. MMC input ports AC timings Figure 65. MMC output waveforms tMMC_CLK MMC_CLK tMMC_SCLK tMMC_HCLK Outputs Table 105. MMC output ports AC timings Symbol Parameter Min Max Units tMMC_CLK MMC_CLK period 20.0 - ns tMMC_SCLK Output setup to MMC_CLK rising edge 6.0 - ns tMMC_HCLK Output hold from MMC_CLK rising edge 2.5 - ns DocID023557 Rev 10 515/604 Information classified Confidential - Do not copy (See last page for obligations) l MMC_CLK PIO port registers 23 Caution: STiH271EL PIO port registers Register bits that are shown as reserved must not be modified by software as this will cause unpredictable behavior. Each 8-bit PIO port has a set of eight-bit registers. Each of the eight bits of each register refers to the corresponding pin in the corresponding port. Register addresses are provided as PIOnBaseAddress + offset 0x00 PIOn_POUT 0x04 PIOn_SET_POUT 0x08 PIOn_CLR_POUT 0x10 PIOn_PIN 0x20, 0x30, 0x40 PIOn_PCx 0x24, 0x34, 0x44 Description l Register name ti a Offset Page page 517 Set bits of POUT page 517 Clear bits of POUT page 517 PIO input page 518 PIO configuration page 518 PIOn_SET_PCx Set bits of PC[2:0] page 519 0x28, 0x38, 0x48 PIOn_CLR_PCx Clear bits of PCx page 519 0x50 PIOn_PCOMP PIO input comparison page 520 0x54 PIOn_SET_PCOMP Set bits of PCOMP page 520 0x58 PIOn_CLR_PCOMP Clear bits of PCOMP page 521 PIOn_PMASK PIO input comparison mask page 521 PIOn_SET_PMASK Set bits of PMASK page 521 PIOn_CLR_PMASK Clear bits of PMASK page 522 0x60 0x68 C 0x64 fid en PIO output on Confidential Table 106. PIO_port registers list The PIO registers described in this chapter are used only when the PIOs are used for their primary function. Control of the PIOs when used for their alternate functions is exercised by the system configuration registers. Refer to Chapter 19: System configuration registers for a description of the relevant system configuration registers. 516/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Refer to Chapter 11: Memory and on-chip peripherals address map on page 286 for details of the PIO register base addresses. STiH271EL PIO port registers PIOn_POUT 7 PIO output 6 5 4 3 2 1 0 POUT[7:0] Address: PIOnBaseAddress + 0x00 Type: RW Reset: 0x0 ti a [7:0] POUT[7:0]: Bit 7 to 0 of output data for port. PIOn_SET_POUT 6 5 4 3 2 1 0 en 7 Set bits of POUT PIOnBaseAddress + 0x04 Type: W Description: This register allows the bits of PIOn_POUT to be set individually. fid Address: on [7:0] SET_POUT[7:0]: 0: Leaves the corresponding bit unchanged. 1: Sets the corresponding bit in the PIOn_POUT register. PIOn_CLR_POUT 7 6 C Confidential SET_POUT[7:0] 5 Clear bits of POUT 4 3 2 1 0 CLR_POUT[7:0] Address: PIOnBaseAddress + 0x08 Type: W Description: This register allows the bits of PIOn_POUT to be cleared individually. [7:0] CLR_POUT[7:0]: 0: Leaves the corresponding bit unchanged. 1: Clears the corresponding bit in the PIOn_POUT register. DocID023557 Rev 10 517/604 Information classified Confidential - Do not copy (See last page for obligations) Holds output data for the port. Each bit defines the output value of the corresponding bit of the port. This register is mapped on to two additional addresses, PIOn_SET_POUT and PIOn_CLR_POUT, so that bits can be set or cleared individually. l Description: PIO port registers STiH271EL PIOn_PIN PIO input 7 6 5 4 3 2 1 0 PIN[7:0] Address: PIOnBaseAddress + 0x10 Type: R Reset: 0x0 Description: PIOn_PCx 6 5 4 en 7 3 PIOn_PC1 1 0 CONFIGDATA1[7:0] CONFIGDATA2[7:0] fid PIOn_PC2 PIOnBaseAddress + 0x20 + x * 0x10 (where x = 0 to 2) Type: RW Reset: 0x0 on Address: Description: 2 CONFIGDATA0[7:0] There are three configuration registers (PIOn_PC0, PIOn_PC1 and PIOn_PC2) for each port. These are used to configure the PIO port pins. Each pin can be configured as an input, output, bidirectional, or alternative function pin (if any), with options for the output driver configuration. C Confidential PIOn_PC0 PIO configuration Three bits, one bit from each of the three registers, configure the corresponding bit of the port. The configuration of the corresponding I/O pin for each valid bit setting is given in Table 107. PIOn_PC0: [7:0] CONFIGDATA0[7:0]: PIO configuration data 0, bits 7 to 0. PIOn_PC1: [7:0] CONFIGDATA1[7:0]: PIO configuration data 1, bits 7 to 0. PIOn_PC2: [7:0] CONFIGDATA2[7:0]: PIO configuration data 2, bits 7 to 0. 518/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) [7:0] PIN[7:0]: Bit 7 to 0 of input data for port. ti a l The data read from this register gives the logic level present on the input pins of the port at the start of the read cycle to this register. Each bit reflects the input value of the corresponding bit of the port. The read data is the last value written to the register regardless of the pin configuration selected. STiH271EL PIO port registers PC2[y] PC1[y] PC0[y] Bit y configuration Bit y output 0 0 0 Input Weak pull up (default) 0 0 or 1 1 Bidirectional Open drain 0 1 0 Output Push-pull 1 0 0 or 1 Input High impedance 1 1 0 Alternative function output Push-pull 1 1 1 Alternative function bidirectional Open drain ti a l The PIOn_PC[2:0] registers are each mapped on to two additional addresses, PIOn_SET_PCx and PIOn_CLR_PCx, so that bits can be set or cleared individually. PIOn_SET_PCx 7 6 5 4 2 1 0 SET_PC0[7:0] PIOn_SET_PC1 SET_PC1[7:0] PIOn_SET_PC2 SET_PC2[7:0] PIOnBaseAddress + 0x24 + x * 0x10 (where x = 0 to 2) Type: W Description: This register allow the bits of registers PIOn_PCx to be set individually. on fid Address: PIOn_SET_PC0: [7:0] SET_PC0[7:0]: PIOn_SET_PC1: [7:0] 0: Leaves the corresponding bit unchanged. PIOn_SET_PC2: [7:0] 1: Sets the corresponding bit in the PIOn_PCx register. PIOn_CLR_PCx 7 C Confidential 3 en PIOn_SET_PC0 Set bits of PCx Clear bits of PCx 6 5 4 3 PIOn_CLR_PC0 CLR_PC0[7:0] PIOn_CLR_PC1 CLR_PC1[7:0] PIOn_CLR_PC2 CLR_PC2[7:0] 2 1 Address: PIOnBaseAddress + 0x28 + x * 0x10 (where x = 0 to 2) Type: W Description: This register allows the bits of registers PIOn_PCx to be cleared individually. 0 PIOn_CLR_PC0: [7:0] CLR_PC0[7:0]: PIOn_CLR_PC1: [7:0] 0: Leaves the corresponding bit unchanged. PIOn_CLR_PC2: [7:0] 1: Clears the corresponding bit in the PIOn_PCx register. DocID023557 Rev 10 519/604 Information classified Confidential - Do not copy (See last page for obligations) Table 107. PIO bit configuration encoding PIO port registers STiH271EL PIOn_PCOMP 7 PIO input comparison 6 5 4 3 2 1 0 PCOMP[7:0] Address: PIOnBaseAddress + 0x50 Type: RW Reset: 0x0 This register can be used to cause an interrupt, if the input value differs from a fixed value. ti a l The input data from the PIO ports pins are compared with the value held in this register. If any of the input bits is different from the corresponding bit in this register and the corresponding bit position in the PIOn_PMASK register is set to 1, then the internal interrupt signal for the port is set to 1. en The compare function is operational in all configurations for each PIO bit, including the alternative function modes. fid The PIOn_PCOMP register is mapped onto two additional addresses, PIOn_SET_PCOMP and PIOn_CLR_PCOMP, so that bits can be set or cleared individually. on [7:0] PCOMP[7:0]: 8-bit value to which PIn is compared. PIOn_SET_PCOMP 7 6 5 C Confidential The compare function is sensitive to changes in levels on the pins. For the comparison to be seen as a valid interrupt by an interrupt handler, the change in state on the input pin must be longer in duration than the interrupt response time. Set bits of PCOMP 4 3 2 1 SET_PCOMP[7:0] Address: PIOnBaseAddress + 0x54 Type: W Description: This register allows the bits of PIOn_PCOMP to be set individually. [7:0] SET_PCOMP[7:0]: 0: Leaves the corresponding bit unchanged. 1: Sets the corresponding bit in the PIOn_PCOMP register. 520/604 DocID023557 Rev 10 0 Information classified Confidential - Do not copy (See last page for obligations) Description: STiH271EL PIO port registers PIOn_CLR_PCOMP 7 6 Clear bits of PCOMP 5 4 3 2 1 0 Address: PIOnBaseAddress + 0x58 Type: W Description: This register allows the bits of PIOn_PCOMP to be cleared individually. ti a l [7:0] CLR_PCOMP[7:0]: 0: Leaves the corresponding bit unchanged. 1: Clears the corresponding bit in the PIOn_PCOMP register. PIOn_PMASK 7 6 5 4 PIO input comparison mask 3 2 1 0 Type: RW Reset: 0 Description: en PIOnBaseAddress + 0x60 fid Address: When a bit is set to 1, the compare function for the internal interrupt for the port is enabled for that bit. If the respective bit ([7:0]) of the input is different from the corresponding bit in the PIOn_PCOMP register, then an interrupt is generated. on This register is mapped on to two additional addresses, PIOn_SET_PMASK and PIOn_CLR_PMASK, so that bits can be set or cleared individually. [7:0] PMASK[7:0]: When set to 1, interrupt generated when difference between PCompBitn and PInBitn detected. PIOn_SET_PMASK 7 6 C Confidential PMASK[7:0] Set bits of PMASK 5 4 3 2 1 0 SET_PMASK[7:0] Address: PIOnBaseAddress + 0x64 Type: W Description: This register allows the bits of PIOn_PMASK to be set individually. [7:0] SET_PMASK[7:0]: 0: Leaves the corresponding bit unchanged. 1: Sets the corresponding bit in the PIOn_PMASK register. DocID023557 Rev 10 521/604 Information classified Confidential - Do not copy (See last page for obligations) CLR_PCOMP[7:0] PIO port registers STiH271EL PIOn_CLR_PMASK 7 Clear bits of PMASK 6 5 4 3 2 1 0 Address: PIOnBaseAddress + 0x68 Type: W Description: This register allows the bits of PIOn_PMASK to be cleared individually. C on fid Confidential en ti a l [7:0] CLR_PMASK[7:0]: 0: Leaves the corresponding bit unchanged. 1: Clears the corresponding bit in the PIOn_PMASK register. 522/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) CLR_PMASK[7:0] STiH271EL 24 PIO port multiplexing PIO port multiplexing This chapter gives details of the PIO port multiplexing, and describes how the ports are configured using system configuration registers for alternate functions, and the registers in the PIO IP block for primary PIO functions. For a full description of the individual port/pin assignments, see Chapter 25: Alternate functions on PIO on page 528. Overview ti a l Each pad used for PIO multiplexing is controlled, driven and routed through the PIO multiplexing block. This generic logic supports one PIO general purpose function (primary mode - Alt0) and multiple alternate functions on each PIO bit. en PIO bank organization The 16 PIO ports are organized as four sets (or banks) of PIOs. PIO_Bank10: PIO0 to PIO3 (always on). PIO_Bank1: PIO4 to PIO8. PIO_Bank2: PIO9 to PIO12. PIO_Bank 3: PIO13 to PIO15. on 24.1.1 fid Registers in the system configuration block are used for controlling the PIO ports in all the alternate function modes. Their use is described in the sections bellow. C Confidential When a PIO port is used in its primary function mode, Output Enable (OE), Open Drain (OD), and Pull Up (PU) for the primary PIO functions are driven by the related PIO block in the same way as for previous devices; for example, to configure pad PIO1[2] in push-pull mode, the PIO1, output 2 should be programmed in push pull mode using the registers PIOn_PCx described in Chapter 23: PIO port registers on page 516. The system configuration registers for selection of the alternate function and pad direction of PIO0 to PIO3 are located in bank 0 of the system configuration registers. See Section 19.2: Bank 0 register descriptions on page 371. The system configuration registers for selection of the alternate function and pad direction of PIO4 to PIO8 are located in bank 1 of the system configuration registers. See Section 19.3: Bank 1 registers descriptions on page 396. The system configuration registers for selection of the alternate function and pad direction of PIO9 to PIO12 are located in bank 1 of the system configuration registers. See Section 19.3: Bank 1 registers descriptions on page 396. The system configuration registers for selection of the alternate function and pad direction of PIO13 to PIO15 are located in bank 2 of the system configuration registers. See Section 19.4: Bank 2 registers descriptions on page 435. The four fields (`selection', `output enable', `pullup enable', `open drain') are arranged in the system configuration registers in a regular structure to facilitate software coding. DocID023557 Rev 10 523/604 Information classified Confidential - Do not copy (See last page for obligations) 24.1 PIO port multiplexing STiH271EL The following table shows the available settings of the PIO block registers (for primary - Alt0 mode) and the system configuration registers (for the other alternate modes): Table 108. PIO data direction and control registers - primary and alt functions Output SYSCFG_ PIOx_y_PU SYSCFG_ PIOx_y_OE 1 0 1 Open Drain, no internal pullup 1 1 Open Drain with internal pullup. N.B. this mode is not possible for PIO function 0 1 Output 0 0 0 Input, no pullup 0 1 0 Input with pullup 0 1 1 Reserved 0 1 0 0 Reserved 1 1 1 0 Reserved PIOx.PC1[y] PIOx.PC0[y] 0 0 1 0 1 1 OpenDrain Output push-pull Output 0 1 0 Input Hi-Z 1 0 0 Input with Pull up Hi-Z 0 0 0 Reserved 1 0 1 Reserved 1 1 Reserved 1 1 Alternate functions controlled by system configuration registers fid 24.1.2 0 l 1 OpenDrain en Not supported Bidir, with pullup Each PIO multiplexing port (that is, 8 bits grouped together) is controlled though four types of system configuration register: on Data path selection: Alternate function output control for PIOx: (for example, SYSTEM_CONFIG100 on page 396) This register contains the PIOx_y_SELECTOR[n:0] system configuration bus. This bus selects the general purpose function or one of the alternate functions of each PIO bit according to the following values: C Confidential Bidir, no pullup Comments SYSCFG_ PIOx_y_OD PIOx.PC2[y] ti a Configuration Alt function 1, 2, 3, ... 00: PIO general purpose function 01: Alternate function 1 10: Alternate function 2 11: Alternate function 3 ... 1111: Alternate function 15 Default values can be set to the general purpose function (`0') or to one of the alternate function values. Output enable pad control for all PIO alternate functions: (for example, SYSTEM_CONFIG203 on page 440) This register contains the SYSCFG_PIOx_y_OE system configuration bit, whose active value can be high or low. 524/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Alt function 0 (PIO) STiH271EL PIO port multiplexing Default value can be set to `0' or `1'. Pull up pad control for all PIO alternate functions: (for example SYSTEM_CONFIG204 on page 441) This register contains the SYSCFG_PIOx_y_PU system configuration bit, whose active value is always high. Default value can be set to `0' or `1'. Open drain pad control for all PIO alternate functions: (for example, SYSTEM_CONFIG205 on page 442 This register contains the SYSCFG_PIOx_y_OD system configuration bit, whose active value is always high. ti a - Demultiplexed if many pads may drive the internal IP pin. This is controlled automatically by alternate function selection programming in the system configuration register - Forced to logic one or zero when unused en Routed directly (feed through in PIO multiplexing block) to internal IP pin from pad) Output mode (DATA OUT). This mode supports: - Demultiplexed if many IP pins drive the same pad This is controlled automatically by the system configuration register bits: PIOx_y_SELECTOR[n:0] - Routed to many pads fid - Pad Output Enable (OE). Can be controlled by: - A system configuration register bit shared between all alternate functions (SYSCFG_PIOx_y_OE/SYSCFG_PIOx_y_OEN) - A comms configuration register bit - A logic value one or zero - A dedicated signal driven by an internal IP on Input mode (DATA IN). This mode supports: C Confidential l Each PIO bit can be configured separately in the following modes: Pad Pull-Up (PU). Can be controlled by: - A system configuration register bit shared between all alternate functions (SYSCFG_PIOx_y_PU) - A comms configuration register bit - A logic value one or zero - A dedicated signal driven by an internal IP Pad Open-Drain (OD). Function is controlled by: - A system configuration register bit shared between all alternate functions (SYSCFG_PIOx_y_OD) - A comms configuration register bit - A logic value one or zero - A dedicated signal driven by an internal IP DocID023557 Rev 10 525/604 Information classified Confidential - Do not copy (See last page for obligations) Default value can be set to `0' or `1'. PIO port multiplexing STiH271EL The following figure shows the STiH271EL PIO multiplexing block diagram. Figure 66. STiH271EL PIO multiplexing block diagram PU[n:0] [i] OE[n:0] [i] Output [i] enable OD[n:0] glue ti a l PIOX[x] DATA OUT[n:0] en Confidential [i] DATA IN[n:0] vdd PUN PUN OEN EN 0 1 1 IO DATA OUT A DATA IN ZI 0 fid GND From other pads PIOX_x_SELECTOR[n:0] C Configuration register on [i] The following figure shows the STiH271EL PIO output glue logic diagram. Figure 67. STiH271EL PIO output enable glue logic PIOX[x] vdd OE PUN PU EN 0 OD 1 DATA OUT 1 IO A PIOX_x_SELECTOR[n:0] Configuration register 526/604 DocID023557 Rev 10 ZI 0 Information classified Confidential - Do not copy (See last page for obligations) GND STiH271EL PIO port multiplexing The following figure shows the STiH271EL pad retime diagram. Figure 68. STiH271EL pad retime 0 dataout_from_core 0 0 1 clkout0_int 1 dataout_to_pad 1 cfg_retime cfg_clk1notclk0 clkout_retime[1:0] clkout1_int clkout0_int/ clkout1_int cfg_double_edge clkout_retime[0] 0 1 ti a cfg_clknotdata 0 clkin_to_core 1 l cfg_clk1notclk0 cfg_invertclk datain_from_pad gnd 0 en 1 fid datain_to_core cfg_invertclk 0 0 0 1 cfg_retime oen_to_pad 1 1 on cfg_clk1notclk0 D 0.2 to 0.4 ns BC 0.5 to 1.0 ns WC clkin_retime[1:0] clkin_retime[0] clkin_retime[1] C Confidential cfg_clknotdata oen_from_core 1 cfg_double_edge cfg_delay_input Data-combiner used in the retiming of both single and double-edge data. Single/Double-edge configuration DocID023557 Rev 10 527/604 Information classified Confidential - Do not copy (See last page for obligations) 0 clkout_retime[1] Confidential Alternate functions on PIO This chapter gives both a global overview and also concise details of the alternate functions on the PIO ports. The details include the configuration registers that control the individual PIO ports. For a description of the overall multiplexing arrangements, and how the ports are configured, see Chapter 24: PIO port multiplexing. For details of the system configuration registers that control the PIO alternate functions, see Chapter 19: System configuration registers. C 25.1 Alternate functions on PIO 528/604 25 on PIO global summary fid The table gives an overview of the all the alternate signals on PIO. DocID023557 Rev 10 Table 109. PIO global summary table PIO pins Alternate 1 Dir Alternate 2 Dir PIO0(1) RMII, TMII PIO0[0] ETH_TXD[0] O PIO0[1] ETH_TXD[1] O PIO0[2] ETH_TXD[2] O KEYSCAN_IN[0](2) I PIO0[3] ETH_TXD[3] O KEYSCAN_IN[1](2) I PIO0[4] ETH_TXER O KEYSCAN_OUT[0](2) O PIO0[5] ETH_TXEN O PIO0[6] ETH_TXCLK I PIO0[7] ETH_COL I PIO1(1) RMII, TMII PIO1[0] ETH_MDIO B PIO1[1] ETH_MDC O PIO1[2] ETH_CRS I PIO1[3] ETH_MDINT I PIO1[4] ETH_RXD[0] I Key scan Alternate 3 Dir External interrupt 1 en Alternate 4 Dir Alternate 5 Dir Alternate 6 Dir ti a l KEYSCAN_OUT[1](2) O EXT_IT[1](2) SSC12 B RTC external clock B RTC_EXT_CLK(2) I Information classified Confidential - Do not copy (See last page for obligations) STiH271EL SSC12_MRST(2) Confidential PIO pins Alternate 1 Dir Alternate 2 Dir PIO1[5] ETH_RXD[1] I PIO1[6] ETH_RXD[2] I SSC12_MTSR(2) B I SSC12_SCL(2) B PIO1[7] ETH_RXD[3] PIO2(1) RMII, TMII, HDMI PIO2[0] ETH_RXDV I PIO2[1] ETH_RXER I PIO2[2] ETH_RXCLK I PIO2[3] ETH_PHYCLK O PIO2[4] HDMI_CEC B SSC11, external interrupt 0, RMII Alternate 3 Dir C ETH_PHYCLK I VALIDATION_OUTPUT Dir Alternate 5 Dir Alternate 6 Dir PWM10[1], UART10, external interrupt 3 IRB0 input 1, UART11 on Alternate 4 STiH271EL Table 109. PIO global summary table (continued) O UART10_NOTOE(2) O EXT_IT[3](2) B PWM10[1]_OUT(2) O PWM10[1]_CAPTUREIN I DocID023557 Rev 10 fid PWM10[1]_COMPAREO O UT PIO2[5] EXT_IT[0] B PIO2[6] SSC11_SCL B UART11_TXD O PIO2[7] SSC11_MTSR B UART11_RXD I SSC11, UART10, external interrupt 2, alternate reference clock for SBC IRB0_IRIN1 I en PWM10[0], SSC10, IRB0 input 0, FP_RESETN PIO3[0] PWM10[0]_OUT O SBC_SYS_CLKINAL T I UART11_CTS I KEYSCAN_IN[2] I PIO3[1] PWM10[0]_COMPA REOUT O EXT_IT[2] B UART11_RTS O KEYSCAN_OUT[2] O PIO3[2] PWM10[0]_CAPTU REIN I SSC11_MRST B UART11_NOTOE O KEYSCAN_IN[3] I PIO3[3] FP_RESETN I PIO3[4] IRB0_IRIN0 I UART10_RTS O LPM_CLK O PIO3[5] SSC10_SCL B UART10_TXD O IRB10_IRDATAOUT O PIO3[6] SSC10_MTSR B UART10_RXD I IRB10_DATAOUTOD O PIO3[7] SOC_REG_CTRL O UART10_CTS I SSC10_MRST B KEYSCAN_OUT[3] O PIO4 USB0, USB1, SSC1, audio S/PDIF UART11, SSC10, IRB10 Key scan ti a l CEC, SSC1 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO 529/604 PIO3(1) Confidential PIO pins Alternate 1 Dir Alternate 2 Dir Alternate 3 Dir Alternate 4 Dir Alternate 5 PIO4[0] PIO4[1] AUDSPDIF_OUT O PIO4[2] USB0_PRTOVRCU R I PIO4[3] USB0_PRTPWR O PIO4[4] USB1_PRTOVRCU R I PIO4[5] USB1_PRTPWR O DocID023557 Rev 10 PIO4[6] SSC1_SCL B PIO4[7] SSC1_MTSR B PIO5 TSIN0 (serial/parallel) PIO5[0] TSIN0_ERROR I PIO5[1] TSIN0_VALID I PIO5[2] TSIN0_PACKETCL K I PIO5[3] TSIN0_BYTECLK B PIO5[4] TSIN0_DATA[7] I CEC B C SSC1_MRST Dir Alternate 6 Dir Alternate functions on PIO 530/604 Table 109. PIO global summary table (continued) B on fid TSIN3 (serial) en ti a PIO5[5] TSIN0_DATA[6] I TSIN3_ERROR I PIO5[6] TSIN0_DATA[5] I TSIN3_VALID I PIO5[7] TSIN0_DATA[4] I TSIN3_PACKETCLK I PIO6 TSIN0 (parallel), TSIN1 (serial/parallel) l TSOUT0 (serial/parallel) TSIN3 (serial), SSC0 TSIN0_DATA[3] I TSIN3_BYTECLK B PIO6[1] TSIN0_DATA[2] I TSIN3_DATA[7] I PIO6[2] TSIN0_DATA[1] I SSC0_SCL B PIO6[3] TSIN0_DATA[0] I SSC0_MTSR B PIO6[4] TSIN1_ERROR I TSOUT0_ERROR O PIO6[5] TSIN1_VALID I TSOUT0_VALID O Information classified Confidential - Do not copy (See last page for obligations) STiH271EL PIO6[0] Confidential PIO pins Alternate 1 Dir Alternate 2 Dir Alternate 3 Dir PIO6[6] TSIN1_PACKETCL K I TSOUT0_PACKETCLK O PIO6[7] TSIN1_BYTECLK B TSOUT0_BYTECLK B PIO7 TSIN1 (serial/parallel) PIO7[0] TSIN1_DATA[7] I PIO7[1] TSIN1_DATA[6] I PIO7[2] TSIN1_DATA[5] PIO7[3] PIO7[4] Alternate 4 Dir Alternate 5 Dir Alternate 6 Dir STiH271EL Table 109. PIO global summary table (continued) TSOUT0 (serial/parallel) SSC2 SSC2_MRST B TSOUT0_DATA[7] O C DocID023557 Rev 10 O I TSOUT0_DATA[5] O TSIN1_DATA[4] I TSOUT0_DATA[4] O TSIN1_DATA[3] I TSOUT0_DATA[3] O PIO7[5] TSIN1_DATA[2] I TSOUT0_DATA[2] PIO7[6] TSIN1_DATA[1] I SSC2_SCL B TSOUT0_DATA[1] PIO7[7] TSIN1_DATA[0] I SSC2_MTSR B TSOUT0_DATA[0] PIO8 TSIN2 (serial), TSIN3 (serial) PIO8[0] TSIN2_ERROR I VALIDATION_OUTPUT O PIO8[1] TSIN2_VALID I VALIDATION_OUTPUT O PIO8[2] TSIN2_PACKETCL K I VALIDATION_OUTPUT O PIO8[3] TSIN2_BYTECLK B PIO8[4] TSIN2_DATA[7] I VALIDATION_OUTPUT O PIO8[5] TSIN3_ERROR I TSIN2_DATA[6] I VALIDATION_OUTPUT O PIO8[6] TSIN3_VALID I TSIN2_DATA[5] I VALIDATION_OUTPUT O EXTDMA_REQ0 PIO8[7] TSIN3_PACKETCL K I TSIN2_DATA[4] I VALIDATION_OUTPUT O EXTDMA_REQ1 PIO9 TSIN3 (serial), SSC0, external interrupt 4 PIO9[0] TSIN3_BYTECLK B TSIN2_DATA[3] I PIO9[1] TSIN3_DATA[7] I TSIN2_DATA[2] I VALIDATION_OUTPUT O PIO9[2] SSC0_SCL B TSIN2_DATA[1] I VALIDATION_OUTPUT O on fid O O O TSIN2 (parallel) en EXTDMA_REQ SSC2 ti a l SSC2_MRST B I SSC2_SCL B I SSC2_MTSR B TSIN2 (p), SSC2, S/PDIF Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO 531/604 TSOUT0_DATA[6] Confidential PIO pins PIO9[3] Alternate 1 SSC0_MTSR Dir B PIO9[4] PIO9[5] Alternate 2 Dir TSIN2_DATA[0] I SSC2_SCL B Alternate 3 Dir VALIDATION_OUTPUT DocID023557 Rev 10 SSC2_MTSR B PIO9[6] EXT_IT[4] I AUDSPDIF_OUT O PIO9[7] SSC0_MRST B SSC2_MRST B PIO10 Smartcard0 PIO10[0] SC0_C4 B UART0_TXD O PIO10[1] SC0_C7 B UART0_RXD I PIO10[2] SC0_RESET O UART0_CTS I PIO10[3] SC0_NOTSETVCC O UART0_RTS O PIO10[4] SC0_NOTSETVPP O UART0_NOTOE O PIO10[5] SC0_CLKGEN B PIO10[6] SC0_C8 B VALIDATION_OUTPUT PIO10[7] SC0_DETECT I VALIDATION_OUTPUT PIO11 SSC1 Dir Alternate 5 Dir O C UART0 Alternate 4 ClockGen A0, A1 clock observation SSC2, NMI on fid NMI O CKGENA1_CLK1 O Dir I en SSC2_SCL B O SSC2_MTSR B O SSC2_MRST UART1 CKGENA0_CLK1 Alternate 6 Alternate functions on PIO 532/604 Table 109. PIO global summary table (continued) B ti a Smartcard1 PIO11[0] UART1_TXD O SC1_C4 B PIO11[1] UART1_RXD I SC1_C7 B PIO11[2] UART1_RTS O SC1_RESET O PIO11[3] PIO11[4] UART1_NOTOE O SC1_NOTSETVCC O UART1_CTS I SC1_NOTSETVPP O PIO11[5] SC1_CLKGEN B PIO11[6] SC1_C8 B SC1_DETECT I SSC1_MRST B PIO12 SSC1, Serial Flash controller PIO12[0] SSC1_SCL B CKGENA0_CLK0 O PIO12[1] SSC1_MTSR B CKGENA1_CLK0 O ClockGen A0, A1 clock observation Information classified Confidential - Do not copy (See last page for obligations) STiH271EL PIO11[7] l Confidential PIO pins Alternate 1 Dir DocID023557 Rev 10 PIO12[2] SPI_CLOCK O PIO12[3] SPI_NOTCS O PIO12[4] SPI_DI B PIO12[5] SPI_DO B PIO12[6] SPI_HOLD B PIO12[7] SPI_WRPROTECT B PIO13 MMC PIO13[0] MMC_DATA[0] B PIO13[1] MMC_DATA[1] B PIO13[2] MMC_DATA[2] B PIO13[3] MMC_DATA[3] B PIO13[4] MMC_DATA[4] B PIO13[5] MMC_DATA[5] PIO13[6] Alternate 2 Dir Alternate 3 Dir C Alternate 4 Dir Alternate 5 Dir Alternate 6 SSC3 on fid SSC3_SCL B B SSC3_MTSR B MMC_DATA[6] B SSC3_MRST B PIO13[7] MMC_DATA[7] B PIO14 MMC PIO14[0] MMC_LED O PIO14[1] MMC_CLK B PIO14[2] MMC_CMD B PIO14[3] MMC_WP I PIO14[4] VALIDATION_OUTP O UT PIO14[5] MMC_CP O PIO14[6] MMC_CD I en ti a UART2 l O 533/604 SSC3, UART2 PIO15[0] SSC3_SCL SSC3 B AUDPCMOUT0 AUDPCMOUT0_DATA[0 ] AUDPCMIN0, EXT_IT[5] O AUDPCMIN0_DATA[0] AUDPCMIN0 I Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO UART2_NOTOE PIO14[7] PIO15 Dir STiH271EL Table 109. PIO global summary table (continued) Confidential PIO pins Alternate 1 Dir Alternate 2 Dir Alternate 3 Dir Alternate 4 Dir PIO15[1] SSC3_MTSR B AUDPCMOUT0_MCLK B AUDPCMIN0_MCLK B PIO15[2] SSC3_MRST B AUDPCMOUT0_SCLK O AUDPCMIN0_SCLK I AUDPCMOUT0_LRCLK O AUDPCMIN0_LRCLK I PIO15[4] UART2_TXD O PIO15[5] UART2_RXD I SSC3_SCL PIO15[6] UART2_CTS I SSC3_MTSR PIO15[7] UART2_RTS O SSC3_MRST PIO15[3] Alternate 5 B C B EXT_IT[5] B I Dir Alternate 6 Dir AUDPCMIN0_DATA[0] I AUDPCMIN0_MCLK B AUDPCMIN0_SCLK I AUDPCMIN0_LRCLK I Alternate functions on PIO 534/604 Table 109. PIO global summary table (continued) on 1. The PIO0[7:0], PIO1[7:0], PIO2[7:0] and PIO3[7:0] are in Always ON domain. 2. This function is available only if the internal Ethernet PHY is not used. DocID023557 Rev 10 25.2 fid PIO details en The tables in this section give concise details of the signals on PIO and their associated configuration registers. 25.2.1 PIO0 Table 110. PIO0 Parameter PIO Alternate 1 Function Standard PIO RMII, TMII ti a Pin PIO0[0] ETH_TXD[0] Desc PIO general purpose RMII, TMII, transmit data Dir B O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[24,16] = pio0_cfg_delay_1,0[0] SYSTEM_CONFIG7[0] = pio0_cfg_clk1notclk0[0] SYSTEM_CONFIG8[24] = pio0_cfg_double_edge[0] SYSTEM_CONFIG8[16] = pio0_cfg_clknotdata[0] SYSTEM_CONFIG8[8] = pio0_cfg_retime[0] SYSTEM_CONFIG8[0] = pio0_cfg_invertclk[0] Retime: Data retimed by clock ETH_TXCLK cfg_retime: SYSTEM_CONFIG8[8] = 1 cfg_clknotdata: SYSTEM_CONFIG8[16] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[0] = 0 Alt func: SYSTEM_CONFIG0[2:0] = 001 Open drain: SYSTEM_CONFIG6[0] = to be set by user Pull up: SYSTEM_CONFIG5[0] = to be set by user Output enable: SYSTEM_CONFIG4[0] = 1, active HIGH PIO0[0] Alternate 3 Key scan External interrupt 1 l Information classified Confidential - Do not copy (See last page for obligations) STiH271EL Name Alternate 2 Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII Key scan External interrupt 1 Pin Name PIO0[1] ETH_TXD[1] Desc PIO general purpose RMII, TMII, transmit data Dir B O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[25,17] = pio0_cfg_delay_1,0[1] SYSTEM_CONFIG7[1] = pio0_cfg_clk1notclk0[1] SYSTEM_CONFIG8[25] = pio0_cfg_double_edge[1] SYSTEM_CONFIG8[17] = pio0_cfg_clknotdata[1] SYSTEM_CONFIG8[9] = pio0_cfg_retime[1] SYSTEM_CONFIG8[1] = pio0_cfg_invertclk[1] Retime: Data retimed by clock ETH_TXCLK cfg_retime: SYSTEM_CONFIG8[9] =1 cfg_clknotdata: SYSTEM_CONFIG8[17] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[1] = 0 Alt func: SYSTEM_CONFIG0[6:4] = 001 Open drain: SYSTEM_CONFIG6[1] = to be set by user Pull up: SYSTEM_CONFIG5[1] = to be set by user Output enable: SYSTEM_CONFIG4[1] = 1, active HIGH Name PIO0[2] ETH_TXD[2] C PIO0[1] on DocID023557 Rev 10 fid KEYSCAN_IN[0] en Desc PIO general purpose (RMII optional), TMII, transmit data Key scanning - data input Dir B O I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[26,18] = pio0_cfg_delay_1,0[2] SYSTEM_CONFIG7[2] = pio0_cfg_clk1notclk0[2] SYSTEM_CONFIG8[26] = pio0_cfg_double_edge[2] SYSTEM_CONFIG8[18] = pio0_cfg_clknotdata[2] SYSTEM_CONFIG8[10] = pio0_cfg_retime[2] SYSTEM_CONFIG8[2] = pio0_cfg_invertclk[2] Retime: Data retimed by clock ETH_TXCLK cfg_retime: SYSTEM_CONFIG8[10] = 1 cfg_clknotdata: SYSTEM_CONFIG8[18] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[2] = 0 Alt func: SYSTEM_CONFIG0[10:8] = 001 Open drain: SYSTEM_CONFIG6[2] = to be set by user Pull up: SYSTEM_CONFIG5[2] = to be set by user Output enable: SYSTEM_CONFIG4[2] = 1, active HIGH PIO0[2] STiH271EL Table 110. PIO0 (continued) ti a Open drain: SYSTEM_CONFIG6[2] = to be set by user Pull up: SYSTEM_CONFIG5[2] = to be set by user Output enable: SYSTEM_CONFIG4[2] = 0, active HIGH l Alternate functions on PIO 535/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII Key scan External interrupt 1 Pin Name PIO0[3] ETH_TXD[3] KEYSCAN_IN[1] Desc PIO general purpose (RMII is optional), TMII, transmit data Key scanning data input Dir B O I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[27,19] = pio0_cfg_delay_1,0[3] SYSTEM_CONFIG7[3] = pio0_cfg_clk1notclk0[3] SYSTEM_CONFIG8[27] = pio0_cfg_double_edge[3] SYSTEM_CONFIG8[19] = pio0_cfg_clknotdata[3] SYSTEM_CONFIG8[11] = pio0_cfg_retime[3] SYSTEM_CONFIG8[3] = pio0_cfg_invertclk[3] Retime: Data retimed by clock ETH_TXCLK cfg_retime: SYSTEM_CONFIG8[11] = 1 cfg_clknotdata: SYSTEM_CONFIG8[19] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[3] = 0 Alt func: SYSTEM_CONFIG0[14:12] = 001 Open drain: SYSTEM_CONFIG6[3] = to be set by user Pull up: SYSTEM_CONFIG5[3] = to be set by user Output enable: SYSTEM_CONFIG4[3] = 1, active HIGH Open drain: SYSTEM_CONFIG6[3] = to be set by user Pull up: SYSTEM_CONFIG5[3] = to be set by user Output Enable: SYSTEM_CONFIG4[3] = 0, active HIGH Name PIO0[4] ETH_TXER KEYSCAN_OUT[0] C PIO0[3] on DocID023557 Rev 10 fid en Desc PIO general purpose (RMII is optional), TMII, transmit error Key scanning data output Dir B O O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[28,20] = pio0_cfg_delay_1,0[4] SYSTEM_CONFIG7[4] = pio0_cfg_clk1notclk0[4] SYSTEM_CONFIG8[28] = pio0_cfg_double_edge[4] SYSTEM_CONFIG8[20] = pio0_cfg_clknotdata[4] SYSTEM_CONFIG8[12] = pio0_cfg_retime[4] SYSTEM_CONFIG8[4] = pio0_cfg_invertclk[4] Retime: Data retimed by clock ETH_TXCLK cfg_retime: SYSTEM_CONFIG8[12] = 1 cfg_clknotdata: SYSTEM_CONFIG8[20] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[4] = 0 Alt func: SYSTEM_CONFIG0[18:16] = 001 Open drain: SYSTEM_CONFIG6[4] = to be set by user Pull up: SYSTEM_CONFIG5[4] = to be set by user Output enable: SYSTEM_CONFIG4[4] = 1, active HIGH PIO0[4] Alternate functions on PIO 536/604 Table 110. PIO0 (continued) ti a Alt func: SYSTEM_CONFIG0[18:16] = 010 Open drain: SYSTEM_CONFIG6[4] = to be set by user Pull up: SYSTEM_CONFIG5[4] = to be set by user Output enable: SYSTEM_CONFIG4[4] = 1, active HIGH l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII Key scan External interrupt 1 Pin Name PIO0[5] ETH_TXEN Desc PIO general purpose RMII, TMII, TX enable Dir B O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[29,21] = pio0_cfg_delay_1,0[5] SYSTEM_CONFIG7[5] = pio0_cfg_clk1notclk0[5] SYSTEM_CONFIG8[29] = pio0_cfg_double_edge[5] SYSTEM_CONFIG8[21] = pio0_cfg_clknotdata[5] SYSTEM_CONFIG8[13] = pio0_cfg_retime[5] SYSTEM_CONFIG8[5] = pio0_cfg_invertclk[5] Retime: Data retimed by clock ETH_TXCLK cfg_retime: SYSTEM_CONFIG8[13] = 1 cfg_clknotdata: SYSTEM_CONFIG8[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[5] = 0 Alt func: SYSTEM_CONFIG0[22:20] = 001 Open drain: SYSTEM_CONFIG6[5] = to be set by user Pull up: SYSTEM_CONFIG5[5] = to be set by user Output enable: SYSTEM_CONFIG4[5] = 1, active HIGH Name PIO0[6] ETH_TXCLK Desc PIO general purpose (RMII is optional), TMII, transmit clock for TXD Key scanning data output Dir B I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[30,22] = pio0_cfg_delay_1,0[6] SYSTEM_CONFIG7[6] = pio0_cfg_clk1notclk0[6] SYSTEM_CONFIG8[30] = pio0_cfg_double_edge[6] SYSTEM_CONFIG8[22] = pio0_cfg_clknotdata[6] SYSTEM_CONFIG8[14] = pio0_cfg_retime[6] SYSTEM_CONFIG8[6] = pio0_cfg_invertclk[6] Retime: Input clock cfg_clknotdata: SYSTEM_CONFIG8[22] = 1 Open Drain: SYSTEM_CONFIG6[6] = to be set by user Pull Up: SYSTEM_CONFIG5[6] = to be set by user Output Enable: SYSTEM_CONFIG4[6] = 0, active HIGH C PIO0[5] DocID023557 Rev 10 PIO0[6] STiH271EL Table 110. PIO0 (continued) on fid KEYSCAN_OUT[1] en O Alt func: SYSTEM_CONFIG0[26:24]= 010 Open drain: SYSTEM_CONFIG6[6] = to be set by user Pull up: SYSTEM_CONFIG5[6] = to be set by user Output enable: SYSTEM_CONFIG4[6] = 1, active HIGH ti a l Alternate functions on PIO 537/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII Key scan External interrupt 1 Pin PIO0[7] ETH_COL EXT_IT[1] Desc PIO general purpose (RMII is optional), TMII collision detected External interrupt Dir B I B Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG7[31,23] = pio0_cfg_delay_1,0[7] SYSTEM_CONFIG7[7] = pio0_cfg_clk1notclk0[7] SYSTEM_CONFIG8[31] = pio0_cfg_double_edge[7] SYSTEM_CONFIG8[23] = pio0_cfg_clknotdata[7] SYSTEM_CONFIG8[15] = pio0_cfg_retime[7] SYSTEM_CONFIG8[7] = pio0_cfg_invertclk[7] Retime: data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG8[15] = 1 cfg_clknotdata: SYSTEM_CONFIG8[23] = 0 cfg_clk1notclk0: SYSTEM_CONFIG7[7] = 0 Open drain: SYSTEM_CONFIG6[7] = to be set by user Pull up: SYSTEM_CONFIG5[7] = to be set by user Output enable: SYSTEM_CONFIG4[7] = 0, active HIGH Alt func: SYSTEM_CONFIG0[30:28] = 011 Open drain: SYSTEM_CONFIG6[7] = to be set by user Pull up: SYSTEM_CONFIG5[7] = to be set by user Output enable: SYSTEM_CONFIG4[7] = to be set by user, active HIGH Cleaned input: When unselected at 0 Name C PIO0[7] on DocID023557 Rev 10 25.2.2 PIO1 Table 111. PIO1 fid en Parameter PIO Alternate 1 Function Standard PIO RMII, TMII Pin PIO1[0] ETH_MDIO Desc PIO general purpose RMII, TMII, management data Dir B B Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[24,16] = pio1_cfg_delay_1,0[0] SYSTEM_CONFIG9[0] = pio1_cfg_clk1notclk0[0] SYSTEM_CONFIG10[24] = pio1_cfg_double_edge[0] SYSTEM_CONFIG10[16] = pio1_cfg_clknotdata[0] SYSTEM_CONFIG10[8] = pio1_cfg_retime[0] SYSTEM_CONFIG10[0] = pio1_cfg_invertclk[0] Retime: Data retimed by clock ETH_MDC cfg_retime: SYSTEM_CONFIG10[8] = 1 cfg_clknotdata: SYSTEM_CONFIG10[16] = 0 cfg_clk1notclk0(output): SYSTEM_CONFIG9[0] =0 cfg_clk1notclk0(input): SYSTEM_CONFIG9[0] = 0 Alt func: SYSTEM_CONFIG1[2:0] = 001 Open drain: SYSTEM_CONFIG6[8] = to be set by user Pull up: SYSTEM_CONFIG5[8] = to be set by user Output enable: mii_1(mii_mdio_oen) = to be set by user, active LOW ti a Alternate 2 Alternate 3 SSC12 RTC external clock l Information classified Confidential - Do not copy (See last page for obligations) STiH271EL Name PIO1[0] Alternate functions on PIO 538/604 Table 110. PIO0 (continued) Confidential PIO1 (continued) Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII SSC12 RTC external clock Pin Name PIO1[1] ETH_MDC Desc PIO general purpose RMII, TMII, management output clock Dir B O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[25,17] = pio1_cfg_delay_1,0[1] SYSTEM_CONFIG9[1] = pio1_cfg_clk1notclk0[1] SYSTEM_CONFIG10[25] = pio1_cfg_double_edge[1] SYSTEM_CONFIG10[17] = pio1_cfg_clknotdata[1] SYSTEM_CONFIG10[9] = pio1_cfg_retime[1] SYSTEM_CONFIG10[1] = pio1_cfg_invertclk[1] Retime: Output clock cfg_clknotdata: SYSTEM_CONFIG10[17] = 1 cfg_clk1notclk0 (output): SYSTEM_CONFIG9[1] =0 Alt func: SYSTEM_CONFIG1[6:4] = 001 Open drain: SYSTEM_CONFIG6[9] = to be set by user Pull up: SYSTEM_CONFIG5[9] = to be set by user Output enable: SYSTEM_CONFIG4[9] = 1, active HIGH Name PIO1[2] ETH_CRS Desc PIO general purpose Dir Config C PIO1[1] DocID023557 Rev 10 PIO1[2] STiH271EL Table 111. on fid RTC_EXT_CLK (RMII is optional), TMII, carrier sense detected SSC data bit master receive/slave transmit, full duplex External real time clock input B I B I (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[26,18] = pio1_cfg_delay_1,0[2] SYSTEM_CONFIG9[2] = pio1_cfg_clk1notclk0[2] SYSTEM_CONFIG10[26] = pio1_cfg_double_edge[2] SYSTEM_CONFIG10[18] = pio1_cfg_clknotdata[2] SYSTEM_CONFIG10[10] = pio1_cfg_retime[2] SYSTEM_CONFIG10[2] = pio1_cfg_invertclk[2] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG10[10] = 1 cfg_clknotdata: SYSTEM_CONFIG10[18] = 0 cfg_clk1notclk0: SYSTEM_CONFIG9[2] = 0 Open drain: SYSTEM_CONFIG6[10] = to be set by user Pull up: SYSTEM_CONFIG5[10] = to be set by user Output enable: SYSTEM_CONFIG4[10] = 0, active HIGH Alt Func: SYSTEM_CONFIG1[10:8] = 010 Open drain: SYSTEM_CONFIG6[10] = to be set by user Pull up: SYSTEM_CONFIG5[10] = to be set by user Output enable: SYSTEM_CONFIG4[10] = to be set by user, active HIGH Open drain: SYSTEM_CONFIG6[10] = to be set by user Pull up: SYSTEM_CONFIG5[10] = to be set by user Output enable: SYSTEM_CONFIG4[10] = 0, active HIGH en ti a l 539/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO SSC12_MRST Confidential PIO1 (continued) Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII SSC12 RTC external clock Pin Name PIO1[3] ETH_MDINT Desc PIO general purpose RMII, TMII, management data interrupt Dir B I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[27,19] = pio1_cfg_delay_1,0[3] SYSTEM_CONFIG9[3] = pio1_cfg_clk1notclk0[3] SYSTEM_CONFIG10[27] = pio1_cfg_double_edge[3] SYSTEM_CONFIG10[19] = pio1_cfg_clknotdata[3] SYSTEM_CONFIG10[11] = pio1_cfg_retime[3] SYSTEM_CONFIG10[3] = pio1_cfg_invertclk[3] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG10[11] = 1 cfg_clknotdata: SYSTEM_CONFIG10[19] = 0 cfg_clk1notclk0: SYSTEM_CONFIG9[3] = 0 Alt func: SYSTEM_CONFIG1[14:12] = 001 Open drain: SYSTEM_CONFIG6[11] = to be set by user Pull up: SYSTEM_CONFIG5[11] = to be set by user Output enable: SYSTEM_CONFIG4[11] = 0, active HIGH Cleaned input: When unselected at 0 PIO1[4] ETH_RXD[0] C PIO1[3] DocID023557 Rev 10 Name on fid en Desc PIO general purpose RMII, TMII, receive data Dir B I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[28,20] = pio1_cfg_delay_1,0[4] SYSTEM_CONFIG9[4] = pio1_cfg_clk1notclk0[4] SYSTEM_CONFIG10[28] = pio1_cfg_double_edge[4] SYSTEM_CONFIG10[20] = pio1_cfg_clknotdata[4] SYSTEM_CONFIG10[12] = pio1_cfg_retime[4] SYSTEM_CONFIG10[4] = pio1_cfg_invertclk[4] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG10[12] = 1 cfg_clknotdata: SYSTEM_CONFIG10[20] = 0 cfg_clk1notclk0: SYSTEM_CONFIG9[4] = 0 Open drain: SYSTEM_CONFIG6[12] = to be set by user Pull up: SYSTEM_CONFIG5[12] = to be set by user Output enable: SYSTEM_CONFIG4[12] = 0, active HIGH PIO1[4] Alternate functions on PIO 540/604 Table 111. ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO1 (continued) Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII SSC12 RTC external clock Pin Name PIO1[5] ETH_RXD[1] Desc PIO general purpose RMII, TMII, receive data Dir B I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[29,21] = pio1_cfg_delay_1,0[5] SYSTEM_CONFIG9[5] = pio1_cfg_clk1notclk0[5] SYSTEM_CONFIG10[29] = pio1_cfg_double_edge[5] SYSTEM_CONFIG10[21] = pio1_cfg_clknotdata[5] SYSTEM_CONFIG10[13] = pio1_cfg_retime[5] SYSTEM_CONFIG10[5] = pio1_cfg_invertclk[5] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG10[13] = 1 cfg_clknotdata: SYSTEM_CONFIG10[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG9[5] = 0 Open drain: SYSTEM_CONFIG6[13] = to be set by user Pull up: SYSTEM_CONFIG5[13] = to be set by user Output enable: SYSTEM_CONFIG4[13] = "0", active HIGH Name PIO1[6] ETH_RXD[2] Desc PIO general purpose (RMII is optional), TMII, receive data SSC data bit master transmit/slave receive, full duplex Dir B I B Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[30,22] = pio1_cfg_delay_1,0[6] SYSTEM_CONFIG9[6] = pio1_cfg_clk1notclk0[6] SYSTEM_CONFIG10[30] = pio1_cfg_double_edge[6] SYSTEM_CONFIG10[22] = pio1_cfg_clknotdata[6] SYSTEM_CONFIG10[14] = pio1_cfg_retime[6] SYSTEM_CONFIG10[6] = pio1_cfg_invertclk[6] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG10[14] = 1 cfg_clknotdata: SYSTEM_CONFIG10[22] = 0 cfg_clk1notclk0: SYSTEM_CONFIG9[6] = 0 Open drain: SYSTEM_CONFIG6[14] = to be set by user Pull up: SYSTEM_CONFIG5[14] = to be set by user Output enable: SYSTEM_CONFIG4[14] = 0, active HIGH C PIO1[5] DocID023557 Rev 10 PIO1[6] STiH271EL Table 111. on fid en SSC12_MTSR ti a Alt func: SYSTEM_CONFIG1[26:24] = 010 Open drain: SYSTEM_CONFIG6[14] = to be set by user Pull up: SYSTEM_CONFIG5[14] = to be set by user Output enable: SYSTEM_CONFIG4[14] = to be set by user, active HIGH l Alternate functions on PIO 541/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO1 (continued) Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO RMII, TMII SSC12 RTC external clock Pin Name PIO1[7] ETH_RXD[3] Desc PIO general purpose (RMII is optional), TMII, receive data SSC - serial clock Dir B I B Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG9[31,23] = pio1_cfg_delay_1,0[7] SYSTEM_CONFIG9[7] = pio1_cfg_clk1notclk0[7] SYSTEM_CONFIG10[31] = pio1_cfg_double_edge[7] SYSTEM_CONFIG10[23] = pio1_cfg_clknotdata[7] SYSTEM_CONFIG10[15] = pio1_cfg_retime[7] SYSTEM_CONFIG10[7] = pio1_cfg_invertclk[7] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG10[15] = 1 cfg_clknotdata: SYSTEM_CONFIG10[23] = 0 cfg_clk1notclk0: SYSTEM_CONFIG9[7] = 0 Open drain: SYSTEM_CONFIG6[15] = to be set by user Pull up: SYSTEM_CONFIG5[15] = to be set by user Output enable: SYSTEM_CONFIG4[15] = 0, active HIGH Alt func: SYSTEM_CONFIG1[30:28] = 010 Open drain: SYSTEM_CONFIG6[15] = to be set by user Pull up: SYSTEM_CONFIG5[15] = to be set by user Output enable: SYSTEM_CONFIG4[15] = to be set by user, active HIGH C PIO1[7] SSC12_SCL on DocID023557 Rev 10 fid Alternate functions on PIO 542/604 Table 111. en ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO2 Table 112. PIO2 Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO RMII, TMII, HDMI SSC11, external interrupt 0, RMII IRB0 input 1, UART11 PWM10[1], UART10, external interrupt 3 Pin Name PIO2[0] ETH_RXDV UART10_NOTOE Desc PIO general purpose RMII,TMII, receive data valid (RXDV), RMII (CRS_DV) UART output enable Dir B C I O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG11[24,16] = pio2_cfg_delay_1,0[0] SYSTEM_CONFIG11[0] = pio2_cfg_clk1notclk0[0] SYSTEM_CONFIG12[24] = pio2_cfg_double_edge[0] SYSTEM_CONFIG12[16] = pio2_cfg_clknotdata[0] SYSTEM_CONFIG12[8] = pio2_cfg_retime[0] SYSTEM_CONFIG12[0] = pio2_cfg_invertclk[0] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG12[8] = 1 cfg_clknotdata: SYSTEM_CONFIG12[16] = 0 cfg_clk1notclk0: SYSTEM_CONFIG11[0] = 0 Open drain: SYSTEM_CONFIG6[16] = to be set by user Pull up: SYSTEM_CONFIG5[16] = to be set by user Output enable: SYSTEM_CONFIG4[16] = 0, active HIGH Name PIO2[1] ETH_RXER Desc PIO general purpose RMII, TMII, receive error Dir B I Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG11[25,17] = pio2_cfg_delay_1,0[1] SYSTEM_CONFIG11[1] = pio2_cfg_clk1notclk0[1] SYSTEM_CONFIG12[25] = pio2_cfg_double_edge[1] SYSTEM_CONFIG12[17] = pio2_cfg_clknotdata[1] SYSTEM_CONFIG12[9] = pio2_cfg_retime[1] SYSTEM_CONFIG12[1] = pio2_cfg_invertclk[1] Retime: Data retimed by clock ETH_RXCLK cfg_retime: SYSTEM_CONFIG12[9] = 1 cfg_clknotdata: SYSTEM_CONFIG12[17] = 0 cfg_clk1notclk0: SYSTEM_CONFIG11[1] = 0 Open drain: SYSTEM_CONFIG6[17] = to be set by user Pull up: SYSTEM_CONFIG5[17] = to be set by user Output enable: SYSTEM_CONFIG4[17] = 0, active HIGH PIO2[0] DocID023557 Rev 10 Alt func: SYSTEM_CONFIG2[2:0] = 100 Open drain: SYSTEM_CONFIG6[16] = to be set by user Pull up: SYSTEM_CONFIG5[16] = to be set by user Output enable: SYSTEM_CONFIG4[16] = 1, active HIGH fid en ti a EXT_IT[3] l 543/604 Information classified Confidential - Do not copy (See last page for obligations) External interrupt B Alt func: SYSTEM_CONFIG2[6:4] = 100 Open drain: SYSTEM_CONFIG6[17] = to be set by user Pull up: SYSTEM_CONFIG5[17] = to be set by user Output enable: SYSTEM_CONFIG4[17] = to be set by user, active HIGH Cleaned input: When unselected at 0 Alternate functions on PIO PIO2[1] on STiH271EL 25.2.3 Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO RMII, TMII, HDMI SSC11, external interrupt 0, RMII IRB0 input 1, UART11 PWM10[1], UART10, external interrupt 3 Pin Name PIO2[2] ETH_RXCLK PWM10[1]_OUT Desc PIO general purpose (RMII is optional), TMII, receive clock for RXD PWM output Dir B I O Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG11[26,18] = pio2_cfg_delay_1,0[2] SYSTEM_CONFIG11[2] = pio2_cfg_clk1notclk0[2] SYSTEM_CONFIG12[26] = pio2_cfg_double_edge[2] SYSTEM_CONFIG12[18] = pio2_cfg_clknotdata[2] SYSTEM_CONFIG12[10] = pio2_cfg_retime[2] SYSTEM_CONFIG12[2] = pio2_cfg_invertclk[2] PIO2[2] C DocID023557 Rev 10 fid en PIO2[3] ETH_PHYCLK ETH_PHYCLK VALIDATION_OUTPUT PWM10[1]_CAPTUREIN Desc PIO general purpose RMII, (TMII is optional), reference clock to PHY (REF_CLK) RMII reference clock from PHY (REF_CLK) ST-only validation function. Safe to keep default function if PIO not used by application PWM capture input Dir B Config Partition: Bank10 Retime logic control: SYSTEM_CONFIG11[27,19] = pio2_cfg_delay_1,0[3] SYSTEM_CONFIG11[3] = pio2_cfg_clk1notclk0[3] SYSTEM_CONFIG12[27] = pio2_cfg_double_edge[3] SYSTEM_CONFIG12[19] = pio2_cfg_clknotdata[3] SYSTEM_CONFIG12[11] = pio2_cfg_retime[3] SYSTEM_CONFIG12[3] = pio2_cfg_invertclk[3] O I O Retime: output clock cfg_clknotdata: SYSTEM_CONFIG12[19] = 1 cfg_clk1notclk0 (output): SYSTEM_CONFIG11[3] = 0 Alt func: SYSTEM_CONFIG2[14:12] = 001 Open drain: SYSTEM_CONFIG6[19] = to be set by user Pull up: SYSTEM_CONFIG5[19] = to be set by user Output enable: SYSTEM_CONFIG4[19] = 1, active HIGH Retime: input clock cfg_clknotdata: SYSTEM_CONFIG12[19] = 1 Open drain: SYSTEM_CONFIG6[19] = to be set by user Pull up: SYSTEM_CONFIG5[19] = to be set by user Output enable: SYSTEM_CONFIG4[19] = 0, active HIGH ti a l (Default) Information classified Confidential - Do not copy (See last page for obligations) I Open drain: SYSTEM_CONFIG6[19] = to be set by user Pull up: SYSTEM_CONFIG5[19] = to be set by user Output enable: SYSTEM_CONFIG4[19] = 0, active HIGH STiH271EL Name PIO2[3] Alt func: SYSTEM_CONFIG2[10:8] = 100 Open drain: SYSTEM_CONFIG6[18] = to be set by user Pull up: SYSTEM_CONFIG5[18] = to be set by user Output enable: SYSTEM_CONFIG4[18] = 1, active HIGH on Retime: input clock cfg_clknotdata: SYSTEM_CONFIG12[18] = 1 Open drain: SYSTEM_CONFIG6[18] = to be set by user Pull up: SYSTEM_CONFIG5[18] = to be set by user Output enable: SYSTEM_CONFIG4[18] = 0, active HIGH Alternate functions on PIO 544/604 Table 112. PIO2 (continued) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO RMII, TMII, HDMI SSC11, external interrupt 0, RMII IRB0 input 1, UART11 PWM10[1], UART10, external interrupt 3 Pin Name PIO2[4] HDMI_CEC PWM10[1]_COMPAREOUT Desc PIO general purpose HDMI CEC line PWM compare output Dir B B O C Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG11[28,20] = pio2_cfg_delay_1,0[4] SYSTEM_CONFIG11[4] = pio2_cfg_clk1notclk0[4] SYSTEM_CONFIG12[28] = pio2_cfg_double_edge[4] SYSTEM_CONFIG12[20] = pio2_cfg_clknotdata[4] SYSTEM_CONFIG12[12] = pio2_cfg_retime[4] SYSTEM_CONFIG12[4] = pio2_cfg_invertclk[4] PIO2[4] DocID023557 Rev 10 Alt func: SYSTEM_CONFIG2[18:16] = 100 Open drain: SYSTEM_CONFIG6[20] = to be set by user Pull up: SYSTEM_CONFIG5[20] = to be set by user Output enable: SYSTEM_CONFIG4[20] = 1, active HIGH Alt func: SYSTEM_CONFIG2[18:16] = 001 Open drain: SYSTEM_CONFIG6[20] = to be set by user Pull up: SYSTEM_CONFIG5[20] = to be set by user Output enable: SYSTEM_CONFIG4[20] = to be set by user, active HIGH on fid en PIO2[5] EXT_IT[0] Desc PIO general purpose External interrupt Dir B B Config (Default) Partition: Bank10 Retime logic control: SYSTEM_CONFIG11[29,21] = pio2_cfg_delay_1,0[5] SYSTEM_CONFIG11[5] = pio2_cfg_clk1notclk0[5] SYSTEM_CONFIG12[29] = pio2_cfg_double_edge[5] SYSTEM_CONFIG12[21] = pio2_cfg_clknotdata[5] SYSTEM_CONFIG12[13] = pio2_cfg_retime[5] SYSTEM_CONFIG12[5] = pio2_cfg_invertclk[5] Alt func: SYSTEM_CONFIG2[22:20] = 010 Open drain: SYSTEM_CONFIG6[21] = to be set by user Pull up: SYSTEM_CONFIG5[21] = to be set by user Output enable: SYSTEM_CONFIG4[21] = to be set by user, active HIGH Cleaned input: When unselected at 0 Name PIO2[5] STiH271EL Table 112. PIO2 (continued) IRB0_IRIN1 ti a IR blaster/UHF data input I l 545/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO Open drain: SYSTEM_CONFIG6[21] = to be set by user Pull up: SYSTEM_CONFIG5[21] = to be set by user Output enable: SYSTEM_CONFIG4[21] = 0, active HIGH Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO RMII, TMII, HDMI SSC11, external interrupt 0, RMII IRB0 input 1, UART11 PWM10[1], UART10, external interrupt 3 Pin PIO2[6] SSC11_SCL Desc PIO general purpose SSC serial clock UART transmit data Dir B B O Alt func: SYSTEM_CONFIG2[26:24] = 010 Open drain: SYSTEM_CONFIG6[22] = to be set by user Pull up: SYSTEM_CONFIG5[22] = to be set by user Output enable: SYSTEM_CONFIG4[22] = to be set by user, active HIGH Alt func: SYSTEM_CONFIG2[26:24] = 011 Open drain: SYSTEM_CONFIG6[22] = to be set by user Pull up: SYSTEM_CONFIG5[22] = to be set by user Output enable: SYSTEM_CONFIG4[22] = 1, active HIGH Name C PIO2[6] Config (Default) Partition: Bank10 Mode pin used during reset on UART11_TXD DocID023557 Rev 10 fid en Name PIO2[7] SSC11_MTSR UART11_RXD Desc PIO general purpose SSC data bit master transmit/slave receive, full duplex UART transmit data Dir B B I (Default) Partition: Bank10 Mode pin used during reset Alt func: SYSTEM_CONFIG2[30:28] = 010 Open drain: SYSTEM_CONFIG6[23] = to be set by user Pull up: SYSTEM_CONFIG5[23] = to be set by user Output enable: SYSTEM_CONFIG4[23] = to be set by user, active HIGH PIO2[7] Config Alternate functions on PIO 546/604 Table 112. PIO2 (continued) ti a l Open drain: SYSTEM_CONFIG6[23] = to be set by user Pull up: SYSTEM_CONFIG5[23] = to be set by user Output enable: SYSTEM_CONFIG4[23] = 0, active HIGH STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO3 Table 113. PIO3 Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO PWM10[0], SSC10, IRB0 input 0, FP_RESETN SSC11, UART 10, external interrupt 2, alternate reference clock for SBC UART11, SSC10, IRB10 Key scan Pin Name PIO3[0] PWM10[0]_OUT Desc Adaptive Voltage Scaling feedback PWM output Dir B O DocID023557 Rev 10 UART11_CTS KEYSCAN_IN[2] Alternate reference clock for SBC UART transmit data Key scanning data input I I I Alt func: SYSTEM_CONFIG3[2:0] = 001 Open drain: SYSTEM_CONFIG6[24] = to be set by user Pull up: SYSTEM_CONFIG5[24] = to be set by user Output enable: SYSTEM_CONFIG4[24] = 1, active HIGH Alt func: SYSTEM_CONFIG3[2:0] = 010 Open drain: SYSTEM_CONFIG6[24] = to be set by user Pull up: SYSTEM_CONFIG5[24] = to be set by user Output enable: SYSTEM_CONFIG4[24] = 0, active HIGH Cleaned input: When unselected at 0 Open drain: SYSTEM_CONFIG6[24] = to be set by user Pull up: SYSTEM_CONFIG5[24] = to be set by user Output enable: SYSTEM_CONFIG4[24] = 0, active HIGH Open drain: SYSTEM_CONFIG6[24] = to be set by user Pull up: SYSTEM_CONFIG5[24] = to be set by user Output enable: SYSTEM_CONFIG4[24] = 0, active HIGH C PIO3[0] Config SBC_SYS_CLKINALT (Default) Partition: Bank10 Mode pin used during reset on fid en ti a PIO3[1] PWM10[0]_COMPAREOUT EXT_IT[2] Desc PIO general purpose PWM compare output External interrupt Dir B O B O Alt func: SYSTEM_CONFIG3[6:4] = 001 Open drain: SYSTEM_CONFIG6[25] = to be set by user Pull up: SYSTEM_CONFIG5[25] = to be set by user Output enable: SYSTEM_CONFIG4[25] = 1, active HIGH Alt func: SYSTEM_CONFIG3[6:4] = 010 Open drain: SYSTEM_CONFIG6[25] = to be set by user Pull up: SYSTEM_CONFIG5[25] = to be set by user Output enable: SYSTEM_CONFIG4[25] = to be set by user, active HIGH Cleaned input: When unselected at 0 Alt func: SYSTEM_CONFIG3[6:4] = 011 Open drain: SYSTEM_CONFIG6[25] = to be set by user Pull up: SYSTEM_CONFIG5[25] = to be set by user Output enable: SYSTEM_CONFIG4[25] = 1, active HIGH PIO3[1] Config (Default) Partition: Bank10 Mode pin used during reset UART11_RTS KEYSCAN_OUT[2] UART transmit data Key scanning data output l 547/604 Information classified Confidential - Do not copy (See last page for obligations) O Alt func: SYSTEM_CONFIG3[6:4] = 100 Open drain: SYSTEM_CONFIG6[25] = to be set by user Pull up: SYSTEM_CONFIG5[25] = to be set by user Output enable: SYSTEM_CONFIG4[25] = 1, active HIGH Alternate functions on PIO Name STiH271EL 25.2.4 Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO PWM10[0], SSC10, IRB0 input 0, FP_RESETN SSC11, UART 10, external interrupt 2, alternate reference clock for SBC UART11, SSC10, IRB10 Key scan Pin Name PIO3[2] PWM10[0]_CAPTUREIN SSC11_MRST UART11_NOTOE KEYSCAN_IN[3] Desc PIO general purpose PWM capture input SSC data bit master receive/slave transmit, full duplex UART output enable Key scanning data input Dir B I B O I (Default) Partition: Bank10 Mode pin used during reset Open drain: SYSTEM_CONFIG6[26] = to be set by user Pull up: SYSTEM_CONFIG5[26] = to be set by user Output enable: SYSTEM_CONFIG4[26] = 0, active HIGH Alt func: SYSTEM_CONFIG3[10:8] = 010 Open drain: SYSTEM_CONFIG6[26] = to be set by user Pull up: SYSTEM_CONFIG5[26] = to be set by user Output enable: SYSTEM_CONFIG4[26] = to be set by user, active HIGH Alt func: SYSTEM_CONFIG3[10:8] = 011 Open drain: SYSTEM_CONFIG6[26] = to be set by user Pull up: SYSTEM_CONFIG5[26] = to be set by user Output enable: SYSTEM_CONFIG4[26] = 1, active HIGH Open drain: SYSTEM_CONFIG6[26] = to be set by user Pull up: SYSTEM_CONFIG5[26] = to be set by user Output enable: SYSTEM_CONFIG4[26] = 0, active HIGH Name PIO3[3] FP_RESETN Desc PIO general purpose Front-panel reset Dir B I (Default) Partition: Bank10 Mode pin used during reset Alt func: SYSTEM_CONFIG3[14:12] = 001 Open drain: SYSTEM_CONFIG6[27] = to be set by user Pull up: SYSTEM_CONFIG5[27] = to be set by user Output enable: SYSTEM_CONFIG4[27] = 0, active HIGH Cleaned input: When unselected at 1 PIO3[2] Config DocID023557 Rev 10 PIO3[3] Config C on fid Alternate functions on PIO 548/604 Table 113. PIO3 (continued) en ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO PWM10[0], SSC10, IRB0 input 0, FP_RESETN SSC11, UART 10, external interrupt 2, alternate reference clock for SBC UART11, SSC10, IRB10 Key scan Pin Name PIO3[4] IRB0_IRIN0 UART10_RTS LPM_CLK Desc PIO general purpose IR blaster data input UART ready to send signal Low power monitor clock Dir B I O O (Default) Partition: Bank10 Mode pin used during reset Open drain: SYSTEM_CONFIG6[28] = to be set by user Pull up: SYSTEM_CONFIG5[28] = to be set by user Output enable: SYSTEM_CONFIG4[28] = 0, active HIGH Alt func: SYSTEM_CONFIG3[18:16] = 010 Open drain: SYSTEM_CONFIG6[28] = to be set by user Pull up: SYSTEM_CONFIG5[28] = to be set by user Output enable: SYSTEM_CONFIG4[28] = 1, active HIGH Alt func: SYSTEM_CONFIG3[18:16] = 100 Open drain: SYSTEM_CONFIG6[28] = to be set by user Pull up: SYSTEM_CONFIG5[28] = to be set by user Output enable: SYSTEM_CONFIG4[28] = 1, active HIGH PIO3[5] SSC10_SCL UART10_TXD Desc PIO general purpose SSC serial clock UART transmit signal IR blaster data output Dir B B O O (Default) Partition: Bank10 Mode pin used during reset Alt func: SYSTEM_CONFIG3[22:20] = 001 Open drain: SYSTEM_CONFIG6[29] = to be set by user Pull up: SYSTEM_CONFIG5[29] = to be set by user Output enable: SYSTEM_CONFIG4[29] = to be set by user, active HIGH Alt func: SYSTEM_CONFIG3[22:20] = 010 Open drain: SYSTEM_CONFIG6[29] = to be set by user Pull up: SYSTEM_CONFIG5[29] = to be set by user Output enable: SYSTEM_CONFIG4[29] = 1, active HIGH C PIO3[4] Config DocID023557 Rev 10 Name PIO3[5] Config on fid STiH271EL Table 113. PIO3 (continued) IRB10_IRDATAOUT en ti a Alt func: SYSTEM_CONFIG3[22:20] = 011 Open drain: SYSTEM_CONFIG6[29] = to be set by user Pull up: SYSTEM_CONFIG5[29] = to be set by user Output enable: SYSTEM_CONFIG4[29] = 1, active HIGH l Alternate functions on PIO 549/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Function Standard PIO PWM10[0], SSC10, IRB0 input 0, FP_RESETN SSC11, UART 10, external interrupt 2, alternate reference clock for SBC UART11, SSC10, IRB10 Key scan Pin Name PIO3[6] SSC10_MTSR UART10_RXD IRB10_DATAOUTOD Desc PIO general purpose SSC data bit master transmit/slave receive, full duplex UART receive signal IR blaster data output open drain Dir B B I O (Default) Partition: Bank10 Mode pin used during reset Alt func: SYSTEM_CONFIG3[26:24] = 001 Open drain: SYSTEM_CONFIG6[30] = to be set by user Pull up: SYSTEM_CONFIG5[30] = to be set by user Output enable: SYSTEM_CONFIG4[30] = to be set by user, active HIGH Open drain: SYSTEM_CONFIG6[30] = to be set by user Pull up: SYSTEM_CONFIG5[30] = to be set by user Output enable: SYSTEM_CONFIG4[30] = 0, active HIGH Alt func: SYSTEM_CONFIG3[26:24] = 011 Open drain: SYSTEM_CONFIG6[30] = to be set by user Pull up: SYSTEM_CONFIG5[30] = to be set by user Output enable: SYSTEM_CONFIG4[30] = 1, active HIGH Name PIO3[7] SOC_REG_CTRL UART10_CTS SSC10_MRST KEYSCAN_OUT[3] Desc PIO general purpose SoC regulator control UART clear to send signal SSC data bit master receive/slave transmit, full duplex Key scanning data output Dir B O I (Default) Partition: Bank10 Mode pin used during reset Alt func: SYSTEM_CONFIG3[30:28]=001 Open drain: SYSTEM_CONFIG6[31] = to be set by user Pull up: SYSTEM_CONFIG5[31] = to be set by user Output enable: SYSTEM_CONFIG4[31] = to be set by user, active HIGH Open drain: SYSTEM_CONFIG6[31] = to be set by user Pull up: SYSTEM_CONFIG5[31] = to be set by user Output enable: SYSTEM_CONFIG4[31] = 0, active HIGH PIO3[6] Config DocID023557 Rev 10 PIO3[7] Config C on fid en ti a B O Alt func: SYSTEM_CONFIG3[30:28] = 011 Open drain: SYSTEM_CONFIG6[31] = to be set by user Pull up: SYSTEM_CONFIG5[31] = to be set by user Output enable: SYSTEM_CONFIG4[31] = to be set by user, active HIGH Alt func: SYSTEM_CONFIG3[30:28] = 100 Open drain: SYSTEM_CONFIG6[31] = to be set by user Pull up: SYSTEM_CONFIG5[31] = to be set by user Output enable: SYSTEM_CONFIG4[31] = 1, active HIGH l Alternate functions on PIO 550/604 Table 113. PIO3 (continued) STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO4 Table 114. PIO4 Parameter PIO Alternate 1 Alternate 2 Function Standard PIO USB0, USB1, SSC1, audio S/PDIF CEC, SSC1 Pin Name PIO4[0] Desc PIO general purpose Dir B Config (Default) Partition: Bank1 Name PIO4[1] Desc PIO general purpose Dir B O Config (Default) Partition: Bank1 Alt func: SYSTEM_CONFIG100[5:4] = 01 Open drain: SYSTEM_CONFIG115[1] = to be set by user Pull up: SYSTEM_CONFIG112[1] = to be set by user Output enable: SYSTEM_CONFIG109[1] = 1, active HIGH Data output: Multiplexed Name PIO4[2] USB0_PRTOVRCUR Desc PIO general purpose USB over current Dir B I Config (Default) Partition: Bank1 Open drain: SYSTEM_CONFIG115[2] = to be set by user Pull up: SYSTEM_CONFIG112[2] = to be set by user Output enable: SYSTEM_CONFIG109[2] = 0, active HIGH Name PIO4[3] USB0_PRTPWR Desc PIO general purpose USB power enable Dir B O Config (Default) Partition: Bank1 Alt func: SYSTEM_CONFIG100[12] = 1 Open drain: SYSTEM_CONFIG115[3] = to be set by user Pull up: SYSTEM_CONFIG112[3] = to be set by user Output enable: SYSTEM_CONFIG109[3] = 1, active HIGH PIO4[0] DocID023557 Rev 10 PIO4[1] STiH271EL 25.2.5 C on AUDSPDIF_OUT CEC S/PDIF out CEC line fid B en Alt func: SYSTEM_CONFIG100[5:4] = 10 Open drain: SYSTEM_CONFIG115[1] = to be set by user Pull up: SYSTEM_CONFIG112[1] = to be set by user Output enable: SYSTEM_CONFIG109[1] = to be set by user, active HIGH ti a PIO4[2] l 551/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO PIO4[3] Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO USB0, USB1, SSC1, audio S/PDIF CEC, SSC1 Pin Name PIO4[4] USB1_PRTOVRCUR Desc PIO general purpose USB over current Dir B I Config (Default) Partition: Bank1 Open drain: SYSTEM_CONFIG115[4] = to be set by user Pull up: SYSTEM_CONFIG112[4] = to be set by user Output enable: SYSTEM_CONFIG109[4] = 0, active HIGH Name PIO4[5] PIO4[4] Desc PIO general purpose Dir B C on USB1_PRTPWR SSC1_MRST USB power enable SSC data bit master receive/slave transmit, full duplex O B DocID023557 Rev 10 PIO4[5] fid Config (Default) Partition: Bank1 Alt func: SYSTEM_CONFIG100[21:20] = 01 Open drain: SYSTEM_CONFIG115[5] = to be set by user Pull up: SYSTEM_CONFIG112[5] = to be set by user Output enable: SYSTEM_CONFIG109[5] = 1, active HIGH Name PIO4[6] SSC1_SCL Desc PIO general purpose SSC serial clock Dir B B Config (Default) Partition: Bank1 Alt func: SYSTEM_CONFIG100[24] = 1 Open drain: SYSTEM_CONFIG115[6] = to be set by user Pull up: SYSTEM_CONFIG112[6] = to be set by user Output enable: SYSTEM_CONFIG109[6] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Name PIO4[7] SSC1_MTSR Desc PIO general purpose SSC data bit for half duplex Dir B B (Default) Partition: Bank1 Alt func: SYSTEM_CONFIG100[28] = 1 Open drain: SYSTEM_CONFIG115[7] = to be set by user Pull up: SYSTEM_CONFIG112[7] = to be set by user Output enable: SYSTEM_CONFIG109[7] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed PIO4[6] PIO4[7] en Alt func: SYSTEM_CONFIG100[21:20] = 10 Open drain: SYSTEM_CONFIG115[5] = to be set by user Pull up: SYSTEM_CONFIG112[5] = to be set by user Output enable: SYSTEM_CONFIG109[5] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed ti a l Information classified Confidential - Do not copy (See last page for obligations) STiH271EL Config Alternate functions on PIO 552/604 Table 114. PIO4 (continued) Confidential PIO5 Table 115. PIO5 Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN0 (serial/parallel) TSIN3 (serial) Pin Name PIO5[0] TSIN0_ERROR Desc PIO general purpose TS serial/parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[24,16] = pio5_cfg_delay_1,0[0] SYSTEM_CONFIG120[0] = pio5_cfg_clk1notclk0[0] SYSTEM_CONFIG121[24] = pio5_cfg_double_edge[0] SYSTEM_CONFIG121[16] = pio5_cfg_clknotdata[0] SYSTEM_CONFIG121[8] = pio5_cfg_retime[0] SYSTEM_CONFIG121[0] = pio5_cfg_invertclk[0] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[8] = 1 cfg_clknotdata: SYSTEM_CONFIG121[16] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[0] = 0 Open drain: SYSTEM_CONFIG115[8] = to be set by user Pull up: SYSTEM_CONFIG112[8] = to be set by user Output enable: SYSTEM_CONFIG109[8] = 0, active HIGH Name PIO5[1] TSIN0_VALID Desc PIO general purpose TS serial/parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[25,17] = pio5_cfg_delay_1,0[1] SYSTEM_CONFIG120[1] = pio5_cfg_clk1notclk0[1] SYSTEM_CONFIG121[25] = pio5_cfg_double_edge[1] SYSTEM_CONFIG121[17] = pio5_cfg_clknotdata[1] SYSTEM_CONFIG121[9] = pio5_cfg_retime[1] SYSTEM_CONFIG121[1] = pio5_cfg_invertclk[1] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[9] = 1 cfg_clknotdata: SYSTEM_CONFIG121[17] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[1] = 0 Open drain: SYSTEM_CONFIG115[9] = to be set by user Pull up: SYSTEM_CONFIG112[9] = to be set by user Output enable: SYSTEM_CONFIG109[9] = 0, active HIGH Name PIO5[2] TSIN0_PACKETCLK Desc PIO general purpose TS serial/parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[26,18] = pio5_cfg_delay_1,0[2] SYSTEM_CONFIG120[2] = pio5_cfg_clk1notclk0[2] SYSTEM_CONFIG121[26] = pio5_cfg_double_edge[2] SYSTEM_CONFIG121[18] = pio5_cfg_clknotdata[2] SYSTEM_CONFIG121[10] = pio5_cfg_retime[2] SYSTEM_CONFIG121[2] = pio5_cfg_invertclk[2] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[10] = 1 cfg_clknotdata: SYSTEM_CONFIG121[18] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[2] = 0 Open drain: SYSTEM_CONFIG115[10] = to be set by user Pull up: SYSTEM_CONFIG112[10] = to be set by user Output enable: SYSTEM_CONFIG109[10] = 0, active HIGH C PIO5[0] DocID023557 Rev 10 PIO5[1] on fid en ti a l 553/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO PIO5[2] STiH271EL 25.2.6 Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN0 (serial/parallel) TSIN3 (serial) Pin Name PIO5[3] TSIN0_BYTECLK Desc PIO general purpose TS serial/parallel input Dir B B Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[27,19] = pio5_cfg_delay_1,0[3] SYSTEM_CONFIG120[3] = pio5_cfg_clk1notclk0[3] SYSTEM_CONFIG121[27] = pio5_cfg_double_edge[3] SYSTEM_CONFIG121[19] = pio5_cfg_clknotdata[3] SYSTEM_CONFIG121[11] = pio5_cfg_retime[3] SYSTEM_CONFIG121[3] = pio5_cfg_invertclk[3] Retime: Input clock cfg_clknotdata: SYSTEM_CONFIG121[19] = 1 Alt func: SYSTEM_CONFIG101[14:12] = 001 Open drain: SYSTEM_CONFIG115[11] = to be set by user Pull up: SYSTEM_CONFIG112[11] = to be set by user Output enable: SYSTEM_CONFIG109[11] = to be set by user, active HIGH Name PIO5[4] TSIN0_DATA[7] Desc PIO general purpose TS serial/parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[28,20] = pio5_cfg_delay_1,0[4] SYSTEM_CONFIG120[4] = pio5_cfg_clk1notclk0[4] SYSTEM_CONFIG121[28] = pio5_cfg_double_edge[4] SYSTEM_CONFIG121[20] = pio5_cfg_clknotdata[4] SYSTEM_CONFIG121[12] = pio5_cfg_retime[4] SYSTEM_CONFIG121[4] = pio5_cfg_invertclk[4] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[12] = 1 cfg_clknotdata: SYSTEM_CONFIG121[20] =0 cfg_clk1notclk0: SYSTEM_CONFIG120[4] = 0 Open drain: SYSTEM_CONFIG115[12] = to be set by user Pull up: SYSTEM_CONFIG112[12] = to be set by user Output enable: SYSTEM_CONFIG109[12] = 0, active HIGH Name PIO5[5] TSIN0_DATA[6] TSIN3_ERROR Desc PIO general purpose TS parallel input TS serial input Dir B I I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[29,21] = pio5_cfg_delay_1,0[5] SYSTEM_CONFIG120[5] = pio5_cfg_clk1notclk0[5] SYSTEM_CONFIG121[29] = pio5_cfg_double_edge[5] SYSTEM_CONFIG121[21] = pio5_cfg_clknotdata[5] SYSTEM_CONFIG121[13] = pio5_cfg_retime[5] SYSTEM_CONFIG121[5] = pio5_cfg_invertclk[5] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[13] = 1 cfg_clknotdata: SYSTEM_CONFIG121[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[5] = 0 Open drain: SYSTEM_CONFIG115[13] = to be set by user Pull up: SYSTEM_CONFIG112[13] = to be set by user Output enable: SYSTEM_CONFIG109[13] = 0, active HIGH Retime: Data retimed by clock TSIN3_BYTECLK cfg_retime: SYSTEM_CONFIG121[13] = 1 cfg_clknotdata: SYSTEM_CONFIG121[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[5] = 1 Open drain: SYSTEM_CONFIG115[13] = to be set by user Pull up: SYSTEM_CONFIG112[13] = to be set by user Output enable: SYSTEM_CONFIG109[13] = 0, active HIGH Data input: Demultiplexed by alt func C PIO5[3] DocID023557 Rev 10 PIO5[4] PIO5[5] Alternate functions on PIO 554/604 Table 115. PIO5 (continued) on fid en ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN0 (serial/parallel) TSIN3 (serial) Pin Name PIO5[6] TSIN0_DATA[5] TSIN3_VALID Desc PIO general purpose TS parallel input TS serial input Dir B I I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[30,22] = pio5_cfg_delay_1,0[6] SYSTEM_CONFIG120[6] = pio5_cfg_clk1notclk0[6] SYSTEM_CONFIG121[30] = pio5_cfg_double_edge[6] SYSTEM_CONFIG121[22] = pio5_cfg_clknotdata[6] SYSTEM_CONFIG121[14] = pio5_cfg_retime[6] SYSTEM_CONFIG121[6] = pio5_cfg_invertclk[6] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[14] = 1 cfg_clknotdata: SYSTEM_CONFIG121[22] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[6] = 0 Open drain: SYSTEM_CONFIG115[14] = to be set by user Pull up: SYSTEM_CONFIG112[14] = to be set by user Output enable: SYSTEM_CONFIG109[14] = 0, active HIGH Retime: data retimed by clock TSIN3_BYTECLK cfg_retime: SYSTEM_CONFIG121[14] = "1" cfg_clknotdata: SYSTEM_CONFIG121[22] = "0" cfg_clk1notclk0: SYSTEM_CONFIG120[6] = "1" Open Drain: SYSTEM_CONFIG115[14] = to be set by user Pull Up: SYSTEM_CONFIG112[14] = to be set by user Output Enable: SYSTEM_CONFIG109[14] = "0", active HIGH Data Input: demultiplexed by Alt Func Name PIO5[7] TSIN0_DATA[4] TSIN3_PACKETCLK Desc PIO general purpose TS parallel input TS serial input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG120[31,23] = pio5_cfg_delay_1,0[7] SYSTEM_CONFIG120[7] = pio5_cfg_clk1notclk0[7] SYSTEM_CONFIG121[31] = pio5_cfg_double_edge[7] SYSTEM_CONFIG121[23] = pio5_cfg_clknotdata[7] SYSTEM_CONFIG121[15] = pio5_cfg_retime[7] SYSTEM_CONFIG121[7] = pio5_cfg_invertclk[7] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG121[15] = 1 cfg_clknotdata: SYSTEM_CONFIG121[23] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[7] = 0 Open drain: SYSTEM_CONFIG115[15] = to be set by user Pull up: SYSTEM_CONFIG112[15] = to be set by user Output enable: SYSTEM_CONFIG109[15] = 0, active HIGH C PIO5[6] DocID023557 Rev 10 PIO5[7] on fid en STiH271EL Table 115. PIO5 (continued) I ti a Retime: Data retimed by clock TSIN3_BYTECLK cfg_retime: SYSTEM_CONFIG121[15] = 1 cfg_clknotdata: SYSTEM_CONFIG121[23] = 0 cfg_clk1notclk0: SYSTEM_CONFIG120[7] = 1 Open drain: SYSTEM_CONFIG115[15] = to be set by user Pull up: SYSTEM_CONFIG112[15] = to be set by user Output enable: SYSTEM_CONFIG109[15] = 0, active HIGH Data input: Demultiplexed by alt func l Alternate functions on PIO 555/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO6 Table 116. PIO6 Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN0 (p), TSIN1 (s/p) TSIN3(s) TSOUT0 (s/p) Pin Name PIO6[0] TSIN0_DATA[3] TSIN3_BYTECLK Desc PIO general purpose TS parallel input TS serial input Dir B Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[24,16] = pio6_cfg_delay_1,0[0] SYSTEM_CONFIG122[0] = pio6_cfg_clk1notclk0[0] SYSTEM_CONFIG123[24] = pio6_cfg_double_edge[0] SYSTEM_CONFIG123[16] = pio6_cfg_clknotdata[0] SYSTEM_CONFIG123[8] = pio6_cfg_retime[0] SYSTEM_CONFIG123[0] = pio6_cfg_invertclk[0] PIO6[0] C I B on DocID023557 Rev 10 Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG123[8] = 1 cfg_clknotdata: SYSTEM_CONFIG123[16] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[0] =0 Open drain: SYSTEM_CONFIG115[16] = to be set by user Pull up: SYSTEM_CONFIG112[16] = to be set by user Output enable: SYSTEM_CONFIG109[16] = 0, active HIGH Retime: Input clock cfg_clknotdata: SYSTEM_CONFIG123[16] = 1 Alt func: SYSTEM_CONFIG102[2:0] = 010 Open drain: SYSTEM_CONFIG115[16] = to be set by user Pull up: SYSTEM_CONFIG112[16] = to be set by user Output enable: SYSTEM_CONFIG109[16] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed fid en ti a Name PIO6[1] TSIN0_DATA[2] TSIN3_DATA[7] Desc PIO general purpose TS parallel input TS serial input Dir B I I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[25,17] = pio6_cfg_delay_1,0[1] SYSTEM_CONFIG122[1] = pio6_cfg_clk1notclk0[1] SYSTEM_CONFIG123[25] = pio6_cfg_double_edge[1] SYSTEM_CONFIG123[17] = pio6_cfg_clknotdata[1] SYSTEM_CONFIG123[9] = pio6_cfg_retime[1] SYSTEM_CONFIG123[1] = pio6_cfg_invertclk[1] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG123[9] = 1 cfg_clknotdata: SYSTEM_CONFIG123[17] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[1] =0 Open drain: SYSTEM_CONFIG115[17] = to be set by user Pull up: SYSTEM_CONFIG112[17] = to be set by user Output enable: SYSTEM_CONFIG109[17] = 0, active HIGH Retime: Data retimed by clock TSIN3_BYTECLK cfg_retime: SYSTEM_CONFIG123[9] = 1 cfg_clknotdata: SYSTEM_CONFIG123[17] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[1] =1 Open drain: SYSTEM_CONFIG115[17] = to be set by user Pull up: SYSTEM_CONFIG112[17] = to be set by user Output enable: SYSTEM_CONFIG109[17] = 0, active HIGH Data input: Demultiplexed by alt func PIO6[1] Alternate functions on PIO 556/604 25.2.7 l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN0 (p), TSIN1 (s/p) TSIN3(s) TSOUT0 (s/p) Pin Name PIO6[2] TSIN0_DATA[1] SSC0_SCL Desc PIO general purpose TS parallel input I2C serial clock Dir B I B Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[26,18] = pio6_cfg_delay_1,0[2] SYSTEM_CONFIG122[2] = pio6_cfg_clk1notclk0[2] SYSTEM_CONFIG123[26] = pio6_cfg_double_edge[2] SYSTEM_CONFIG123[18] = pio6_cfg_clknotdata[2] SYSTEM_CONFIG123[10] = pio6_cfg_retime[2] SYSTEM_CONFIG123[2] = pio6_cfg_invertclk[2] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG123[10] = 1 cfg_clknotdata: SYSTEM_CONFIG123[18] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[2] =0 Open drain: SYSTEM_CONFIG115[18] = to be set by user Pull up: SYSTEM_CONFIG112[18] = to be set by user Output enable: SYSTEM_CONFIG109[18] = 0, active HIGH Alt func: SYSTEM_CONFIG102[10:8] = 010 Open drain: SYSTEM_CONFIG115[18] = to be set by user Pull up: SYSTEM_CONFIG112[18] = to be set by user Output enable: SYSTEM_CONFIG109[18] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed SSC0_MTSR PIO6[2] C on DocID023557 Rev 10 fid en Name PIO6[3] TSIN0_DATA[0] Desc PIO general purpose TS parallel input Dir B I B Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[27,19] = pio6_cfg_delay_1,0[3] SYSTEM_CONFIG122[3] = pio6_cfg_clk1notclk0[3] SYSTEM_CONFIG123[27] = pio6_cfg_double_edge[3] SYSTEM_CONFIG123[19] = pio6_cfg_clknotdata[3] SYSTEM_CONFIG123[11] = pio6_cfg_retime[3] SYSTEM_CONFIG123[3] = pio6_cfg_invertclk[3] Retime: Data retimed by clock TSIN0_BYTECLK cfg_retime: SYSTEM_CONFIG123[11] = 1 cfg_clknotdata: SYSTEM_CONFIG123[19] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[3] =0 Open drain: SYSTEM_CONFIG115[19] = to be set by user Pull up: SYSTEM_CONFIG112[19] = to be set by user Output enable: SYSTEM_CONFIG109[19] = 0, active HIGH Alt func: SYSTEM_CONFIG102[14:12] = 010 Open drain: SYSTEM_CONFIG115[19] = to be set by user Pull up: SYSTEM_CONFIG112[19] = to be set by user Output enable: SYSTEM_CONFIG109[19] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed PIO6[3] STiH271EL Table 116. PIO6 (continued) I2C data bit for half duplex ti a l Alternate functions on PIO 557/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN0 (p), TSIN1 (s/p) TSIN3(s) TSOUT0 (s/p) Pin Name PIO6[4] TSIN1_ERROR TSOUT0_ERROR Desc PIO general purpose TS serial/parallel input TS serial/parallel output Dir B I O Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[28,20] = pio6_cfg_delay_1,0[4] SYSTEM_CONFIG122[4] = pio6_cfg_clk1notclk0[4] SYSTEM_CONFIG123[28] = pio6_cfg_double_edge[4] SYSTEM_CONFIG123[20] = pio6_cfg_clknotdata[4] SYSTEM_CONFIG123[12] = pio6_cfg_retime[4] SYSTEM_CONFIG123[4] = pio6_cfg_invertclk[4] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG123[12] = 1 cfg_clknotdata: SYSTEM_CONFIG123[20] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[4] =0 Open drain: SYSTEM_CONFIG115[20] = to be set by user Pull up: SYSTEM_CONFIG112[20] = to be set by user Output enable: SYSTEM_CONFIG109[20] = 0, active HIGH Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG123[12] = 1 cfg_clknotdata: SYSTEM_CONFIG123[20] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[4] =0 Alt func: SYSTEM_CONFIG102[18:16] = 011 Open drain: SYSTEM_CONFIG115[20] = to be set by user Pull up: SYSTEM_CONFIG112[20] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_error_oen) = 0, active LOW TSOUT0_VALID PIO6[4] C on DocID023557 Rev 10 fid en Name PIO6[5] TSIN1_VALID Desc PIO general purpose TS serial/parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[29,21] = pio6_cfg_delay_1,0[5] SYSTEM_CONFIG122[5] = pio6_cfg_clk1notclk0[5] SYSTEM_CONFIG123[29] = pio6_cfg_double_edge[5] SYSTEM_CONFIG123[21] = pio6_cfg_clknotdata[5] SYSTEM_CONFIG123[13] = pio6_cfg_retime[5] SYSTEM_CONFIG123[5] = pio6_cfg_invertclk[5] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG123[13] = 1 cfg_clknotdata: SYSTEM_CONFIG123[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[5] =0 Open drain: SYSTEM_CONFIG115[21] = to be set by user Pull up: SYSTEM_CONFIG112[21] = to be set by user Output enable: SYSTEM_CONFIG109[21] = 0, active HIGH PIO6[5] Alternate functions on PIO 558/604 Table 116. PIO6 (continued) TS serial/parallel output ti a O l Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG123[13] = 1 cfg_clknotdata: SYSTEM_CONFIG123[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[5] =0 Alt func: SYSTEM_CONFIG102[22:20] = 011 Open drain: SYSTEM_CONFIG115[21] = to be set by user Pull up: SYSTEM_CONFIG112[21] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_valid_oen) = 0, active LOW STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN0 (p), TSIN1 (s/p) TSIN3(s) TSOUT0 (s/p) Pin Name PIO6[6] TSIN1_PACKETCLK TSOUT0_PACKETCLK Desc PIO general purpose TS serial/parallel input TS serial/parallel output Dir B I O Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[30,22] = pio6_cfg_delay_1,0[6] SYSTEM_CONFIG122[6] = pio6_cfg_clk1notclk0[6] SYSTEM_CONFIG123[30] = pio6_cfg_double_edge[6] SYSTEM_CONFIG123[22] = pio6_cfg_clknotdata[6] SYSTEM_CONFIG123[14] = pio6_cfg_retime[6] SYSTEM_CONFIG123[6] = pio6_cfg_invertclk[6] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG123[14] = 1 cfg_clknotdata: SYSTEM_CONFIG123[22] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[6] =0 Open drain: SYSTEM_CONFIG115[22] = to be set by user Pull up: SYSTEM_CONFIG112[22] = to be set by user Output enable: SYSTEM_CONFIG109[22] = 0, active HIGH Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG123[14] = 1 cfg_clknotdata: SYSTEM_CONFIG123[22] = 0 cfg_clk1notclk0: SYSTEM_CONFIG122[6] =0 Alt func: SYSTEM_CONFIG102[26:24] = 011 Open drain: SYSTEM_CONFIG115[22] = to be set by user Pull up: SYSTEM_CONFIG112[22] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_packetclk_oen) = 0, active LOW TSOUT0_BYTECLK PIO6[6] C on DocID023557 Rev 10 fid en PIO6[7] TSIN1_BYTECLK Desc PIO general purpose TS serial/parallel input Dir B B Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG122[31,23] = pio6_cfg_delay_1,0[7] SYSTEM_CONFIG122[7] = pio6_cfg_clk1notclk0[7] SYSTEM_CONFIG123[31] = pio6_cfg_double_edge[7] SYSTEM_CONFIG123[23] = pio6_cfg_clknotdata[7] SYSTEM_CONFIG123[15] = pio6_cfg_retime[7] SYSTEM_CONFIG123[7] = pio6_cfg_invertclk[7] Retime: Input clock cfg_clknotdata: SYSTEM_CONFIG123[23] = 1 Alt func: SYSTEM_CONFIG102[30:28] = 001 Open drain: SYSTEM_CONFIG115[23] = to be set by user Pull up: SYSTEM_CONFIG112[23] = to be set by user Output enable: SYSTEM_CONFIG109[23] = to be set by user, active HIGH PIO6[7] TS serial/parallel output ti a B l 559/604 Information classified Confidential - Do not copy (See last page for obligations) Retime: Output clock cfg_clknotdata: SYSTEM_CONFIG123[23] = 1 cfg_clk1notclk0 (output): SYSTEM_CONFIG122[7] = 0 Alt func: SYSTEM_CONFIG102[30:28] = 011 Open drain: SYSTEM_CONFIG115[23] = to be set by user Pull up: SYSTEM_CONFIG112[23] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_byteclk_oen) = to be set by user, active LOW Alternate functions on PIO Name STiH271EL Table 116. PIO6 (continued) Confidential PIO7 Table 117. PIO7 Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN1 (serial/parallel) SSC2 TSOUT0 (serial/parallel) Pin Name PIO7[0] TSIN1_DATA[7] SSC2_MRST TSOUT0_DATA[7] Desc PIO general purpose TS serial/parallel input SSC - data bit master receive/slave transmit, full duplex TS serial/parallel output Dir B B O Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[24,16] = pio7_cfg_delay_1,0[0] SYSTEM_CONFIG124[0] = pio7_cfg_clk1notclk0[0] SYSTEM_CONFIG125[24] = pio7_cfg_double_edge[0] SYSTEM_CONFIG125[16] = pio7_cfg_clknotdata[0] SYSTEM_CONFIG125[8] = pio7_cfg_retime[0] SYSTEM_CONFIG125[0] = pio7_cfg_invertclk[0] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[8] = 1 cfg_clknotdata: SYSTEM_CONFIG125[16] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[0] =0 Open drain: SYSTEM_CONFIG115[24] = to be set by user Pull up: SYSTEM_CONFIG112[24] = to be set by user Output enable: SYSTEM_CONFIG109[24] = 0, active HIGH Alt func: SYSTEM_CONFIG103[2:0] = 010 Open drain: SYSTEM_CONFIG115[24] = to be set by user Pull up: SYSTEM_CONFIG112[24] = to be set by user Output enable: SYSTEM_CONFIG109[24] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[8] = 1 cfg_clknotdata: SYSTEM_CONFIG125[16] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[0] =0 Alt func: SYSTEM_CONFIG103[2:0] = 011 Open drain: SYSTEM_CONFIG115[24] = to be set by user Pull up: SYSTEM_CONFIG112[24] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_7_oen) = 0, active LOW Name PIO7[1] TSIN1_DATA[6] Desc PIO general purpose TS parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[25,17] = pio7_cfg_delay_1,0[1] SYSTEM_CONFIG124[1] = pio7_cfg_clk1notclk0[1] SYSTEM_CONFIG125[25] = pio7_cfg_double_edge[1] SYSTEM_CONFIG125[17] = pio7_cfg_clknotdata[1] SYSTEM_CONFIG125[9] = pio7_cfg_retime[1] SYSTEM_CONFIG125[1] = pio7_cfg_invertclk[1] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[9] = 1 cfg_clknotdata: SYSTEM_CONFIG125[17] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[1] =0 Open drain: SYSTEM_CONFIG115[25] = to be set by user Pull up: SYSTEM_CONFIG112[25] = to be set by user Output enable: SYSTEM_CONFIG109[25] = 0, active HIGH PIO7[0] DocID023557 Rev 10 PIO7[1] C I on fid en ti a Alternate functions on PIO 560/604 25.2.8 TSOUT0_DATA[6] TS parallel output l Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[9] = 1 cfg_clknotdata: SYSTEM_CONFIG125[17] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[1] =0 Alt func: SYSTEM_CONFIG103[6:4] = 011 Open drain: SYSTEM_CONFIG115[25] = to be set by user Pull up: SYSTEM_CONFIG112[25] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_6_oen) = 0, active LOW STiH271EL Information classified Confidential - Do not copy (See last page for obligations) O Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN1 (serial/parallel) SSC2 TSOUT0 (serial/parallel) Pin Name PIO7[2] TSIN1_DATA[5] TSOUT0_DATA[5] Desc PIO general purpose TS parallel input TS parallel output Dir B I O Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[26,18] = pio7_cfg_delay_1,0[2] SYSTEM_CONFIG124[2] = pio7_cfg_clk1notclk0[2] SYSTEM_CONFIG125[26] = pio7_cfg_double_edge[2] SYSTEM_CONFIG125[18] = pio7_cfg_clknotdata[2] SYSTEM_CONFIG125[10] = pio7_cfg_retime[2] SYSTEM_CONFIG125[2] = pio7_cfg_invertclk[2] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[10] = 1 cfg_clknotdata: SYSTEM_CONFIG125[18] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[2] =0 Open drain: SYSTEM_CONFIG115[26] = to be set by user Pull up: SYSTEM_CONFIG112[26] = to be set by user Output enable: SYSTEM_CONFIG109[26] = 0, active HIGH Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[10] = 1 cfg_clknotdata: SYSTEM_CONFIG125[18] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[2] =0 Alt func: SYSTEM_CONFIG103[10:8] = 011 Open drain: SYSTEM_CONFIG115[26] = to be set by user Pull up: SYSTEM_CONFIG112[26] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_5_oen) = 0, active LOW PIO7[3] TSIN1_DATA[4] TSOUT0_DATA[4] Desc PIO general purpose TS parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[27,19] = pio7_cfg_delay_1,0[3] SYSTEM_CONFIG124[3] = pio7_cfg_clk1notclk0[3] SYSTEM_CONFIG125[27] = pio7_cfg_double_edge[3] SYSTEM_CONFIG125[19] = pio7_cfg_clknotdata[3] SYSTEM_CONFIG125[11] = pio7_cfg_retime[3] SYSTEM_CONFIG125[3] = pio7_cfg_invertclk[3] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[11] = 1 cfg_clknotdata: SYSTEM_CONFIG125[19] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[3] =0 Open drain: SYSTEM_CONFIG115[27] = to be set by user Pull up: SYSTEM_CONFIG112[27] = to be set by user Output enable: SYSTEM_CONFIG109[27] = 0, active HIGH PIO7[2] DocID023557 Rev 10 Name PIO7[3] C on fid en STiH271EL Table 117. PIO7 (continued) TS parallel output ti a O l Alternate functions on PIO 561/604 Information classified Confidential - Do not copy (See last page for obligations) Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[11] = 1 cfg_clknotdata: SYSTEM_CONFIG125[19] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[3] =0 Alt func: SYSTEM_CONFIG103[14:12] = 011 Open drain: SYSTEM_CONFIG115[27] = to be set by user Pull up: SYSTEM_CONFIG112[27] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_4_oen) = 0, active LOW Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN1 (serial/parallel) SSC2 TSOUT0 (serial/parallel) Pin Name PIO7[4] TSIN1_DATA[3] TSOUT0_DATA[3] Desc PIO general purpose TS parallel input TS parallel output Dir B I O Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[28,20] = pio7_cfg_delay_1,0[4] SYSTEM_CONFIG124[4] = pio7_cfg_clk1notclk0[4] SYSTEM_CONFIG125[28] = pio7_cfg_double_edge[4] SYSTEM_CONFIG125[20] = pio7_cfg_clknotdata[4] SYSTEM_CONFIG125[12] = pio7_cfg_retime[4] SYSTEM_CONFIG125[4] = pio7_cfg_invertclk[4] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[12] = 1 cfg_clknotdata: SYSTEM_CONFIG125[20] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[4] =0 Open drain: SYSTEM_CONFIG115[28] = to be set by user Pull up: SYSTEM_CONFIG112[28] = to be set by user Output enable: SYSTEM_CONFIG109[28] = 0, active HIGH Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[12] = 1 cfg_clknotdata: SYSTEM_CONFIG125[20] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[4] =0 Alt func: SYSTEM_CONFIG103[17:16] = 11 Open drain: SYSTEM_CONFIG115[28] = to be set by user Pull up: SYSTEM_CONFIG112[28] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_3_oen) = 0, active LOW PIO7[5] TSIN1_DATA[2] TSOUT0_DATA[2] Desc PIO general purpose TS parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[29,21] = pio7_cfg_delay_1,0[5] SYSTEM_CONFIG124[5] = pio7_cfg_clk1notclk0[5] SYSTEM_CONFIG125[29] = pio7_cfg_double_edge[5] SYSTEM_CONFIG125[21] = pio7_cfg_clknotdata[5] SYSTEM_CONFIG125[13] = pio7_cfg_retime[5] SYSTEM_CONFIG125[5] = pio7_cfg_invertclk[5] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[13] = 1 cfg_clknotdata: SYSTEM_CONFIG125[21] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[5] =0 Open drain: SYSTEM_CONFIG115[29] = to be set by user Pull up: SYSTEM_CONFIG112[29] = to be set by user Output enable: SYSTEM_CONFIG109[29] = 0, active HIGH PIO7[4] DocID023557 Rev 10 Name PIO7[5] C on fid en Alternate functions on PIO 562/604 Table 117. PIO7 (continued) TS parallel output ti a O l Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[13] = 1 cfg_clknotdata: SYSTEM_CONFIG125[21] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[5] =0 Alt func: SYSTEM_CONFIG103[22:20] = 011 Open drain: SYSTEM_CONFIG115[29] = to be set by user Pull up: SYSTEM_CONFIG112[29] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_2_oen) = 0, active LOW STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Function Standard PIO TSIN1 (serial/parallel) SSC2 TSOUT0 (serial/parallel) Pin Name PIO7[6] TSIN1_DATA[1] SSC2_SCL TSOUT0_DATA[1] Desc PIO general purpose TS parallel input SSC serial clock TS parallel output Dir B I B O Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[30,22] = pio7_cfg_delay_1,0[6] SYSTEM_CONFIG124[6] = pio7_cfg_clk1notclk0[6] SYSTEM_CONFIG125[30] = pio7_cfg_double_edge[6] SYSTEM_CONFIG125[22] = pio7_cfg_clknotdata[6] SYSTEM_CONFIG125[14] = pio7_cfg_retime[6] SYSTEM_CONFIG125[6] = pio7_cfg_invertclk[6] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[14] = 1 cfg_clknotdata: SYSTEM_CONFIG125[22] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[6] =0 Open drain: SYSTEM_CONFIG115[30] = to be set by user Pull up: SYSTEM_CONFIG112[30] = to be set by user Output enable: SYSTEM_CONFIG109[30] = 0, active HIGH Alt func: SYSTEM_CONFIG103[26:24] = 010 Open drain: SYSTEM_CONFIG115[30] = to be set by user Pull up: SYSTEM_CONFIG112[30] = to be set by user Output enable: SYSTEM_CONFIG109[30] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[14] = 1 cfg_clknotdata: SYSTEM_CONFIG125[22] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[6] =0 Alt func: SYSTEM_CONFIG103[26:24] = 011 Open drain: SYSTEM_CONFIG115[30] = to be set by user Pull up: SYSTEM_CONFIG112[30] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_1_oen) = 0, active LOW TSIN1_DATA[0] SSC2_MTSR PIO7[6] DocID023557 Rev 10 Name PIO7[7] C on fid en PIO general purpose TS parallel input Dir B I Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG124[31,23] = pio7_cfg_delay_1,0[7] SYSTEM_CONFIG124[7] = pio7_cfg_clk1notclk0[7] SYSTEM_CONFIG125[31] = pio7_cfg_double_edge[7] SYSTEM_CONFIG125[23] = pio7_cfg_clknotdata[7] SYSTEM_CONFIG125[15] = pio7_cfg_retime[7] SYSTEM_CONFIG125[7] = pio7_cfg_invertclk[7] Retime: Data retimed by clock TSIN1_BYTECLK cfg_retime: SYSTEM_CONFIG125[15] = 1 cfg_clknotdata: SYSTEM_CONFIG125[23] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[7] =0 Open drain: SYSTEM_CONFIG115[31] = to be set by user Pull up: SYSTEM_CONFIG112[31] = to be set by user Output enable: SYSTEM_CONFIG109[31] = 0, active HIGH PIO7[7] TSOUT0_DATA[0] SSC data bit for half duplex TS parallel output B O ti a l Alt func: SYSTEM_CONFIG103[30:28] = 010 Open drain: SYSTEM_CONFIG115[31] = to be set by user Pull up: SYSTEM_CONFIG112[31] = to be set by user Output enable: SYSTEM_CONFIG109[31] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed 563/604 Information classified Confidential - Do not copy (See last page for obligations) Retime: Data retimed by clock TSOUT0_BYTECLK cfg_retime: SYSTEM_CONFIG125[15] = 1 cfg_clknotdata: SYSTEM_CONFIG125[23] =0 cfg_clk1notclk0: SYSTEM_CONFIG124[7] =0 Alt func: SYSTEM_CONFIG103[30:28] = 011 Open drain: SYSTEM_CONFIG115[31] = to be set by user Pull up: SYSTEM_CONFIG112[31] = to be set by user Output enable: dvbs2ip_sass1 (tsout0_data_0_oen) = 0, active LOW Alternate functions on PIO Desc STiH271EL Table 117. PIO7 (continued) Confidential PIO8 Table 118. PIO8 Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO TSIN2 (serial), TSIN3 (serial) PIO8[0] VALIDATION_OUTPUT TSIN2_ERROR ST-only validation function. Safe to keep default function if PIO not used by application C Desc PIO general purpose TS serial input Dir B I Config Partition: Bank1 Retime logic control: SYSTEM_CONFIG126[24,16] = pio8_cfg_delay_1,0[0] SYSTEM_CONFIG126[0] = pio8_cfg_clk1notclk0[0] SYSTEM_CONFIG127[24] = pio8_cfg_double_edge[0] SYSTEM_CONFIG127[16] = pio8_cfg_clknotdata[0] SYSTEM_CONFIG127[8] = pio8_cfg_retime[0] SYSTEM_CONFIG127[0] = pio8_cfg_invertclk[0] Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG127[8] = 1 cfg_clknotdata: SYSTEM_CONFIG127[16] = 0 cfg_clk1notclk0: SYSTEM_CONFIG126[0] = 0 Open drain: SYSTEM_CONFIG116[0] = to be set by user Pull up: SYSTEM_CONFIG113[0] = to be set by user Output enable: SYSTEM_CONFIG110[0] = 0, active HIGH PIO8[0] TSIN2 (parallel) on Alternate functions on PIO 564/604 25.2.9 O DocID023557 Rev 10 fid en (Default) ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO PIO8[1] TSIN2 (serial), TSIN3 (serial) TSIN2 (parallel) TSIN2_VALID VALIDATION_OUTPUT ST-only validation function. Safe to keep default function if PIO not used by application Desc PIO general purpose TS serial input Dir B I Config Retime: Data retimed by clock Partition: Bank1 TSIN2_BYTECLK Retime logic control: cfg_retime: SYSTEM_CONFIG126[25,17] SYSTEM_CONFIG127[9] = 1 = pio8_cfg_delay_1,0[1] cfg_clknotdata: SYSTEM_CONFIG126[1] = SYSTEM_CONFIG127[17] = 0 pio8_cfg_clk1notclk0[1] cfg_clk1notclk0: SYSTEM_CONFIG127[25] = SYSTEM_CONFIG126[1] = 0 pio8_cfg_double_edge[1] Open drain: SYSTEM_CONFIG127[17] = SYSTEM_CONFIG116[1] = to be pio8_cfg_clknotdata[1] set by user SYSTEM_CONFIG127[9] = Pull up: SYSTEM_CONFIG113[1] = pio8_cfg_retime[1] to be set by user SYSTEM_CONFIG127[1] = Output enable: pio8_cfg_invertclk[1] SYSTEM_CONFIG110[1] = 0, active HIGH C STiH271EL Table 118. PIO8 (continued) O on PIO8[1] DocID023557 Rev 10 fid (Default) en ti a l Alternate functions on PIO 565/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO TSIN2 (serial), TSIN3 (serial) PIO8[2] TSIN2 (parallel) TSIN2_PACKETCLK VALIDATION_OUTPUT ST-only validation function. Safe to keep default function if PIO not used by application Desc PIO general purpose TS serial input Dir B I Config Retime: Data retimed by clock TSIN2_BYTECLK Partition: Bank1 cfg_retime: Retime logic control: SYSTEM_CONFIG127[10] = 1 SYSTEM_CONFIG126[26,18] cfg_clknotdata: = pio8_cfg_delay_1,0[2] SYSTEM_CONFIG127[18] = 0 SYSTEM_CONFIG126[2] = cfg_clk1notclk0: pio8_cfg_clk1notclk0[2] SYSTEM_CONFIG126[2] = 0 SYSTEM_CONFIG127[26] = Open drain: pio8_cfg_double_edge[2] SYSTEM_CONFIG116[2] = to be SYSTEM_CONFIG127[18] = set by user pio8_cfg_clknotdata[2] Pull up: SYSTEM_CONFIG113[2] = SYSTEM_CONFIG127[10] = to be set by user pio8_cfg_retime[2] Output enable: SYSTEM_CONFIG127[2] = SYSTEM_CONFIG110[2] = 0, pio8_cfg_invertclk[2] active HIGH C O Alternate functions on PIO 566/604 Table 118. PIO8 (continued) on PIO8[2] DocID023557 Rev 10 PIO8[3] TSIN2_BYTECLK Desc PIO general purpose TS serial input Dir B B Config (Default) Partition: Bank1 Retime logic control: SYSTEM_CONFIG126[27,19] = pio8_cfg_delay_1,0[3] SYSTEM_CONFIG126[3] = pio8_cfg_clk1notclk0[3] SYSTEM_CONFIG127[27] = pio8_cfg_double_edge[3] SYSTEM_CONFIG127[19] = pio8_cfg_clknotdata[3] SYSTEM_CONFIG127[11] = pio8_cfg_retime[3] SYSTEM_CONFIG127[3] = pio8_cfg_invertclk[3] Retime: Input clock cfg_clknotdata: SYSTEM_CONFIG127[19] = 1 Alt func: SYSTEM_CONFIG104[14:12] = 001 Open drain: SYSTEM_CONFIG116[3] = to be set by user Pull up: SYSTEM_CONFIG113[3] = to be set by user Output enable: SYSTEM_CONFIG110[3] = to be set by user, active HIGH PIO8[3] (Default) en ti a l Information classified Confidential - Do not copy (See last page for obligations) STiH271EL Name fid Confidential Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO PIO8[4] TSIN2 (serial), TSIN3 (serial) TSIN2 (parallel) TSIN2_DATA[7] VALIDATION_OUTPUT ST-only validation function. Safe to keep default function if PIO not used by application Desc PIO general purpose TS serial input Dir B I Config Retime: Data retimed by clock Partition: Bank1 TSIN2_BYTECLK Retime logic control: cfg_retime: SYSTEM_CONFIG126[28,20] SYSTEM_CONFIG127[12] = 1 = pio8_cfg_delay_1,0[4] cfg_clknotdata: SYSTEM_CONFIG126[4] = SYSTEM_CONFIG127[20] = 0 pio8_cfg_clk1notclk0[4] cfg_clk1notclk0: SYSTEM_CONFIG127[28] = SYSTEM_CONFIG126[4] = 0 pio8_cfg_double_edge[4] Open drain: SYSTEM_CONFIG127[20] = SYSTEM_CONFIG116[4] = to be pio8_cfg_clknotdata[4] set by user SYSTEM_CONFIG127[12] = Pull up: SYSTEM_CONFIG113[4] = pio8_cfg_retime[4] to be set by user SYSTEM_CONFIG127[4] = Output enable: pio8_cfg_invertclk[4] SYSTEM_CONFIG110[4] = 0, active HIGH C STiH271EL Table 118. PIO8 (continued) O on PIO8[4] DocID023557 Rev 10 fid (Default) en ti a l Alternate functions on PIO 567/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO PIO8[5] TSIN2 (serial), TSIN3 (serial) TSIN3_ERROR Desc PIO general purpose TS serial input Dir B I Config Retime: data retimed by clock TSIN3_BYTECLK cfg_retime: Partition: Bank1 SYSTEM_CONFIG127[13] = 1 Retime logic control: cfg_clknotdata: SYSTEM_CONFIG126[29,21] SYSTEM_CONFIG127[21] = 0 = pio8_cfg_delay_1,0[5] cfg_clk1notclk0: SYSTEM_CONFIG126[5] = SYSTEM_CONFIG126[5] = 0 pio8_cfg_clk1notclk0[5] Open drain: SYSTEM_CONFIG127[29] = SYSTEM_CONFIG116[5] = to be pio8_cfg_double_edge[5] set by user SYSTEM_CONFIG127[21] = Pull up: SYSTEM_CONFIG113[5] = pio8_cfg_clknotdata[5] to be set by user SYSTEM_CONFIG127[13] = Output enable: pio8_cfg_retime[5] SYSTEM_CONFIG110[5] = 0, SYSTEM_CONFIG127[5] = active HIGH pio8_cfg_invertclk[5] Data input: Demultiplexed by alt func C on PIO8[5] TSIN2 (parallel) TSIN2_DATA[6] VALIDATION_OUTPUT SSC2_MRST TS serial input ST-only validation function. Safe to keep default function if PIO not used by application SSC data bit master receive/slave transmit, full duplex I O B DocID023557 Rev 10 Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG127[13] = 1 cfg_clknotdata: SYSTEM_CONFIG127[21] = 0 cfg_clk1notclk0: SYSTEM_CONFIG126[5] = 1 Open drain: (Default) SYSTEM_CONFIG116[5] = to be set by user Pull up: SYSTEM_CONFIG113[5] = to be set by user Output enable: SYSTEM_CONFIG110[5] = 0, active HIGH fid en ti a l Alternate functions on PIO 568/604 Table 118. PIO8 (continued) Alt func: SYSTEM_CONFIG10 4[22:20] = 101 Open drain: SYSTEM_CONFIG11 6[5] = to be set by user Pull up: SYSTEM_CONFIG11 3[5] = to be set by user Output enable: SYSTEM_CONFIG11 0[5] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO PIO8[6] TSIN2 (serial), TSIN3 (serial) TSIN3_VALID Desc PIO general purpose TS serial input Dir B I C on PIO8[6] DocID023557 Rev 10 Config Retime: Data retimed by clock TSIN3_BYTECLK Partition: Bank1 cfg_retime: Retime logic control: SYSTEM_CONFIG127[14] = 1 SYSTEM_CONFIG126[30,22] cfg_clknotdata: = pio8_cfg_delay_1,0[6] SYSTEM_CONFIG127[22] = 0 SYSTEM_CONFIG126[6] = cfg_clk1notclk0: pio8_cfg_clk1notclk0[6] SYSTEM_CONFIG126[6] = 0 SYSTEM_CONFIG127[30] = Open drain: pio8_cfg_double_edge[6] SYSTEM_CONFIG116[6] = to be SYSTEM_CONFIG127[22] = set by user pio8_cfg_clknotdata[6] Pull up: SYSTEM_CONFIG113[6] = SYSTEM_CONFIG127[14] = to be set by user pio8_cfg_retime[6] Output enable: SYSTEM_CONFIG127[6] = SYSTEM_CONFIG110[6] = 0, pio8_cfg_invertclk[6] active HIGH Data input: Demultiplexed by alt func TSIN2 (parallel) TSIN2_DATA[5] VALIDATION_OUTPUT EXTDMA_REQ0 SSC2_SCL TS serial input ST-only validation function. Safe to keep default function if PIO not used by application External DMA request SSC serial clock I O I B Alt func: SYSTEM_CONFIG10 4[26:24] = 100 Open drain: SYSTEM_CONFIG11 6 [6] = to be set by user Pull up: SYSTEM_CONFIG11 3[6] = to be set by user Output enable: SYSTEM_CONFIG11 0[6] = 0, active HIGH Cleaned input: When unselected at "0 Alt func: SYSTEM_CONFIG10 4[26:24]= 101 Open drain: SYSTEM_CONFIG11 6[6] = to be set by user Pull up: SYSTEM_CONFIG11 3[6] = to be set by user Output enable: SYSTEM_CONFIG11 0[6] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG127[14] = 1 cfg_clknotdata: SYSTEM_CONFIG127[22] = 0 cfg_clk1notclk0: SYSTEM_CONFIG126[6] = 1 Open drain: (Default) SYSTEM_CONFIG116[6] = to be set by user Pull up: SYSTEM_CONFIG113[6] = to be set by user Output enable: SYSTEM_CONFIG110[6] = 0, active HIGH fid en ti a l STiH271EL Table 118. PIO8 (continued) Alternate functions on PIO 569/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Pin Alternate 4 Alternate 5 EXTDMA_REQ SSC2 Alternate 3 Function Name Standard PIO PIO8[7] TSIN2 (serial), TSIN3 (serial) TSIN3_PACKETCLK Desc PIO general purpose TS serial input Dir B I C on PIO8[7] DocID023557 Rev 10 Config Retime: Data retimed by clock TSIN3_BYTECLK Partition: Bank1 cfg_retime: Retime logic control: SYSTEM_CONFIG127[15] = 1 SYSTEM_CONFIG126[31,23] cfg_clknotdata: = pio8_cfg_delay_1,0[7] SYSTEM_CONFIG127[23] = 0 SYSTEM_CONFIG126[7] = cfg_clk1notclk0: pio8_cfg_clk1notclk0[7] SYSTEM_CONFIG126[7] = 0 SYSTEM_CONFIG127[31] = Open drain: pio8_cfg_double_edge[7] SYSTEM_CONFIG116[7] = to be SYSTEM_CONFIG127[23] = set by user pio8_cfg_clknotdata[7] Pull up: SYSTEM_CONFIG113[7] = SYSTEM_CONFIG127[15] = to be set by user pio8_cfg_retime[7] Output enable: SYSTEM_CONFIG127[7] = SYSTEM_CONFIG110[7] = 0, pio8_cfg_invertclk[7] active HIGH Data input: Demultiplexed by alt func TSIN2 (parallel) TSIN2_DATA[4] VALIDATION_OUTPUT EXTDMA_REQ1 SSC2_MTSR TS serial input ST-only validation function. Safe to keep default function if PIO not used by application External DMA request SSC data bit master transmit/slave receive, full duplex I O I B Alt func: SYSTEM_CONFIG10 4[30:28] = 100 Open drain: SYSTEM_CONFIG11 6[7] = to be set by user Pull up: SYSTEM_CONFIG11 3[7] = to be set by user Output enable: SYSTEM_CONFIG11 0[7] = 0, active HIGH Cleaned input: When unselected at 0 Alt func: SYSTEM_CONFIG10 4[30:28] = 101 Open drain: SYSTEM_CONFIG11 6[7] = to be set by user Pull up: SYSTEM_CONFIG11 3[7] = to be set by user Output enable: SYSTEM_CONFIG11 0[7] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG127[15] = 1 cfg_clknotdata: SYSTEM_CONFIG127[23] = 0 cfg_clk1notclk0: SYSTEM_CONFIG126[7] = 1 Open drain: (Default) SYSTEM_CONFIG116[7] = to be set by user Pull up: SYSTEM_CONFIG113[7] = to be set by user Output enable: SYSTEM_CONFIG110[7] = 0, active HIGH fid en ti a l Alternate functions on PIO 570/604 Table 118. PIO8 (continued) STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO9 Table 119. PIO9 Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN3 (serial), SSC0, external interrupt 4 TSIN2 (p), SSC2, S/PDIF Pin Alternate 3 Name PIO9[0] TSIN3_BYTECLK TSIN2_DATA[3] Desc PIO general purpose TS serial input TS serial input Dir B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG128[24,16] = pio9_cfg_delay_1,0[0] SYSTEM_CONFIG128[0] = pio9_cfg_clk1notclk0[0] SYSTEM_CONFIG129[24] = pio9_cfg_double_edge[0] SYSTEM_CONFIG129[16] = pio9_cfg_clknotdata[0] SYSTEM_CONFIG129[8] = pio9_cfg_retime[0] SYSTEM_CONFIG129[0] = pio9_cfg_invertclk[0] Retime: Input clock cfg_clknotdata: SYSTEM_CONFIG129[16] =1 Alt func: SYSTEM_CONFIG105[2:0] = 001 Open drain: SYSTEM_CONFIG116[8] = to be set by user Pull up: SYSTEM_CONFIG113[8] = to be set by user Output enable: SYSTEM_CONFIG110[8] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG129[8] = 1 cfg_clknotdata: SYSTEM_CONFIG129[16] =0 cfg_clk1notclk0: SYSTEM_CONFIG128[0] =0 Open Drain: SYSTEM_CONFIG116[8] = to be set by user Pull Up: SYSTEM_CONFIG113[8] = to be set by user Output Enable: SYSTEM_CONFIG110[8] = 0, active HIGH Name PIO9[1] TSIN3_DATA[7] TSIN2_DATA[2] VALIDATION_OUTPUT Desc PIO general purpose TS serial input TS serial input ST-only validation function. Safe to keep default function if PIO not used by application Dir B I I Config Partition: Bank2 Retime logic control: SYSTEM_CONFIG128[25,17] = pio9_cfg_delay_1,0[1] SYSTEM_CONFIG128[1] = pio9_cfg_clk1notclk0[1] SYSTEM_CONFIG129[25] = pio9_cfg_double_edge[1] SYSTEM_CONFIG129[17] = pio9_cfg_clknotdata[1] SYSTEM_CONFIG129[9] = pio9_cfg_retime[1] SYSTEM_CONFIG129[1] = pio9_cfg_invertclk[1] Retime: Data retimed by clock TSIN3_BYTECLK cfg_retime: SYSTEM_CONFIG129[9] = 1 cfg_clknotdata: SYSTEM_CONFIG129[17] =0 cfg_clk1notclk0: SYSTEM_CONFIG128[1] =0 Open drain: SYSTEM_CONFIG116[9] = to be set by user Pull up: SYSTEM_CONFIG113[9] = to be set by user Output enable: SYSTEM_CONFIG110[9] = 0, active HIGH Data input: Demultiplexed by alt func Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG129[9] = 1 cfg_clknotdata: SYSTEM_CONFIG129[17] =0 cfg_clk1notclk0: SYSTEM_CONFIG128[1] =1 (Default) Open drain: SYSTEM_CONFIG116[9] = to be set by user Pull up: SYSTEM_CONFIG113[9] = to be set by user Output enable: SYSTEM_CONFIG110[9] = 0, active HIGH PIO9[0] DocID023557 Rev 10 B I on fid en ti a l 571/604 Information classified Confidential - Do not copy (See last page for obligations) O Alternate functions on PIO PIO9[1] C STiH271EL 25.2.10 Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN3 (serial), SSC0, external interrupt 4 TSIN2 (p), SSC2, S/PDIF Pin Alternate 3 Name PIO9[2] SSC0_SCL TSIN2_DATA[1] VALIDATION_OUTPUT Desc PIO general purpose SSC serial clock TS serial input ST-only validation function. Safe to keep default function if PIO not used by application Dir B B I O Config Partition: Bank2 Retime logic control: SYSTEM_CONFIG128[26,18] = pio9_cfg_delay_1,0[2] SYSTEM_CONFIG128[2] = pio9_cfg_clk1notclk0[2] SYSTEM_CONFIG129[26] = pio9_cfg_double_edge[2] SYSTEM_CONFIG129[18] = pio9_cfg_clknotdata[2] SYSTEM_CONFIG129[10] = pio9_cfg_retime[2] SYSTEM_CONFIG129[2] = pio9_cfg_invertclk[2] Alt func: SYSTEM_CONFIG105[10:8] = 001 Open drain: SYSTEM_CONFIG116[10] = to be set by user Pull up: SYSTEM_CONFIG113[10] = to be set by user Output enable: SYSTEM_CONFIG110[10] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG129[10] = 1 cfg_clknotdata: SYSTEM_CONFIG129[18] =0 cfg_clk1notclk0: SYSTEM_CONFIG128[2] (Default) =0 Open drain: SYSTEM_CONFIG116[10] = to be set by user Pull up: SYSTEM_CONFIG113[10] = to be set by user Output enable: SYSTEM_CONFIG110[10] = 0, active HIGH PIO9[2] C on DocID023557 Rev 10 fid en Name PIO9[3] SSC0_MTSR TSIN2_DATA[0] VALIDATION_OUTPUT Desc PIO general purpose SSC data bit for half duplex TS serial input ST-only validation function. Safe to keep default function if PIO not used by application Dir B B I Alt func: SYSTEM_CONFIG105[14:12] = 001 Open drain: SYSTEM_CONFIG116[11] = to be set by user Pull up: SYSTEM_CONFIG113[11] = to be set by user Output enable: SYSTEM_CONFIG110[11] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Retime: Data retimed by clock TSIN2_BYTECLK cfg_retime: SYSTEM_CONFIG129[11] = 1 cfg_clknotdata: SYSTEM_CONFIG129[19] =0 cfg_clk1notclk0: SYSTEM_CONFIG128[3] =0 (Default) Open drain: SYSTEM_CONFIG116[11] = to be set by user Pull up: SYSTEM_CONFIG113[11] = to be set by user Output enable: SYSTEM_CONFIG110[11] = 0, active HIGH PIO9[3] Config ti a l Information classified Confidential - Do not copy (See last page for obligations) O STiH271EL Partition: Bank2 Retime logic control: SYSTEM_CONFIG128[27,19] = pio9_cfg_delay_1,0[3] SYSTEM_CONFIG128[3] = pio9_cfg_clk1notclk0[3] SYSTEM_CONFIG129[27] = pio9_cfg_double_edge[3] SYSTEM_CONFIG129[19] = pio9_cfg_clknotdata[3] SYSTEM_CONFIG129[11] = pio9_cfg_retime[3] SYSTEM_CONFIG129[3] = pio9_cfg_invertclk[3] Alternate functions on PIO 572/604 Table 119. PIO9 (continued) Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN3 (serial), SSC0, external interrupt 4 TSIN2 (p), SSC2, S/PDIF Pin Name PIO9[4] SSC2_SCL Desc PIO general purpose SSC serial clock Dir B B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG128[28,20] = pio9_cfg_delay_1,0[4] SYSTEM_CONFIG128[4] = pio9_cfg_clk1notclk0[4] SYSTEM_CONFIG129[28] = pio9_cfg_double_edge[4] SYSTEM_CONFIG129[20] = pio9_cfg_clknotdata[4] SYSTEM_CONFIG129[12] = pio9_cfg_retime[4] SYSTEM_CONFIG129[4] = pio9_cfg_invertclk[4] PIO9[4] Alternate 3 C on DocID023557 Rev 10 fid Alt func: SYSTEM_CONFIG105[18:16] = 010 Open drain: SYSTEM_CONFIG116[12] = to be set by user Pull up: SYSTEM_CONFIG113[12] = to be set by user Output enable: SYSTEM_CONFIG110[12] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed en Name PIO9[5] Desc PIO general purpose SSC data bit for half duplex Dir B B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG128[29,21] = pio9_cfg_delay_1,0[5] SYSTEM_CONFIG128[5] = pio9_cfg_clk1notclk0[5] SYSTEM_CONFIG129[29] = pio9_cfg_double_edge[5] SYSTEM_CONFIG129[21] = pio9_cfg_clknotdata[5] SYSTEM_CONFIG129[13] = pio9_cfg_retime[5] SYSTEM_CONFIG129[5] = pio9_cfg_invertclk[5] Alt func: SYSTEM_CONFIG105[22:20] = 010 Open drain: SYSTEM_CONFIG116[13] = to be set by user Pull up: SYSTEM_CONFIG113[13] = to be set by user Output enable: SYSTEM_CONFIG110[13] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed PIO9[5] STiH271EL Table 119. PIO9 (continued) SSC2_MTSR ti a l Alternate functions on PIO 573/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO TSIN3 (serial), SSC0, external interrupt 4 TSIN2 (p), SSC2, S/PDIF Pin Alternate 3 Name PIO9[6] EXT_IT[4] AUDSPDIF_OUT Desc PIO general purpose External interrupt S/PDIF out Dir B I O Alt func: SYSTEM_CONFIG105[25:24] = 10 Open drain: SYSTEM_CONFIG116[14] = to be set by user Pull up: SYSTEM_CONFIG113[14] = to be set by user Output enable: SYSTEM_CONFIG110[14] = 1, active HIGH Data output: Multiplexed SSC2_MRST Config (Default) Partition: Bank2 Alt func: SYSTEM_CONFIG105[25:24] = 01 Open drain: SYSTEM_CONFIG116[14] = to be set by user Pull up: SYSTEM_CONFIG113[14] = to be set by user Output enable: SYSTEM_CONFIG110[14] = 0, active HIGH Cleaned input: When unselected at 0 Name PIO9[7] SSC0_MRST Desc PIO general purpose SSC data bit master receive/slave transmit, full duplex Dir B B (Default) Partition: Bank2 Alt func: SYSTEM_CONFIG105[29:28] = 01 Open drain: SYSTEM_CONFIG116[15] = to be set by user Pull up: SYSTEM_CONFIG113[15] = to be set by user Output enable: SYSTEM_CONFIG110[15] = to be set by user, active HIGH C PIO9[6] DocID023557 Rev 10 PIO9[7] Config on fid Alternate functions on PIO 574/604 Table 119. PIO9 (continued) SSC data bit master receive/slave transmit, full duplex en B Alt func: SYSTEM_CONFIG105[29:28] = 10 Open drain: SYSTEM_CONFIG116[15] = to be set by user Pull up: SYSTEM_CONFIG113[15] = to be set by user Output enable: SYSTEM_CONFIG110[15] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO10 Table 120. PIO10 Parameter PIO Alternate 1 Alternate 2 Function Standard PIO Smartcard0 UART 0 Alternate 4 Pin Alternate 3 SSC2, NMI Alternate 5 ClockGen A0, A1 clock observation Name PIO10[0] SC0_C4 UART0_TXD CKGENA0_CLK1 Desc PIO general purpose Smartcard UART transmit signal ClockGen A0 left clock output Dir B B O O Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG130[24,1 6] = pio10_cfg_delay_1,0[0] SYSTEM_CONFIG130[0] = pio10_cfg_clk1notclk0[0] SYSTEM_CONFIG131[24] = pio10_cfg_double_edge[0] SYSTEM_CONFIG131[16] = pio10_cfg_clknotdata[0] SYSTEM_CONFIG131[8] = pio10_cfg_retime[0] SYSTEM_CONFIG131[0] = pio10_cfg_invertclk[0] Alt func: SYSTEM_CONFIG106[2:0 ] = 001 Open drain: SYSTEM_CONFIG116[16] = to be set by user Pull up: SYSTEM_CONFIG113[16] = to be set by user Output enable: SYSTEM_CONFIG110[16] = to be set by user, active HIGH Alt func: SYSTEM_CONFIG106[2:0] = 010 Open drain: SYSTEM_CONFIG116[16] = to be set by user Pull up: SYSTEM_CONFIG113[16] = to be set by user Output enable: SYSTEM_CONFIG110[16] = 1, active HIGH Name PIO10[1] SC0_C7 UART0_RXD Desc PIO general purpose Smartcard UART receive signal Dir B B I O Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG130[25,1 7] = pio10_cfg_delay_1,0[1] SYSTEM_CONFIG130[1] = pio10_cfg_clk1notclk0[1] SYSTEM_CONFIG131[25] = pio10_cfg_double_edge[1] SYSTEM_CONFIG131[17] = pio10_cfg_clknotdata[1] SYSTEM_CONFIG131[9] = pio10_cfg_retime[1] SYSTEM_CONFIG131[1] = pio10_cfg_invertclk[1] Alt func: SYSTEM_CONFIG106[6:4 ] = 001 Open drain: SYSTEM_CONFIG116[17] = to be set by user Pull up: SYSTEM_CONFIG113[17] = to be set by user Output enable: SYSTEM_CONFIG110[17] = to be set by user, active HIGH Open drain: SYSTEM_CONFIG116[17] = to be set by user Pull up: SYSTEM_CONFIG113[17] = to be set by user Output enable: SYSTEM_CONFIG110[17] = 0, active HIGH Alt func: SYSTEM_CONFIG106[6:4] = 101 Open drain: SYSTEM_CONFIG116[17] = to be set by user Pull up: SYSTEM_CONFIG113[17] = to be set by user Output enable: SYSTEM_CONFIG110[17] = 1, active HIGH PIO10[0] DocID023557 Rev 10 on Alt func: SYSTEM_CONFIG106[2:0] = 101 Open drain: SYSTEM_CONFIG116[16] = to be set by user Pull up: SYSTEM_CONFIG113[16] = to be set by user Output enable: SYSTEM_CONFIG110[16] = 1, active HIGH fid en ti a CKGENA1_CLK1 l 575/604 Information classified Confidential - Do not copy (See last page for obligations) ClockGen A1 left clock output Alternate functions on PIO PIO10[1] C STiH271EL 25.2.11 Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 4 Pin Alternate 3 Function Name Standard PIO Smartcard0 UART 0 SSC2, NMI PIO10[2] SC0_RESET UART0_CTS Desc PIO general purpose Smartcard UART clear to send signal Dir B O I Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG130[26,1 8] = pio10_cfg_delay_1,0[2] SYSTEM_CONFIG130[2] = pio10_cfg_clk1notclk0[2] SYSTEM_CONFIG131[26] = pio10_cfg_double_edge[2] SYSTEM_CONFIG131[18] = pio10_cfg_clknotdata[2] SYSTEM_CONFIG131[10] = pio10_cfg_retime[2] SYSTEM_CONFIG131[2] = pio10_cfg_invertclk[2] Alt func: SYSTEM_CONFIG106[10: 8] = 001 Open drain: SYSTEM_CONFIG116[18] = to be set by user Pull up: SYSTEM_CONFIG113[18] = to be set by user Output enable: SYSTEM_CONFIG110[18] = 1, active HIGH Open drain: SYSTEM_CONFIG116[18] = to be set by user Pull up: SYSTEM_CONFIG113[18] = to be set by user Output enable: SYSTEM_CONFIG110[18] = 0, active HIGH Name PIO10[3] SC0_NOTSETVCC UART0_RTS Desc PIO general purpose Smartcard UART ready to send signal Dir B O O Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG130[27,1 9] = pio10_cfg_delay_1,0[3] SYSTEM_CONFIG130[3] = pio10_cfg_clk1notclk0[3] SYSTEM_CONFIG131[27] = pio10_cfg_double_edge[3] SYSTEM_CONFIG131[19] = pio10_cfg_clknotdata[3] SYSTEM_CONFIG131[11] = pio10_cfg_retime[3] SYSTEM_CONFIG131[3] = pio10_cfg_invertclk[3] Alt func: SYSTEM_CONFIG106[14: 12] = 001 Open drain: SYSTEM_CONFIG116[19] = to be set by user Pull up: SYSTEM_CONFIG113[19] = to be set by user Output enable: SYSTEM_CONFIG110[19] = 1, active HIGH Alt func: SYSTEM_CONFIG106[14:1 2] = 010 Open drain: SYSTEM_CONFIG116[19] = to be set by user Pull up: SYSTEM_CONFIG113[19] = to be set by user Output enable: SYSTEM_CONFIG110[19] = 1, active HIGH PIO10[2] DocID023557 Rev 10 PIO10[3] C Alternate 5 ClockGen A0, A1 clock observation Alternate functions on PIO 576/604 Table 120. PIO10 (continued) on fid en ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 4 Pin Alternate 3 Function Name Standard PIO Smartcard0 PIO10[4] SC0_NOTSETVPP UART 0 SSC2, NMI UART0_NOTOE NMI Desc PIO general purpose Smartcard UART output enable Non-maskable interrupt Dir B O O I Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG130[28,2 0] = pio10_cfg_delay_1,0[4] SYSTEM_CONFIG130[4] = pio10_cfg_clk1notclk0[4] SYSTEM_CONFIG131[28] = pio10_cfg_double_edge[4] SYSTEM_CONFIG131[20] = pio10_cfg_clknotdata[4] SYSTEM_CONFIG131[12] = pio10_cfg_retime[4] SYSTEM_CONFIG131[4] = pio10_cfg_invertclk[4] Alt func: SYSTEM_CONFIG106[18: 16] = 001 Open drain: SYSTEM_CONFIG116[20] = to be set by user Pull up: SYSTEM_CONFIG113[20] = to be set by user Output enable: SYSTEM_CONFIG110[20] = 1, active HIGH Alt func: SYSTEM_CONFIG106[18:1 6] = 010 Open drain: SYSTEM_CONFIG116[20] = to be set by user Pull up: SYSTEM_CONFIG113[20] = to be set by user Output enable: SYSTEM_CONFIG110[20] = 1, active HIGH Alt func: SYSTEM_CONFIG106[18:1 6] = 100 Open drain: SYSTEM_CONFIG116[20] = to be set by user Pull up: SYSTEM_CONFIG113[20] = to be set by user Output enable: SYSTEM_CONFIG110[20] = 0, active HIGH Cleaned input: When unselected at "0" PIO10[5] SC0_CLKGEN PIO10[4] DocID023557 Rev 10 Name C on Desc PIO general purpose Smartcard Dir B B (Default) Partition: Bank2 Alt func: SYSTEM_CONFIG106[22: 20] = 001 Open drain: SYSTEM_CONFIG116[21] = to be set by user Pull up: SYSTEM_CONFIG113[21] = to be set by user Output enable: SYSTEM_CONFIG110[21] = to be set by user, active HIGH fid en Alternate 5 ClockGen A0, A1 clock observation STiH271EL Table 120. PIO10 (continued) SSC2_SCL ti a SSC serial clock B l PIO10[5] 577/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO Config Alt func: SYSTEM_CONFIG106[22:2 0] = 100 Open drain: SYSTEM_CONFIG116[21] = to be set by user Pull up: SYSTEM_CONFIG113[21] = to be set by user Output enable: SYSTEM_CONFIG110[21] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 4 Pin Alternate 3 Function Name Standard PIO PIO10[6] Smartcard0 UART 0 SSC2, NMI SC0_C8 VALIDATION_OUTPUT SSC2_MTSR ST-only validation function. Safe to keep default function if PIO not used by application SSC data bit master transmit/slave receive, full duplex Desc PIO general purpose Smartcard Dir B B C B (Default) Alt func: SYSTEM_CONFIG106[26:2 4] = 100 Open drain: SYSTEM_CONFIG116[22] = to be set by user Pull up: SYSTEM_CONFIG113[22] = to be set by user Output enable: SYSTEM_CONFIG110[22] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed on PIO10[6] DocID023557 Rev 10 O Config Partition: Bank2 Alt func: SYSTEM_CONFIG106[26: 24] = 001 Open drain: SYSTEM_CONFIG116[22] = to be set by user Pull up: SYSTEM_CONFIG113[22] = to be set by user Output enable: SYSTEM_CONFIG110[22] = to be set by user, active HIGH fid en Alternate 5 ClockGen A0, A1 clock observation Alternate functions on PIO 578/604 Table 120. PIO10 (continued) ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 4 Pin Alternate 3 Function Name Standard PIO PIO10[7] Smartcard0 UART 0 SSC2, NMI SC0_DETECT VALIDATION_OUTPUT SSC2_MRST ST-only validation function. Safe to keep default function if PIO not used by application SSC data bit master receive/slave transmit, full duplex Desc PIO general purpose Smartcard Dir B I C B (Default) Alt func: SYSTEM_CONFIG106[30:2 8] = 100 Open drain: SYSTEM_CONFIG116[23] = to be set by user Pull up: SYSTEM_CONFIG113[23] = to be set by user Output enable: SYSTEM_CONFIG110[23] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed on PIO10[7] DocID023557 Rev 10 O Config Partition: Bank2 Open drain: SYSTEM_CONFIG116[23] = to be set by user Pull up: SYSTEM_CONFIG113[23] = to be set by user Output enable: SYSTEM_CONFIG110[23] = 0, active HIGH fid en Alternate 5 ClockGen A0, A1 clock observation STiH271EL Table 120. PIO10 (continued) ti a l Alternate functions on PIO 579/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO11 Table 121. PIO11 Parameter PIO Alternate 1 Pin Alternate 3 Alternate 5 Alternate 2 Function Standard PIO Alternate 4 SSC1 UART1 SmartCard1 Name PIO11[0] UART1_TXD SC1_C4 Desc PIO general purpose UART transmit signal Smartcard Dir B O B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[24,16] = pio11_cfg_delay_1,0[0] SYSTEM_CONFIG132[0] = pio11_cfg_clk1notclk0[0] SYSTEM_CONFIG133[24] = pio11_cfg_double_edge[0] SYSTEM_CONFIG133[16] = pio11_cfg_clknotdata[0] SYSTEM_CONFIG133[8] = pio11_cfg_retime[0] SYSTEM_CONFIG133[0] = pio11_cfg_invertclk[0] Alt func: SYSTEM_CONFIG107[2:0] = 011 Open drain: SYSTEM_CONFIG116[24] = to be set by user Pull up: SYSTEM_CONFIG113[24] = to be set by user Output enable: SYSTEM_CONFIG110[24] = 1, active HIGH Alt func: SYSTEM_CONFIG107[2:0] = 101 Open drain: SYSTEM_CONFIG116[24] = to be set by user Pull up: SYSTEM_CONFIG113[24] = to be set by user Output enable: SYSTEM_CONFIG110[24] = to be set by user, active HIGH PIO11[0] C on DocID023557 Rev 10 fid en ti a Name PIO11[1] UART1_RXD SC1_C7 Desc PIO general purpose UART receive signal Smartcard Dir B I Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[25,17] = pio11_cfg_delay_1,0[1] SYSTEM_CONFIG132[1] = pio11_cfg_clk1notclk0[1] SYSTEM_CONFIG133[25] = pio11_cfg_double_edge[1] SYSTEM_CONFIG133[17] = pio11_cfg_clknotdata[1] SYSTEM_CONFIG133[9] = pio11_cfg_retime[1] SYSTEM_CONFIG133[1] = pio11_cfg_invertclk[1] Open drain: SYSTEM_CONFIG116[25] = to be set by user Pull up: SYSTEM_CONFIG113[25] = to be set by user Output enable: SYSTEM_CONFIG110[25] = 0, active HIGH PIO11[1] l B Alt func: SYSTEM_CONFIG107[6:4] = 101 Open drain: SYSTEM_CONFIG116[25] = to be set by user Pull up: SYSTEM_CONFIG113[25] = to be set by user Output enable: SYSTEM_CONFIG110[25] = to be set by user, active HIGH STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO 580/604 25.2.12 Confidential Parameter PIO Alternate 1 Pin Alternate 3 Alternate 5 Alternate 2 Function Name Standard PIO Alternate 4 SSC1 UART1 SmartCard1 PIO11[2] UART1_RTS SC1_RESET Desc PIO general purpose UART ready to send signal Smartcard Dir B O O Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[26,18] = pio11_cfg_delay_1,0[2] SYSTEM_CONFIG132[2] = pio11_cfg_clk1notclk0[2] SYSTEM_CONFIG133[26] = pio11_cfg_double_edge[2] SYSTEM_CONFIG133[18] = pio11_cfg_clknotdata[2] SYSTEM_CONFIG133[10] = pio11_cfg_retime[2] SYSTEM_CONFIG133[2] = pio11_cfg_invertclk[2] Alt func: SYSTEM_CONFIG107[10:8] = 011 Open drain: SYSTEM_CONFIG116[26] = to be set by user Pull up: SYSTEM_CONFIG113[26] = to be set by user Output enable: SYSTEM_CONFIG110[26] = 1, active HIGH Alt func: SYSTEM_CONFIG107[10:8] = 101 Open drain: SYSTEM_CONFIG116[26] = to be set by user Pull up: SYSTEM_CONFIG113[26] = to be set by user Output enable: SYSTEM_CONFIG110[26] = 1, active HIGH PIO11[2] DocID023557 Rev 10 Name PIO11[3] C on fid en UART1_NOTOE SC1_NOTSETVCC PIO general purpose UART output enable Smartcard Dir B O O Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[27,19] = pio11_cfg_delay_1,0[3] SYSTEM_CONFIG132[3] = pio11_cfg_clk1notclk0[3] SYSTEM_CONFIG133[27] = pio11_cfg_double_edge[3] SYSTEM_CONFIG133[19] = pio11_cfg_clknotdata[3] SYSTEM_CONFIG133[11] = pio11_cfg_retime[3] SYSTEM_CONFIG133[3] = pio11_cfg_invertclk[3] Alt func: SYSTEM_CONFIG107[14:12] = 011 Open drain: SYSTEM_CONFIG116[27] = to be set by user Pull up: SYSTEM_CONFIG113[27] = to be set by user Output enable: SYSTEM_CONFIG110[27] = 1, active HIGH PIO11[3] ti a l 581/604 Information classified Confidential - Do not copy (See last page for obligations) Alt func: SYSTEM_CONFIG107[14:12] = 101 Open drain: SYSTEM_CONFIG116[27] = to be set by user Pull up: SYSTEM_CONFIG113[27] = to be set by user Output enable: SYSTEM_CONFIG110[27] = 1, active HIGH Alternate functions on PIO Desc STiH271EL Table 121. PIO11 (continued) Confidential Parameter PIO Alternate 1 Pin Alternate 3 Alternate 5 Alternate 2 Function Name Standard PIO Alternate 4 SSC1 UART1 SmartCard1 PIO11[4] UART1_CTS SC1_NOTSETVPP Desc PIO general purpose UART clear to send signal Smartcard Dir B I O Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[28,20] = pio11_cfg_delay_1,0[4] SYSTEM_CONFIG132[4] = pio11_cfg_clk1notclk0[4] SYSTEM_CONFIG133[28] = pio11_cfg_double_edge[4] SYSTEM_CONFIG133[20] = pio11_cfg_clknotdata[4] SYSTEM_CONFIG133[12] = pio11_cfg_retime[4] SYSTEM_CONFIG133[4] = pio11_cfg_invertclk[4] Open drain: SYSTEM_CONFIG116[28] = to be set by user Pull up: SYSTEM_CONFIG113[28] = to be set by user Output enable: SYSTEM_CONFIG110[28] = 0, active HIGH Alt func: SYSTEM_CONFIG107[18:16] = 101 Open drain: SYSTEM_CONFIG116[28] = to be set by user Pull up: SYSTEM_CONFIG113[28] = to be set by user Output enable: SYSTEM_CONFIG110[28] = 1, active HIGH PIO11[4] DocID023557 Rev 10 Name PIO11[5] Desc PIO general purpose Dir B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[29,21] = pio11_cfg_delay_1,0[5] SYSTEM_CONFIG132[5] = pio11_cfg_clk1notclk0[5] SYSTEM_CONFIG133[29] = pio11_cfg_double_edge[5] SYSTEM_CONFIG133[21] = pio11_cfg_clknotdata[5] SYSTEM_CONFIG133[13] = pio11_cfg_retime[5] SYSTEM_CONFIG133[5] = pio11_cfg_invertclk[5] PIO11[5] C on fid en Alternate functions on PIO 582/604 Table 121. PIO11 (continued) SC1_CLKGEN Smartcard ti a B l Alt func: SYSTEM_CONFIG107[22:20] = 101 Open drain: SYSTEM_CONFIG116[29] = to be set by user Pull up: SYSTEM_CONFIG113[29] = to be set by user Output enable: SYSTEM_CONFIG110[29] = to be set by user, active HIGH STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 3 Pin Alternate 5 Alternate 2 Function Name Standard PIO SSC1 Alternate 4 UART1 SmartCard1 PIO11[6] SC1_C8 Desc PIO general purpose Smartcard Dir B B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[30,22] = pio11_cfg_delay_1,0[6] SYSTEM_CONFIG132[6] = pio11_cfg_clk1notclk0[6] SYSTEM_CONFIG133[30] = pio11_cfg_double_edge[6] SYSTEM_CONFIG133[22] = pio11_cfg_clknotdata[6] SYSTEM_CONFIG133[14] = pio11_cfg_retime[6] SYSTEM_CONFIG133[6] = pio11_cfg_invertclk[6] PIO11[6] C DocID023557 Rev 10 fid SSC1_MRST Desc PIO general purpose SSC data bit master receive/slave transmit, full duplex Dir B B Config (Default) Partition: Bank2 Retime logic control: SYSTEM_CONFIG132[31,23] = pio11_cfg_delay_1,0[7] SYSTEM_CONFIG132[7] = pio11_cfg_clk1notclk0[7] SYSTEM_CONFIG133[31] = pio11_cfg_double_edge[7] SYSTEM_CONFIG133[23] = pio11_cfg_clknotdata[7] SYSTEM_CONFIG133[15] = pio11_cfg_retime[7] SYSTEM_CONFIG133[7] = pio11_cfg_invertclk[7] Alt func: SYSTEM_CONFIG107[30:28] = 001 Open drain: SYSTEM_CONFIG116[31] = to be set by user Pull up: SYSTEM_CONFIG113[31] = to be set by user Output enable: SYSTEM_CONFIG110[31] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed en SC1_DETECT ti a Smartcard I l 583/604 Information classified Confidential - Do not copy (See last page for obligations) Open drain: SYSTEM_CONFIG116[31] = to be set by user Pull up: SYSTEM_CONFIG113[31] = to be set by user Output enable: SYSTEM_CONFIG110[31] = 0, active HIGH Alternate functions on PIO PIO11[7] PIO11[7] Alt func: SYSTEM_CONFIG107[26:24] = 101 Open drain: SYSTEM_CONFIG116[30] = to be set by user Pull up: SYSTEM_CONFIG113[30] = to be set by user Output enable: SYSTEM_CONFIG110[30] = to be set by user, active HIGH on Name STiH271EL Table 121. PIO11 (continued) Confidential PIO12 Table 122. PIO12 Parameter PIO Alternate 1 Alternate 3 Pin Alternate 2 Function Standard PIO SSC1, Serial Flash controller ClockGen A0, A1 clock observation Name PIO12[0] SSC1_SCL CKGENA0_CLK0 Desc PIO general purpose SSC serial clock ClockGen A0 right clock output Dir B B O Alt func: SYSTEM_CONFIG108[2:0] = 001 Open drain: SYSTEM_CONFIG117[0] = to be set by user Pull up: SYSTEM_CONFIG114[0] = to be set by user Output enable: SYSTEM_CONFIG111[0] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Alt func: SYSTEM_CONFIG108[2:0] = 011 Open drain: SYSTEM_CONFIG117[0] = to be set by user Pull up: SYSTEM_CONFIG114[0] = to be set by user Output enable: SYSTEM_CONFIG111[0] = 1, active HIGH CKGENA1_CLK0 C PIO12[0] Config (Default) Partition: Bank2 on DocID023557 Rev 10 fid en Name PIO12[1] SSC1_MTSR Desc PIO general purpose SSC data bit for half duplex Dir B B (Default) Partition: Bank2 Alt func: SYSTEM_CONFIG108[6:4] = 001 Open drain: SYSTEM_CONFIG117[1] = to be set by user Pull up: SYSTEM_CONFIG114[1] = to be set by user Output enable: SYSTEM_CONFIG111[1] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed PIO12[1] Config Alternate functions on PIO 584/604 25.2.13 ClockGen A1 right clock output ti a O l Alt func: SYSTEM_CONFIG108[6:4] = 011 Open drain: SYSTEM_CONFIG117[1] = to be set by user Pull up: SYSTEM_CONFIG114[1] = to be set by user Output enable: SYSTEM_CONFIG111[1] = 1, active HIGH STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 3 Pin Alternate 2 Function Name Standard PIO SSC1, Serial Flash controller PIO12[2] SPI_CLOCK Desc PIO general purpose Serial Flash controller Dir B O Config Partition: Bank2 (Default) Alt func: SYSTEM_CONFIG108[8] = 1 Open drain: SYSTEM_CONFIG117[2] = to be set by user Pull up: SYSTEM_CONFIG114[2] = to be set by user Output enable: SYSTEM_CONFIG111[2] = 1, active HIGH Name PIO12[3] SPI_NOTCS Desc PIO general purpose Serial Flash controller Dir B O Partition: Bank2 (Default) Alt func: SYSTEM_CONFIG108[14:12] = 001 Open drain: SYSTEM_CONFIG117[3] = to be set by user Pull up: SYSTEM_CONFIG114[3] = to be set by user Output enable: SYSTEM_CONFIG111[3] = 1, active HIGH C PIO12[2] DocID023557 Rev 10 PIO12[3] Config Name on fid en SPI_DI Desc PIO general purpose Serial Flash controller Dir B B Partition: Bank2 (Default) Alt func: SYSTEM_CONFIG108[18:16] = 001 Open drain: SYSTEM_CONFIG117[4] = to be set by user Pull up: SYSTEM_CONFIG114[4] = to be set by user Output enable: emii0 (spi_data_out_enb) = to be set by user, active HIGH Config ti a l 585/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO PIO12[4] PIO12[4] ClockGen A0, A1 clock observation STiH271EL Table 122. PIO12 (continued) Confidential Parameter PIO Alternate 1 Alternate 3 Pin Alternate 2 Function Name Standard PIO SSC1, Serial Flash controller PIO12[5] SPI_DO Desc PIO general purpose Serial Flash controller Dir B B Config Partition: Bank2 (Default) Alt func: SYSTEM_CONFIG108[22:20] = 001 Open drain: SYSTEM_CONFIG117[5] = to be set by user Pull up: SYSTEM_CONFIG114[5] = to be set by user Output enable: emii0 (spi_data_in_enb) = to be set by user, active HIGH Name PIO12[6] SPI_HOLD Desc PIO general purpose Serial Flash controller Dir B B Partition: Bank2 (Default) Alt func: SYSTEM_CONFIG108[26:24] = 001 Open drain: SYSTEM_CONFIG117[6] = to be set by user Pull up: SYSTEM_CONFIG114[6] = to be set by user Output enable: emii0 (spi_hold_out_enb) = to be set by user, active HIGH C PIO12[5] DocID023557 Rev 10 PIO12[6] Config Name on fid en SPI_WRPROTECT Desc PIO general purpose Serial Flash controller Dir B B Partition: Bank2 (Default) Alt func: SYSTEM_CONFIG108[30:28] = 001 Open drain: SYSTEM_CONFIG117[7] = to be set by user Pull up: SYSTEM_CONFIG114[7] = to be set by user Output enable: emii0 (spi_wrprotectenb) = to be set by user, active HIGH Config ti a l Information classified Confidential - Do not copy (See last page for obligations) STiH271EL PIO12[7] PIO12[7] ClockGen A0, A1 clock observation Alternate functions on PIO 586/604 Table 122. PIO12 (continued) Confidential PIO13 Table 123. PIO13 Parameter PIO Alternate 1 Pin Alternate 4 Alternate 2 Function Standard PIO MMC Name PIO13[0] MMC_DATA[0] Desc PIO general purpose MMC data Dir B PIO13[0] C SSC3 B (Default) Alt func: SYSTEM_CONFIG200[2:0] = 001 Open drain: SYSTEM_CONFIG205[0] = to be set by user Pull up: SYSTEM_CONFIG204[0] = to be set by user Output enable: MMC (card_data_en[0]) = to be set by user, active HIGH on DocID023557 Rev 10 Config Partition: Bank 3 Name PIO13[1] MMC_DATA[1] Desc PIO general purpose MMC data Dir B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG200[6:4] = 001 Open drain: SYSTEM_CONFIG205[1] = to be set by user Pull up: SYSTEM_CONFIG204[1] = to be set by user Output enable: MMC (card_data_en[1]) = to be set by user, active HIGH PIO13[1] Config fid en PIO13[2] MMC_DATA[2] Desc PIO general purpose MMC data Dir B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG200[10:8] = 001 Open drain: SYSTEM_CONFIG205[2] = to be set by user Pull up: SYSTEM_CONFIG204[2] = to be set by user Output enable: MMC (card_data_en[2]) = to be set by user, active HIGH Config ti a l 587/604 Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO Name PIO13[2] Alternate 3 STiH271EL 25.2.14 Confidential Parameter PIO Alternate 1 Pin Alternate 4 Alternate 2 Function Name Standard PIO MMC PIO13[3] SSC3 MMC_DATA[3] Desc PIO general purpose MMC data Dir B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG200[14:12] = 001 Open drain: SYSTEM_CONFIG205[3] = to be set by user Pull up: SYSTEM_CONFIG204[3] = to be set by user Output enable: MMC (card_data_en[3]) = to be set by user, active HIGH PIO13[3] C Config Alternate 3 Alternate functions on PIO 588/604 Table 123. PIO13 (continued) on Name PIO13[4] DocID023557 Rev 10 fid MMC_DATA[4] SSC3_SCL SSC serial clock Desc PIO general purpose MMC data Dir B B Config Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG200[18:16] = 001 Open drain: SYSTEM_CONFIG205[4] = to be set by user Pull up: SYSTEM_CONFIG204[4] = to be set by user Output enable: MMC (card_data_en[4]) = to be set by user, active HIGH Name PIO13[5] MMC_DATA[5] Desc PIO general purpose MMC data SSC data bit master transmit/slave receive, full duplex Dir B B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG200[22:20] = 001 Open drain: SYSTEM_CONFIG205[5] = to be set by user Pull up: SYSTEM_CONFIG204[5] = to be set by user Output enable: MMC (card_data_en[5]) = to be set by user, active HIGH Alt func: SYSTEM_CONFIG200[22:20] = 100 Open drain: SYSTEM_CONFIG205[5] = to be set by user Pull up: SYSTEM_CONFIG204[5] = to be set by user Output enable: SYSTEM_CONFIG203[5] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed B en PIO13[4] PIO13[5] Config ti a l SSC3_MTSR STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Alt func: SYSTEM_CONFIG200[18:16] = 100 Open drain: SYSTEM_CONFIG205[4] = to be set by user Pull up: SYSTEM_CONFIG204[4] = to be set by user Output enable: SYSTEM_CONFIG203[4] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Confidential Parameter PIO Alternate 1 Pin Alternate 4 Alternate 2 Function Standard PIO Alternate 3 MMC SSC3 Name PIO13[6] MMC_DATA[6] SSC3_MRST Desc PIO general purpose MMC data SSC data bit master receive/slave transmit, full duplex Dir B B B (Default) Alt func: SYSTEM_CONFIG200[26:24] = 001 Open drain: SYSTEM_CONFIG205[6] = to be set by user Pull up: SYSTEM_CONFIG204[6] = to be set by user Output enable: MMC (card_data_en[6]) = to be set by user, active HIGH Alt func: SYSTEM_CONFIG200[26:24] = 100 Open drain: SYSTEM_CONFIG205[6] = to be set by user Pull up: SYSTEM_CONFIG204[6] = to be set by user Output enable: SYSTEM_CONFIG203[6] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed C PIO13[6] DocID023557 Rev 10 Config Partition: Bank 3 Name PIO13[7] on fid MMC_DATA[7] Desc PIO general purpose MMC data Dir B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG200[30:28] = 001 Open drain: SYSTEM_CONFIG205[7] = to be set by user Pull up: SYSTEM_CONFIG204[7] = to be set by user Output enable: MMC (card_data_en[7]) = to be set by user, active HIGH PIO13[7] Config STiH271EL Table 123. PIO13 (continued) en ti a l Alternate functions on PIO 589/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential PIO14 Table 124. PIO14 Parameter PIO Alternate 1 Alternate 2 Function Standard PIO MMC UART2 Pin Name PIO14[0] MMC_LED Desc PIO general purpose MMC LED on Dir B C PIO14[0] O (Default) Alt func: SYSTEM_CONFIG201[2:0] = 001 Open drain: SYSTEM_CONFIG205[8] = to be set by user Pull up: SYSTEM_CONFIG204[8] = to be set by user Output enable: SYSTEM_CONFIG203[8] = 1, active HIGH on DocID023557 Rev 10 Config Partition: Bank 3 Name PIO14[1] MMC_CLK Desc PIO general purpose MMC clock Dir B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG201[6:4] = 001 Open drain: SYSTEM_CONFIG205[9] = to be set by user Pull up: SYSTEM_CONFIG204[9] = to be set by user Output enable: SYSTEM_CONFIG203[9] = to be set by user, active HIGH fid en PIO14[1] Config ti a Name PIO14[2] MMC_CMD Desc PIO general purpose MMC command Dir B B Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG201[10:8] = 001 Open drain: SYSTEM_CONFIG205[10] = to be set by user Pull up: SYSTEM_CONFIG204[10] = to be set by user Output enable: MMC (card_cmd_en) = to be set by user, active HIGH Cleaned input: When unselected at 0 PIO14[2] Config Alternate functions on PIO 590/604 25.2.15 l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO MMC UART2 Pin Name PIO14[3] STiH271EL Table 124. PIO14 (continued) MMC_WP Desc PIO general purpose MMC write protection Dir B I Config Partition: Bank 3 (Default) Open drain: SYSTEM_CONFIG205[11] = to be set by user Pull up: SYSTEM_CONFIG204[11] = to be set by user Output enable: SYSTEM_CONFIG203[11] = 0, active HIGH Name PIO14[4] Desc PIO general purpose Dir B PIO14[3] C on VALIDATION_OUTPUT UART2_NOTOE ST-only validation function. UART output enable Safe to keep default function if PIO not used by application DocID023557 Rev 10 fid O O Alt func: SYSTEM_CONFIG201[18:16] = 010 Open drain: SYSTEM_CONFIG205[12] = to be set by user Pull up: SYSTEM_CONFIG204[12] = to be set by user Output enable: SYSTEM_CONFIG203[12] = 1, active HIGH PIO14[4] en Config Partition: Bank 3 (Default) Name PIO14[5] MMC_CP Desc PIO general purpose MMC card power Dir B O Config Partition: Bank 3 (Default) Alt func: SYSTEM_CONFIG201[22:20] = 001 Open drain: SYSTEM_CONFIG205[13] = to be set by user Pull up: SYSTEM_CONFIG204[13] = to be set by user Output enable: SYSTEM_CONFIG203[13] = 1, active HIGH Name PIO14[6] MMC_CD Desc PIO general purpose MMC card detect Dir B I Partition: Bank 3 (Default) Open drain: SYSTEM_CONFIG205[14] = to be set by user Pull up: SYSTEM_CONFIG204[14] = to be set by user Output enable: SYSTEM_CONFIG203[14] = 0, active HIGH PIO14[5] ti a l 591/604 Config Information classified Confidential - Do not copy (See last page for obligations) Alternate functions on PIO PIO14[6] Confidential Parameter PIO Alternate 1 Alternate 2 Function Standard PIO MMC UART2 Pin Name PIO14[7] Desc PIO general purpose Dir B Config (Default) Partition: Bank 3 PIO14[7] 25.2.16 C PIO15 on Table 125. PIO15 Parameter PIO Alternate 1 DocID023557 Rev 10 Pin Function Standard PIO SSC3, UART2 fid Alternate 2 SSC3 Alternate 3 Alternate 4 AUDPCMIN0, external interrupt 5 AUDPCMOUT0 en Name PIO15[0] SSC3_SCL AUDPCMOUT0_DATA[0] AUDPCMIN0_DATA[0] Desc PIO general purpose SSC serial clock PCMOUT data Dir B B O Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[24 ,16] = pio15_cfg_delay_1,0[0] SYSTEM_CONFIG210[0] = pio15_cfg_clk1notclk0[0] SYSTEM_CONFIG211[24 ]= pio15_cfg_double_edge[0] SYSTEM_CONFIG211[16 ]= pio15_cfg_clknotdata[0] SYSTEM_CONFIG211[8] = pio15_cfg_retime[0] SYSTEM_CONFIG211[0] = pio15_cfg_invertclk[0] Alt func: SYSTEM_CONFIG202[2 :0] = 001 Open drain: SYSTEM_CONFIG205[1 6] = to be set by user Pull up: SYSTEM_CONFIG204[1 6] = to be set by user Output enable: SYSTEM_CONFIG203[1 6] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Alt func: SYSTEM_CONFIG202[2 :0] = 011 Open drain: SYSTEM_CONFIG205[1 6] = to be set by user Pull up: SYSTEM_CONFIG204[1 6] = to be set by user Output enable: SYSTEM_CONFIG203[1 6] = 1, active HIGH PIO15[0] Alternate functions on PIO 592/604 Table 124. PIO14 (continued) Alternate 6 Alternate 5 AUDPCMIN0 PCMIN data ti a I l Open drain: SYSTEM_CONFIG205[1 6] = to be set by user Pull up: SYSTEM_CONFIG204[1 6] = to be set by user Output enable: SYSTEM_CONFIG203[1 6] = 0, active HIGH Data input: Demultiplexed by alt func STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Pin Function Standard PIO SSC3, UART2 SSC3 AUDPCMOUT0 AUDPCMIN0, external interrupt 5 Name PIO15[1] SSC3_MTSR AUDPCMOUT0_MCLK AUDPCMIN0_MCLK Desc PIO general purpose SSC data bit for half duplex PCMOUT clock PCMIN clock Dir B B B B Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[25 ,17] = pio15_cfg_delay_1,0[1] SYSTEM_CONFIG210[1] = pio15_cfg_clk1notclk0[1] SYSTEM_CONFIG211[25 ]= pio15_cfg_double_edge[1] SYSTEM_CONFIG211[17 ]= pio15_cfg_clknotdata[1] SYSTEM_CONFIG211[9] = pio15_cfg_retime[1] SYSTEM_CONFIG211[1] = pio15_cfg_invertclk[1] Alt func: SYSTEM_CONFIG202[6 :4] = 001 Open drain: SYSTEM_CONFIG205[1 7] = to be set by user Pull up: SYSTEM_CONFIG204[1 7] = to be set by user Output enable: SYSTEM_CONFIG203[1 7] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Alt func: SYSTEM_CONFIG202[6 :4] = 011 Open drain: SYSTEM_CONFIG205[1 7] = to be set by user Pull up: SYSTEM_CONFIG204[1 7] = to be set by user Output enable: SYSTEM_CONFIG203[1 7] = to be set by user, active HIGH Alt func: SYSTEM_CONFIG202[6 :4] = 100 Open drain: SYSTEM_CONFIG205[1 7] = to be set by user Pull up: SYSTEM_CONFIG204[1 7] = to be set by user Output enable: SYSTEM_CONFIG203[1 7] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed PIO15[1] C on DocID023557 Rev 10 fid en Alternate 6 Alternate 5 AUDPCMIN0 STiH271EL Table 125. PIO15 (continued) ti a l Alternate functions on PIO 593/604 Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Pin Function Standard PIO SSC3, UART2 SSC3 AUDPCMIN0, external interrupt 5 AUDPCMOUT0 Name PIO15[2] SSC3_MRST AUDPCMOUT0_SCLK AUDPCMIN0_SCLK Desc PIO general purpose SSC data bit master receive/slave transmit, full duplex PCMOUT serial clock PCMIN serial clock Dir B B O I Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[26 ,18] = pio15_cfg_delay_1,0[2] SYSTEM_CONFIG210[2] = pio15_cfg_clk1notclk0[2] SYSTEM_CONFIG211[26 ]= pio15_cfg_double_edge[2] SYSTEM_CONFIG211[18 ]= pio15_cfg_clknotdata[2] SYSTEM_CONFIG211[10 ] = pio15_cfg_retime[2] SYSTEM_CONFIG211[2] = pio15_cfg_invertclk[2] Alt func: SYSTEM_CONFIG202[1 0:8] = 001 Open drain: SYSTEM_CONFIG205[1 8] = to be set by user Pull up: SYSTEM_CONFIG204[1 8] = to be set by user Output enable: SYSTEM_CONFIG203[1 8] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Alt func: SYSTEM_CONFIG202[1 0:8] = 011 Open drain: SYSTEM_CONFIG205[1 8] = to be set by user Pull up: SYSTEM_CONFIG204[1 8] = to be set by user Output enable: SYSTEM_CONFIG203[1 8] = 1, active HIGH Open drain: SYSTEM_CONFIG205[1 8] = to be set by user Pull up: SYSTEM_CONFIG204[1 8] = to be set by user Output enable: SYSTEM_CONFIG203[1 8] = 0, active HIGH Data input: Demultiplexed by alt func PIO15[2] C on DocID023557 Rev 10 fid en Alternate 6 Alternate 5 AUDPCMIN0 Alternate functions on PIO 594/604 Table 125. PIO15 (continued) ti a l STiH271EL Information classified Confidential - Do not copy (See last page for obligations) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Pin Function Standard PIO SSC3, UART2 SSC3 AUDPCMIN0, external interrupt 5 AUDPCMOUT0 PIO15[3] AUDPCMOUT0_LRCLK AUDPCMIN0_LRCLK Desc PIO general purpose PCMOUT left right clock PCMIN left right clock Dir B O I Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[27 ,19] = pio15_cfg_delay_1,0[3] SYSTEM_CONFIG210[3] = pio15_cfg_clk1notclk0[3] SYSTEM_CONFIG211[27 ]= pio15_cfg_double_edge[3] SYSTEM_CONFIG211[19 ]= pio15_cfg_clknotdata[3] SYSTEM_CONFIG211[11] = pio15_cfg_retime[3] SYSTEM_CONFIG211[3] = pio15_cfg_invertclk[3] Alt func: SYSTEM_CONFIG202[1 4:12] = 011 Open drain: SYSTEM_CONFIG205[1 9] = to be set by user Pull up: SYSTEM_CONFIG204[1 9] = to be set by user Output enable: SYSTEM_CONFIG203[1 9] = 1, active HIGH Open drain: SYSTEM_CONFIG205[1 9] = to be set by user Pull up: SYSTEM_CONFIG204[1 9] = to be set by user Output enable: SYSTEM_CONFIG203[1 9] = 0, active HIGH Data input: Demultiplexed by alt func Name PIO15[3] DocID023557 Rev 10 Name AUDPCMIN0 C on fid en UART2_TXD Desc PIO general purpose UART transmit signal Dir B O Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[28 ,20] = pio15_cfg_delay_1,0[4] SYSTEM_CONFIG210[4] = pio15_cfg_clk1notclk0[4] SYSTEM_CONFIG211[28 ]= pio15_cfg_double_edge[4] SYSTEM_CONFIG211[20 ]= pio15_cfg_clknotdata[4] SYSTEM_CONFIG211[12 ] = pio15_cfg_retime[4] SYSTEM_CONFIG211[4] = pio15_cfg_invertclk[4] Alt func: SYSTEM_CONFIG202[1 8:16] = 001 Open drain: SYSTEM_CONFIG205[2 0] = to be set by user Pull up: SYSTEM_CONFIG204[2 0] = to be set by user Output enable: SYSTEM_CONFIG203[2 0] = 1, active HIGH ti a AUDPCMIN0_DATA[0] PCMIN data l 595/604 Information classified Confidential - Do not copy (See last page for obligations) I Open drain: SYSTEM_CONFIG205[20] = to be set by user Pull up: SYSTEM_CONFIG204[20] = to be set by user Output enable: SYSTEM_CONFIG203[20] = 0, active HIGH Data input: Demultiplexed by alt func Alternate functions on PIO PIO15[4] PIO15[4] Alternate 6 Alternate 5 STiH271EL Table 125. PIO15 (continued) Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Pin Function Standard PIO SSC3, UART2 SSC3 AUDPCMOUT0 AUDPCMIN0, external interrupt 5 Alternate 6 Alternate 5 AUDPCMIN0 PIO15[5] UART2_RXD SSC3_SCL AUDPCMIN0_MCLK Desc PIO general purpose UART receive signal SSC serial clock PCMIN clock Dir B I B B Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[29 ,21] = pio15_cfg_delay_1,0[5] SYSTEM_CONFIG210[5] = pio15_cfg_clk1notclk0[5] SYSTEM_CONFIG211[29 ]= pio15_cfg_double_edge[5] SYSTEM_CONFIG211[21 ]= pio15_cfg_clknotdata[5] SYSTEM_CONFIG211[13 ] = pio15_cfg_retime[5] SYSTEM_CONFIG211[5] = pio15_cfg_invertclk[5] Open drain: SYSTEM_CONFIG205[2 1] = to be set by user Pull up: SYSTEM_CONFIG204[2 1] = to be set by user Output enable: SYSTEM_CONFIG203[2 1] = 0, active HIGH Alt func: SYSTEM_CONFIG202[2 2:20] = 010 Open drain: SYSTEM_CONFIG205[2 1] = to be set by user Pull up: SYSTEM_CONFIG204[2 1] = to be set by user Output enable: SYSTEM_CONFIG203[2 1] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Alt func: SYSTEM_CONFIG202[22: 20] = 110 Open drain: SYSTEM_CONFIG205[21] = to be set by user Pull up: SYSTEM_CONFIG204[21] = to be set by user Output enable: SYSTEM_CONFIG203[21] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Name PIO15[6] UART2_CTS SSC3_MTSR Desc PIO general purpose UART clear to send signal SSC data bit for half duplex Dir B I B Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[30 ,22] = pio15_cfg_delay_1,0[6] SYSTEM_CONFIG210[6] = pio15_cfg_clk1notclk0[6] SYSTEM_CONFIG211[30 ]= pio15_cfg_double_edge[6] SYSTEM_CONFIG211[22 ]= pio15_cfg_clknotdata[6] SYSTEM_CONFIG211[14 ] = pio15_cfg_retime[6] SYSTEM_CONFIG211[6] = pio15_cfg_invertclk[6] Open drain: SYSTEM_CONFIG205[2 2] = to be set by user Pull up: SYSTEM_CONFIG204[2 2] = to be set by user Output enable: SYSTEM_CONFIG203[2 2] = 0, active HIGH Alt func: SYSTEM_CONFIG202[2 6:24] = 010 Open drain: SYSTEM_CONFIG205[2 2] = to be set by user Pull up: SYSTEM_CONFIG204[2 2] = to be set by user Output enable: SYSTEM_CONFIG203[2 2] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Name PIO15[5] DocID023557 Rev 10 PIO15[6] C on fid en ti a Alternate functions on PIO 596/604 Table 125. PIO15 (continued) AUDPCMIN0_SCLK l I Open drain: SYSTEM_CONFIG205[22] = to be set by user Pull up: SYSTEM_CONFIG204[22] = to be set by user Output enable: SYSTEM_CONFIG203[22] = 0, active HIGH Data input: Demultiplexed by alt func STiH271EL Information classified Confidential - Do not copy (See last page for obligations) PCMIN serial clock Confidential Parameter PIO Alternate 1 Alternate 2 Alternate 3 Alternate 4 Pin Function Standard PIO SSC3, UART2 SSC3 AUDPCMIN0, external interrupt 5 AUDPCMOUT0 Alternate 6 Alternate 5 AUDPCMIN0 Name PIO15[7] UART2_RTS SSC3_MRST EXT_IT[5] AUDPCMIN0_LRCLK Desc PIO general purpose UART ready to send signal SSC data bit master receive/slave transmit, full duplex External interrupt PCMIN left right clock Dir B O B I I Config (Default) Partition: Bank 3 Retime logic control: SYSTEM_CONFIG210[31 ,23] = pio15_cfg_delay_1,0[7] SYSTEM_CONFIG210[7] = pio15_cfg_clk1notclk0[7] SYSTEM_CONFIG211[31 ]= pio15_cfg_double_edge[7] SYSTEM_CONFIG211[23 ]= pio15_cfg_clknotdata[7] SYSTEM_CONFIG211[15 ] = pio15_cfg_retime[7] SYSTEM_CONFIG211[7] = pio15_cfg_invertclk[7] Alt func: SYSTEM_CONFIG202[3 0:28] = 010 Open drain: SYSTEM_CONFIG205[2 3] = to be set by user Pull up: SYSTEM_CONFIG204[2 3] = to be set by user Output enable: SYSTEM_CONFIG203[2 3] = to be set by user, active HIGH Data input: Demultiplexed by alt func Data output: Multiplexed Alt func: SYSTEM_CONFIG202[3 0:28] = 100 Open drain: SYSTEM_CONFIG205[2 3] = to be set by user Pull up: SYSTEM_CONFIG204[2 3] = to be set by user Output enable: SYSTEM_CONFIG203[2 3] = 0, active HIGH Cleaned input: When unselected at 0 Open drain: SYSTEM_CONFIG205[23] = to be set by user Pull up: SYSTEM_CONFIG204[23] = to be set by user Output enable: SYSTEM_CONFIG203[23] = 0, active HIGH Data input: Demultiplexed by alt func PIO15[7] C on DocID023557 Rev 10 Alt func: SYSTEM_CONFIG202[3 0:28] = 001 Open drain: SYSTEM_CONFIG205[2 3] = to be set by user Pull up: SYSTEM_CONFIG204[2 3] = to be set by user Output enable: SYSTEM_CONFIG203[2 3] = 1, active HIGH fid en STiH271EL Table 125. PIO15 (continued) ti a l Alternate functions on PIO 597/604 Information classified Confidential - Do not copy (See last page for obligations) Licenses 26 STiH271EL Licenses Supply of this product does not convey a license under the relevant intellectual property of the companies mentioned in this chapter nor imply any right to use this intellectual property in any finished end-user or ready to use final product. An independent license for such use is required and can be obtained by contacting the company or companies concerned. Once the license is obtained, a copy must be sent to STMicroelectronics. l The features requiring licenses include: ti a CSS en CSS DVD Copy Protection is intellectual property of Matsushita Electronics Industrial Co. The CSS DVD Copy Protection license allows the use of the CSS decryption cell embedded in the STiH271EL. Confidential For all details, contact Matsushita at: Matsushita Electronics Industrial Co. LTD, CSS Interim License Organization, 1006 Kadoma, Kadoma-Shi, Osaka 571-8503 JAPAN fid Dolby(R) Digital EX, Pro Logic(R) II, MLP LosslessTM on Dolby Digital, Pro Logic and MLP Lossless are intellectual properties of Dolby Labs. The Dolby Digital, Pro Logic or MLP Lossless license allows the use of the corresponding decoder embedded in the STiH271EL. Two types of license exist: S license must be obtained for samples (up to 25 units). P license must be obtained for production. C For all details, contact Dolby Labs at: Dolby Labs, 100 Potrero Avenue, San Francisco, CA 94103, USA Dwight Cavendish The STiH271EL is enabled with the Dwight Cavendish copy protection process. Activation of the Dwight Cavendish copy protection is subject to Dwight Cavendish Intellectual Property Rights and is not permitted otherwise than with an express written license from Dwight Cavendish. TruSurround XTTM, CircleSurroundTM II The CircleSurround II, TruSurround XT and SRS technology rights incorporated in this chip are owned by SRS Labs, a U.S. corporation and licensed to ST Microelectronics. Purchasers of this chip, who use the SRS technology incorporated herein, must sign a license for use of the chip and display of the SRS trademarks. Any product using the SRS technology incorporated in this chip must be sent to SRS Labs for review. Circle Surround II, TruSurround XT and SRS are protected under U.S. and foreign patents issued and/or pending. Neither the purchase of this chip, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS 598/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) The details of all the features requiring licenses are not provided within the datasheet and register manual. They are provided only after a copy of the license has been received by STMicroelectronics. STiH271EL Licenses technology. SRS requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual. For all details, contact SRS Labs at: SRS Labs Inc., 2909 Daimler Street, Santa Ana, CA 92705 USA DTS(R) (ES, 96/24, Neo) DTS ES, DTS 96/24 and DTS Neo are intellectual properties of Digital Theater Systems Inc. The DTS licenses allow the use of the corresponding decoder executed in the STiH271EL. For all details, contact Digital Theater Systems Inc at: DTS, 5171 Clareton Drive, Agoura Hills, CA 91301, USA ti a l CPRM/CPPM technology is intellectual property of 4C Entity. The CPRM/CPPM license allows the use of the CPRM/CPPM technology embedded in the STiH271EL. For all details, contact 4C Entity at: 4C Entity, LLC, 225 B Cochrane Circle, Morgan Hill, CA 95037, USA en fid Windows Media is intellectual property of Microsoft Corporation. The Windows Media license allows the use of the Windows Media audio and video decoders executed in the STiH271EL. For all details, contact Microsoft at: Microsoft Corporation, One Microsoft Way, Redmond, WA 98052-6399, USA on USB (Universal Serial Bus) USB is intellectual property of USB-IF. The USB license gives the right to display the certified USB logo with a product when the product has passed USB-IF compliance testing for product quality. For all details, contact USB-IF: USB Implementers Forum, Inc., 5440 SW Westgate Drive, Suite 217, Portland, OR 97221, USA C Confidential Windows Media(R) (audio [WMA] and video [WMV]) HDMITM (High-definition multimedia interfaceTM) HDMI and High-definition multimedia interface are intellectual properties of HDMI Licensing, LLC. The HDMI license allows the use of HDMI in the STiH271EL. For all details, contact HDMI Licensing, LLC at: 1060 E. Arques Avenue, Suite 100, Sunnyvale, CA 94085, USA HDCP HDCP is an intellectual property of Digital Content Protection, LLC. The HDCP license allows the use of HDCP in the STiH271EL. For all details, contact Digital Content Protection, LLC at: C/O Intel Corporation, Stephen Balogh, JF2-55, 2111 NE 25th Ave, Hillsboro, OR 97124 DocID023557 Rev 10 599/604 Information classified Confidential - Do not copy (See last page for obligations) CPRM/CPPM Licenses STiH271EL AACS AACS is an intellectual property of AACS LA, LLC. The AACS license allows the use of AACS in the STiH271EL. For all details, contact AACS LA, LLC at: c/o AACS Administration, 5440 SW Westgate Drive, Suite 217, Portland, Oregon 97221 AAC 600/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) C on fid Confidential en ti a l AAC is an intellectual property of Fraunhofer Institut Integrierte Schaltungen. For all details, contact Fraunhofer Institute IIS, Am Wolfsmantel 33, 91058 Erlangen, Germany. STiH271EL 27 Ordering information Ordering information Table 126. Ordering information Description STIH271ELKB FPBGA 27 mm X 27 mm X 2.19 mm Development version, all options Information classified Confidential - Do not copy (See last page for obligations) Packaging C on fid Confidential en ti a l Order code DocID023557 Rev 10 601/604 Revision history 28 STiH271EL Revision history Table 127. Document revision history Revision 14-Aug-2012 1 Initial revision. 08-Oct-2012 2 - Updated Table 66 and Table 67 for clock CLK_TP. - Updated Table 83 and Table 84. - Updated the HDMI version to 1.4b. Updated the description of balls N32 and BG19. Added the Start and End offsets for the BART region in Table 56. Updated the clock frequency of the ST40 CPU to 650 MHz. Updated Table 66. Added AVS description in Section 21.2. Added AVS values in Table 84. Updated footnotes 3 and 4 of Table 84. Updated the RthJA value in Table 84. Updated Config parameter of Alternate 1 function for PIO0[6], PIO1[1], PIO2[2] and PIO2[3] in Table 110, Table 111 and Table 112, respectively. - Updated the description of PIO3[0] in Table 5, Table 27, Table 113 and SYSTEM_CONFIG3. - Updated Section 3.11 and Section 4.7. ti a en fid 3 l - - - - - - - - - Updated Section 3.11, Section 4.3, Section 4.7, and Section 4.9.6. Updated the description of LMI_VDD1V5_1V8_DECAP. Updated Section 20.1.1 Updated the config parameter of Alternate 1 function for PIO8[3]. Updated Table 83 for ESD values. 4 20-Dec-2012 5 - Updated cfg_clknotdata parameter of PIOs: PIO2[3], PIO6[0] and PIO6[7]. 08-Mar-2013 6 14-Mar-2013 7 602/604 on 18-Dec-2012 - - - - - C Confidential 03-Dec-2012 Changes Updated Figure 49: JTAG recommended connections. Updated descriptions of AD31 and AD32 in Table 17: Ethernet PHY. Updated SYSTEM_CONFIG441. Updated PIO3[7] (SOC_REG_CTRL) direction and config detail in Chapter 25: Alternate functions on PIO. - Updated the LMI and DECAP power ball/pin names throughout. - - - - - Updated Chapter 19: System configuration registers for MMC. - Updated Section 4.7: High-definition video decoder. DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) Date STiH271EL Revision history Table 127. Document revision history (continued) Changes 11-Nov-2013 - - 8 - - - - Updated "decoding of H.264" and "3DTV" bullets on cover page. - Updated link-list bullet in Section 2.1.5: Display and output. - Replaced 3DTV display by 3DTV signaling in HDMI point in Section 2.1.5: Display and output. - Removed AVS HD from Section 2.1.3: Video decoding and post processing. - Updated Section 2.1.6: 3DTV signaling capability. - Updated Section 2.1.4: High-quality video reformatting. - Updated Section 4.7: High-definition video decoder. - Updated last two bullets in Section 4.8.1: High quality video display processor (HQVDP) lite. - Added last sentence in Section 4.9.5: Auxiliary display output stage. - Updated Section 4.9.6: 3DTV on HDMI 1.4b. - Updated first bullet of Section 4.13.1: USB. - Updated C11 in Figure 11: Ball map. - Updated ball C11 in Table 5: Ball list - sorted on ball number. - Added ball C11 (LMI_VREFDQ[1]) in Table 15: LMI. - Updated Table 66: Clock generator A0 clock mapping and nominal frequencies (MHz) for CLK_THNS. - Updated Section 20.3: On-chip voltage sensing feedback. - Updated introduction of Section 20.9: Ethernet PHY. - Updated Section 22.5: LMI DDR3-SDRAM timings. - Added debug signals in Chapter 25: Alternate functions on PIO. 9 C 25-Aug-2014 on fid Confidential en - Updated the order code in Table 126: Ordering information. Updated Section 20.1.2: Power supply sequencing. Updated Figure 48: Oscillators recommended external circuitry. Updated Figure 51: USB 2.0 application circuit. Updated Table 41: TSIn0 signals on PIO and Table 42: TSIn1 signals on PIO. Updated Bank name column in Table 77: System configuration registers banks summary. Updated introduction of Chapter 19: System configuration registers. Replaced SYSCFG_SBC by SYSCFG_BANK0 in Table 56: STiH271EL peripheral address map. Updated the ST231 and audio processor frequency. Updated Table 84: Operating conditions. Updated Figure 46: STiH271EL reset scheme for SYS_AONOTWDOGRSTOUT signal. Replaced I2C by SSC in the description of SSCx_SCL, SSCx_MTSR and SSCx_MRST signals for PIO4[6, 7], PIO7[6, 7], PIO9[2, 3, 4, 5], PIO12[0, 1] and PIO15[0, 1, 5, 6] in Chapter 25: Alternate functions on PIO. l - - - - - - 11-Nov-2014 10 - Alternate function name SPI_CS on PIO12[3] is changed to SPI_NOTCS throughout the document. - Updated Figure 4 for the use case: Two tuners + X-coder. - Updated Section 4.6.1: Transport subsystem description for general transport packet handling features. DocID023557 Rev 10 603/604 Information classified Confidential - Do not copy (See last page for obligations) Revision ti a Date IMPORTANT NOTICE - PLEASE READ CAREFULLY C STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2014 STMicroelectronics - All rights reserved 604/604 DocID023557 Rev 10 Information classified Confidential - Do not copy (See last page for obligations) on fid Confidential en ti a l STiH271EL