FUNCTIONAL BLOCK DIAGRAMS
19.95k⍀
20k⍀
0.5mA
I
REF
DAC
I
OUT
=
4 ⴛ I
REF
ⴛ CODE
AD565A
9.95k⍀
5k⍀
8k⍀
I
O
20V SPAN
10V SPAN
DAC OUT
POWER
GND
–V
EE
REF
GND
BIPOLAR OFF
5k⍀
CODE INPUT
LSBMSB
10V
V
CC
REF OUT
REF
IN
19.95k⍀
20k⍀
0.5mA
I
REF
DAC
I
OUT
=
4 ⴛ I
REF
ⴛ CODE
AD566A
9.95k⍀5k⍀
8k⍀
I
O
20V SPAN
10V SPAN
DAC OUT
POWER
GND
–V
EE
REF
GND
BIPOLAR OFF
5k⍀
CODE INPUT
LSB
MSB
REF
IN
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
High Speed 12-Bit
Monolithic D/A Converters
AD565A/AD566A
FEATURES
Single Chip Construction
Very High Speed Settling to 1/2 LSB
AD565A: 250 ns max
AD566A: 350 ns max
Full-Scale Switching Time: 30 ns
Guaranteed for Operation with ⴞ12 V (565A) Supplies,
with –12 V Supply (AD566A)
Linearity Guaranteed Overtemperature
1/2 LSB max (K, T Grades)
Monotonicity Guaranteed Overtemperature
Low Power: AD566A = 180 mW max;
AD565A = 225 mW max
Use with On-Board High Stability Reference (AD565A)
or with External Reference (AD566A)
Low Cost
MlL-STD-883-Compliant Versions Available
PRODUCT DESCRIPTION
The AD565A and AD566A are fast 12-bit digital-to-analog
converters that incorporate the latest advances in analog circuit
design to achieve high speeds at low cost.
The AD565A and AD566A use 12 precision, high speed bipolar
current-steering switches, a control amplifier, and a laser-trimmed
thin-film resistor network to produce a very fast, high accuracy
analog output current. The AD565A also includes a buried
Zener reference that features low noise, long-term stability, and
temperature drift characteristics comparable to the best discrete
reference diodes.
The combination of performance and flexibility in the AD565A and
AD566A has resulted from major innovations in circuit design,
an important new high speed bipolar process, and continuing
advances in laser-wafer-trimming techniques (LWT). The
AD565A and AD566A have a 10%–90% full-scale transition
time less than 35 ns and settle to within ±1/2 LSB in 250 ns max
(350 ns for AD566A). Both are laser-trimmed at the wafer level
to ±1/8 LSB typical linearity and are specified to ±1/4 LSB max
error (K and T grades) at +25°C. High speed and accuracy make
the AD565A and AD566A the ideal choice for high speed display
drivers as well as for fast analog-to-digital converters.
The laser trimming process that provides the excellent linearity
is also used to trim both the absolute value and the temperature
coefficient of the reference of the AD565A, resulting in a typical
full-scale gain TC of 10 ppm/°C. When tighter TC performance
is required or when a system reference is available, the AD566A
may be used with an external reference.
AD565A and AD566A are available in four performance
grades. The J and K grades are specified for use over the 0°C to
+70°C temperature range while the S and T grades are speci-
fied for the –55°C to +125°C range. The D grades are all pack-
aged in a 24-lead, hermetically sealed, ceramic, dual-in-line
package. The JR grade is packaged in a 28-lead plastic SOIC.
PRODUCT HIGHLIGHTS
1. The wide output compliance range of the AD565A and
AD566A are ideally suited for fast, low noise, accurate voltage
output configurations without an output amplifier.
2. The devices incorporate a newly developed, fully differential,
nonsaturating precision current switching cell structure that
combines the dc accuracy and stability first developed in the
AD562/AD563 with very fast switching times and an optimally
damped settling characteristic.
3. The devices also contain SiCr thin-film application resistors
that can be used with an external op amp to provide a preci-
sion voltage output or as input resistors for a successive-
approximation A/D converter. The resistors are matched to
the internal ladder network to guarantee a low gain temperature
coefficient and are laser-trimmed for minimum full-scale and
bipolar offset errors.
4. The AD565A and AD566A are available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military
Products Databook or current /883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD565A–SPECIFICATIONS
AD565AJ AD565AK
Parameter Min Typ Max Min Typ Max Unit
DATA INPUTS
1
(Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 0.8 0.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 120 300 µA
Bit OFF Logic “0” 35 100 35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ±1.0 ⴞ1.2 ⴞ0.8 ±1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 3, R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
T
MIN
to T
MAX
–1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C±1/4 ⴞ1/2 ±1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
T
MIN
to T
MAX
±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
T
MIN
to T
MAX
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero 1 212ppm/°C
Bipolar Zero 5 10 510 ppm/°C
Gain (Full Scale) 15 50 10 20 ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 400 250 400 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
TEMPERATURE RANGE
Operating 0 +70 0 +70 °C
Storage –65 +150 –65 +150 °C
POWER REQUIREMENTS
V
CC
, +11.4 to +16.5 V dc 3 535mA
V
EE
, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY
2
V
CC
= +11.4 to +16.5 V dc 3 10 310 ppm of F.S./%
V
EE
= –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2) ±0.1 ⴞ0.25 ±0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3) ±0.05 ⴞ0.15 ±0.05 ±0.1 % of F.S. Range
Gain Adjustment Range (Figure 2) ±0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ±0.15 ±0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
REFERENCE OUTPUT
Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads)
3
1.5 2.5 1.5 2.5 mA
POWER DISSIPATION 225 345 225 345 mW
NOTES
1
The digital inputs are guaranteed but not tested over the operating temperature range.
2
The power supply gain sensitivity is tested in reference to a V
CC
, V
EE
of ±15 V dc.
3
For operation at elevated temperatures, the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.
(TA = 25ⴗC, VCC = 15 V, VEE = 15 V, unless otherwise noted.)
REV. E
–2–
AD565A/AD566A
AD565AS AD565AT
Parameter Min Typ Max Min Typ Max Unit
DATA INPUTS
1
(Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 0.8 0.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 120 300 µA
Bit OFF Logic “0” 35 100 35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ±1.0 ⴞ1.2 ⴞ0.8 ±1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 3, R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
T
MIN
to T
MAX
–1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C±1/4 ⴞ1/2 ±1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
T
MIN
to T
MAX
±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
T
MIN
to T
MAX
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero 1 212ppm/°C
Bipolar Zero 5 10 510 ppm/°C
Gain (Full Scale) 15 30 10 15 ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 400 250 400 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
TEMPERATURE RANGE
Operating –55 +125 –55 +125 °C
Storage –65 +150 –65 +150 °C
POWER REQUIREMENTS
V
CC
, +11.4 to +16.5 V dc 3 535mA
V
EE
, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY
2
V
CC
= +11.4 to +16.5 V dc 3 10 310 ppm of F.S./%
V
EE
= –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2) ±0.1 ⴞ0.25 ±0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3) ±0.05 ⴞ0.15 ±0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 2) ±0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ±0.15 ±0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
REFERENCE OUTPUT
Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads)
3
1.5 2.5 1.5 2.5 mA
POWER DISSIPATION 225 345 225 345 mW
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
REV. E –3–
AD566A–SPECIFICATIONS
AD566AJ AD566AK
Parameter
Min Typ Max Min Typ Max Unit
DATA INPUTS
1
(Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 00.8 00.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 120 300 µA
Bit OFF Logic “0” 35 100 35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ±1.0 ⴞ1.2 ⴞ0.8 ±1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar (Adjustable to Zero per Figure 3) 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
T
MIN
to T
MAX
–1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C±1/4 ⴞ1/2 ±1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
T
MIN
to T
MAX
±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
T
MIN
to T
MAX
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
Unipolar Zero 1 212ppm/°C
Bipolar Zero 5 10 510 ppm/°C
Gain (Full Scale) 7 10 35ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 350 250 350 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
POWER REQUIREMENTS
V
EE
, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY
2
V
EE
= –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3) ±0.1 ⴞ0.25 ±0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4) ±0.05 ⴞ0.15 ±0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 3) ±0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ±0.15 ±0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
POWER DISSIPATION 180 300 180 300 mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants Two (2): Bipolar Operation at Digital Input Only
Reference Voltage 1 V to 10 V, Unipolar
Accuracy 10 Bits (±0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough) 40 kHz typ
Output Slew Rate 10%–90% 5 mA/µs
90%–10% 1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage) 1.5 µs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth 300 kHz
Small-Signal Closed-Loop Bandwidth 1.8 MHz
NOTES
1
The digital input levels are guaranteed but not tested over the temperature range.
2
The power supply gain sensitivity is tested in reference to a V
EE
of –1.5 V dc.
Specifications subject to change without notice.
(TA = 25ⴗC, VEE = –15 V, unless otherwise noted)
–4– REV. E
AD565A/AD566A
AD566AS AD566AT
Parameter Min Typ Max Min Typ Max Unit
DATA INPUTS
1
(Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 00.8 00.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 +120 300 µA
Bit OFF Logic “0” 35 100 +35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ±1.0 ⴞ1.2 ⴞ0.8 ±1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar (Adjustable to Zero per Figure 3) 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
T
MIN
to T
MAX
–1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C±1/4 ⴞ1/2 ±1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
T
MIN
to T
MAX
±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C±1/2 ⴞ3/4 ±1/4 ⴞ1/2 LSB
T
MIN
to T
MAX
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
Unipolar Zero 1 212ppm/°C
Bipolar Zero 5 10 510 ppm/°C
Gain (Full Scale) 7 10 35ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 350 250 350 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
POWER REQUIREMENTS
V
EE
, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY
2
V
EE
= –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3) ±0.1 ⴞ0.25 ±0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4) ±0.05 ⴞ0.15 ±0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 3) ±0.25 ±0.25 % of F.S. Range
Bipolar Zero Adjustment Range ±0.15 ±0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
POWER DISSIPATION 180 300 180 300 mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants Two (2): Bipolar Operation at Digital Input Only
Reference Voltage 1 V to 10 V, Unipolar
Accuracy 10 Bits (±0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for l/2 LSB [p-p] Feedthrough) 40 kHz typ
Output Slew Rate 10%–90% 5 mA/µs
90%–10% 1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage) 1.5 µs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth 300 kHz
Small-Signal Closed-Loop Bandwidth 1.8 MHz
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
–5–
REV. E
AD565A/AD566A
REV.E
–6–
ABSOLUTE MAXIMUM RATINGS
V
CC
to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V
EE
to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 V
Voltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 V
Digital Inputs (Pins 13 to 24) to
Power Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
REF IN to Reference Ground . . . . . . . . . . . . . . . . . . . . ±12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . ±12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . ±12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . ±24 V
REF OUT (AD565A) . . . . . Indefinite Short to Power Ground
Momentary Short to V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
GROUNDING RULES
The AD565A and AD566A use separate reference and power
grounds to allow optimum connections for low noise and high
speed performance. These grounds should be tied together at one
point, usually the device power ground. The separate ground
returns minimize current flow in low level signal paths. In this
way, logic return currents are not summed into the same return
path with analog signals.
AD565A ORDERING GUIDE
Max Gain Linearity
T.C. (ppm Temperature Error Max Package
Model
1
of F.S./
°
C) Range @ +25
°
C Options
2
AD565AJD 50 0°C to +70°C±1/2 LSB Ceramic (D-24)
AD565AJR 50 0°C to +70°C±1/2 LSB SOIC (RW-28)
AD565AKD 20 0°C to +70°C±1/4 LSB Ceramic (D-24)
AD565ASD 30 –55°C to +125°C±1/2 LSB Ceramic (D-24)
AD565ATD 15 –55°C to +125°C±1/4 LSB Ceramic (D-24)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data sheet.
2
D = Ceramic DIP, R = SOIC.
AD566A ORDERING GUIDE
Max Gain Linearity
T.C. (ppm Temperature Error Max Package
Model
1
of F.S./
°
C) Range @ +25
°
COption
2
AD566AJD 10 0°C to +70°C±1/2 LSB Ceramic (D-24
AD566AKD 3 0°C to +70°C±1/4 LSB Ceramic (D-24)
AD566ASD 10 –55°C to +125°C±1/2 LSB Ceramic (D-24)
AD566ATD 3 –55°C to +125°C±1/4 LSB Ceramic (D-24)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data sheet.
2
D = Ceramic DIP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD565A/AD566A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD565A/AD566A
REV. E –7–
PIN CONFIGURATIONS
28-Lead SOIC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
(Not to Scale)
AD566A
NC = NO CONNECT
PWR GND
20V SPAN R
10V SPAN R
DAC OUT (–2mA F.S.)
NC
NC
NC
REF GND
AMP SUMMING JUNCTION
BIPOLAR OFFSET IN
–VEE –15V IN (20mA)
REF V HI IN
BIT 12 IN (LSB)
BIT 11 IN
BIT 10 IN
BIT 9 IN
BIT 8 IN
BIT 1 IN (MSB)
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 6 IN
BIT 5 IN
BIT 7 IN
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
NC = NO CONNECT
TOP VIEW
(Not to Scale)
AD565A
PWR GND
20V SPAN R
10V SPAN R
DAC OUT (–2mA F.S.)
BIPOLAR OFFSET IN
NC
NC
VCC
REF OUT (+10V ±1%)
–VEE
REF IN
REF GND
BIT 12 IN (LSB)
BIT 11 IN
BIT 10 IN
BIT 9 IN
BIT 8 IN
BIT 1 IN (MSB)
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 6 IN
BIT 5 IN
BIT 7 IN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
(Not to Scale)
AD565A
NC = NO CONNECT
20V SPAN R
10V SPAN R
NC
DAC OUT
BIPOLAR OFFSET IN
–VEE
NC
NC
NC
NC
VCC
REF IN
REF GND
REF OUT (10V)
PWR GND
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
NC
BIT 1 (MSB)
BIT 2
BIT 3
BIT 6
BIT 5
BIT 4
24-Lead DIP
24-Lead DIP
AD565A/AD566A
REV.E
–8–
CONNECTING THE AD565A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using an
operational amplifier are shown in Figures 1, 2, and 3 with the
preferred trimming techniques. If a low offset operational amplifier
(OP77, AD741L, OP07) is used, excellent performance can be
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for
the 100 Ω trimmer, unipolar zero is typically within ±1/2 LSB
(plus op amp offset) and full-scale accuracy is within 0.1%
(0.25% max). Substituting a 50 Ω resistor for the 100 Ω bipo-
lar offset trimmer gives a bipolar zero error typically within
±2 LSB (0.05%).
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ±1/2 LSB of
1 µs. The feedback capacitor is shown with the optimum value
for each application; this capacitor is required to compen-
sate for the 25 pF DAC output capacitance.
FIGURE 1. UNIPOLAR CONFIGURATION
This configuration provides a unipolar 0 V to 10 V output
range. In this mode, the bipolar terminal, Pin 8, should be
grounded if not used for trimming.
19.95k⍀
20k⍀
0.5mA
IREF DAC
IOUT =
4 ⴛ IREF
ⴛ CODE
AD565A
9.95k⍀5k⍀
8k⍀
IO
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–VEE
REF
GND
BIPOLAR OFF
5k⍀
CODE
INPUT
LSB
MSB
10V
VCC
REF
OUT
REF
IN
R2
100⍀
10pF
AD509
OUTPUT
0V TO
+10V
100⍀
100k⍀
+15V
–15V
R1
50k⍀
2.4k⍀
Figure 1. 0 V to 10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer R1 until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is not
needed, but Pin 8 should then be connected to Pin 12.
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust 100 Ω gain trimmer R2 until the
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
(exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the gain
resistor at Pin 10 to the op amp output.
FIGURE 2. BIPOLAR CONFIGURATION
This configuration provides a bipolar output voltage from
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s).
19.95k⍀
20k⍀
0.5mA
IREF
DAC
IOUT =
4 ⴛ IREF
ⴛ CODE
AD565A
9.95k⍀5k⍀
8k⍀
IO
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–VEE
REF
GND
BIPOLAR OFF
5k⍀
CODE
INPUT
LSBMSB
10V
VCC
REF
OUT
REF
IN
R2
100⍀
10pF
AD509
OUTPUT
–5V TO
+5V
2.4k⍀
R1
100⍀
Figure 2.
±
5 V Bipolar Voltage Output
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000 V
output.
STEP II . . . GAIN ADJUST
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a
reading of +4.9976 V.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
FIGURE 3. OTHER VOLTAGE RANGES
The AD565A can also be easily configured for a unipolar 0 V to
+5 V range or ±2.5 V and ±10 V bipolar ranges by using the
additional 5 kΩ application resistor provided at the 20 V span R
terminal, Pin 11. For a 5 V span (0 V to +5 V, or ±2.5 V), the
two 5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9
and connecting Pin 10 to the op amp output and the bipolar
offset either to ground for unipolar or to REF OUT for the
bipolar offset either to ground for unipolar or to REF OUT for
the bipolar range. For the ±10 V range (20 V span) use the 5 kΩ
resistors in series by connecting only Pin 11 to the op amp output
and the bipolar offset connected as shown. The ±10 V option is
shown in Figure 3.
19.95k⍀
20k⍀
0.5mA
IREF
DAC
IOUT =
4 ⴛ IREF
ⴛ CODE
AD565A
9.95k⍀5k⍀
8k⍀
IO
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–VEE
REF
GND
BIPOLAR OFF
5k⍀
CODE
INPUT
LSBMSB
10V
VCC
REF
OUT
REF
IN
R2
100⍀
10pF
AD509
OUTPUT
–10V TO
+10V
3.0k⍀
R1
100⍀
Figure 3.
±
10 V Voltage Output
AD565A/AD566A
REV. E –9–
CONNECTING THE AD566A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using an
operational amplifier are shown in Figures 4, 5, and 6 with the
preferred trimming techniques. If a low offset operational amplifier
(OP77, AD741L, OP07) is used, excellent performance can be
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for the
100 Ω trimmer, unipolar zero typically is within ±1/2 LSB (plus op
amp offset), and full-scale accuracy is within 0.1% (0.25% max).
Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer
gives a bipolar zero error typically within ±2 LSB (0.05%).
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ±1/2 LSB of 1 µs. The
feedback capacitor is shown with the optimum value for each
application; this capacitor is required to compensate for the
25 pF DAC output capacitance.
FIGURE 4. UNIPOLAR CONFIGURATION
This configuration provides a unipolar 0 V to 10 V output range.
In this mode, the bipolar terminal, Pin 7, should be grounded if not
used for trimming.
100k⍀
+15V
–15V
R1
50k⍀
19.95k⍀
20k⍀
0.5mA
I
REF
DAC
I
OUT
=
4 ⴛ I
REF
ⴛ CODE
AD566A
9.95k⍀5k⍀
8k⍀
I
O
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–V
EE
REF
GND
BIPOLAR OFF
5k⍀
CODE
INPUT
LSBMSB
R2
100⍀
10pF
AD509
2.4k⍀
100⍀
10V
E
REF
AD561
+V
REF
IN
Figure 4. 0 V to 10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is
not needed, but Pin 7 should then be connected to Pin 12.
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust 100 Ω gain trimmer, R2, until the
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
(exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the
gain resistor at Pin 10 to the op amp output.
FIGURE 5. BIPOLAR CONFIGURATION
This configuration provides a bipolar output voltage from
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s).
19.95k⍀
20k⍀
0.5mA
I
REF DAC
I
OUT
=
4 ⴛ I
REF
ⴛ CODE
AD566A
9.95k⍀5k⍀
8k⍀
I
O
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–V
EE
REF
GND
BIPOLAR OFF
5k⍀
CODE
INPUT
LSBMSB
R2
100⍀10pF
AD509
2.4k⍀
10V
E
REF
AD561
+V
REF
IN
R1
100⍀
Figure 5.
±
5 V Bipolar Voltage Output
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
output V.
STEP II . . . GAIN ADJUST
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a read-
ing of +4.9976 V.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
AD565A/AD566A
REV.E
–10–
FIGURE 6. OTHER VOLTAGE RANGES
The AD566A can also be easily configured for a unipolar 0 V to
+5 V range or ±2.5 V and ±10 V bipolar ranges by using the
additional 5 kΩ application resistor provided at the 20 V span R
terminal, Pin 11. For a 5 V span (0 V to +5 V or ±2.5 V), the two
5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9 and
connecting Pin 10 to the op amp output and the bipolar offset
resistor either to ground for unipolar or to V
REF
for the bipolar
range. For the ±10 V range (20 V span), use the 5 kΩ resistors in
series by connecting only Pin 11 to the op amp output and the
bipolar offset connected as shown. The ±10 V option is shown
in Figure 6.
Table I. Digital Input Codes
DIGITAL INPUT ANALOG OUTPUT
MSB LSB Straight Binary Offset Binary Twos Complement*
0 0 0 0 0 0 0 0 0 0 0 0 Zero –FS Zero
0 1 1 1 1 1 1 1 1 1 1 1 Mid Scale – 1 LSB Zero – 1 LSB +FS – 1 LSB
1 0 0 0 0 0 0 0 0 0 0 0 +1/2 FS Zero –FS
1 1 1 1 1 1 1 1 1 1 1 1 +FS – l LSB +FS – 1 LSB Zero – 1 LSB
*Inverts the MSB of the offset binary code with an external inverter to obtain twos complement.
19.95k⍀
20k⍀
0.5mA
I
REF
DAC
I
OUT
=
4 ⴛ I
REF
ⴛ CODE
AD566A
9.95k⍀5k⍀
8k⍀
I
O
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–V
EE
REF
GND
BIPOLAR OFF
5k⍀
CODE
INPUT
LSB
MSB
R2
5k⍀
10pF
AD509
2.4k⍀
7.5V
E
REF
AD561
–V
REF
IN
R1
5k⍀
14k⍀
*
THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTOR
AND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPANDED ON PREVIOUS PAGE.
R3
26k⍀*
Figure 6.
±
10 V Voltage Output
AD565A/AD566A
REV. E –11–
OUTLINE DIMENSIONS
24-Lead Side-Brazed Solder Lid Ceramic DIP [DIP/SB]
(D-24)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.075 (1.91)
0.015 (0.38)
0.225 (5.72)
MAX
0.200 (5.08)
0.120 (3.05)
0.070 (1.78)
0.030 (0.76)
0.150
(3.81)
MIN
1.290 (32.77) MAX
0.100 (2.54)
BSC
24
112
13
0.610 (15.49)
0.500 (12.70)
PIN 1
0.098 (2.49) MAX
0.005 (0.13) MIN
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Standard Small Outline Package [SOIC]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AE
0.32 (0.0126)
0.23 (0.0091)
8ⴗ
0ⴗ
0.75 (0.0295)
0.25 (0.0098) ⴛ 45ⴗ
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.33 (0.0130)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
28 15
14
1
18.10 (0.7126)
17.70 (0.6969)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
COPLANARITY
0.10
Revision History
Location Page
10/02—Data Sheet changed from REV. D to REV. E.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
C00516–0–10/02(E)
PRINTED IN U.S.A.
–12–
