Product Brief September 2001 CelXpresTM T8208 ATM Interconnect Features Programmable priority for control/data cells transmission onto cell bus OC-12 data throughput on UTOPIA (16-bit) (independently on RX and TX UTOPIA) Microprocessor access to all headers of control cell Shared UTOPIA mode Ability to clear counters on read UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level handshake interface (ATM or PHY layers) Simplified looping to any system device with a single register programming Multi-PHY (MPHY) operation UTOPIA clock sourcing with additional settings Programmable ATM layer supports up to 64 PHY ports Programmable operations and maintenance and resource management (OAM/RM) cell routing Egress SDRAM buffer support to extend UTOPIA output priority queues for 32K to 512K cells: -- 128 queues configurable up to four queues per PHY with programmable sizes -- Programmable number of UTOPIA output queues with four levels of priority Support of multicast and broadcast cells per PHY Optional monitoring of misrouted cells Counters for dropped cells per queue Digital loopback before cell bus Microprocessor interface, supporting both Motorola(R) and Intel (R) modes (multiplexed and nonmultiplexed) Control cell transmission and reception through microprocessor port Single 3.3 V power supply 3.3 V TTL I/O (5 V tolerant) 272-pin plastic ball grid array (PBGA) package Industrial temperature range (-40 C to +85 C) Hot insertion capability Eight GPIO pins JTAG support Compatible with Transwitch CellBus(R) Support of ATM traffic management via partial packet discard (PPD), forward explicit congestion notification (FECN), and the cell loss priority (CLP) bit Programmable slew rate GTL+ I/O: -- Programmable as bus arbiter -- 1.7 Gbits/s cell bus operation Flexible per port cell counters Cell header insertion with virtual path identifier (VPI) and virtual channel identifier (VCI) translation via external SRAM (up to 64K entries) Support of network node interface (NNI) and user network interface (UNI) header types with optional generic flow-control (GFC) insertion Optional sourcing of cell bus clocks from device LUT bypass option TX UTOPIA cell buffer increased to 256 cells for better queue management with SDRAM queue bypass option Ability for cell bus arbiter to mask devices on the cell bus Ability to modify cell bus priority based on RX PHY FIFO thresholds Applications Asymmetric digital subscriber line (ADSL) digital subscriber line access multiplexers (DSLAMs) Access gateways Access multiplexers/concentrators Multiservice platforms CelXpres T8208 ATM Interconnect Product Brief September 2001 Description The CelXpres T8208 device integrates all of the required functionality to transport ATM cells at OC-12 rates across a backplane architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the device's functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface. The T8208 device meets the ATM Forum's universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with rates up to 635 Mbits/s. The T8208 supports the required MPHY operation as described in Sections 4.1 and 4.2 of the ATM Forum's level 2 specification. The T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 interface configuration. With four transmit cells available/enable (TxCLAV/Enb*) pairs of signals and receive cell available/enable (RxCLAV/Enb*) pairs of signals, 64 MPHYs can be supported. For a 16-bit UTOPIA 2 interface configuration, the T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 8 PHY ports. With four transmit cell available (TxCLAV/Enb*) signals and four receive cell available (RxCLAV/Enb*) signals, 32 MPHYs can be supported in 16-bit UTOPIA 2 interface configuration. In addition to the required UTOPIA signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided. ONE OR TWO 32K TO 256K x 8 (LUT) SRAMs CELL BUS ARBITER LOOK-UP ENGINE RX UTOPIA RX UTOPIA INTERFACE RX PHY FIFO (16 CELLS) RX UTOPIA FIFO (4 CELLS) MICROPROCESSOR CONTROL CELL TX FIFO (1 CELL) MICROPROCESSOR INTERFACE CELL BUS OUTPUT FIFO (4 CELLS) CELL BUS INTERFACE LOOPBACK FIFO (1 CELL) DIGITAL LOOPBACK CONTROL CELL RX FIFO (16 CELLS) TX UTOPIA TX UTOPIA INTERFACE TX UTOPIA CELL BUFFER (256 CELLS) CELL BUS TX PHY FIFO (256 CELLS) CELL BUS INPUT FIFO (4 CELLS) SDRAM INTERFACE CELL BUS MONITORING 1M TO 16M x 16 SDRAM 5-7542d F Figure 1. Functional Block Diagram 2 Agere Systems Inc. Product Brief September 2001 CelXpres T8208 ATM Interconnect Description (continued) dancy or increase UTOPIA traffic capacity by supporting traffic from multiple cell buses. The T8208 may be configured as an ATM or PHY level device providing cell routing between UTOPIA and a 32-bit wide cell bus. In addition to the 32 data signals, the bus has the following signals: The CelXpres T8208 supports the transport of control and loopback cells with an external microprocessor. Control or loopback cells may be sent or received through the microprocessor interface. The 8-bit microprocessor interface may be configured to be Motorola or Intel compatible and is used to configure and monitor the device. Read clock Write clock Frame sync Acknowledge ATM cells arriving from the UTOPIA interface may get VPI and VCI translation and routing information from a look-up table in external SRAM. An external synchronous dynamic random access memory (SDRAM) is used to extend the buffering for ATM cells destined for the UTOPIA interface. This external SDRAM may be partitioned into four or less independently sized queues per PHY for a configuration of 32 MPHYs and two queues per PHY or a programmable number of queues per PHY for a configuration of 64 MPHYs. The four queues may be used to support quality of service (QoS) by directing different traffic categories to each queue. The CelXpres T8208 provides a shared UTOPIA mode, which allows two devices on different cell buses to share the same UTOPIA bus in ATM mode. Using a glueless interface, the two T8208 devices resolve queue priorities and arbitrate the use of the UTOPIA bus. This shared mode can be used to provide redun- Agere Systems Inc. Figure 2 illustrates the use of the CelXpres T8208 in a system with dual backplane cell buses using shared UTOPIA mode. In this configuration, both T8208 devices on each card receive cells from the UTOPIA bus, and each device uses its translation table to determine if the cell should be transmitted on its backplane cell bus. In the egress direction, each T8208 device receives cells from its cell bus to transmit on the UTOPIA bus. MPHY arbitration and queue priorities are resolved using a six-wire interface between the two devices. Although a single ATM virtual connection is not typically established on both backplane cell buses simultaneously, no restrictions exist for a single PHY utilizing both backplane cell buses for different virtual connections supporting higher throughput from two bus interfaces. Redundant bus configurations can be supported in the event of a bus failure with T8208 devices by configuring one device to assume bus responsibility from the other. In addition to higher performance, the T8208 features numerous enhancements that facilitate various configurations for ATM traffic management. 3 CelXpres T8208 ATM Interconnect Product Brief September 2001 Description (continued) DOWNSTREAM BUFFERING UPSTREAM TRANSLATION UTOPIA T8208 UTOPIA PHYs T8208 DOWNSTREAM BUFFERING UPSTREAM TRANSLATION DOWNSTREAM BUFFERING UPSTREAM TRANSLATION UTOPIA T8208 BACKPLANE BUS UTOPIA PHYs T8208 DOWNSTREAM BUFFERING UPSTREAM TRANSLATION 0041b Figure 2. Dual Bus Implementation Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. Transwitch and CellBus are registered trademarks of Transwitch Corp. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application. CelXpres is a trademark of Agere Systems Inc. Copyright (c) 2001 Agere Systems Inc. All Rights Reserved September 2001 PB01-167DLC (Replaces PB01-121DLC)