Product Brief
September 2001
CelXpres
TM T8208
ATM Interconnect
Features
■OC-12 data throughput on UTOPIA (16-bit)
(independently on RX and TX UTOPIA)
■Shared UTOPIA mode
■UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level
handshake interface (ATM or PHY layers)
■Multi-PHY (MPHY) operation
■Programmable ATM layer supports up to 64 PHY
ports
■Egress SDRAM buffer support to extend UTOPIA
output priority queues for 32K to 512K cells:
— 128 queues configurable up to four queues per
PHY with progr am mab le si ze s
— Programmable number of UTOPIA output
queues with four levels of priority
■Support of ATM traffic management via partial
packet discard (PPD), forward explicit congestion
notification (FECN), and the cell loss priority (CLP)
bit
■Programmable slew rate GTL+ I/O:
— Programmable as bus arbiter
— 1.7 Gbits/s cell bus operation
■Flexible per port cell counters
■Cell header insertion with virtual path identifier
(VPI) and virtual channel identifier (VCI) translation
via external SRAM (up to 64K entries)
■Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow-control (GFC) insertion
■Optional sourcing of cell bus clocks from device
■LUT bypass option
■TX UTOPIA cell buffer increased to 256 cells for
better queue management with SDRAM queue
bypass option
■Ability for cell bus arbiter to mask devices on the
cell bus
■Ability to modify cell bus priority based on RX PHY
FIFO thresholds
■Programmable priority for control/data cells trans-
missio n onto cel l bus
■Microprocessor access to all headers of control
cell
■Ability to clear counters on read
■Simplified looping to any system device with a sin-
gle register programming
■UTOPIA clock sourcing with additional settings
■Programmable operations and maintenance and
resource management (OAM/RM) cell routing
■Support of multicast and broadcast cells per PHY
■Optional monitoring of misrouted cells
■Counters for dropped cells per queue
■Digital loopback before cell bus
■Microprocessor interface, supporting both
Motor-
ola
® and
Intel
® modes (m ult iplex ed and non mul ti-
plexed)
■Cont rol cell transmission and reception thr ough
microprocessor port
■Single 3.3 V power supply
■3.3 V TTL I/O (5 V tolerant)
■272-pin plastic ball grid array (PBGA) package
■Industrial temperature range (–40 °C to +85 °C)
■Hot insertion cap abi li ty
■Eight GPIO pins
■JTAG support
■Compatible with
Transwitch
CellBus
®
Applications
■Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexers (DSLAMs)
■Access gateways
■Access multiplexe rs/concentrators
■Multiservice platforms
2 Agere Systems Inc.
Product Brief
September 2001
ATM Interconnect
CelXpres
T8208
Description
The
CelXpres
T8208 device integrates all of the
required functionality to transport ATM cells at OC-12
rates across a backplane architecture with high-speed
cell traffic exceeding 1.5 Gbits/s to a maximum of 32
destinations. The management of multiple service cat-
egories and monitoring of performance on ATM and
PHY interfaces is incorporated in the device’s function-
ality. Traffic delivery to multi-PHYs (MPHYs) is man-
aged through the UTOPIA interface.
The T8208 device meets the ATM Forum’s universal
test and operations PHY interface for ATM (UTOPIA)
Level 1, Version 2.01 and Level 2, Version 1.0 specifi-
cations for cell-level handshake and MPHY data path
operation with rates up to 635 Mbits/s. The T8208 sup-
ports the required MPHY operation as described in
Sections 4.1 and 4.2 of the ATM Forum’s level 2 speci-
fication. The T8208 supports MPHY operation with one
transmit cell available (TxCLA V) signal and one receive
cell available (RxCLAV) signal for up to 16 PHY ports
for an 8-bit UTOPIA 2 interface configuration. With
four transmit cells available/enable (TxCLAV/Enb*)
pairs of signals and receive cell available/enable
(RxCLAV/Enb*) pairs of signals, 64 MPHYs can be
support ed. For a 16-bit UTOPIA 2 inter fac e config ur a-
tion, the T8208 supports MPHY operation with one
transmit cell available (TxCLA V) signal and one receive
cell available (RxCLAV) signal for up to 8 PHY ports.
With four transmit cell available (TxCLA V/Enb*) signals
and four receive cell available (RxCLAV/Enb*) signals,
32 MPHYs can be supported in 16-bit UTOPIA 2 inter-
face configuration. In addition to the required UTOPIA
signals, the optional transmit parity (TxPRTY) and
receive parity (RxPRTY) signals are provided.
5-7542d F
Figure 1. Functional Block Diagram
ONE OR TWO
32K TO 256K x 8
LOOK-UP
ENGINE
RX
UTOPIA
INTERFACE
RX PHY
FIFO
(1 6 CELLS)
CONTROL CELL
TX FIFO
(1 CELL)
LOOPBACK
FIFO
(1 CELL)
CONTROL CELL
RX FIFO
(16 CELLS)
TX PHY
FIFO
(256 CELLS)
SDRAM
INTERFACE
TX UTOPIA
1M TO 16 M x 16
SDRAM
MICROPROCESSOR
INTERFACE
MICROPROCESSOR
CELL BUS
CELL BUS
ARBITER
CELL BUS
MONITORING
CELL BUS
INTERFACE CELL BUS
TX
UTOPIA
INTERFACE
RX
UTOPIA
TX
UTOPIA
(4 CELLS)
INPUT FIFO
(256 CELLS)
CELL BUFFER
(LUT) SR AMs
RX UTOPIA
FIFO
DIGITAL LOOPBACK
(4 CELLS)
CELL BUS
OUTPU T FIF O
(4 CELLS)
Agere Systems Inc. 3
Product Brief
September 2001 AT M Interconnect
CelXpres
T8208
Description (continued)
The T8208 may be configured as an ATM or PHY level
device providing cell routing between UTOPIA and a
32-bit wide cell bus. In addition to the 32 data signals,
the bus has the following signals:
■Read clock
■Write clock
■Frame sync
■Acknowledge
ATM cells arriving from the UTOPIA interface may get
VPI and VCI translation and routing information from a
look-up table in external SRAM. An external synchro-
nous dyn amic rando m acc es s mem ory (S DRA M) is
used to extend the buffering for ATM cells destined for
the UTOPIA interface. This external SDRAM may be
partitioned into four or less independently sized queues
per PHY for a configuration of 32 MPHYs and two
queues per PHY or a programmable number of queues
per PHY for a configuration of 64 MPHYs. The four
queues may be used to support quality of service
(QoS) by directing different traffic categories to each
queue.
The
CelXpres
T8208 provides a shared UTOPIA mode,
which allows two devices on different cell buses to
share the same UTOPIA bus in ATM mode. Using a
glueless interface, the two T8208 devices resolve
queue priorities and arbitrate the use of the UTOPIA
bus. This shared mode can be used to provide redun-
dancy or increase UTOPIA traffic capacity by support-
ing traffic from multiple cell buses.
The
CelXpres
T8208 supports the transport of control
and loopback cells with an external microprocessor.
Control or loopback cells may be sent or received
through the microprocessor interface. The 8-bit micro-
processor interface may be configured to be
Motorola
or
Intel
compatible and is used to configure and moni-
tor the device.
Figure 2 illustrates the use of the
CelXpres
T8208 in a
system with dual backplane cell buses using shared
UTOPIA mode. In this configuration, both T8208
devices on each card receive ce lls from the UTOPIA
bus, and each device uses its translation table to deter-
mine if the cell should be transmitted on its backplane
cell bus. In the egress direction, each T8208 device
receives cells from its cell bus to transmit on the UTO-
PIA bus. MPHY arbitration and queue priorities are
resolved using a six-wire interface between the two
devices. Although a single ATM virtual connection is
not typically established on both backplane cell buses
simultaneously, no restrictions exist for a single PHY
utilizing both backplane cell buses for different virtual
connections supporting higher throughput from two
bus interfaces. Redundant bus configurations can be
supported in the event of a bus failure with T8208
devices by configuring one device to assume bus
responsibility from the other.
In addition to higher performance, the T8208 features
numerous enhancements that facilitate various config-
urations for ATM traffic management.
Product Brief
September 2001
ATM Interconnect
CelXpres
T8208
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
CelXpres
is a trademark of Agere Systems Inc.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
September 2001
PB01-167DLC (Replaces PB01-121DLC)
For additional informatio n, co nta ct you r Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc ., 555 Union Bou le vard , Room 30L-15 P-BA, Allentown , PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA: Agere Systems Hon g K on g Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Ha rbo ur City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-504 7- 1212 (Shangha i) , (86) 10-6522-5566 (Beijing), ( 86) 755-695-7224 (Shenzh en)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPOR E: (65) 77 8-8833, TAIWAN: (886) 2- 2725-5858 (Taipei)
EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Description (continued)
0041b
Figure 2. Dual Bus Implementation
DOWNSTREAM
BUFFERING UPSTREAM
TRANSLATION
UTOPIA
T8208
DOWNSTREAM
BUFFERING UPSTREAM
TRANSLATION
UTOPIA
PHYs
T8208
BACKPLANE
BUS
DOWNSTREAM
BUFFERING UPSTREAM
TRANSLATION
UTOPIA
T8208
DOWNSTREAM
BUFFERING UPSTREAM
TRANSLATION
UTOPIA
PHYs
T8208
Motorola
is a registered trademark of Motorola, Inc.
Intel
is a registered trademark of Intel Corporation.
Transwitch
and
CellBus
are registered trademarks of Transwitch Corp.
