LTC2315CTS8-12#TRMPBF - LINEAR TECHNOLOGY

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

TYPICAL APPLICATION

FEATURES DESCRIPTION

12-Bit, 5Msps Serial

Sampling ADC in TSOT

The LTC

2315-12 is a 12-bit, 5Msps, serial sampling A/D

converter that draws only 6.4mA from a wide range analog

supply adjustable from 2.7V to 5.25V. The LTC2315-12

contains an integrated bandgap and reference buffer which

provide a low cost, high performance (20ppm/°C max)

and space saving applications solution. The LTC2315-12

achieves outstanding AC performance of 72.6dB SINAD

and –84dB THD while sampling a 500kHz input frequency.

The extremely high sample rate-to-power ratio makes the

LTC2315-12 ideal for compact, low power, high speed

systems. The LTC2315-12 also provides both nap and

sleep modes for further optimization of the device power

within a system.

The LTC2315-12 has a high-speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3V and 5V logic. The

fast 5Msps throughput makes the LTC2315-12 ideally

suited for a wide variety of high speed applications.

Complete 14-/12-Bit Pin-Compatible SAR ADC Family

500ksps 2.5Msps 4.5Msps 5Msps

14-Bit LTC2312-14 LTC2313-14 LTC2314-14

12-Bit LTC2312-12 LTC2313-12 LTC2315-12

Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW

APPLICATIONS

n 5Msps Throughput Rate

n Guaranteed 12-Bit No Missing Codes

n Internal Reference: 2.048V/4.096V Span

n Low Noise: 73dB SNR

n Low Power: 6.4mA at 5Msps and 5V

n Dual Supply Range: 3V/5V operation

n Sleep Mode with < 1µA Typical Supply Current

n Nap Mode with Quick Wake-up < 1 conversion

n Separate 1.8V to 5V Digital I/O Supply

n High Speed SPI-Compatible Serial I/O

n Guaranteed Operation from –40°C to 125°C

n 8-Lead TSOT-23 Package

n Communication Systems

n High Speed Data Acquisition

n Handheld Terminal Interface

n Medical Imaging

n Uninterrupted Power Supplies

n Battery Operated Systems

n Automotive

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

5V Supply, Internal Reference, 5Msps, 12-bit Sampling ADC

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTERS

ANALOG INPUT

0V TO 4.096V

2.2µF

231512 TA01

GND

VDD

REF

AIN OVDD

SCK

SDO

LTC2315-12

DIGITAL OUTPUT SUPPLY

1.8V TO 5V

16k Point FFT, fS = 5Msps, fIN = 500kHz

231512 TA01a

FREQUENCY (kHz)

AMPLITUDE (dBFS)

0 25002000

1000500 1500

–20

–40

–60

–80

–100

–120

–140

VDD = 5V

SNR = 73.1dBFS

SINAD = 72.6dBFS

THD = –84dB

SFDR = 87dBc

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD, OVDD) .......................................6V

Reference (REF) and Analog Input (AIN) Voltage

(Note 3) ......................................(–0.3V) to (VDD + 0.3V)

Digital Input Voltage (Note 3) .. (–0.3V) to (OVDD + 0.3V)

Digital Output Voltage ............. (–0.3V) to (OVDD + 0.3V)

Power Dissipation ...............................................100mW

Operating Temperature Range

LTC2315C ................................................ 0°C to 70°C

LTC2315I ..............................................–40°C to 85°C

LTC2315H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature Range (Soldering, 10 sec) ........300°C

(Notes 1, 2)

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

SCK

SDO

OVDD

VDD

REF

GND

AIN

TJMAX = 150°C, θJA = 195°C/W

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2315CTS8-12#TRMPBF LTC2315CTS8-12#TRPBF LTFZG 8-Lead Plastic TSOT-23 0°C to 70°C

LTC2315ITS8-12#TRMPBF LTC2315ITS8-12#TRPBF LTFZG 8-Lead Plastic TSOT-23 –40˚C to 85˚C

LTC2315HTS8-12#TRMPBF LTC2315HTS8-12#TRPBF LTFZG 8-Lead Plastic TSOT-23 –40˚C to 125˚C

TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

ELECTRICAL CHARACTERISTICS

CONVERTER CHARACTERISTICS

DYNAMIC ACCURACY

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VAIN Absolute Input Range l–0.05 VDD + 0.05 V

VIN Input Voltage Range (Note 11) 0 VREF V

IIN Analog Input DC Leakage Current l–1 1 µA

CIN Analog Input Capacitance Sample Mode

Hold Mode

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution l12 Bits

No Missing Codes l12 Bits

Transition Noise (Note 6) 0.33 LSBRMS

INL Integral Linearity Error VDD = 5V (Note 5)

VDD = 3V (Note 5)

–1.25

–1.5

±0.25

±0.3

1.25

1.5

LSB

DNL Differential Linearity Error VDD = 5V

VDD = 3V

–0.99

±0.15

±0.2

0.99

LSB

Offset Error VDD = 5V

VDD = 3V

–4

–6

±0.5

±1

LSB

Full-Scale Error VDD = 5V

VDD = 3V

–7

–9

±1.5

±2

LSB

Total Unadjusted Error VDD = 5V

VDD = 3V

–8

–10

±2

±2.5

LSB

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SINAD Signal-to-(Noise + Distortion) Ratio fIN = 500kHz, VDD = 5V

fIN = 500kHz, VDD = 3V

69.5

67.5

72.6

69.5

SNR Signal-to-Noise Ratio fIN = 500kHz, VDD = 5V

fIN = 500kHz, VDD = 3V

THD Total Harmonic Distortion

First 5 Harmonics

fIN = 500kHz, VDD = 5V

fIN = 500kHz, VDD = 3V

–84

–76

–75

SFDR Spurious Free Dynamic Range fIN = 500kHz, VDD = 5V

fIN = 500kHz, VDD = 3V

IMD Intermodulation Distortion

2nd Order Terms

3rd Order Terms

fIN1 = 461kHz, fIN2 = 541kHz

AIN1, AIN2 = –7dBFS

–77

–89

dBc

Full Power Bandwidth At 3dB

At 0.1dB

130

MHz

–3dB Input Linear Bandwidth SINAD ≥ 68dB 5 MHz

tAP Aperture Delay 1 ns

tJITTER Aperture Jitter 10 psRMS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Note 4)

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

REFERENCE INPUT/OUTPUT

POWER REQUIREMENTS

DIGITAL INPUTS AND DIGITAL OUTPUTS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF VREF Output Voltage 2.7V ≤ VDD ≤ 3.6V

4.75 ≤ VDD ≤ 5.25V

2.040

4.080

2.048

4.096

2.056

4.112

VREF Temperature Coefficient l7 20 ppm/°C

VREF Output Resistance Normal Operation

Overdrive Condition

(VREFIN ≥ VREFOUT + 50mV)

kΩ

VREF Line Regulation 2.7V ≤ VDD ≤ 3.6V

4.75 ≤ VDD ≤ 5.25V

0.8

mV/V

VREF 2.048V/4.096V Supply Threshold 4.15 V

VREF 2.048V/4.096V Supply Threshold Hysteresis 150 mV

VREF Input Voltage Range

(External Reference Input)

2.7V ≤ VDD ≤ 3.6V

4.75 ≤ VDD ≤ 5.25V

VREF + 50mV

VDD

4.3

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage

3V Operational Range

5V Operational Range

2.7

4.75

3.6

5.25

OVDD Digital Output Supply Voltage l1.71 5.25 V

ITOTAL =

IVDD + IOVDD

Supply Current, Static Mode

Operational Mode

Nap Mode

Sleep Mode

CS = 0V, SCK = 0V l

3.5

6.4

1.8

0.8

7.5

µA

PDPower Dissipation, Static Mode

Operational Mode

Nap Mode

Sleep Mode

CS = 0V, SCK = 0V l

17.5

37.5

µW

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage l0.8 • OVDD V

VIL Low Level Input Voltage l0.2 • OVDD V

IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA

CIN Digital Input Capacitance 5 pF

VOH High Level Output Voltage IO = –500µA (Source) lOVDD–0.2 V

VOL Low Level Output Voltage IO = 500µA (Sink) l0.2 V

IOZ High-Z Output Leakage Current VOUT = 0V to OVDD, CS = High l–10 10 µA

COZ High-Z Output Capacitance CS = High 4 pF

ISOURCE Output Source Current VOUT = 0V, OVDD = 1.8V –20 mA

ISINK Output Sink Current VOUT = OVDD = 1.8V 20 mA

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 4)

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 4)

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

ADC TIMING CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSAMPLE(MAX) Maximum Sampling Frequency (Notes 7, 8) l5 MHz

fSCK Shift Clock Frequency (Notes 7, 8) l87.5 MHz

tSCK Shift Clock Period l11.4 ns

tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l200 ns

tCONV Conversion Time l160 ns

tACQ Acquisition Time l40 ns

t1Minimum CS Pulse Width (Note 7) l5 ns

t2SCK

↔

Setup Time After CS↓(Note 7) l5 ns

t3SDO Enable Time After CS↓(Notes 7, 8) l10 ns

t4SDO Data Valid Access Time after SCK↓(Notes 7, 8, 9) l9.1 ns

t5SCLK Low Time l4.5 ns

t6SCLK High Time l4.5 ns

t7SDO Data Valid Hold Time After SCK↓(Notes 7, 8, 9) l1 ns

t8SDO into Hi-Z State Time After 16th SCK↓(Notes 7, 8, 10) l3 10 ns

t9SDO into Hi-Z State Time After CS↑(Notes 7, 8, 10) l3 10 ns

t10 CS↑ Setup Time After 14th SCK↓(Note 7) l5 ns

Latency l1 Cycle Latency

tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns

tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. All voltage values are with respect to ground.

Note 3. When these pin voltages are taken below ground or above VDD

(AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal

diodes. This product can handle input currents up to 100mA below ground

or above VDD or OVDD without latch-up.

Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 5MHz, fSCK = 87.5MHz, AIN =

–1dBFS and internal reference unless otherwise noted.

Note 5. Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6. Typical RMS noise at code transitions.

Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals

are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a

voltage level of OVDD/2.

Note 8. All timing specifications given are with a 10pF capacitance load.

Load capacitances greater than this will require a digital buffer.

Note 9. The time required for the output to cross the VIH or VIL voltage.

Note 10. Guaranteed by design, not subject to test.

Note 11. Recommended operating conditions.

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

TYPICAL PERFORMANCE CHARACTERISTICS

16k Point FFT, fS = 5Msps

fIN = 500kHz

SNR, SINAD vs Input Frequency

(100kHz to 2.2MHz)

THD, Harmonics vs Input

Frequency (100kHz to 2.2MHz)

THD, Harmonics vs Input

Frequency (100kHz to 2.2MHz)

SNR, SINAD vs Temperature,

fIN = 500kHz

THD, Harmonics vs Temperature,

fIN = 500kHz

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram Near Mid-Scale

(Code 2048)

TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps,

unless otherwise noted.

OUTPUT CODE

–1.0

–0.8

–0.6

–0.4

DNL (LSB)

–0.2

0.4

0.2

0.0

0.6

0.8

1.0

1024 2048 3072 4096

231512 G02

CODE

2047

COUNTS

2049

231512 G03

2048 2050 2051

σ = 0.33

10000

20000

30000

40000

60000

50000

231512 G04

INPUT FREQUENCY (kHz)

AMPLITUDE (dBFS)

0 25002000

1000500 1500

–20

–40

–60

–80

–100

–120

–140

VDD = 5V

SNR = 73.1dBFS

SINAD = 72.6dBFS

THD = –84dB

SFDR = 87dBc

INPUT FREQUENCY (kHz)

SNR, SINAD (dBFS)

500 1000 1500 2000 2500

231512 G05

SINAD

SNR

SINAD

SNR

VDD = 5V

VDD = 3V

INPUT FREQUENCY (kHz)

–100

–95

THD, HARMONICS (dB)

–90

–85

–80

–75

500 1000 1500 2000 2500

231512 G06

THD

2ND

3RD

RIN/CIN = 50Ω/47pF

fS = 5Msps

VDD = 3V

TEMPERATURE (°C)

–55 –35

SNR, SINAD (dBFS)

–15 5 25 45 65 85 105 125

231512 G07

SNR

SINAD

VDD = 5V

VDD = 3V

TEMPERATURE (°C)

–55 –35

–100

–95

THD, HARMONICS (dB)

–90

–85

–80

–75

–15 5 25 45 65 85 105 125

231512 G08

THD

3RD

2ND

VDD = 3V

OUTPUT CODE

–1.0

–0.8

–0.6

–0.4

INL (LSB)

–0.2

0.4

0.2

0.0

0.6

0.8

1.0

1024 2048 3072 4096

231512 G01

INPUT FREQUENCY (kHz)

–100

–95

THD, HARMONICS (dB)

–90

–85

–80

–75

500 1000 1500 2000 2500

231512 G06a

THD

2ND

3RD

RIN/CIN = 50Ω/47pF

fS = 5Msps

VDD = 5V

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current vs Temperature

Shutdown Current vs Temperature Supply Current vs SCK Frequency

Reference Current

vs Reference Voltage

Full-Scale Error vs Temperature Offset Error vs Temperature

SNR, SINAD vs Reference Voltage

fIN = 500kHz

THD, Harmonics vs Temperature,

fIN = 500kHz

TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps,

unless otherwise noted.

REFERENCE VOLTAGE (V)

SNR, SINAD (dBFS)

2.5 3 3.5 4 4.5

231512 G10

SNR

SINAD

VDD = 3.6V

OPERATION

NOT ALLOWED

VDD = 5V

REFERENCE VOLTAGE (V)

REFERENCE CURRENT (µA)

200

100

300

400

500

600

2.5 3 3.5 4 4.5

231512 G11

VDD = 3.6V

fS = 5Msps

fS = 3Msps

OPERATION

NOT ALLOWED

VDD = 5V

TEMPERATURE (°C)

–55

–4

FULL-SCALE ERROR (LSB)

–1

–3

–2

–35 –15 5 4525 8565 105 125

231512 G12

TEMPERATURE (°C)

–55

–1

OFFSET ERROR (LSB)

–0.5

0.5

–35 –15 5 4525 8565 105 125

231512 G13

TEMPERATURE (°C)

–55

SUPPLY CURRENT (mA)

5.75

5.5

5.25

6.5

6.25

–35 –15 5 4525 8565 105 125

231512 G14

VDD = 5V

VDD = 3V

TEMPERATURE (°C)

–55

SHUTDOWN CURRENT (µA)

0.25

0.5

0.75

–35 –15 5 4525 8565 105 125

231512 G15

VDD = 5V

VDD = 3V

IVDD + IOVDD

SCK FREQUENCY (MHz)

SUPPLY CURRENT (mA)

20 30 5040 7060 80 90

231512 G16

ITOT

IVDD

VDD = 3V

OVDD = 1.8V

IOVDD

TEMPERATURE (°C)

–55 –35

–100

–95

THD, HARMONICS (dB)

–90

–85

–80

–75

–15 5 25 45 65 85 105 125

231512 G08a

THD

3RD

2ND

VDD = 5V

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps,

unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

PIN FUNCTIONS

VDD (Pin 1): Power Supply. The ranges of VDD are 2.7V

to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a

2.2µF ceramic chip capacitor.

REF (Pin 2): Reference Input/Output. The REF pin volt-

age defines the input span of the ADC, 0V to VREF. By

default, REF is an output pin and produces a reference

voltage VREF of either 2.048V or 4.096V depending on

VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR,

high quality ceramic chip capacitor. The REF pin may be

overdriven with a voltage at least 50mV higher than the

internal reference voltage output.

GND (Pin 3): Ground. The GND pin must be tied directly

to a solid ground plane.

AIN (Pin 4): Analog Input. AIN is a single-ended input with

respect to GND with a range from 0V to VREF.

OVDD (Pin 5): I/O Interface Digital Power. The OVDD range

is 1.71V to 5.25V. This supply is nominally set to the

same supply as the host interface (1.8V, 2.5V, 3.3V or

5V). Bypass to GND with a 2.2µF ceramic chip capacitor.

SDO (Pin 6): Serial Data Output. The A/D conversion result

is shifted out on SDO as a serial data stream with the MSB

first through the LSB last. There is 1 cycle of conversion

latency. Logic levels are determined by OVDD.

SCK (Pin 7): Serial Data Clock Input. The SCK serial clock

falling edge advances the conversion process and outputs

a bit of the serialized conversion result, MSB first to LSB

last. SDO data transitions on the falling edge of SCK. A

continuous or burst clock may be used. Logic levels are

determined by OVDD.

CS (Pin 8): Chip Select Input. This active low signal starts

a conversion on the falling edge and frames the serial data

transfer. Bringing CS high places the sample-and-hold

into sample mode and also forces the SDO pin into high

impedance. Logic levels are determined by OVDD.

Output Supply Current (IOVDD)

vs Output Supply Voltage (OVDD)

OUTPUT SUPPLY VOLTAGE (V)

1.7

OUTPUT SUPPLY CURRENT (mA)

0.5

1.0

2.5

2.0

1.5

2.92.3 4.13.5 4.7 5.3

231512 G18

5Msps

fSCK = 87.5MHz

3Msps

fSCK = 52.5MHz

Supply Current (IVDD)

vs Supply Voltage (VDD)

SUPPLY VOLTAGE (V)

2.6

4.50

SUPPLY CURRENT (mA)

5.25

5.00

4.75

5.50

5.75

6.00

6.50

6.25

2.9 3.83.53.2 4.1 4.74.4 5.35.0

231512 G17

5Msps

fSCK = 87.5MHz

3Msps

fSCK = 52.5MHz

OPERATION

NOT ALLOWED

5Msps

3Msps

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

TIMING DIAGRAMS

231512 TD04231512 TD03

231512 TD02231512 TD01

Hi-Z

SCK OVDD/2

SDO

16TH EDGE

Hi-Z

CS OVDD/2

SDO

VOH

VOL

SCK OVDD/2

SDO

VOH

VOL

SCK OVDD/2

SDO

Figure 1. SDO Into Hi-Z after 16TH SCK↓

Figure 3. SDO Data Valid Hold after SCK↓

Figure 2. SDO Into Hi-Z after CS↑

Figure 4. SDO Data Valid Access after SCK↓

tTHROUGHPUT

tACQ-MIN

tACQ-MIN = 40ns

tCONV

tCONV = 13.5 • tSCK + t2 + t10

1413124321

SCK

SDO HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B0 0B9B10B11*0

231512 TD05

t4t7t9

t10

Figure 5: LTC2315-12 Serial Interface Timing Diagram (SCK Low During tACQ)

BLOCK DIAGRAM

231512 BD

–

S/H

2.5V LDO

2×/4×1.024V

BANDGAP

TIMING

LOGIC

THREE-STATE

SERIAL

OUTPUT

PORT

12-BIT SAR ADC

AIN

REF

VDD OVDD

2.2µF GND

ANALOG

INPUT RANGE

0V TO VREF

ANALOG SUPPLY

RANGE 2.7V TO 5.25V

DIGITAL SUPPLY

RANGE 1.71V TO 5.25V

2.2µF2.2µF

SDO

SCK

TS8 PACKAGE

ALL CAPACITORS UNLESS

NOTED ARE HIGH QUALITY,

CERAMIC CHIP TYPE

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

tTHROUGHPUT

tACQ-MIN

tACQ-MIN = 40ns

tCONV

tCONV(MIN) = 13 • tSCK + t2 + t10

141354321

SCK

SDO HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B0 0B1B9B10B11*00

231512 TD06

t4t7

t10

Figure 6: LTC2315-12 Serial Interface Timing Diagram (SCK High During tACQ)

tTHROUGHPUT = 18 • tSCK

tACQ

tACQ = 4 • tSCK

tCONV

tCONV = 14 • tSCK

13 14 15 16 17 1818 4 5321

SCK

SDO HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B1 B0 0B9B10B11*00

231512 TD07

t4t7

t10

Figure 7: LTC2315-12 Serial Interface Timing Diagram (SCK Continuous)

TIMING DIAGRAMS

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

APPLICATIONS INFORMATION

Overview

The LT C

2315-12 is a low noise, high speed, 12-bit succes-

sive approximation register (SAR) ADC. The LTC2315-12

operates over a wide supply range (2.7V to 5.25V) and

provides a low drift (20ppm/°C maximum), internal refer-

ence and reference buffer. The internal reference buffer is

automatically configured to a 2.048V span in low supply

range (2.7V to 3.6V) and to a 4.096V span in the high

supply range (4.75V to 5.25V). The LTC2315-12 samples

at a 5Msps rate and supports an 87.5MHz data clock. The

LTC2315-12 achieves excellent dynamic performance

(73dB SNR, 84dB THD) while dissipating only 32mW from

a 5V supply at the 5Msps conversion rate.

The LTC2315-12 outputs the conversion data with one

cycle of conversion latency on the SDO pin. The SDO pin

output logic levels are supplied by the dedicated OVDD

supply pin which has a wide supply range (1.71V to 5.25V)

allowing the LTC2315-12 to communicate with 1.8V, 2.5V,

3V or 5V systems.

The LTC2315-12 provides both nap and sleep power-down

modes through serial interface control to reduce power

dissipation during inactive periods.

Serial Interface

The LT2315-12 communicates with microcontrollers, DSPs

and other external circuitry via a 3-wire interface. A falling

CS edge starts a conversion and frames the serial data

transfer. SCK provides the conversion clock for the current

sample and controls the data readout on the SDO pin of

the previous sample. CS transitioning low clocks out the

first leading zero and subsequent SCK falling edges clock

out the remaining data as shown in Figures 5, 6 and 7 for

three different timing schemes. Data is serially output MSB

first through LSB last, followed by trailing zeros if further

SCK falling edges are applied. Figure 5 illustrates that dur-

ing the case where SCK is held low during the acquisition

phase, only one leading zero is output. Figures 6 and 7

illustrate that for the SCK held high during acquisition or

continuous clocking mode two leading zeros are output.

Leading zeros allow the 12-bit data result to be framed

with both leading and trailing zeros for timing and data

verification. Since the rising edge of SCK will be coincident

with the falling edge of CS, delay t2 is the delay to the first

falling edge of SCK, which is simply 0.5 • tSCK. Delays t2

(CS falling edge to SCK leading edge) and t10 (14th falling

SCK edge to CS rising edge) must be observed for Figures

5, 6 and 7 and any timing implementation in order for the

conversion process and data readout to occur correctly.

The user can bring CS high after the 14th falling SCK edge

provided that timing delay t10 is observed. Prematurely

terminating the conversion by bringing CS high before

the 14th falling SCK edge plus delay t10 will cause a loss

of conversion data for that sample. The sample-and-hold

is placed in sample mode when CS is brought high. As

shown in Figure 6, a sample rate of 5Msps can be achieved

on the LTC2315-12 by using an 87.5MHz SCK data clock

and a minimum acquisition time of 40ns which results in

the minimum throughput time (tTHROUGHPUT) of 200ns.

Note that the maximum throughput of 5Msps can only be

achieved with the timing implementation of SCK held high

during acquisition as shown in Figure 6.

The LTC2315-12 also supports a continuous data clock

as shown in Figure 7. With a continuous data clock the

acquisition time period and conversion time period must

be designed as an exact integer number of data clock

periods. Because the minimum acquisition time is not an

exact multiple of the minimum SCK period, the maximum

sample rate for the continuous SCK timing is less than

5Msps. For example, a 4.86Msps throughput is achieved

using exactly 18 data clock periods with the maximum data

clock frequency of 87.5MHz. For this particular case, the

acquisition time period and conversion clock period are

designed as 4 data clock periods (TACQ = 45.7ns) and 14

data clock periods (TCONV = 160ns) respectively, yielding

a throughput time of 205.7ns.

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

APPLICATIONS INFORMATION

The following table illustrates the maximum throughput

achievable for each of the three timing patterns. Note

that in order to achieve the maximum throughput rate of

5Msps, the timing pattern where SCK is held high during

the acquisition time must be used.

Table 1: Maximum Throughput vs Timing Pattern

TIMING PATTERN MAXIMUM

THROUGHPUT

SCK high during TACQ 5Msps

SCK low during TACQ 4.86Msps

SCK continuous (tTHROUGHPUT = 18 periods) 4.86Msps

Serial Data Output (SDO)

The SDO output is always forced into the high impedance

state while CS is high. The falling edge of CS starts the

conversion and enables SDO. The A/D conversion result

is shifted out on the SDO pin as a serial data stream with

the MSB first. The data stream consists of either one

leading zero (SCK held low during acquisition, Fig. 5) or

two leading zeros (SCK held high during acquisition, Fig.

6) followed by 12 bits of conversion data. There is 1 cycle

of conversion latency. Subsequent falling SCK edges after

the LSB is output will output zeros on the SDO pin. The

SDO output returns to the high impedance state after the

16th falling edge of SCK.

The output swing on the SDO pin is controlled by the

OVDD pin voltage and supports a wide operating range

from 1.71V to 5.25V independent of the VDD pin voltage.

Power Considerations

The LTC2315-12 provides two sets of power supply pins:

the analog 5V power supply (VDD) and the digital input/

output interface power supply (OVDD). The flexible OVDD

supply allows the LTC2315-12 to communicate with any

digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

Entering Nap/Sleep Mode

Pulsing CS two times and holding SCK static places the

LTC2315-12 into nap mode. Pulsing CS four times and

holding SCK static places the LTC2315-12 into sleep

mode. In sleep mode, all bias circuitry is shut down,

including the internal bandgap and reference buffer, and

only leakage currents remain (0.8µA typical). Because

the reference buffer is externally bypassed with a large

capacitor (2.2µF), the LTC2315-12 requires a significant

wait time (1.1ms) to recharge this capacitance before an

accurate conversion can be made. In contrast, nap mode

does not power down the internal bandgap or reference

buffer allowing for a fast wake-up and accurate conversion

within one conversion clock cycle. Supply current during

nap mode is nominally 1.8mA.

Exiting Nap/Sleep Mode

Waking up the LTC2315-12 from either nap or sleep mode,

as shown in Figures 8 and 9, requires SCK to be pulsed

one time. A conversion may be started immediately fol-

lowing nap mode as shown in Figure 8. A period of time

allowing the reference voltage to recover must follow

waking up from sleep mode as shown in Figure 9. The

wait period required before initiating a conversion for the

recommended value of CREF of 2.2µF is 1.1ms.

Power Supply Sequencing

The LTC2315-12 does not have any specific power sup-

ply sequencing requirements. Care should be taken to

observe the maximum voltage relationships described in

the Absolute Maximum Ratings section.

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

Figure 8: LTC2315-12 Entering/Exiting Nap Mode

Figure 9: LTC2315-12 Entering/Exiting Sleep Mode

SCK

1 2

SDO HI-Z STATE

231512 F08

NAP MODE

HOLD STATIC HIGH or LOW HOLD STATIC HIGH or LOW

START tACQ

0 0

SCK

1 2

Z Z

3 4

SDO HI-Z STATE

231512 F09

NAP MODE SLEEP MODE

HOLD STATIC HIGH or LOW

START tACQ

VREF RECOVERY

0 0

tWAIT

APPLICATIONS INFORMATION

Single-Ended Analog Input Drive

The analog input of the LTC2315-12 is easy to drive. The

input draws only one small current spike while charging

the sample-and-hold capacitor at the end of conversion.

During the conversion, the analog input draws only a small

leakage current. If the source impedance of the driving

circuit is low, then the input of the LTC2315-12 can be

driven directly. As the source impedance increases, so

will the acquisition time. For minimum acquisition time

with high source impedance, a buffer amplifier should be

used. The main requirement is that the amplifier driving

the analog input must settle after the small current spike

before the next conversion starts. Settling time must be less

than tACQ-MIN (40ns) for full performance at the maximum

throughput rate. While choosing an input amplifier, also

keep in mind the amount of noise and harmonic distortion

the amplifier contributes.

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<50Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain

of 1 and has a unity-gain bandwidth of 100MHz, then the

output impedance at 100MHz must be less than 50Ω. The

second requirement is that the closed-loop bandwidth

must be greater than 100MHz to ensure adequate small

signal settling for full throughput rate. If slower op amps

are used, more time for settling can be provided by in-

creasing the time between conversions. The best choice

for an op amp to drive the LTC2315-12 will depend on the

application. Generally, applications fall into two categories:

AC applications where dynamic specifications are most

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

APPLICATIONS INFORMATION

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is a

summary of the op amps that are suitable for driving the

LTC2315-12. (More detailed information is available on

the Linear Technology website at www.linear.com.)

LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/

Amplifier, 1.1nV/√Hz.

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz, Unity-

Gain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/√Hz.

LT1818/LT1819: 400MHz GBWP, –85dBc Distortion at

5MHz, Unity-Gain Stable, 9mA/Amplifier, Single/Dual

Voltage Mode Operational Amplifier.

Input Drive Circuits

The analog input of the LTC2315-12 is designed to be driven

single-ended with respect to GND. A low impedance source

can directly drive the high impedance analog input of the

LTC2315-12 without gain error. A high impedance source

should be buffered to minimize settling time during acquisi-

tion and to optimize the distortion performance of the ADC.

For best performance, a buffer amplifier should be used

to drive the analog input of the LTC2315-12. The amplifier

provides low output impedance to allow for fast settling

of the analog signal during the acquisition phase. It also

provides isolation between the signal source and the ADC

inputs which draw a small current spike during acquisition.

Input Filtering

The noise and distortion of the buffer amplifier and other

circuitry must be considered since they add to the ADC

noise and distortion. Noisy input circuitry should be filtered

prior to the analog inputs to minimize noise. A simple

1-pole RC filter is sufficient for many applications.

Large filter RC time constants slow down the settling at

the analog inputs. It is important that the overall RC time

constants be short enough to allow the analog inputs to

completely settle to >12-bit resolution within the minimum

acquisition time (tACQ-MIN) of 40ns.

A simple 1-pole RC filter is sufficient for many applica-

tions. For example, Figure 10 shows a recommended

single-ended buffered drive circuit using the LT1818 in

unity gain mode. The 47pF capacitor from AIN to ground

and 50Ω source resistor limits the input bandwidth to

68MHz. The 47pF capacitor also acts as a charge reservoir

for the input sample-and-hold and isolates the LT1818

from sampling glitch kick-back. The 50Ω source resistor

is used to help stabilize the settling response of the drive

amplifier. When choosing values of source resistance

and shunt capacitance, the drive amplifier data sheet

should be consulted and followed for optimum settling

response. If lower input bandwidths are desired, care

should be taken to optimize the settling response of the

driver amplifier with higher values of shunt capacitance

or series resistance. High quality capacitors and resistors

should be used in the RC filter since these components

can add distortion. NP0/C0G and silver mica type dielectric

capacitors have excellent linearity. Carbon surface mount

resistors can generate distortion from self heating and

from damage that may occur during soldering. Metal film

surface mount resistors are much less susceptible to both

problems. When high amplitude unwanted signals are close

in frequency to the desired signal frequency, a multiple

pole filter is required. High external source resistance,

combined with external shunt capacitance at Pin 4 and

13pF of input capacitance on the LTC2315-12 in sample

mode, will significantly reduce the internal 130MHz input

bandwidth and may increase the required acquisition time

beyond the minimum acquisition time (tACQ-MIN) of 40ns.

47pF

50Ω

2315112 F10

AIN

LTC2315-12

LT1818 GND

ANALOG IN +

–

Figure 10. RC Input Filter

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

Figure 11. LTC2315-12 Transfer Function

INPUT VOLTAGE (V)

OUTPUT CODE

231512 F11

111...111

111...110

000...000

000...001

FS – 1LSB0 1LSB

APPLICATIONS INFORMATION

ADC Reference

A low noise, low temperature drift reference is critical to

achieving the full data sheet performance of the ADC. The

LTC2315-12 provides an excellent internal reference with

a guaranteed 20ppm/°C maximum temperature coefficient.

For added flexibility, an external reference may also be used.

The high speed, low noise internal reference buffer is used

only in the internal reference configuration. The reference

buffer must be overdriven in the external reference con-

figuration with a voltage 50mV higher than the nominal

reference output voltage in the internal configuration.

Using the Internal Reference

The internal bandgap and reference buffer are active by

default when the LTC2315-12 is not in sleep mode. The

reference voltage at the REF pin scales automatically with

the supply voltage at the VDD pin. The scaling of the refer-

ence voltage with supply is shown in the following table.

Table 2: Reference Voltage vs Supply Range

SUPPLY VOLTAGE (VDD) REF VOLTAGE (VREF)

2.7V –> 3.6V 2.048V

4.75V –> 5.25V 4.096V

The reference voltage also determines the full-scale analog

input range of the LTC2315-12. For example, a 2.048V

reference voltage will accommodate an analog input range

from 0V to 2.048V. An analog input voltage that goes below

0V will be coded as all zeros and an analog input voltage

that exceeds 2.048V will be coded as all ones.

It is recommended that the REF pin be bypassed to ground

with a low ESR, 2.2µF ceramic chip capacitor for optimum

performance.

External Reference

An external reference can be used with the LTC2315-12

if better performance is required or to accommodate a

larger input voltage span. The only constraints are that

the external reference voltage must be 50mV higher than

the internal reference voltage (see Table 2) and must be

less than or equal to the supply voltage (or 4.3V for the 5V

supply range). For example, a 3.3V external reference may

be used with a 3.3V VDD supply voltage to provide a 3.3V

analog input voltage span (i.e. 3.3V > 2.048V + 50mV).

Or alternatively, a 2.5V reference may be used with a 3V

supply voltage to provide a 2.5V input voltage range (i.e.

2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5,

available from Linear Technology, may be suitable for

many applications requiring a high performance external

reference for either 3.3V or 2.5V input spans respectively.

Transfer Function

Figure 11 depicts the transfer function of the LTC2315-12.

The code transitions occur midway between successive

integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB… FS-

0.5LSB). The output code is straight binary with 1LSB =

VREF/4,096.

DC Performance

The noise of an ADC can be evaluated in two ways: signal-to-

noise ratio (SNR) in the frequency domain and histogram in

the time domain. The LTC2315-12 excels in both. The noise in

the time domain histogram is the transition noise associated

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

APPLICATIONS INFORMATION

with a 12-bit resolution ADC which can be measured with a

fixed DC signal applied to the input of the ADC. The resulting

output codes are collected over a large number of conversions.

The shape of the distribution of codes will give an indication

of the magnitude of the transition noise. In Figure 12, the

distribution of output codes is shown for a DC input that has

been digitized 16,384 times. The distribution is Gaussian and

the RMS code transition noise is 0.33LSB. This corresponds to

a noise level of 73dB relative to a full scale voltage of 4.096V.

Figure 12. Histogram for 16384 Conversions

CODE

2047

COUNTS

2049

231512 F12

2048 2050 2051

σ = 0.33

10000

20000

30000

40000

60000

50000

Dynamic Performance

The LTC2315-12 has excellent high speed sampling

capability. Fast Fourier Transform (FFT) techniques are

used to test the ADC’s frequency response, distortion and

noise at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined

for frequencies outside the applied fundamental. The

LTC2315-12 provides guaranteed tested limits for both

AC distortion and noise measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

to frequencies from above DC and below half the sampling

frequency. Figure 14 shows the LTC2315-12 maintains a

SINAD above 71dB up to the Nyquist input frequency of

2.5MHz.

Effective Number of Bits (ENOB)

The effective number of bits (ENOB) is a measurement of

the resolution of an ADC and is directly related to SINAD

by the equation where ENOB is the effective number of

bits of resolution and SINAD is expressed in dB:

ENOB = (SINAD – 1.76)/6.02

At the maximum sampling rate of 5MHz, the LTC2315-12

maintains an ENOB above 11.7 bits up to the Nyquist input

frequency of 2.5MHz. (Figure 14)

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 13 shows

that the LTC2315-12 achieves a typical SNR of 73dB at a

5MHz sampling rate with a 500kHz input frequency.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (THD) is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD=20log V22+V32+V42+VN

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the second

through Nth harmonics. THD versus Input Frequency is

shown in the Typical Performance Characteristics section.

The LTC2315-12 has excellent distortion performance up

to the Nyquist frequency.

Intermodulation Distortion (IMD)

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

Figure 13. 16k Point FFT of the LTC2315-12 at fIN = 500 kHz

Figure 14. LTC2315-12 ENOB/SINAD vs fIN

Figure 15. LTC2315-12 IMD Plot

231512 F13

FREQUENCY (kHz)

AMPLITUDE (dBFS)

0 25002000

1000500 1500

–20

–40

–60

–80

–100

–120

–140

VDD = 5V

SNR = 73.1dBFS

SINAD = 72.6dBFS

THD = –84dB

SFDR = 87dBc

INPUT FREQUENCY (kHz)

SINAD (dBFS)

ENOB

11.2

11.3

11.5

11.7

11.8

12.0

500 1000 1500 2000 2500

231512 F14

VDD = 5V

VDD = 3V

INPUT FREQUENCY (kHz)

–160

–120

–140

MAGNITUDE (dB)

–80

–100

–60

–40

–20

500 1000 1500 2000 2500

231512 F15

VDD = 5V

fS = 5Msps

fa = 461.421kHz

fb = 541.421kHz

IMD2 (fb + fa) = –77.4dBc

IMD3 (2fb –fa) = –89.4dBc

APPLICATIONS INFORMATION

If two pure sine waves of frequencies fa and fb are ap-

plied to the ADC input, nonlinearities in the ADC transfer

function can create distortion products at the sum and

difference frequencies m • fa ± n • fb , where m and n = 0,

1, 2, 3, etc. For example, the 2nd order IMD terms include

(fa ± fb). If the two input sine waves are equal in magnitude,

the value (in decibels) of the 2nd order IMD products can

be expressed by the following formula:

IMD(fa ± fb) = 20 • log[VA (fa ± fb)/VA (fa)]

The LTC2315-12 has excellent IMD as shown in Figure 15.

Spurious Free Dynamic Range (SFDR)

The spurious free dynamic range is the largest spectral

component excluding DC, the input signal and the harmon-

ics included in the THD. This value is expressed in decibels

relative to the RMS value of a full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is the input frequency at which

the amplitude of the reconstructed fundamental is reduced

by 3dB for a full-scale input signal.

The full-linear bandwidth is the input frequency at which

the SINAD has dropped to 68dB (11 effective bits). The

LTC2315-12 has been designed to optimize the input

bandwidth, allowing the ADC to under-sample input signals

with frequencies above the converter’s Nyquist frequency.

The noise floor stays very low at high frequencies and

SINAD becomes dominated by distortion at frequencies

beyond Nyquist.

Recommended Layout

To obtain the best performance from the LTC2315-12 a

printed circuit board is required. Layout for the printed

circuit board (PCB) should ensure the digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital clocks or

signals alongside analog signals or underneath the ADC.

The following is an example of a recommended PCB layout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

APPLICATIONS INFORMATION

Figure 16. Top Silkscreen

Figure 17. Layer 1 Top Layer

Figure 18. Layer 2 GND Plane

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1563, the

evaluation kit for the LTC2315-12.

Bypassing Considerations

High quality tantalum and ceramic bypass capacitors

should be used at the VDD, OVDD and REF pins. For opti-

mum performance, a 2.2µF ceramic chip capacitor should

be used for the VDD and OVDD pins. The recommended

bypassing for the REF pin is also a low ESR, 2.2µF ceramic

capacitor. The traces connecting the pins and the bypass

capacitors must be kept as short as possible and should

be made as wide as possible avoiding the use of vias.

The following is an example of a recommended PCB layout.

All analog circuitry grounds should be terminated at the

LTC2315-12. The ground return from the LTC2315-12 to

the power supply should be low impedance for noise free

operation. Digital circuitry grounds must be connected to

the digital supply common.

In applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feed-through from the

microprocessor to the successive approximation com-

parator. The problem can be eliminated by forcing the

microprocessor into a “Wait” state during conversion or

by using three-state buffers to isolate the ADC data bus.

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer

Figure 21. Partial DC1563 Demo Board Schematic

APPLICATIONS INFORMATION

9V TO 10V

LT1790ACS6-2.048

COUPLING

2 3

GND

VDD REF

CSL

SCK

CSL

SCK

SDO SDO

OVDD

VI VO VCM VDD VCCIO

10µF C9

4.7µF

C10

OPT

C11

OPT

C12

4.7µF

OPT

REF

4.7µF

C18

OPT

R18

31.024V

2.048V

HD1X3-100

C17

1µF JP2

VCM

R14

R15

49.9Ω

R16

33Ω

3231512 F21

1 2 5

C19

47pF

NPO

JP1

HD1X3-100

AIN

0V TO 4.096V AIN

GND

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3)

TS8 TSOT-23 0710 REV A

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.40

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 10/13 Added pin-compatible family table

Changed TJMAX to 150°C

Changed SINAD condition for –3dB Input Linear Bandwidth to ≥68dB

Reordered/Renumbered Notes

3, 16

3, 4, 5

LTC2315-12

231512fa

For more information www.linear.com/LTC2315-12

RELATED PARTS

TYPICAL APPLICATION

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

50Ω

0.1µF

VCC

NC7SVU04P5X

NL17SZ74

NC7SVUO4P5X

MASTER CLOCK

CONV ENABLE

PRE

CLR

CONV

SCK

SDO

LTC2315-12

33Ω 231512 TA03

Low-Jitter Clock Timing with RF Sine Generator Using Clock

Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC2313-12 12-Bit, 2.5Msps Serial ADC 3V/5V, 14mW/25mW, 20ppm/°C Max Internal Reference,

Single-Ended Input, 8-Lead TSOT-23 Package

LTC2312-12 12-Bit, 500ksps Serial ADC 3V/5V, 9mW/15mW, 20ppm/°C Max Internal Reference,

Single-Ended Input, 8-Lead TSOT-23 Package

LTC1403/LTC1403-1 12-Bit, 2.8Msps Serial ADC 3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package

LTC1407/LTC1407-1 12-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW,

MSOP Package

LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, Differential, Input, 18mW, MSOP Package

LTC2365/LTC2366 12-Bit, 1Msps/3Msps Serial Sampling ADC 3.3V Supply, 8mW, TSOT-23 Package

Amplifiers

LT6236/LT6237 Single/Dual Operation Amplifier with Low

Wideband Noise

215MHz, 3.5mA/Amplifier, 1.1nV/√Hz

LT6200/LT6201 Single/Dual Operational Amplifiers 165MHz, 0.95nV/√Hz

LT6230/LT6231 Single/Dual Operational Amplifiers 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz

LT1818/LT1819 Single/Dual Operational Amplifiers 400MHz, 9mA/Amplifier, 6nV/√Hz

References

LTC6655-2.5/LTC6655-3.3 Precision Low Drift Low Noise Buffered Reference 2.5V/3.3V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

LT1461-3/LT1461-3.3V Precision Series Voltage Family 0.05% Initial Accuracy, 3ppm Drift

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2315-12

 LINEAR TECHNOLOGY CORPORATION 2013

LT 1013 REV A • PRINTED IN USA