ATMEGA649V-8AU - MICROCHIP TECHNOLOGY

Features

•High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16MHz

– On-Chip 2-cycle Multiplier

•High Endurance Non-volatile Memory Segments

– In-System Self-programmable Flash Program Memory

• 32KBytes (ATmega329/ATmega3290)

• 64KBytes (ATmega649/ATmega6490)

– EEPROM

• 1Kbytes (ATmega329/ATmega3290)

• 2Kbytes (ATmega649/ATmega6490)

– Internal SRAM

• 2Kbytes (ATmega329/ATmega3290)

• 4Kbytes (ATmega649/ATmega6490)

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

•JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

– 4 x 25 Segment LCD Driver (ATmega329/ATmega649)

– 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490)

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

–Four PWM Channels

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

•I/O and Packages

– 53/68 Programmable I/O Lines

– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

•Speed Grade:

– ATmega329V/ATmega3290V/ATmega649V/ATmega6490V:

– 0 - 4MHz @ 1.8 - 5.5V, 0 - 8MHz @ 2.7 - 5.5V

– ATmega329/3290/649/6490:

– 0 - 8MHz @ 2.7 - 5.5V, 0 - 16MHz @ 4.5 - 5.5V

•Temperature range:

– -40°C to 85°C Industrial

•Ultra-Low Power Consumption

– Active Mode:

• 1MHz, 1.8V: 350µA

• 32kHz, 1.8V: 20µA (including Oscillator)

• 32kHz, 1.8V: 40µA (including Oscillator and LCD)

– Power-down Mode:

• 100nA at 1.8V

8-bit Atmel

Microcontroller

with In-System

Programmable

Flash

ATmega329/V

ATmega3290/V

ATmega649/V

ATmega6490/V

2552K–AVR–04/11

ATmega329/3290/649/6490

1. Pin Configurations

Figure 1-1. Pinout ATmega3290/6490

(OC2A/PCINT15) PB7

DNC

(T1/SEG33) PG3

(T0/SEG32) PG4

RESET/PG5

VCC

GND

(TOSC2) XTAL2

(TOSC1) XTAL1

DNC

(PCINT26/SEG31) PJ2

(PCINT27/SEG30) PJ3

(PCINT28/SEG29) PJ4

(PCINT29/SEG28) PJ5

(PCINT30/SEG27) PJ6

DNC

(ICP1/SEG26) PD0

(INT0/SEG25) PD1

(SEG24) PD2

(SEG23) PD3

(SEG22) PD4

(SEG21) PD5

(SEG20) PD6

(SEG19) PD7

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

PH7 (PCINT23/SEG36)

PH6 (PCINT22/SEG37)

PH5 (PCINT21/SEG38)

PH4 (PCINT20/SEG39)

DNC

GND

VCC

DNC

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

DNC

PH3 (PCINT19/SEG7)

PH2 (PCINT18/SEG8)

PH1 (PCINT17/SEG9)

PH0 (PCINT16/SEG10)

DNC

PC5 (SEG11)

PC4 (SEG12)

PC3 (SEG13)

PC2 (SEG14)

PC1 (SEG15)

PC0 (SEG16)

PG1 (SEG17)

PG0 (SEG18)

INDEX CORNER

ATmega3290/6490

100

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24/SEG35) PJ0

(PCINT25/SEG34) PJ1

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

2552K–AVR–04/11

ATmega329/3290/649/6490

Figure 1-2. Pinout ATmega329/649

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If

the center pad is left unconnected, the package might loosen from the board.

PC0 (SEG12)

VCC

GND

PF0 (ADC0)

PF7 (ADC7/TDI)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

AREF

GND

AVCC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

LCDCAP

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC2A/PCINT15) PB7

(T1/SEG24) PG3

(OC1B/PCINT14) PB6

(T0/SEG23) PG4

(OC1A/PCINT13) PB5

PC1 (SEG11)

PG0 (SEG14)

(SEG15) PD7

PC2 (SEG10)

PC3 (SEG9)

PC4 (SEG8)

PC5 (SEG7)

PC6 (SEG6)

PC7 (SEG5)

PA7 (SEG3)

PG2 (SEG4)

PA6 (SEG2)

PA5 (SEG1)

PA4 (SEG0)

PA3 (COM3)

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PG1 (SEG13)

(SEG16) PD6

(SEG17) PD5

(SEG18) PD4

(SEG19) PD3

(SEG20) PD2

(INT0/SEG21) PD1

(ICP1/SEG22) PD0

(TOSC1) XTAL1

(TOSC2) XTAL2

RESET/PG5

GND

VCC

INDEX CORNER

(SS/PCINT8) PB0

ATmega329/649

2552K–AVR–04/11

ATmega329/3290/649/6490

2. Overview

The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architec-

ture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs

approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATA REGISTER

PORTD

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI

USART

STATUS

ALU

PORTB DRIVERS

PORTE DRIVERS

PORTA DRIVERS

PORTF DRIVERS

PORTD DRIVERS

PORTC DRIVERS

PB0 - PB7PE0 - PE7

PA0 - PA7PF0 - PF7

VCCGND

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PC0 - PC7

8-BIT DATA BUS

RESET

CALIB. OSC

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORTF

DATA REGISTER

PORTF

ADC

PD0 - PD7

DATA DIR.

REG. PORTG

DATA REG.

PORTG

PORTG DRIVERS

PG0 - PG4

AGND

AREF

AVCC

UNIVERSAL

SERIAL INTERFACE

AVR CPU

LCD

CONTROLLER/

DRIVER

PORTH DRIVERS

PH0 - PH7

DATA DIR.

REG. PORTH

DATA REGISTER

PORTH

PORTJ DRIVERS

PJ0 - PJ6

DATA DIR.

REG. PORTJ

DATA REGISTER

PORTJ

2552K–AVR–04/11

ATmega329/3290/649/6490

The Atmel® AVR® core combines a rich instruction set with 32 general purpose working regis-

ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction executed in one clock cycle. The

resulting architecture is more code efficient while achieving throughputs up to ten times faster

than conventional CISC microcontrollers.

The Atmel ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-Sys-

tem Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte

SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface

for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD

controller with internal contrast control, three flexible Timer/Counters with compare modes, inter-

nal and external interrupts, a serial programmable USART, Universal Serial Interface with Start

Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal

Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to con-

tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator,

disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,

the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a

timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise

Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller

and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys-

tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast

start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip In-System re-Programmable (ISP) Flash allows the program memory to be repro-

grammed In-System through an SPI serial interface, by a conventional non-volatile memory

programmer, or by an On-chip Boot program running on the AVR core. The Boot program can

use any interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is updated,

providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System

Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a pow-

erful microcontroller that provides a highly flexible and cost effective solution to many embedded

control applications.

The Atmel ATmega329/3290/649/6490 is supported with a full suite of program and system

development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,

In-Circuit Emulators, and Evaluation kits.

2552K–AVR–04/11

ATmega329/3290/649/6490

2.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490

The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes,

pin count and pinout. Table 2-1 on page 6 summarizes the different configurations for the four

devices.

2.3 Pin Descriptions

The following section describes the I/O-pin special functions.

2.3.1 VCC

Digital supply voltage.

2.3.2 GND

Ground.

2.3.3 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATmega329/3290/649/6490

as listed on page 67.

2.3.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega329/3290/649/6490

as listed on page 68.

Table 2-1. Configuration Summary

Device Flash EEPROM RAM

LCD

Segments

General Purpose

I/O Pins

ATmega329 32Kbytes 1Kbytes 2Kbytes 4 x 25 54

ATmega3290 32Kbytes 1K bytes 2Kbytes 4 x 40 69

ATmega649 64Kbytes 2Kbytes 4Kbytes 4 x 25 54

ATmega6490 64Kbytes 2Kbytes 4Kbytes 4 x 40 69

2552K–AVR–04/11

ATmega329/3290/649/6490

2.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed

on page 71.

2.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega329/3290/649/6490

as listed on page 73.

2.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the ATmega329/3290/649/6490

as listed on page 75.

2.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2552K–AVR–04/11

ATmega329/3290/649/6490

2.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port G output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port G also serves the functions of various special features of the ATmega329/3290/649/6490

as listed on page 75.

2.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port H output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3290/6490 as listed

on page 75.

2.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port J output buffers have symmetrical drive characteristics with both high sink and source capa-

bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3290/6490 as listed on

page 75.

2.3.12 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in “System and Reset

Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset.

2.3.13 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.3.14 XTAL2

Output from the inverting Oscillator amplifier.

2.3.15 AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC

through a low-pass filter.

2.3.16 AREF

This is the analog reference pin for the A/D Converter.

2552K–AVR–04/11

ATmega329/3290/649/6490

2.3.17 LCDCAP

An external capacitor (typical > 470nF) must be connected to the LCDCAP pin as shown in Fig-

ure 23-2. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces

ripple on VLCD but increases the time until VLCD reaches its target value.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

2552K–AVR–04/11

ATmega329/3290/649/6490

6. AVR CPU Core

6.1 Overview

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

6.2 Architectural Overview

Figure 6-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

2552K–AVR–04/11

ATmega329/3290/649/6490

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash memory section must

reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

ATmega329/3290/649/6490 has Extended I/O space from 0x60 - 0xFF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

6.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

2552K–AVR–04/11

ATmega329/3290/649/6490

6.4 AVR Status Register

The Status Register contains information about the result of the most recently executed arithme-

tic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

6.4.1 SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

Bit 76543210

0x3F (0x5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

2552K–AVR–04/11

ATmega329/3290/649/6490

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

6.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

•One 8-bit output operand and one 8-bit result input

•Two 8-bit output operands and one 8-bit result input

•Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R280x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

2552K–AVR–04/11

ATmega329/3290/649/6490

6.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 6-3.

Figure 6-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

6.6 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

Bit 151413121110 9 8

0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

2552K–AVR–04/11

ATmega329/3290/649/6490

6.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 6-5. Single Cycle ALU Operation

6.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 293 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 49. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

2552K–AVR–04/11

ATmega329/3290/649/6490

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 49 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page

278.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

2552K–AVR–04/11

ATmega329/3290/649/6490

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

6.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

2552K–AVR–04/11

ATmega329/3290/649/6490

7. AVR ATmega329/3290/649/6490 Memories

This section describes the different memories in the ATmega329/3290/649/6490. The Atmel®

AVR® architecture has two main memory spaces, the Data Memory and the Program Memory

space. In addition, the ATmega329/3290/649/6490 features an EEPROM Memory for data stor-

age. All three memory spaces are linear.

7.1 In-System Reprogrammable Flash Program Memory

The ATmega329/3290/649/6490 contains 32/64Kbytes On-chip In-System Reprogrammable

Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash

is organized as 16/32K x 16. For software security, the Flash Program memory space is divided

into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega329/3290/649/6490 Program Counter (PC) is 14/15 bits wide, thus addressing the

16/32K program memory locations. The operation of Boot Program section and associated Boot

Lock bits for software protection are described in detail in “Boot Loader Support – Read-While-

Write Self-Programming” on page 278. “Memory Programming” on page 293 contains a detailed

description on Flash data serial downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 15.

Figure 7-1. Program Memory Map

0x0000

0x3FFF/0x7FFF

Program Memory

Application Flash Section

Boot Flash Section

2552K–AVR–04/11

ATmega329/3290/649/6490

7.2 SRAM Data Memory

Figure 7-2 shows how the ATmega329/3290/649/6490 SRAM Memory is organized.

The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than

can be supported within the 64 locations reserved in the Opcode for the IN and OUT instruc-

tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

The lower 2304/4352 data memory locations address both the Register File, the I/O memory,

Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register

File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,

and the next 2048/4096 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 2,048 bytes of internal data SRAM in the ATmega329/3290/649/6490 are all accessible

through all these addressing modes. The Register File is described in “General Purpose Regis-

ter File” on page 13.

Figure 7-2. Data Memory Map

7.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clkCPU cycles as described in Figure 7-3.

32 Registers

64 I/O Registers

Internal SRAM

(2048 x 8)/

(4096 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x08FF/0x10FF

0x0060 - 0x00F

Data Memory

160 Ext I/O Reg.

0x0100

2552K–AVR–04/11

ATmega329/3290/649/6490

Figure 7-3. On-chip Data SRAM Access Cycles

7.3 EEPROM Data Memory

The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory. It is organized

as a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 308, page 313, and page 296 respectively.

7.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-1. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 21. for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

7.3.2 EEPROM Write During Power-down Sleep Mode

When entering Power-down sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the Write Access time has

passed. However, when the write operation is completed, the clock continues running, and as a

clk

Data

Address Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

2552K–AVR–04/11

ATmega329/3290/649/6490

consequence, the device does not enter Power-down entirely. It is therefore recommended to

verify that the EEPROM write operation is completed before entering Power-down.

7.3.3 Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low VCC reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

7.4 I/O Memory

The I/O space definition of the ATmega329/3290/649/6490 is shown in “Register Summary” on

page 365.

All ATmega329/3290/649/6490 I/Os and peripherals are placed in the I/O space. All I/O loca-

tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

Refer to the instruction set section for more details. When using the I/O specific commands IN

and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data

space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be

supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.4.1 General Purpose I/O Registers

The ATmega329/3290/649/6490 contains three General Purpose I/O Registers. These registers

can be used for storing any information, and they are particularly useful for storing global vari-

ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F

are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

2552K–AVR–04/11

ATmega329/3290/649/6490

7.5 Register Description

7.5.1 EEARH and EEARL – The EEPROM Address Register

• Bits 15:11 – Reserved Bits

These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.

• Bits 10:0 – EEAR10:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

1/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

1023/2047. The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

Note: EEAR10 is only valid for ATmega649 and ATmega6490.

7.5.2 EEDR – The EEPROM Data Register

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.5.3 EECR – The EEPROM Control Register

• Bits 7:4 – Reserved Bits

These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

Bit 151413121110 9 8

0x22 (0x42) – – – – – EEAR10 EEAR9 EEAR8 EEARH

0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRR/WR/WR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 X X X

XXXXXXXX

Bit 76543210

0x20 (0x40) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1F (0x3F) ––––EERIEEEMWEEEWEEEREEECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value000000X0

2552K–AVR–04/11

ATmega329/3290/649/6490

the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-Programming” on page 278 for details about Boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-1 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 7-1. EEPROM Programming Time

Symbol

Number of Calibrated

RC Oscillator Cycles Typical Programming Time

EEPROM write (from CPU) 27,072 3.4ms

2552K–AVR–04/11

ATmega329/3290/649/6490

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glob-

ally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

2552K–AVR–04/11

ATmega329/3290/649/6490

7.5.4 GPIOR2 – General Purpose I/O Register 2

7.5.5 GPIOR1 – General Purpose I/O Register 1

7.5.6 GPIOR0 – General Purpose I/O Register 0

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

Bit 76543210

0x2B (0x4B) MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x2A (0x4A) MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1E (0x3E) MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

2552K–AVR–04/11

ATmega329/3290/649/6490

8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 35. The clock systems are detailed below.

Figure 8-1. Clock Distribution

8.1.1 CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

8.1.2 I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also note that start condition detection in the USI module is carried out asynchro-

nously when clkI/O is halted, enabling USI start condition detection in all sleep modes.

8.1.3 Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

General I/O

Modules

Asynchronous

Timer/Counter CPU Core RAM

clk

I/O

clk

ASY

AVR Clock

Control Unit

clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Timer/Counter

Oscillator

Crystal

Oscillator

Low-frequency

Crystal Oscillator

External Clock

LCD Controller

2552K–AVR–04/11

ATmega329/3290/649/6490

8.1.4 Asynchronous Timer Clock – clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller

to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated

clock domain allows using this Timer/Counter as a real-time counter even when the device is in

sleep mode. It also allows the LCD controller output to continue while the rest of the device is in

sleep mode.

ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

8.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before com-

mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the

start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 8-

2. The frequency of the Watchdog Oscillator is voltage dependent as shown in “Typical Charac-

teristics” on page 335.

8.2.1 Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is the Internal RC Oscillator with longest start-up time and an initial system

clock prescaling of 8. This default setting ensures that all users can make their desired clock

source setting using an In-System or Parallel programmer.

Table 8-1. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000

External Low-frequency Crystal 0111 - 0110

Calibrated Internal RC Oscillator 0010

External Clock 0000

Reserved 0011, 0001, 0101, 0100

Table 8-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1ms 4.3ms 4K (4,096)

65ms 69ms 64K (65,536)

2552K–AVR–04/11

ATmega329/3290/649/6490

8.3 Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a

ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 8-3. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

Figure 8-2. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3.

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

8-4.

Table 8-3. Crystal Oscillator Operating Modes

CKSEL3..1

Frequency Range

(MHz)

Recommended Range for Capacitors C1

and C2 for Use with Crystals (pF)

100(1) 0.4 - 0.9 –

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

Table 8-4. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1..0

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V)

Recommended

Usage

000 258 CK(1) 14CK + 4.1ms Ceramic resonator,

fast rising power

001 258 CK(1) 14CK + 65ms Ceramic resonator,

slowly rising power

010 1K CK

(2) 14CK Ceramic resonator,

BOD enabled

XTAL2

XTAL1

GND

2552K–AVR–04/11

ATmega329/3290/649/6490

Note: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

8.4 Low-frequency Crystal Oscillator

To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal

Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111”. The crystal should

be connected as shown in Figure 8-2. When this Oscillator is selected, start-up times are deter-

mined by the SUT Fuses as shown in Table 8-5 and CKSEL1..0 as shown in Table 8-6.

Note: 1. This option should only be used if frequency stability at start-up is not important for the

application

8.5 Calibrated Internal RC Oscillator

The calibrated Internal RC Oscillator by default provides a 8.0MHz clock. The frequency is nom-

inal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See

“System Clock Prescaler” on page 32 for more details.

011 1K CK

(2) 14CK + 4.1ms Ceramic resonator,

fast rising power

100 1K CK

(2) 14CK + 65ms Ceramic resonator,

slowly rising power

101 16K CK 14CK Crystal Oscillator,

BOD enabled

110 16K CK 14CK + 4.1ms Crystal Oscillator, fast

rising power

111 16K CK 14CK + 65ms Crystal Oscillator,

slowly rising power

Table 8-4. Start-up Times for the Crystal Oscillator Clock Selection (Continued)

CKSEL0 SUT1..0

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V)

Recommended

Usage

Table 8-5. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 14CK Fast rising power or BOD enabled

01 14CK + 4.1ms Slowly rising power

10 14CK + 65ms Stable frequency at start-up

11 Reserved

Table 8-6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL3..0

Start-up Time from

Power-down and Power-save Recommended Usage

0110(1) 1K CK

0111 32K CK Stable frequency at start-up

2552K–AVR–04/11

ATmega329/3290/649/6490

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 8-7 on page 30. If selected, it will operate with no external components. During reset,

hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby

automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory

calibration in Table 28-2 on page 329.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 32, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 28-2 on page 329.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section “Calibration Byte” on page 296.

Note: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values.

3. If 8MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-8 on page 30.

Note: 1. The device is shipped with this option selected.

Table 8-7. Internal Calibrated RC Oscillator Operating Modes(1)(3)

Frequency Range(2) (MHz) CKSEL3..0

7.3 - 8.1 0010

Table 8-8. Start-up times for the internal calibrated RC Oscillator clock selection

Power Conditions

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

BOD enabled 6 CK 14CK 00

Fast rising power 6 CK 14CK + 4.1ms 01

Slowly rising power 6 CK 14CK + 65ms(1) 10

Reserved 11

2552K–AVR–04/11

ATmega329/3290/649/6490

8.6 External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

8-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Figure 8-3. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-10.

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

32 for details.

8.7 Clock Output Buffer

When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is

suitable when the chip clock is used to drive other circuits on the system. The clock will be out-

put also during reset and the normal operation of I/O pin will be overridden when the fuse is

programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO

Table 8-9. Crystal Oscillator Clock Frequency

CKSEL3..0 Frequency Range

0000 0 - 16MHz

Table 8-10. Start-up Times for the External Clock Selection

SUT1..0

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4.1ms Fast rising power

10 6 CK 14CK + 65ms Slowly rising power

11 Reserved

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND