Description
BR93H -W series is a serial EEPROM of serial 3-line interface method.
Features
. Withstands electrostatic voltage 8kV, (twice more than other series) (HBM method typ.)
. Wide action range
-
40 ˚C ~ +125 ˚C
(
-
40˚C ~ +85˚C,
-
40˚C ~ +105˚C in other series)
• Conforming to Microwire BUS
. Highly reliable connection by Au pad and Au wire
• Address auto increment function at read action
• Write mistake prevention function
Write prohibition at power on
Write prohibition by command code
Write mistake prevention circuit at low voltage
. Program cycle auto delete and auto end function
. Program condition display by READY / BUSY
. Low current consumption
At write action (5V) : 0.6mA (Typ.)
At read action (5V) : 0.6mA (Typ.)
At standby action (5V) : 0.1µA (Typ.)
. Built-in noise filter CS, SK, DI terminals
. Compact package SOP8, SOP-J8
. High reliability by ROHM original Double-Cell structure
. High reliability ultrafine CMOS process
. Data rewrite up to 1,000,000 times
. Data kept for 40 years• Easily connectable with serial port BR93H series
. Data at shipment all addresses FFFFh
Capacity Bit format
Package type
Type
Power source voltage
SOP8
FRFFJRFJ FV RFV FVT RFVT RFVM RFVJ
SOP-J8
●
●
●
●
●
●
●
●
SSOP-B8 MSOP8TSSOP-B8
TSSOP-B8J
2.7V ~ 5.5V
2.7V ~ 5.5V
2.7V ~ 5.5V
2.7V ~ 5.5V
BR93H66-W
BR93H56-W
BR93H86-W
BR93H76-W
128 × 16
256 × 16
512 × 16
1K × 16
2Kbit
4Kbit
8Kbit
16Kbit
Ver.B Oct. 2005
TECHNICAL NOTE
BR93H56-W, BR93H66-W, BR93H76-W, BR93H86-W
Microwire
BUS
Serial
EEPROMs
HIGH GRADE Specification HIGH RELIABILITY series
Supply voltage 2.7V~5.5V
Operating temperature –40°C~+125°C type
Absolute Maximum Ratings (Ta=25˚C)
Electrical characteristics (Unless otherwise specified, Ta = -40 ~ +125˚C, Vcc = 2.7V ~ 5.5V)
This IC is not designed to be radiation-resistant.
Parameter Symbol Limits Unit
-0.3 ~ +6.5 V
mW
-65 ~ +150 ˚C
˚C
-V
-40 ~ +125
VCC
-0.3 ~ VCC+0.3
Pd
Tstg
Topr
SOP8 (RF) 450 (*1)
450 (*2)
SOP-J8 (RFJ)
Impressed voltage
Permissible dissipation
Storage temperature range
Action temperature range
Terminal voltage
* When using at Ta = 25˚C or higher, 3.6mW (*1, *2) to be reduced per 1˚C.
Recommended operating conditions
Parameter Symbol Limits Unit
V
VIN V
VCC
0 ~ VCC
2.7 ~ 5.5
Power source voltage
Input voltage
Item
Symbol
Unit
Measurement
circuit
Conditions
Limits
Typ.Min.
-0.3
0.7×
Vcc
0.3×
Vcc
Vcc
+0.3
Vcc
-0.2
0 0.4
0.2
Vcc
Vcc
10
10
3.0
1.5
4.5
10
0
2.4
-10
-10
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.1–
Max.
VIL
VIH
VOL1
VOL2
VOH1
VOH2
ILI
ILO
ICC1
ICC2
ICC3
ISB
V
V
V
V
V
V
µA
µA
mA
mA
mA
µA
Fig. 4
Fig. 4
Fig. 5
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 8
Fig. 8
Fig. 9
IOL=2.1mA,4.0 Vcc 5.5V
IOL=100µA
IOH=
-
0.4mA,4.0 Vcc 5.5V
IOH=
-
100µA
VIN=0 ~ Vcc
VOUT=0 ~ Vcc,CS=0V
fSK=1.25MHz,tE/W=10ms (WRITE)
fSK=1.25MHz (READ)
fSK=1.25MHz,tE/W=10ms (WRAL)
CS=0V,DO=OPEN
"L" input voltage
"H" input voltage
"L" output voltage 1
"L" output voltage 2
"H" output voltage 1
"H" output voltage 2
Input leak current
Output leak current
Current consumption
at operation
Standby current
2/16
Sync data input / output timing
Fig.1 Sync data input / output timing diagram
CS
SK
DI
DO (READ)
DO (WRITE) STATUS VALID
tDF
tPD1tPD0
tDIHtDIS
tCSS tCSH
tSKH tSKL
Operation timing characteristics (Ta=-40˚C ~ +125˚C, Vcc=2.7V ~ 5.5V)
Memory cell characteristics (Vcc=2.7V ~ 5.5V)
Item Symbol
Unit
Max.
–
–
–
–
–
Times
Times
Times
Years
Years
Ta 85˚C
Ta 105˚C
Ta 125˚C
Ta 25˚C
Ta 50˚C
Typ.
–
–
–
–
–
Limits
Min.
1,000,000
500,000
300,000
40
10
Number of data
rewrite times *1
Data hold years *1
* 1 NOT 100%TESTED
Conditions
fSK
tSKH
tSKL
tCS
tCSS
tDIS
tCSH
tDIH
tPD1
tPD0
tSV
tDF
tE/W
–
250
250
200
200
100
0
100
–
–
–
–
–
Min.
–
–
–
–
–
–
–
–
–
–
–
–
7
Typ.
1.25
–
–
–
–
–
–
–
300
300
200
200
10
Max.
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Unit
SK frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output establishment
Time from CS to High-Z
Write cycle time
3/16
Data is taken by DI in sync with the rise of SK.
At read action, data is output from DO in sync with the rise of SK.
The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input. This is at the DO
area where CS is "H", and valid until the next command start bit is input. While CS is "L", DO becomes High-Z.
After each mode execution is competed, set CS to "L" once for internal circuit reset, and execute the following action mode.
Characteristic data
The following characteristic data are Typ. values.
Fig.8 Input leak current ILI (CS,SK,DI) Fig.9 Output leak current ILO (DO) Fig.10 Current consumption at WRITE
operation ICC1 (WRITE,fSK=1.25MHz)
Fig.11 Consumption current at READ operation
ICC2 (READ,fSK=1.25MHz) Fig.12 Consumption current at WRAL operation
ICC3 (WRAL,fSK=1.25MHz) Fig.13 Consumption current at standby
operation ISB
Fig.14 SK frequency fSK Fig.15 SK high time tSKH Fig.16 SK low time tSKL
Fig.3 L input voltage VIL (CS,SK,DI)
Fig.4 L output voltage VOL-IOL (VCC=2.7V)
Fig.5 L output voltage VOL-IOL (VCC=4.0V) Fig.6 H output voltage VOH-IOH (VCC=2.7V)
Fig.7 H output voltage VOH-IOH (VCC=4.0V)
Ta=125˚C Ta=125˚C Ta=125˚C
Ta=25˚C Ta=25˚C Ta=25˚C
Ta=-40˚C Ta=-40˚C
Ta=-40˚C
SPEC
SPEC
SPEC SPEC SPEC
SPEC SPEC
SPEC SPEC
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
1
0.8
0.6
0.4
0.2
0
23456 23 012345
456
Fig.2 H input voltage VIH (CS,SK,DI)
Ta=125˚C
Ta=125˚C Ta=125˚C Ta=125˚C
Ta=125˚C
Ta=125˚C
Ta=25˚C
Ta=25˚C Ta=25˚C Ta=25˚C
Ta=25˚C
Ta=25˚C
Ta=-40˚C
Ta=-40˚C
Ta=-40˚C
Ta=-40˚C
Ta=-40˚C
Ta=-40˚C
1
0.8
0.6
0.4
0.2
0
12
10
8
6
4
2
0
0
5
4
3
2
1
0
00.40.81.2 1.6
5
4
3
2
1
0
00.40.81.2 1.612345
23456
12
10
8
6
4
2
0
23456
3.5
3
2.5
2
1.5
1
0.5
0
23456
SPEC
SPEC
SPEC SPEC
SPEC SPEC
Ta=125˚C
Ta=125˚C
Ta=125˚C Ta=125˚C
Ta=125˚C
Ta=125˚C
Ta=25˚C
Ta=25˚C
Ta=25˚C Ta=25˚C
Ta=25˚C Ta=25˚C
Ta=-40˚C
Ta=-40˚C
Ta=-40˚C Ta=-40˚C
Ta=-40˚C
Ta=-40˚C
1.6
1.2
0.8
0.4
0
14
12
10
8
6
4
2
0
300
250
200
150
100
50
0
300
250
200
150
100
50
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
12
10
8
6
4
2
0
2
22
23456
34563456
3456 223456
3456
SUPPLY VOLTAGE : VCC (V)
H INPUT VOLTAGE : VIH (V)
L INPUT VOLTAGE : VIL (V)
L OUTPUT VOLTAGE : VOL (V)
L OUTPUT CURRENT : IOL (mA)
L OUTPUT VOLTAGE : VOL (V)
L OUTPUT CURRENT : IOL (mA)
INPUT LEAK CURRENT : ILI (µA)
AT READING : ICC2 (READ) (mA)
CURRENT CONSUMPTION
AT OPERATING : ICC3 (WRAL) (mA)
CURRENT CONSUMPTION OUTPUT LEAK CURRENT : ILO (µA) H OUTPUT VOLTAGE : VOH (V)
H OUTPUT CURRENT : IOH (mA)
H OUTPUT VOLTAGE : VOH (V)
H OUTPUT CURRENT : IOH (mA)
AT WRITING : ICC1 (WRITE) (mA)
CURRENT CONSUMPTION
STAND BY CURRENT : ISB (µA)
SK FREQUENCY : fSK (MHz)
H SK TIME : tSKH (ns)
L SK TIME : tSKL (ns)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V)
4/16
Fig.17 CS low time tCS Fig.18 CS setup time tCSS Fig.19 DI setup time tDIS
Fig.20 DI hold time tDIH Fig.21 CS hold time tCSH Fig.22 Data "1" output delay time tPD1
Fig.23 Data "0" output delay time tPD0 Fig.24 Time from CS to output establishment tSV Fig.25 Time from CS to High-Z tDF
Fig.26 Write cycle time tE/W
SPEC
SPEC SPEC
300
250
200
150
100
50
0
120
100
80
60
40
20
0
-20
250
200
150
100
50
0
120
100
80
60
40
20
0
Ta=125˚C
Ta=125˚C
Ta=125˚C
Ta=25˚C
Ta=25˚C
Ta=25˚C
Ta=-40˚C Ta=-40˚C Ta=-40˚C
234562
2
50
0
-50
-100
-150
-200
-250
-300
-350
-400
-450
223456
34563456
34
350
300
250
200
150
100
50
0
12
10
8
6
4
2
0
2
23456
3456
350
300
250
200
150
100
50
0
23456
250
200
150
100
50
0
23456
250
200
150
100
50
0
56
SPEC
Ta=125˚C
Ta=25˚C
Ta=-40˚C
SPEC
Ta=125˚C
Ta=25˚C
Ta=-40˚C
SPEC
Ta=125˚C
Ta=25˚C
Ta=-40˚C
SPEC
Ta=125˚C
Ta=25˚C
Ta=-40˚C
SPEC
Ta=125˚C
Ta=25˚C
Ta=-40˚C
SPEC
SPEC
Ta=125˚C
Ta=125˚C
Ta=25˚C
Ta=25˚C
Ta=-40˚C
Ta=-40˚C
CS LOW TIME : tcs (ns)
CS SETUP TIME : tCSS (ns)
DI SETUP TIME : tDIS (ns)
DI HOLD TIME : tDIH (ns)
CS HOLD TIME : tCSH (ns)
DATA "1" OUTPUT DELAY TIME : tPD1 (ns)
DATA "0" OUTPUT DELAY TIME : tPD0 (ns)WRITE CYCLE TIME : tE/W (ms)
TIME BETWEEN CS AND OUTPUT : tSV (ns)
TIME BETWEEN CS AND
OUTPUT HIGH-Z : tDF (ns)
SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V)
SUPPLY VOLTAGE : VCC (V)
5/16
23 456
BR93H66RF-W:SOP8
BR93H66RFJ-W:SOP-J8
BR93H76RF-W:SOP8
BR93H76RFJ-W:SOP-J8
BR93H86RF-W:SOP8
BR93H86RFJ-W:SOP-J8
CS SK DI DO
GND
TEST2 TEST1
VCC
BR93H56RF-W:SOP8
BR93H56RFJ-W:SOP-J8
CS
CS Command decode
Control
Clock generation
Command
register
Dummy bit
SK DI DO
GNDNC TEST
VCC
Block diagram
Pin assignment and function
Pin name
Vcc
GND
CS
SK
DI
DO
TEST
NC
TEST1
TEST2
Input / output
–
–
Input
Input
Input
Output
–
–
–
–
Power source
All input / output reference voltage, 0V
Chip select input
Serial clock input
Start bit, ope code, address, and serial data input
Serial data output, READY / BUSY internal condition display output
TEST terminal, GND or OPEN
Non connected terminal, Vcc, GND or OPEN
TEST terminal, GND or OPEN
TEST terminal, Vcc, GND or OPEN
Function
Fig.27 Block diagram
Fig.28 Pin assignment diagram
Power source voltage detection
High voltage occurrence
Address
buffer Address
decoder
R/W
amplifier
2,048bit
4,096bit
8,192bit
16,384bit
EEPROM
Write
prohibition
Data
register
SK
DO
DI
7bit
8bit
9bit
10bit
16bit 16bit
7bit
8bit
9bit
10bit
6/16
. The write all command is written in bulk in 2Kbit unit.
The write area can be selected up to 3bit. Confirm the settings and write areas of the above B2, B1, and B0.
Write all area
Designation of B2, B1, and B0
B2 B1 B0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
H56
H66
H76
H86
*
*
B1
B1
*
B0
B0
B0
*
*
*
B2
Write area
000h ~ 07Fh
080h ~ 0FFh
100h ~ 17Fh
180h ~ 1FFh
200h ~ 27Fh
280h ~ 2FFh
300h ~ 37Fh
380h ~ 3FFh
Description of operations
CS
Micro-
controller
SK
DO
DI
CS
BR93H BR93H
SK
DI
DO
CS
CS3
CS1
CS0
SK
DO
DI
CS
SK
DI
DO
CS
SK
DI
DO
CS
SK
DI
DO
SK
DIO
CS
SK
DI
DO
Fig.29(a) Connection by 4 lines Fig.29(b) Connection by 3 lines
Fig.29 Connection method with microcontroller
Fig29.(c) Connection example of plural devices
A7 - B0 of BR93H56-W becomes Don't Care.
A9 - B2 of BR93H76-W becomes Don't Care.
Command mode
(*1)
(*2)
(*2,3)
1
1
1
1
1
10
00
01
00
00
A7,
1
A7,
0
0
A6,
1
A6,
1
0
A5,
*
A5,
*
*
A4,
*
A4,
*
*
A3,
*
A3,
*
*
A2,
*
A2,
*
*
A1,
*
A1,
*
*
A0,
*
A0,
B0
*
A7,
*
A7,
*
*
A6,
*
A6,
*
*
A9,
1
A9,
0
0
A8,
1
A8,
1
0
A5,
*
A5,
*
*
A4,
*
A4,
*
*
A3,
*
A3,
*
*
A2,
*
A2,
B2,
*
A1,
*
A1,
B1,
*
A0
*
A0
B0
*
Read (READ)
Write enable (WEN)
Write (WRITE)
Write all (WRAL)
Write disable (WDS)
Command Address Address
BR93H56/66-W BR93H76/86-W Data
Ope code
Start bit
D15~D0
(READ DATA)
D15~D0
(WRITE DATA)
D15~D0
(WRITE DATA)
7/16
. Input the address and the data in MSB.
. As for *, input either VIH or VIL.
* Start bit
Acceptance of all the commands of this IC starts at recognition of the start bit.
The start bit refers to the first "1" input after the rise of CS.
(*1) : For read, by continuous SK clock input after setting the read command, data output of the set address starts, and
address data in significant order are continuously output in sequence. (Auto increment function)
(*2) : When the read and the write all commands are executed, data written in the selected memory cell is automatically
deleted, and input data is written.
(*3) : For the write all command, data written in memory cell of the areas designated by B2, B1, and B0, are automatically
deleted, and input data is written in bulk.
Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input), DO (serial data output), and CS (chip select) for
device selection.When connecting one EEPROM to a microcontroller, connect as shown in Fig. 29 (a) or Fig. 29 (b). When using the input and
output common I/O port of the microcontroller, connect DI and DO via a resistor, as shown in Fig. 29 (b) (Refer to pages 13 and 14.). Connection
by 3 lines is available.For plural connections, refer to Fig. 29 (c).
Micro-
controller
Micro-
controller
Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After input of the start bit,
input ope code, address, and data. Address and data are input all in MSB.
"0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the PIO bit width of the microcontroller, input "0"
before the start bit input, to control the bit width.
When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is synchronized with the SK
rise during A0 acquisition and a ì0î (dummy bit) is output. All further data is output in synchronization with the SK pulse rises. This IC has
an address auto increment function, active only at read command. In this function the above address data is read sequentially by
continuously inputting SK clock. During the auto increment, keep CS at "H".
8/16
2) Write cycle (WRITE)
BR93H56/66-W : n=27,m=7
BR93H76/86-W : n=29,m=9
CS
SK
DI
DO High-Z
011Am A1 A0 D15 D14 D1 D0
STATUSt
CS
READY
BUSY
t
SV
t
E/W
12 4 n
Fig.31 Write cycle
Timing chart
1) Read cycle (READ)
CS
SK
DI
DO
*
1
(
*
2)
D14
D15
D0
D1
D14
D15
0
High-Z
110Am A1 A0
124n
n+1
*1 Start bit
When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input,
it is recognized as a start bit, and the following operation is started. This is common to all the commands to described hereafter.
(*2) The following address data output
(auto increment function)
BR93H56/66-W : n=27, m=7
BR93H76/86-W : n=29, m=9
Fig.30 Read cycle
In this command, input 16bit data (D15 ~ D0) are written to designated addresses (Am ~ A0). The actual write starts by the fall of CS
from the rise of D0 taken SK clock (n-th clock from the start bit input), to the rise of the (n+1)-th clock.
When STATUS is not detected, (CS = "L" fixed) Max. 10ms in conformity with tE/W, and when STATUS is detected (CS = "H"), all
commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any command.
Write is not made even if CS is started after input of clock after (n+1)-th clocks.
Note ) Take tSKH or more from the rise of the n-th clock to the fall of CS.
9/16
3) Write all cycle (WRAL)
BR93H56/66-W : n=27,m=9
BR93H76/86-W : n=29,m=11
Fig.32 Write all cycle
Designation of B2, B1, and B0
H56
H66
H76
H86
*
*
B1
B1
*
B0
B0
B0
*
*
*
B2
4) Write enable (WEN) / disable (WDS) cycle
100
CS
DI
DO High-Z
ENABLE = 1 1
DISABLE= 0 0
12345678n
SK
Fig.33 Write enable / disable cycle
BR93H56/66-W : n=11
BR93H76/86-W : n=13
CS
SK
DI
DO High-Z
11B2B1 B0 D15 D1 D0
12 5 m n
tCS STATUS
READY
tSV
BUSY
000
tE/W
In this command, input 16bit data is written simultaneously to designated block for 128 words. Data is writen in bulk at a write time of only
Max. 10ms in conformity with tE/W. When writing data to all addresses, designate each block by B2, B1, and B0, and execute write. Write
time is Max. 10ms. The actual write starts by the fall of CS from the rise of D0 taken at SK clock (n-th clock from the start bit input), to the
rise of the (n+1)-th clock. When CS is ended after clock input after the rise of the (n+1)-th clock, command is cancelled, and write is not
completed.Note: Take tSKH or more from the rise of the n-th clock to the fall of CS.
At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is necessary to
execute the write enable command. And, once this command is executed, it is valid until the write disable command is executed or the
power is turned off. However, the read command is valid irrespective of write enable / disable command. input to SK after 6 clocks of this
command is available by either "H" or "L", but be sure to input it.
When the write enable command is executed after power on, write enable status gets in. When the write disable command is executed
then, the IC gets in write disable status as same as at power on, and then the write command is cancelled thereafter in software manner.
However, the read command is executable. In write enable status, even when the write command is input by mistake, write is started. To
prevent such a mistake, it is recommended to execute the write disable command after completion of write.
10/16
2) Equivalent circuit
DO
OEint.
Output circuit
Fig.36 DO output equivalent circuit
1) Method to cancel each command
*1 Address is 8 bits in BR93H56-W, and BR93H66-W.
Address is 10 bits in BR93H76-W, and BR93H86-W.
*1 Address is 8 bits in BR93H56-W, and BR93H66-W.
Address is 10 bits in BR93H76-W, and BR93H86-W.
*2 27 clocks in BR93H56-W, and BR93H66-W
29 clocks in BR93H76-W, and BR93H86-W
*3 28 clocks in BR93H56-W, and BR93H66-W
30 clocks in BR93H76-W, and BR93H86-W
READ
WRITE, WRAL
Fig.34 READ cancel available timing
1 bit 2 bits 8 bits 16 bits
Start bit Ope code Address Data
Cancel is available in all areas in read mode.
ü Method to cancel : cancel by CS = "L"
*1
*1
*2
*2
*3
acb
tE/W
Fig.35 WRITE, WRAL cancel available timing
1 bit 2 bits 8 bits 16 bits
Start bit Ope code Address Data
a : from start bit to 27 clock rise
b : 27 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
SK
DI D1
26 27 28 29
D0
Enlarged figure
Rise of a27 clock *2
Cancel by CS = "L"
Cancel by CS = "L"
Application
c : 28 clock rise and after
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is input continuously, cancellation is not available.
a cb
CS
RESETint.
CSint.
EN
TEST1
(TEST) TESTint.
TEST2
Input circuit
LPF
Fig.37 CS input equivalent circuit Fig.39 TEST1 (TEST) input equivalent circuit
Fig.40 TEST2 input equivalent circuit
SK
DI
EN
SK(DI)int.
LPF
Fig.38 SK, DI input equivalent circuit
Note 1) If Vcc is made OFF in this area, designated address data is not guaranteed,
therefore write once again.
Note 2) If CS is started at the same timing as that of the SK rise, write execution / cancel
becomes unstable, therefore, it is recommended to fall in SK = "L" area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
11/16
3) I/O peripheral circuit
Pull down resistance Rpd of CS pin
3-1) Pull down CS.
By making CS = "L" at power ON/OFF, mistake in action and mistake write are prevented.
Refer to the item 6) Notes at power ON/OFF in page 15.
3-2) DO is available in both pull up and pull down.
VOHM
IOHM Rpd
2.4
2×10-3
Rpd
Example) When Vcc = 5V, VIHE = 2V, VOHM = 2.4V, IOHM = 2mA,
from the equation ,
VOHM VIHE . . .
With the value of Rpd to satisfy the above equation, VOHM becomes
2.4V or higher, and with VIHE (= 2.0V), the equation is also satisfied.
Rpd 1.2 (k )
Microcontroller EEPROM
VIHE
"H" output "L" input
. VIHE : EEPROM VIH specifications
. VOHM : microcontroller VOH specifications
. IOHM : microcontroller IOH specifications
DI
SK
CS
DO
DI
SK
CS
DO
DO
D0
High-Z High-Z
READY
READY
Improvement by DO pull up
"H"
Enlarged
BUSY BUSY
BUSY CS=SK=DI="H"
When DO=pull up
CS=SK=DI="H"
When DO=OPEN
Fig.41 CS pull down resistance
Fig.42 READY output timing at DO = OPEN
Pull up resistance Rpu and pull down resistance Rpd of DO pin
VILM IOLE
Rpu
5-0.4
2.1×10-3
Rpu
VCC-VOLE
IOLE
Rpu . . .
Example) When Vcc = 5V, VOLE = 0.4V, IOLE = 2.1mA, VILM = 0.8V,
from the equation ,
VOLE VILM . . .
With the value of Rpu to satisfy the above equation, VOLE becomes
0.4V or below, and with VILM (= 0.8V), the equation is also satisfied.
Rpu 2.2 (k )
Microcontroller EEPROM
VOLE
"L" output
"L" input
Fig43 DO pull up resistance . VOLE : EEPROM VOL specifications
. IOLE : EEPROM IOL specifications
. VILM : microcontroller VIL specifications
To prevent operation and write error at power ON/OFF, CS pull down resistance is necessary. Select an appropriate resistance value
from microcontroller VOH, IOH, and VIL characteristics of this IC.
VOHM
IOHM
Rpd . . .
DO output become "High-Z" in other READY / BUSY output timing than after data output at read command and write command.
When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and pull up DO.
When there is no influence upon the microcontroller actions, DO may be OPEN.
If DO is OPEN, and at timing to output status READY, at timing of CS = "H", SK = "H", DI = "H", EEPROM recognizes this as a start bit,
resets READY output, and DO = "High-Z", therefore, READY signal cannot be detected. To avoid such output, pull up DO pin for
improvement.
As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller VIH, VIL,
and VOH, IOH, VOL, IOL characteristics of this IC.
12/16
VIHM
5-0.2
0.1×10-3
Rpd
VOHE
IOHE
Rpd . . .
Example) When Vcc = 5V, VOHE = Vcc ~ 0.2V, IOHE = 0.1mA, VIHM =
VCC×0.7V, from the equation ,
VOHE VIHM . . .
With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V
or higher, and with VIHM (= 3.5V), the equation is also satisfied.
Rpd 48 (k )
Microcontroller EEPROM
VOHE
"H" output
"H" input
Fig.44 DO pull down resistance
Fig.45 R/B status output timing chart
. VOHE : EEPROM VOH specifications
. IOHE : EEPROM IOH specifications
. VIHM : microcontroller VIH specifications
IOHE
Rpd
READY / BUSY status display (DO terminal) (common to BR93H56-W, BR93H66-W, BR93H76-W, BR93H86-W)
R/B display = "L" (BUSY) = write under execution
R/B display = "H" (READY) = command wait status
CS
SK
DI
DO High-Z READY
BUSY
tSV
CLOCK
STATUS
WRITE
INSTRUCTION
(D0 status)
(D0 status)
4) When to directly connect DI and DO
Fig.46 DI, DO control line common connection
This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart, meanwhile, by inserting
a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line.
Microcontroller EEPROM
DI/O PORT
DI
DO
R
This display outputs the internal status signal. When CS is started after tCS (Min. 200ns) from CS fall after
write command input, "H" or "L" is output.
After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically.
And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted.
Even after tE/W (Max. 10ms) from write of the memory cell, the following command is accepted.
Therefore, CS = "H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI = "L" in
the area CS = "H". (Especially, in the case of shared input port, attention is required.)
Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted.
Therefore, status READY output is cancelled, and malfunction and mistake write may be made.
13/16
Fig.47 Collision timing at read data output at DI, DO direct connection
Fig.48 Collision timing at DI, DO direct connection
Fig.49 Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output)
Data collision of microcontroller DI/DO output and DO output and feedback of DO output to DI input
4-1) 1 clock cycle to take in A0 address data at read command
Dummy bit "0" is output to DO terminal.
→ When address data A0 = "1" input, through current route occurs.
EEPROM CS input
EEPROM SK input
EEPROM DI input
EEPROM DO output
Microcontroller DI/O port
D13
D14
D15
Collision of DI input and DO output
Microcontroller input
High-Z
"H"
High-Z
Microcontroller
output
A1 A0
A1 A0
0
Selection of resistance value R
4-3) Address data A0 = "1" input, dummy bit "0" output timing
(When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI)
· Make the through current to EEPROM 10mA or below.
· See to it that the input level VIH of EEPROM should satisfy the following.
4-2) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output.
When the next start bit input is recognized, "HIGH-Z" enters.
→Particularly, at command input after write, when CS input is started with microcontroller DI/O output "L"
READY output "H" is output from DO terminal, and a through current path occurs.
Feedback input at timing of these 4-1) and 4-2) does not cause disorder in basic operations, if resistance R is inserted.
EEPROM CS input
EEPROM SK input
EEPROM DI input
EEPROM DO output
Microcontroller DI/O port
Collision of DI input and status DO output
Microcontroller input
High-Z
READY
Microcontroller output Microcontroller output
BUSY
READY
BUSY
Write command
Write command
Write command
Write command
Write command
READY
VOHM
VOLE
DI/O PORT DI
IOHM R
At this moment, if VOLE = 0V,
VOHM IOHM × R + VOLE
£
VOHM IOHM × R
£
VOHM VIHE
£
Microcontroller EEPROM
"H" output
"L" output
· VIHE : EEPROM VIH specifications
· VOLE : EEPROM VOL specifications
· VOHM : Microcontroller VOH specifications
· IOHM : Microcontroller IOH specifications
DO
Conditions
VOHM
IOHM
R. . .
Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the same time in the following
points.
The resistance R becomes through current limit resistance at data collision. When through current flows, noises of power source line and
instantaneous stop of power source may occur. When allowable through current is defined as I, the following relation should be satisfied.
Determine allowable current value with consideration of impedance and of power source line in set. Insert resistance R, and set the value R to
satisfy EEPROM input level VIH/VIL, even under influence of voltage decline due to leak current. Insertion of R will not cause any influence
upon basic operations.
14/16
4-4) DO status READY output timing
(When the microcontroller DI/O is "L", EEPROM DO outputs "H", and "L" is input to DI)
.Set the EEPROM input level VIL so as to satisfy the following.
VOHE
VOLM
DI/O PORT DI
IOHM RAt this moment, if VOHE=VCC
VOLM VOHE - IOLM × R
VOLM VCC - IOLM × R
VOLM VILE
Microcontroller EEPROM
"H" output
"L" output
. VILE : EEPROM VIL specifications
. VOHE : EEPROM VOH specifications
. VOLM : Microcontroller VOL specifications
. IOLM : Microcontroller IOL specifications
DO
Conditions
VCC - VOLM
IOLM
R. . .
Example) When Vcc = 5, VOHM = 5V, IOHM = 0.4mA, VOLM = 5V, IOLM = 0.4mA
R VOHM
IOHM
R 5
0.4×10-3
From the equation ,
. . .
R 12.5 [k ]
R VCC - VOLM
IOLM
R 5 - 0.4
2.1×10-3
From the equation ,
. . .
R 2.2 [k ]
R 12.5 [k ]
Therefore, from the equations and ,
5) Notes at test pin wrong input
1. At WEN, WDS, READ command input
There is no influence by TEST1 (TEST) pin.
There is no influence by TEST1 (TEST) pin.a.
a.
Start bit
1 bit 2 bits 8 bits 16 bits
Ope code
Fig.51 TEST1 (TEST) pin wrong input timing Write start
CS rise timing
Address Data tE/W
2. WRITE, WRAL command input
There is no influence of external input upon TEST2 pin.
For TEST1 (TEST) pin, input must be GND or OPEN. If H level is input, the following may occur:
a
*
* BR93H56-W, BR93H66-W, address 8 bits
BR93H76-W,BR93H86-W, address 10 bits
Fig.50 Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output)
If H during write execution, it may not be written correctly. And H area remains BUSY and READY does not go back. Avoid
noise input, and at use, be sure to connect it to GND terminal or set it OPEN.
15/16
6) Notes on power ON/OFF
7) Noise countermeasures
Vcc noise (bypass capacitor)
POR circuit
LVCC circuit
. At power ON/OFF, set CS "L".
Good example
Bad example
GND
VCC
GND
VCC
VCC
CS
Fig.51 Timing at power ON/OFF
(Bad example) CS pin is pulled up to Vcc. (Good example) It is "L" at power ON/OFF.
Fig.52 Rise waveform diagram
tR
tOFF Vbot
VCC
0
Recommended conditions of tR, tOFF, Vbot
10ms or below
tRtOFF Vbot
100ms or below
0.3V or below
0.2V or below
10ms or higher
10ms or higher
1 Set CS = "L".
2 Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit operation.
Cautions on use
When CS is "H", IC gets in input accept status (active). At power ON, set CS "L" to prevent malfunction from noise. (When CS is in "L"
status, all inputs are cancelled.) At power decline low power status may prevail. Therefore, at power OFF, set CS "L" to prevent malfunction
from noise.
In this case, CS becomes "H" (active status). EEPROM may
malfunction or have write error due to noises. This is true even
when CS input is High-Z.
Set 10ms or higher to recharge at power OFF.When power is turned
on without following the above condition, IC internal circuit may not
be reset.
This IC has a POR (Power On Reset) circuit as a mistake write countermeasure.After POR is activated, write disable status is active.
The POR circuit is active only when power is ON, and does not work when power is OFF. However, if CS is "H" at power ON/OFF, it may
enable write status due to noise.For secure actions, observe the following conditions:
LVCC (Vcc - Lockout) circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. = 1.9V) or below, it prevent data rewrite.
When noise or surge gets in the power source line, malfunction may occur. Therefore, it is recommended to attach a by pass capacitor
(0.1µF) between IC Vcc and GND to remove noise or surge. Attach it as close to the IC as possible.It is also recommended to attach a
bypass capacitor between board Vcc and GND.
SK noise
When the rise time (tR) of SK is long, and noise exists, malfunction may occur due to clock bit displacement. To avoid this, a Schmitt
trigger circuit is built into SK input. The hysteresis width of this circuit is set to about 0.2V (at Vcc = 5V). If noises exists at SK input, set
the noise amplitude to 0.2Vp-p or below.It is recommended to set the rise time (tR) of SK to 100ns or below. If the rise time is 100ns or
higher, take sufficient noise countermeasures. Set the clock rise and fall time as small as possible.
(1) Numbers and data in entries are representative design values and are not guaranteed values of the items.
(2) Although ROHM is confident that the example application circuit reflects the best possible recommendations, be sure to verify circuit
characteristics for your particular application. Modification of constants for other externally connected circuits may cause variations in
both static and transient characteristics for external components as well as this Rohm IC. Allow for sucircuit constants.
(3) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings, such as the applied voltage or operating
temperature range (Topr), may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open
mode) when such damage is suffered. A physical safety measure, such as a fuse, should be implemented when using the IC at times
where the absolute maximum ratings may be exceeded.
(4) GND potential Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the
GND at any time, regardless of whether it is a transient signal or not.
(5) Heat design
In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin.
(6) Short circuit between terminals and erroneous mounting Pay attention to the assembly direction of the ICs. Wrong mounting direction
or shorts between terminals, GND, or other components on the circuits, can damage the IC.
(7) Operation in strong electromagnetic field Using the ICs in a strong electromagnetic field can cause operation malfunction
<Package specifications><External appearance> Emboss tapingPackage type
Package quantity
Package direction 2500pcs
E2
(When the reel is gripped by the left hand, and the tape is pulled out by
the right hand, No.1 pin of the product is at the left top.)
Reel Pin No.1 Pulling side
* For ordering, specify a number of multiples of the package quantity.
SOP8/SOP-J8
1234
1234
1234
1234
1234
1234
1234
1234
0.1
0.45Min.
0.42±0.1
4.9±0.2
85
4123
1.27
7 6
• SOP-J8
0.2±0.1
0.175 6.0±0.3
3.9±0.2
1.375±0.1
• SOP8
0.3Min.
0.42±0.1
0.11 6.2±0.3
4.4±0.2
5.0±0.2
85
41
1.27
1.5±0.1
0.1
Selection of order type
Package specifications
BR 93 H 56 RF W E2
ROHM type
name Double cell Taping type name
E2 : reel shape emboss taping
BUS type
93 : Microwire Operating
temperature
L : - 40˚C ~ +85 ˚C
A : -40˚C ~ +105 ˚C
H: -40˚C ~ +125 ˚C
Capacity
Microwire BUS
56=2K
66=4K
76=8K
86=16K
Package type
RF:SOP
RFJ:SOP-J(JEDEC)
–
0.17
+0.1
-
0.05
Catalog No. 05T820A '05.10 ROHM©2000 TSU
The contents described herein are correct as of October, 2005
The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD.
Any part of this application note must not be duplicated or copied without our permission.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding
upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any
warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such
infringement, or arising from or connected with or related to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other
proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer.
The products described herein utilize silicon as the main material.
The products described herein are not designed to be X ray proof.
Published by
Application Engineering Group
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any
means without prior permission of ROHM CO.,LTD.
The contents described herein are subject to change without notice. The specifications for the
product described in this document are for reference only. Upon actual use, therefore, please request
that specifications to be separately delivered.
Application circuit diagrams and circuit constants contained herein are shown as examples of standard
use and operation. Please pay careful attention to the peripheral conditions when designing circuits
and deciding upon circuit constants in the set.
Any data, including, but not limited to application circuit diagrams information, described herein
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of
whatsoever nature in the event of any such infringement, or arising from or connected with or related
to the use of such devices.
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or
otherwise dispose of the same, no express or implied right or license to practice or commercially
exploit any intellectual property rights or other proprietary rights owned or controlled by
ROHM CO., LTD. is granted to any such buyer.
Products listed in this document are no antiradiation design.
Appendix1-Rev2.0
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Copyright © 2007 ROHM CO.,LTD.
The products listed in this document are designed to be used with ordinary electronic equipment or devices
(such as audio visual equipment, office-automation equipment, communications devices, electrical
appliances and electronic toys).
Should you intend to use these products with equipment or devices which require an extremely high level
of reliability and the malfunction of which would directly endanger human life (such as medical
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers
and other safety devices), please be sure to consult with our sales representative in advance.
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM
cannot be held responsible for any damages arising from the use of the products under conditions out of the
range of the specifications or due to non-compliance with the NOTES specified in this catalog.
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FAX : +81-75-315-0172
Appendix
