INTEGRATED CIRCUITS DATA Sil 74LV259 = = | 8-bit addressable latch Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook Philips Semiconductors Di 1998 May 20 PHILIPSPhilips Semiconductors ee 8-bit addressable latch FEATURES Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Voc = 2.7 V and Voc = 3.6 V Typical Vo_p (output ground bounce) < 0.8 V at Voc = 3.3 V, Tamb = 25C Typical Voyy (output Voy undershoot) > 2 V at Voc = 3.3 V, Tamb = 25C Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input @ Useful as a 3-to-8 active HIGH decoder Output capability: standard loc category: MSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; t= t}<2.5ns Product specification 74LV259 DESCRIPTION The 74LV259 is a low-voltage CMOS device and is pin and function compatible with 74HC/HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is a multifunction device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Qo to Q7), functions are available. The 74LV259 also incorporate an active LOW common reset (MR) for resetting all latches, as well as an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (Ag to Ap) and date (D) input. When operating the 74LV259 as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the 74LV259. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay C_ = 15 pF; D, A, to Q, Voc =3.3V 17 tpH_/t TEs n PHU"PLH | TE to Qn 16 ns MR to Q, 14 Cc Input capacitance 3.5 pF Cpp Power dissipation capacitance per latch V, = GND to Vgc! 19 pF NOTE: 1. Cpp is used to determine the dynamic power dissipation (Pp in u.W) Pp = Cpp x Voc? x fi + (CL x Voc? x fo) where: f, = input frequency in MHz; C_ = output load capacity in pF; fy = output frequency in MHz; Vcc = supply voltage in V; (CL x Voc? x fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL 40C to +125C 74LV259 N 74LV259 N SOT38-4 16-Pin Plastic SO 40C to +125C 74LV259 D 74LV259 D SOT109-1 16-Pin Plastic SSOP Type II 40C to +125C 74LV259 DB 74LV259 DB SOT338-1 16-Pin Plastic TSSOP Type | 40C to +125C 74LV259 PW 74LV259PW DH SOT403-1 1998 May 20 853-1988 19420Philips Semiconductors Product specification 8-bit addressable latch 74LV259 PIN CONFIGURATION PIN DESCRIPTION PIN aol VY FE] Veo NUMBER | SYMBOL FUNCTION Ay [2 | 75 wR 1,2,3 Ag to Ap _ | Address inputs A[ 3_| al IE tod, a Qo to Q7 | Latch outputs Qo 4 | 13 | 0 8 GND Ground (0 V) Q [5 | 72 | Q 13 D Data input af e | it | Qs 14 LE Latch enable input (active LOW) al 7] Fo] Qs 15 MR Conditional reset input (active LOW) 16 Voc Positive supply voltage owl Jo, $V01602 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) |" 15 LE gp 4 4 13] D Qy 5 Q2/- 6 5 Q3h- 7 1] Ay Q4- 9 8 2_T A Qs/ 10 7 3 Ao Qs/- 11 9 MR Q7F-- 12 T 10 15 SVv01601 " FUNCTIONAL DIAGRAM 12 1-of-8 DECODER 8 LATCHES Qo] 4 Qi] 5 cP Q3|_ 7 Q4] 9 Qs] 40 Qe] 41 Q7| 12 SV01604 SV01603 MODE SELECT TABLE LE | MR MODE L H Addressable latch H H Memory L L Active HIGH 8-channel demultiplexer H L Reset 1998 May 20Philips Semiconductors Product specification 8-bit addressable latch 74LV259 FUNCTION TABLE OPERATING MODES - wets oT MR L D Ao Ay Ao Qo Qy Qo Q3 Q, Qs Q5 Q; Master reset L H x x x x L L L L L L L L d L L L Qz=d L L L L L L L d H L L L Qz=d L L L L L L L L d L H L L L Q=d L L L L L (eco ich) L L d H H L L L L | Qd]oL L L L decoder L L d L L H L L L L | Qa] oL L L (when D = H) L L d H L H L L L L L Qed L L L L d L H H L L L L L L Qed L L L d H H H L L L L L L L Q=d Store (do nothing) H H x x x x qo qi q2 q3 a4 q5 6 q/ H L d L L L Qz=d qi q2 q3 q4 fele) q6 q7 H L d H L L qo Qz=d q2 q3 q4 fele) q6 q7 H L d L H L qo qi Q=d q3 q4 fele) q6 q7 Addressable latch n . 3 n n . ae a vf ore at a of a7 H L d L L H qo qi q2 q3 Qz=d fele) q6 q7 H L d H L H qo qi q2 q3 q4 Qz=d q6 q7 H L d L H H qo qi q2 q3 q4 fele) Q=q q7? H L d H H H qo qi q2 q3 q4 fele) q6 Q=d z 14 m wn oaxrr nuund HIGH voltage level LOW voltage level dont care HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition lower case letters indicate the state of the referenced output established during the last cycle established during the last cycle in which it was addressed or cleared RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Voc DC supply voltage See Note 1 1.0 3.3 3.6 Vv V| Input voltage 0 - Voc Vv Vo Output voltage 0 - Voc Vv Tamb Operating ambient temperature range in free air S80 nee 4o es C Voc = 1.0V to 2.0V - - 500 tht Input rise and fall times Vec = 2.0V to 2.7V - - 200 ns/V Voc = 2.7V to 3.6V - - 100 NOTE: 1. The LV is guaranteed to function down to Voc = 1.0V (input levels GND or Voc); DC characteristics are guaranteed from Voc = 1.2V to Voc = 5.5V. 1998 May 20Philips Semiconductors Product specification 8-bit addressable latch 74LV259 ABSOLUTE MAXIMUM RATINGS! 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS RATING UNIT Voc DC supply voltage 0.5 to +4.6 Vv tlk DC input diode current V, <-0.5 or Vi > Voc + 0.5V 20 mA tlok DC output diode current Vo < 0.5 or Vo > Veco + 0.5V 50 mA DC output source or sink current tlo standard outputs -0.5V < Vo < Voc + 0.5V 25 mA DC Vcc or GND current for types with HNGND: standard outputs 50 mA Tstg Storage temperature range 65 to +150 C Power dissipation per package for temperature range: 40 to +125C Pp plastic DIL above +70C derate linearly with 12 mW/K 750 mW TOT plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 400 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS -40C to +85C -40C to +125C UNIT MIN TYP! MAX MIN MAX Veo = 1.2V 0.9 0.9 HIGH level Input _ Vin voltage Voc =2.0V 1.4 1.4 Vv Voc = 2.7 to 3.6 V 2.0 2.0 Voc =1.2V 0.3 0.3 LOW level Input _ VIL voltage Voc =2.0V 0.6 0.6 Vv Voc = 2.7 to 3.6 V 0.8 0.8 Voc = 1.2 V;V)= Vin or Vit.-lo= 100A 1.2 Vv HIGH level output Vec =2.0 V; V| = Vin or Vi; -lo = 100A 1.8 2.0 1.8 Vv OH | voltage; all outputs [gg = 2.7 V: Vi = Vin oF Vi:lo = 100uA 25 27 25 Vec = 3.0 V; V| = Vin or Vi; -lo = 100A 2.8 3.0 2.8 HIGH level output voltage; Vou STANDARD Voc = 3.0 V; V| = Vin or Vi_:lo = 6MA 2.40 2.82 2.20 Vv outputs Voc = 1.2 V;V)= Vin or Vi_- lo = 100A 0 Vv LOW level output Vec =2.0V; V| = Vin or Vi; lo = 100A 0 0.2 0.2 Vv OL | voltage; all outputs [gq = 2:7 V: Vj = Vin oF ViL-lo = 100pA 0 0.2 0.2 Vec =3.0V; Vv, = Vin or Vib; lo = 100uA 0 0.2 0.2 LOW level output voltage; VoL STANDARD Voc = 3.0 V; V = Viy or Vi_;lo = 6MA 0.25 0.40 0.50 Vv outputs 1998 May 20Philips Semiconductors Product specification 8-bit addressable latch T4LV259 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS -40C to +85C -40C to +125C UNIT MIN TYP! MAX MIN MAX Input leak: I current age Voc = 3.6 V; Vi = Voc or GND 1.0 1.0 pA Quiescent supply _ ve tae loc current: MSI Voc = 3.6 V; Vi = Voc or GND; Io = 0 20.0 160 pA Additional quiescent Alec supply current per Voc = 2.7 V to 3.6 V; Vi = Voc - 0.6 V 500 850 pA input NOTE: 1. All typical values are measured at Tamp = 25C. AC CHARACTERISTICS GND = OV; t, = j <2.5ns; C_ = 50pF; R, = 1KQ LIMITS CONDITION SYMBOL PARAMETER WAVEFORM 40 to +85 C 40 to +125 C UNIT Vec(V) MIN TYP! MAX MIN MAX 1.2 105 Propagation delay . 2.0 36 49 61 teH_ft Figure 2 ns PHMIPL | D to Qn 9 27 26 36 45 3.0 to 3.6 202 29 36 1.2 105 Propagation delay . 2.0 36 49 61 teH_ft Figure 3 ns PHMIPL | An to. Qn 9 27 26 36 45 3.0 to 3.6 202 29 36 1.2 100 Propagation delay . 2.0 34 48 60 teH_ft Te Figure 1 ns PHL/'PLH LE to Q, g O77 35 35 7 3.0 to 3.6 192 28 35 1.2 90 Propagation delay . 2.0 31 43 53 t We Figure 4 ns pee MR to Qh 9 27 23 31 39 3.0 to 3.6 172 25 31 __ 2.0 34 10 a ty HI Moan Figure 1 27 25 8 30 ns 3.0 to 3.6 20 62 24 _ 2.0 34 10 a ty tose wath Figure 4 27 25 8 30 ns 3.0 to 3.6 20 62 24 1.2 35 Set-up time . 2.0 24 12 29 t TE Fi 5and6 Su D. An to LE gure 9 an O77 18 5 mI ns 3.0 to 3.6 14 72 17 1.2 -30 t Hold time Fi 5 2.0 5 -10 5 h DtoLE gure D7 5 3 5 ns 3.0 to 3.6 5 62 1998 May 20 6Philips Semiconductors Product specification 8-bit addressable latch 74LV259 AC CHARACTERISTICS (Continued) GND = OV; t, = tt} <2.5ns; C_ = 50pF; R, = 1KQ CONDITION 40 to +85 C 40 to +125 C SYMBOL PARAMETER WAVEFORM UNIT Vec(V) MIN TYP! MAX MIN MAX 1.2 -20 t Hold time Figure 6 20 ml ns h A, to LE g 27 5 5 3.0 to 3.6 5 42 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at Voc = 3.3 V. AC WAVEFORMS Vu = 1.5 V at Voc 2 2.7 V and < 3.6V; Vu = 0.5 x Voc at Voc < 2.7 V and> 4.5 V. VoL and Voy are the typical output voltage drop that occur with the output load. An INPUT Vu TE INPUT GND - - - Vou Q, OUTPUT SV01605 Vou Q, OUTPUT SV01607 Figure 3. Address inputs (A,) to output (Q,) propagation delays. Figure 1. Enable input (CE) to output (Q,) propagation delays and the enable input pulse width. Vec Dp INPUT GND Vou Qn OUTPUT SV01608 Q, OUTPUT VoL SV001606 Figure 4. Conditional reset input (MR) to output (Q,,) propagation delays. Figure 2. Data input (D) to output (Q,) propagation delays. 1998 May 20Philips Semiconductors Product specification 8-bit addressable latch 74LV259 AC WAVEFORMS (Continued) Vu = 1.5 V at Voc 2 2.7 V and < 3.6V; Vu = 0.5 x Voc at Voc < 2.7 V and> 4.5 V. VoL and Voy are the typical output voltage drop that occur with the output load. TEST CIRCUIT LE INPUT GND Voc Dp INPUT GND Vou Qn OUTPUT VoL The shaded areas indicate when the input is permitted to change for predictable output performance SV01609 Figure 5. Data set-up and hold times for D input to LE input. Vv PULSE GENERATOR DEFINITIONS R_,_ = Load resistor C._ = Load capacitance includes jig and probe capacitance Rr = Termination resistance should be equal to Zour of pulse generators. SWITCH POSITION TEST Ss Voc vi teLHAPHL Open <2.7V Voc 2.7-3.6V 2.7 SV00905 Vec An INPUT Vu ADDRESS STABLE GND Voc LE INPUT GND The shaded areas indicate when the input is permitted to change for predictable output performance. SV01610 Figure 6. Address set-up and hold times for A, inputs to LE input. 1998 May 20 Figure 7. Load circuitry for switching times.Philips Semiconductors Product specification 8-bit addressable latch 74LV259 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 o Cc & Qa D & 3S oO a 0 5 10 mm be scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ao (1) (1) zi) UNIT | max. | min. | max. b b, bo c D E e e, L Me My w max. 1.73 0.53 1.25 0.36 19.50 | 6.48 3.60 8.25 10.0 mm 4.2 0.54 3.2 1.30 0.38 0.85 0.23 18.55 6.20 2.54 7.62 3.05 7.80 8.3 0.254 0.76 ; 0.068 | 0.021 | 0.049 | 0.014 0.77 0.26 0.14 0.32 0.39 h inenes | 0.17 | 0.020 | 0.13 | 9 951 | 0.015 | 0.033 | 0.009 | 0.73 | 0.24 | %19 | 98 | o42 | 0.31 | 0.33 | 2-01 | 0-080 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 92-44-44 SOT38-4 E+ 95-01-14 1998 May 20 9Philips Semiconductors Product specification 8-bit addressable latch T4LV259 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 t | rooN\ Me fs) A Win tne : : ' : : | 4 ) t L oR Oe Pe 8 co 0 2.5 5mm De scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT max. A, | Ao | Az bp c DM | EM | e He L Lp Q v w y z) | 9 mm | +78 | oa0 | 125 | 929 | 036 | o19| 98 | a8 | t2 | 55 |] o4 | o6 | 22] 9] 1 | 05 | ge ncnes | 0069208] 8957] oo [O12 [00088) 038 1 978 | yaso] 824 aoa [2002/28 o01 | oor [oone| Ome) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES [EUROPEAN ISSUE DATE IEC JEDEC EIAJ $OT109-1 076E07S MS-012AG eo Sep as 1998 May 20 10Philips Semiconductors Product specification 8-bit addressable latch T4LV259 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 aN [ \ T ] | LJ T{ aI) r SS =~ aly He VOR) _ 6 | 9 ' I | | 1 : ff eo | Ao pp ---+---- Ay \ 4 (As) A ! 7 oy" 1 index t | i-~ 6 1 | Lp << i a L +l 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) UNIT max. A, | Ao | Ags | bp | | DO] EM] e He | L Lp | @ v w y | 2] 6 0.21 | 1.80 0.38 | 0.20] 6.4 | 54 7.9 1.03 | 0.9 1.00 | 8 mm | 20 | 905 | 165 | ?5 | 0.25} 009} 60 | 52 | F] 76 | 175} oes] a7 | %? | 21] OT | O55] oe Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT338-1 MO-150AC --} cnop oe 11 1998 May 20Philips Semiconductors Product specification 8-bit addressable latch T4LV259 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 Lt CT detail X Jbod 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) A 1 2 1 UNIT | ax. | At Ao | A3 bp c pM | EA] e He L Lp Q v w y Zz] 6 0.15 | 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8 mm | 119) 905 | o80} 7] 019] 01 | 49 | 43 | 28] 62 | 1 | oso] o3 | %? | 2] OT | oo6 | 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION PROJECTION | 'SSUEDATE IEC JEDEC EIAJ 0407 42 SOT403-1 MO-153 os 95.04.04 1998 May 20 12Philips Semiconductors Product specification 8-bit addressable latch T4LV259 NOTES 1998 May 20 13Philips Semiconductors Product specification 8-bit addressable latch T4LV259 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published ata later date. Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. seine, . This data sheet contains Final Specifications. Philips Semiconductors reserves the rightto make changes Product Specification Full Production . . oo | | F at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. Box 3409 Sunnyvale, California 94088-3409 print code Date of release: 05-96 Telephone 800-234-7381 Document order number: 9397-750-04442 Lett make things betew Semiconductors E> PH I LI PS