THC63LVD1027_Rev.4.00_E THC63LVD1027 Dual Link LVDS Repeater General Description Features * 30bits/pixel dual link LVDS Receiver * 30bits/pixel dual Link LVDS Transmitter * Operating Temperature Range : -40C~85C * Wide LVDS input skew margin: 480ps at 75MHz * Accurate LVDS output timing: 250ps at 75MHz * Reduced swing LVDS output mode supported to The THC63LVD1027 LVDS(Low Voltage Differential Signaling) repeater is designed to support pixel data transmission between Host and Flat Panel Display up to WUXGA resolution. THC63LVD1027 receives the dual link LVDS data streams and transmits the LVDS data through various line rate conversion modes, Dual Link Input / Dual Link Output, Single Link Input / Dual Link Output, and Dual Link Input / Single Link Output. suppress the system EMI * Various line rate conversion modes supported Dual link input / Dual link output [clkout=1x clkin] Single link input / Dual link output [clkout=1/2x clkin] Dual link input / Single link output [clkout=2x clkin] * Distribution (signal duplication) mode supported * Power down mode supported * 3.3V single voltage power supply * No external components required for PLLs * 64pin TSSOP with Exposed PAD (0.5mm lead pitch) Block Diagram Figure 1. Block Diagram Copyright(c)2015 THine Electronics, Inc. 1 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Pin Diagram Figure 2. Pin Diagram Copyright(c)2015 THine Electronics, Inc. 2 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Pin Description Pin Name RA1+/RB1+/RC1+/RD1+/RE1+/RCLK1+/RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/TA1+/TB1+/TC1+/TD1+/TE1+/TCLK1+/TA2+/TB2+/TC2+/TD2+/TE2+/TCLK2+/PD Direction Input Output Table 1. Pin Description Type Description LVDS data input for channel A of 1st Link LVDS data input for channel B of 1st Link LVDS data input for channel C of 1st Link LVDS data input for channel D of 1st Link LVDS data input for channel E of 1st Link LVDS clock input for 1st Link LVDS data input for channel A of 2nd Link LVDS data input for channel B of 2nd Link LVDS data input for channel C of 2nd Link LVDS data input for channel D of 2nd Link LVDS data input for channel E of 2nd Link LVDS clock input for 2nd Link In Distribution and Single-in/Dual-out mode,RCLK2+/- must be Hi-Z. LVDS (See "Mode selection" below in this page.) LVDS data output for channel A of 1st Link LVDS data output for channel B of 1st Link LVDS data output for channel C of 1st Link LVDS data output for channel D of 1st Link LVDS data output for channel E of 1st Link LVDS clock output for 1st Link LVDS data output for channel A of 2nd Link LVDS data output for channel B of 2nd Link LVDS data output for channel C of 2nd Link LVDS data output for channel D of 2nd Link LVDS data output for channel E of 2nd Link LVDS clock output for 2nd Link Power Down H: Normal operation L: Power down state, all LVDS output signals turn to Hi-Z RS LVDS output swing level selection H: Normal swing L: Reduced swing MODE1 MODE0 Input LV-TTL Mode selection MODE1 L L H L H MODE0 L L L H H RCLK2+/Clkin Hi-Z Hi-Z Clkin - Description Dual-in/Dual-out mode Distribution mode Single-in/Dual-out mode Dual-in/Single-out mode Reserved In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z. VDD GND CAP Power - 3.3V power supply pins Ground pins (Exposed PAD is also Ground) Decoupling capacitor pins These pins should be connected to external decoupling capacitors(Ccap). Recommended Ccap is 0.1F + 0.01F. Copyright(c)2015 THine Electronics, Inc. 3 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Mode Setting Table 2. Mode Setting Input/Output Dual-In/Dual-Out RCLK2+/- MODE1 MODE0 (Input mode) (Output mode) H: Single H: Single L: Dual L: Dual CLK in L L Hi-Z L L Hi-Z H L CLK in L H - H H (Fig.3-1,14-1) Distribution (Fig.3-2,14-2) Single-In/Dual-Out (Fig.3-3,14-3) Dual-In/Single-Out (Fig.3-4,14-4) Reserved Signal Flow for Each Setting Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Copyright(c)2015 THine Electronics, Inc. 4 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Output Control / Fail Safe THC63LVD1027 has a function to control output depending on LVDS input condition. Table 3. Output Control RCLK2+/Output * All Hi-Z * All Hi-Z CLK in Refer to p.4 Mode Setting # Hi-Z Refer to p.4 Mode Setting # PD RCLK1+/L * H Hi-Z H CLK in H CLK in *: Don't care #: If a particular input data pair is Hi-Z, the corresponding output data become L according to LVDS DC spec. For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting Hi-Z state. Figure 4. Fail Safe Circuit Copyright(c)2015 THine Electronics, Inc. 5 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Absolute Maximum Ratings Table 4. Absolute Maximum Rating Parameter Min Max Power Supply Voltage -0.3 +4.0 LVDS Input Voltage -0.3 VDD+0.3 125 Junction Temperature -55 125 Storage Temperature 260 / 10sec Reflow Peak Temperature / Time 2.5 Maximum Power Dissipation @+25C Unit V V C C C W Operating Conditions Symbol Ta VDD Fclk Table 5. Operating Condition Parameter Min Typ Operating Ambient Temperature -40 25 Power Supply Voltage 3.0 3.3 Input 20 Dual-In/Dual-Out Output 20 Input 20 Distribution Output 20 Input 40 Single-In/Dual-Out Output 20 Input 20 Dual-In/Single-Out Output 40 - Copyright(c)2015 THine Electronics, Inc. 6 Max +85 3.6 85 85 85 85 135 67.5 42.5 85 Unit C V MHz MHz MHz MHz THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Power Consumption Table 6. Power Consumption Symbol Parameter Conditions CLKIN=40MHz Dual-In/Dual-Out CLKIN=65MHz CLKIN=75MHz CLKIN=85MHz CLKIN=40MHz CLKIN=65MHz Distribution ICCW CLKIN=75MHz Operating Current CLKIN=85MHz (Worst Case Pattern) CLKIN=40MHz CLKIN=65MHz Fig 5. Single-In/Dual-Out RL_Tx=100 CL=5pF RS=VDD CLKIN=75MHz CLKIN=85MHz Fig 6. CLKIN=112MHz CLKIN=135MHz CLKIN=20MHz Dual-In/Single-Out CLKIN=32.5MHz CLKIN=37.5MHz CLKIN=42.5MHz ICCS Power Down Current - - - Min Typ. Max - - 265 305 325 340 215 235 245 260 175 190 200 210 230 250 215 235 245 260 8 Unit mA mA mA mA mA Figure 5. Test Pattern (LVDS Output Full Toggle Pattern) Figure 6. LVDS Output Load Copyright(c)2015 THine Electronics, Inc. 7 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Electrical Characteristics DC Specifications Table 7. DC Specifications Symbol VCAP Parameter Conditions Capacitor pin appearance voltage CCAP=0.1F Min Typ Max Unit - 1.8 - V VIL LV-TTL Input Low Voltage - GND - 0.8 V VIH LV-TTL Input High Voltage - 2.0 - VDD V LV-TTL Input Leakage Current - -4 - +4 A Unit IIN_TTL LVDS Receiver DC Specifications Table 8. LVDS Receiver DC Specifications Symbol Parameter Conditions Min Typ Max VIN_RX LVDS-Rx Input Voltage Range - 0.3 - 2.1 VIC_RX LVDS-Rx Common Voltage - 0.6 1.2 1.8 VTH_RX LVDS-Rx Differential High Threshold - - +100 -100 - - 100 - 600 PD=VDD -0.3 - +0.3 mA PD=GND Vin=GND or VDD -10 - +10 A V VIC_RX = 1.2V VTL_RX LVDS-Rx Differential Low Threshold |VID_RX| LVDS-Rx Differential Input Voltage IIN_RX - LVDS-Rx Input Leakage Current mV LVDS Transmitter DC Specifications Table 9. LVDS Transmitter DC Specifications Symbol VOC_TX VOC_TX Parameter Conditions Min Typ Max Unit LVDS-Tx Common Voltage - 1.125 1.25 1.375 V Change in VOC between complementary output states - - - 35 mV Normal Swing 250 350 450 Reduced Swing 100 200 300 - - - 35 mV |VOD_TX| LVDS-Tx Differential Output Threshold VOD_TX Change in VOD between complementary output states RL_TX = mV 100 IOS_TX LVDS-Tx Output Short Current VDD=3.3V Vout=GND -24 - - mA IOZ_TX LVDS-Tx Output Tri-state Current PD=GND Vout=GND to VDD -10 - +10 A Copyright(c)2015 THine Electronics, Inc. 8 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E AC Specifications Table 10. AC Specifications Symbol Parameter tLT Phase Lock Loop Set Time (Fig 7.) tDL Min Typ Max Unit - - - 10 ms Dual-In/Dual-Out CLKIN=75MHz 9tRCP+3 9tRCP+5 9tRCP+7 Distribution CLKIN=75MHz 9tRCP+3 9tRCP+5 9tRCP+7 Single-In/Dual-Out CLKIN=75MHz (11+2/7)tRCP+3 (11+2/7)tRCP+5 (11+2/7)tRCP+7 Dual-In/Single-Out CLKIN=37.5MHz (11+2/7)tRCP+3 (11+2/7)tRCP+5 (11+2/7)tRCP+7 - 2tRCP - - - 2tRCP - - 4tRCP Must be 2n tRCP (n=integer) - - ns Data Latency (Fig 8.) tDEH DE Input High Time (Fig 9.) tDEL DE Input Low Time (Fig 9.) tDEINT Conditions Single-In/Dual-Out - DE Input Period (Fig 9.) AC Timing Diagrams Figure 7. Phase Lock Loop Set Time Copyright(c)2015 THine Electronics, Inc. 9 THine Electronics, Inc. Security E ns THC63LVD1027_Rev.4.00_E AC Timing Diagrams(Continued) Figure 8. DATA Latency Figure 9. Single Link Input / Dual Link Output Mode RC1(DE) Input Timing Copyright(c)2015 THine Electronics, Inc. 10 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E LVDS Receiver AC Specifications Table 11. LVDS Receiver AC Specifications Symbol Parameter Conditions Min Typ Max tRCP LVDS Clock Period - 7.4 - 50 tRCH LVDS Clock High Duration - 2/7tRCP 4/7tRCP 5/7tRCP tRCL LVDS Clock Low Duration - 2/7tRCP 3/7tRCP 5/7tRCP CLKIN=75MHz(1) 480 - - CLKIN=112MHz(1) 250 - - CLKIN=135MHz(1) 220 - - CLKIN=75MHz(1) 480 - - CLKIN=112MHz(1) 250 - - CLKIN=135MHz(1) 220 - - tRSUP tRHLD LVDS Data Input Setup Margin LVDS Data Input Hold Margin tRIP6 LVDS Data Input Position 6 - 2/7tRCP-tRHLD 2/7tRCP 2/7tRCP+tRSUP tRIP5 LVDS Data Input Position 5 - 3/7tRCP-tRHLD 3/7tRCP 3/7tRCP+tRSUP tRIP4 LVDS Data Input Position 4 - 4/7tRCP-tRHLD 4/7tRCP 4/7tRCP+tRSUP tRIP3 LVDS Data Input Position 3 - 5/7tRCP-tRHLD 5/7tRCP 5/7tRCP+tRSUP tRIP2 LVDS Data Input Position 2 - 6/7tRCP-tRHLD 6/7tRCP 6/7tRCP+tRSUP tRIP1 LVDS Data Input Position 1 - 7/7tRCP-tRHLD 7/7tRCP 7/7tRCP+tRSUP tRIP0 LVDS Data Input Position 0 - 8/7tRCP-tRHLD 8/7tRCP 8/7tRCP+tRSUP - -0.3 tRCP - +0.3 tRCP Skew Time Between RCLK1 and RCLK2 (1) VIC_RX=1.2V, tRCH=4/7 tRCP tCK12 Unit ns ps ps ps ps Copyright(c)2015 THine Electronics, Inc. 11 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E LVDS Receiver Input Timing Figure 10. LVDS Receiver Timing Figure 11. Skew time between RCLK1 and RCLK2 Copyright(c)2015 THine Electronics, Inc. 12 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E LVDS Transmitter AC Specifications Table 12. LVDS Transmitter AC Specifications Symbol Parameter Conditions Min Typ Max tTCP LVDS Clock Period - 11.76 - 50 tTCH LVDS Clock High Duration - - 4/7tTCP - tTCL LVDS Clock Low Duration - - 3/7tTCP - tTSUP LVDS Data Output Setup CLKOUT=75MHz - - 250 ps tTHLD LVDS Data Output Hold CLKOUT=75MHz - - 250 ps tTOP6 LVDS Data Output Position 6 - 2/7tTCP-tTHLD 2/7tTCP 2/7tTCP+tTSUP tTOP5 LVDS Data Output Position 5 - 3/7tTCP-tTHLD 3/7tTCP 3/7tTCP+tTSUP tTOP4 LVDS Data Output Position 4 - 4/7tTCP-tTHLD 4/7tTCP 4/7tTCP+tTSUP tTOP3 LVDS Data Output Position 3 - 5/7tTCP-tTHLD 5/7tTCP 5/7tTCP+tTSUP tTOP2 LVDS Data Output Position 2 - 6/7tTCP-tTHLD 6/7tTCP 6/7tTCP+tTSUP tTOP1 LVDS Data Output Position 1 - 7/7tTCP-tTHLD 7/7tTCP 7/7tTCP+tTSUP tTOP0 LVDS Data Output Position 0 - 8/7tTCP-tTHLD 8/7tTCP 8/7tTCP+tTSUP tLVT LVDS Transition Time (Fig 13.) Fig.6 - 0.6 1.5 Copyright(c)2015 THine Electronics, Inc. 13 Unit ns ps ns THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E LVDS Transmitter Output Diagram Figure 12. LVDS Transmitter Timing Figure 13. LVDS Transition Timing Copyright(c)2015 THine Electronics, Inc. 14 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E LVDS Data Mapping Dual-In / Dual-Out Figure 14-1. Data Mapping for Dual-In/Dual-Out Copyright(c)2015 THine Electronics, Inc. 15 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Distribution Mode In Distribution mode, RCLK2+/- must be Hi-Z. Figure 14-2. Data Mapping for Distribution mode Copyright(c)2015 THine Electronics, Inc. 16 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Single-In / Dual-Out In Single-in / Dual-out mode, RCLK2+/- must be Hi-Z. Figure 14-3(a). Data Mapping for Single-In/Dual-Out Copyright(c)2015 THine Electronics, Inc. 17 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Figure 14-3(b). Data Mapping for Single-In/Dual-Out Copyright(c)2015 THine Electronics, Inc. 18 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Dual-In / Single-Out Figure 14-4. Data Mapping for Dual-In/Single-Out Notes Copyright(c)2015 THine Electronics, Inc. 19 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E 1) LVDS input pin connection When LVDS line is not derived from the previous device, the line is pulled up to 3.3V internally in THC63LVD1027. This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating condition is lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of the whole system including THC63LVD1027. One solution for this problem is PD=L control during no LVDS input period because pull-up resistors are cut off at power down state. Figure 15. LVDS input pin connection 2) Power On Sequence Don't input RCLK1+/- and RCLK2+/- before THC63LVD1027 is on in order to keep absolute maximum ratings. Copyright(c)2015 THine Electronics, Inc. 20 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E 3)Cable Connection and Disconnection Don't connect and disconnect the LVDS cable, when the power is supplied to the system. 4)GND Connection Connect the each GND of the PCB which Transmitter, Receiver and THC63LVD1027 on it. It is better for EMI reduction to place GND cable as close to LVDS cable as possible. 5)Multi Drop Connection Multi drop connection is not recommended. Figure 16.Multi Drop Connection 6)Asynchronous use Asynchronous use such as following systems are not recommended. Page.11 tCK12 spec should be kept. Figure 17-1. Asynchronous Use1 Asynchronous use such as following systems are not recommended. Figure 17-2. Asynchronous Use2 Copyright(c)2015 THine Electronics, Inc. 21 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Package Figure 18. Package Diagram Copyright(c)2015 THine Electronics, Inc. 22 THine Electronics, Inc. Security E THC63LVD1027_Rev.4.00_E Notices and Requests 1. The product specifications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. We are not responsible for possible errors and omissions in this material. Please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. This product is presumed to be used for general electric equipment, not for the applications which require very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipment). Also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please do it after applying appropriate measures to the product. 6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. Please note that this product is not designed to be radiation-proof. 8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. sales@thine.co.jp Copyright(c)2015 THine Electronics, Inc. 23 THine Electronics, Inc. Security E