PCA9555DGVR - Texas Instruments

1. General description

The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel

Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to

enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements

include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O

conﬁguration, and smaller packaging. I/O expanders provide a simple solution when

additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.

The PCA9555 consists of two 8-bit Conﬁguration (Input or Output selection); Input, Output

and Polarity Inversion (active HIGH or active LOW operation) registers. The system

master can enable the I/Os as either inputs or outputs by writing to the I/O conﬁguration

bits. The data for each Input or Output is kept in the corresponding Input or Output

address compatible with the PCF8575, software changes are required due to the

enhancements, and are discussed in

Application Note AN469

The PCA9555 open-drain interrupt output is activated when any input state differs from its

corresponding input port register state and is used to indicate to the system master that

an input state has changed. The power-on reset sets the registers to their default values

and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the ﬁxed I2C-bus address and allow up to eight

devices to share the same I2C-bus/SMBus. The ﬁxed I2C-bus address of the PCA9555 is

the same as the PCA9554, allowing up to eight of these devices in any combination to

share the same I2C-bus/SMBus.

2. Features

nOperating power supply voltage range of 2.3 V to 5.5 V

n5 V tolerant I/Os

nPolarity Inversion register

nActive LOW interrupt output

nLow standby current

nNoise ﬁlter on SCL/SDA inputs

nNo glitch on power-up

nInternal power-on reset

n16 I/O pins which default to 16 inputs

n0 Hz to 400 kHz clock frequency

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Rev. 08 — 22 October 2009 Product data sheet

Product data sheet Rev. 08 — 22 October 2009 2 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nSix packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24

3. Ordering information

3.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

PCA9555N DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1

PCA9555D SO24 plastic small outline package; 24 leads;

body width 7.5 mm SOT137-1

PCA9555DB SSOP24 plastic shrink small outline package; 24 leads;

body width 5.3 mm SOT340-1

PCA9555PW TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

PCA9555BS HVQFN24 plastic thermal enhanced very thin quad ﬂat package;

no leads; 24 terminals; body 4 ×4×0.85 mm SOT616-1

PCA9555HF HWQFN24 plastic thermal enhanced very very thin quad ﬂat

package; no leads; 24 terminals; body 4 ×4×0.75 mm SOT994-1

Table 2. Ordering options

Type number Topside mark Temperature range

PCA9555N PCA9555 −40 °C to +85 °C

PCA9555D PCA9555D −40 °C to +85 °C

PCA9555DB PCA9555 −40 °C to +85 °C

PCA9555PW PCA9555 −40 °C to +85 °C

PCA9555BS 9555 −40 °C to +85 °C

PCA9555HF P55H −40 °C to +85 °C

Product data sheet Rev. 08 — 22 October 2009 3 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

4. Block diagram

5. Pinning information

5.1 Pinning

Remark: All I/Os are set to inputs at reset.

Fig 1. Block diagram of PCA9555

PCA9555

POWER-ON

RESET

002aac702

I2C-BUS/SMBus

CONTROL

INPUT

FILTER

SCL

SDA

VDD

INPUT/

OUTPUT

PORTS

IO0_0

VSS

8-bit

write pulse

read pulse

IO0_2

IO0_1

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

INPUT/

OUTPUT

PORTS

IO1_0

8-bit

write pulse

read pulse

IO1_2

IO1_1

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

INT

LP filter

VDD

Fig 2. Pin conﬁguration for DIP24 Fig 3. Pin conﬁguration for SO24

VDD

SDA

SCL

IO1_7

IO1_6

IO1_5

IO1_4

IO1_3

IO1_2

IO1_1

IO1_0

INT

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

VSS

PCA9555N

002aac697

23 INT VDD

A1 SDA

A2 SCL

IO0_0 A0

IO0_1 IO1_7

IO0_2 IO1_6

IO0_3 IO1_5

IO0_4 IO1_4

IO0_5 IO1_3

IO0_6 IO1_2

IO0_7 IO1_1

VSS IO1_0

PCA9555D

002aac698

Product data sheet Rev. 08 — 22 October 2009 4 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 4. Pin conﬁguration for SSOP24 Fig 5. Pin conﬁguration for TSSOP24

Fig 6. Pin conﬁguration for HVQFN24 Fig 7. Pin conﬁguration for HWQFN24

INT

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

VSS

PCA9555DB

002aac699

23 VDD

SDA

SCL

IO1_7

IO1_6

IO1_5

IO1_4

IO1_3

IO1_2

IO1_1

IO1_0

VDD

SDA

SCL

IO1_7

IO1_6

IO1_5

IO1_4

IO1_3

IO1_2

IO1_1

IO1_0

INT

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

VSS

PCA9555PW

002aac700

002aac701

PCA9555BS

Transparent top view

IO1_3

IO0_4

IO0_5

IO1_4

IO0_3 IO1_5

IO0_2 IO1_6

IO0_1 IO1_7

IO0_0 A0

IO0_6

IO0_7

VSS

IO1_0

IO1_1

IO1_2

VDD

SDA

SCL

terminal 1

index area

613

514

4 15

3 16

2 17

118

INT

002aac881

Transparent top view

IO1_3

IO0_4

IO0_5

IO1_4

IO0_3 IO1_5

IO0_2 IO1_6

IO0_1 IO1_7

IO0_0 A0

IO0_6

IO0_7

VSS

IO1_0

IO1_1

IO1_2

INT

VDD

SDA

SCL

terminal 1

index area

613

514

4 15

3 16

2 17

118

PCA9555HF

Product data sheet Rev. 08 — 22 October 2009 5 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

5.2 Pin description

[1] HVQFN and HWQFN package die supply ground is connected to both the VSS pin and the exposed center

pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board-level performance, the exposed pad needs to be soldered to the board using a

corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias

need to be incorporated in the PCB in the thermal pad region.

Table 3. Pin description

Symbol Pin Description

DIP24, SO24,

SSOP24, TSSOP24 HVQFN24,

HWQFN24

INT 1 22 interrupt output (open-drain)

A1 2 23 address input 1

A2 3 24 address input 2

IO0_0 4 1 port 0 input/output

IO0_1 5 2

IO0_2 6 3

IO0_3 7 4

IO0_4 8 5

IO0_5 9 6

IO0_6 10 7

IO0_7 11 8

VSS 12 9[1] supply ground

IO1_0 13 10 port 1 input/output

IO1_1 14 11

IO1_2 15 12

IO1_3 16 13

IO1_4 17 14

IO1_5 18 15

IO1_6 19 16

IO1_7 20 17

A0 21 18 address input 0

SCL 22 19 serial clock line

SDA 23 20 serial data line

VDD 24 21 supply voltage

Product data sheet Rev. 08 — 22 October 2009 6 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

6. Functional description

Refer to Figure 1 “Block diagram of PCA9555”.

6.1 Device address

6.2 Registers

6.2.1 Command byte

The command byte is the ﬁrst byte to follow the address byte during a write transmission.

It is used as a pointer to determine which of the following registers will be written or read.

Fig 8. PCA9555 device address

R/W

002aac219

0 1 0 0 A2 A1 A0

programmable

slave address

fixed

Table 4. Command byte

Command Register

0 Input port 0

1 Input port 1

2 Output port 0

3 Output port 1

4 Polarity Inversion port 0

5 Polarity Inversion port 1

6 Conﬁguration port 0

7 Conﬁguration port 1

Product data sheet Rev. 08 — 22 October 2009 7 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

6.2.2 Registers 0 and 1: Input port registers

This register is an input-only port. It reﬂects the incoming logic levels of the pins,

regardless of whether the pin is deﬁned as an input or an output by Register 3. Writes to

this register have no effect.

The default value ‘X’ is determined by the externally applied logic level.

6.2.3 Registers 2 and 3: Output port registers

This register is an output-only port. It reﬂects the outgoing logic levels of the pins deﬁned

as outputs by Registers 6 and 7. Bit values in this register have no effect on pins deﬁned

as inputs. In turn, reads from this register reﬂect the value that is in the ﬂip-ﬂop controlling

the output selection, not the actual pin value.

6.2.4 Registers 4 and 5: Polarity Inversion registers

This register allows the user to invert the polarity of the Input port register data. If a bit in

this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this

Table 5. Input port 0 Register

Bit 76543210

Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0

Default XXXXXXXX

Table 6. Input port 1 register

Bit 76543210

Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0

Default XXXXXXXX

Table 7. Output port 0 register

Bit 76543210

Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0

Default 11111111

Table 8. Output port 1 register

Bit 76543210

Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0

Default 11111111

Table 9. Polarity Inversion port 0 register

Bit 76543210

Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

Default 00000000

Table 10. Polarity Inversion port 1 register

Bit 76543210

Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

Default 00000000

Product data sheet Rev. 08 — 22 October 2009 8 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

6.2.5 Registers 6 and 7: Conﬁguration registers

This register conﬁgures the directions of the I/O pins. If a bit in this register is set (written

with ‘1’), the corresponding port pin is enabled as an input with high-impedance output

driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is

enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At

reset, the device's ports are inputs with a pull-up to VDD.

6.3 Power-on reset

When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset

condition until VDD has reached VPOR. At that point, the reset condition is released and the

PCA9555 registers and SMBus state machine will initialize to their default states. The

power-on reset typically completes the reset and enables the part by the time the power

supply is above VPOR. However, when it is required to reset the part by lowering the power

supply, it is necessary to lower it below 0.2 V.

6.4 I/O port

When an I/O is conﬁgured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input with a weak pull-up to VDD. The input voltage may be raised above

VDD to a maximum of 5.5 V.

If the I/O is conﬁgured as an output, then either Q1 or Q2 is on, depending on the state of

the Output Port register. Care should be exercised if an external voltage is applied to an

I/O conﬁgured as an output because of the low-impedance path that exists between the

pin and either VDD or VSS.

Table 11. Conﬁguration port 0 register

Bit 76543210

Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

Default 11111111

Table 12. Conﬁguration port 1 register

Bit 76543210

Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

Default 11111111

Product data sheet Rev. 08 — 22 October 2009 9 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

6.5 Bus transactions

6.5.1 Writing to the port registers

Data is transmitted to the PCA9555 by sending the device address and setting the least

signiﬁcant bit to a logic 0 (see Figure 8 “PCA9555 device address”). The command byte is

sent after the address and determines which register will receive the data following the

command byte.

The eight registers within the PCA9555 are conﬁgured to operate as four register pairs.

The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Conﬁguration

Ports. After sending data to one register, the next data byte will be sent to the other

Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this

way, each 8-bit register may be updated independently of the other registers.

At power-on reset, all registers return to default values.

Fig 9. Simpliﬁed schematic of I/Os

VDD

I/O pin

output port

configuration

CK Q

data from

shift register

write

configuration

pulse

output port

write pulse

polarity inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity

inversion

002aac703

data from

shift register

VSS

to INT

100 kΩ

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Product data sheet Rev. 08 — 22 October 2009 10 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 10. Write to Output port registers

1 0 0 A2 A1 A0 0 AS0

START condition R/W acknowledge

from slave

002aac220

SCL

SDA A

write to port

data out

from port 0

tv(Q)

987654321

command byte data to port 0

DATA 0

slave address

00000100

STOP

condition

0.00.7

acknowledge

from slave acknowledge

from slave

data to port 1

DATA 1 1.01.7 A

data out

from port 1

tv(Q)

DATA VALID

Fig 11. Write to Conﬁguration registers

1 0 0 A2 A1 A0 0 AS0

START condition R/W acknowledge

from slave

002aac221

SCL

SDA A P

987654321

command byte data to register

DATA 0

slave address

00001100

STOP

condition

LSBMSB

acknowledge

from slave acknowledge

from slave

data to register

DATA 1

LSBMSB

Product data sheet Rev. 08 — 22 October 2009 11 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

6.5.2 Reading the port registers

In order to read data from the PCA9555, the bus master must ﬁrst send the PCA9555

address with the least signiﬁcant bit set to a logic 0 (see Figure 8 “PCA9555 device

address”). The command byte is sent after the address and determines which register will

be accessed. After a restart, the device address is sent again, but this time the least

signiﬁcant bit is set to a logic 1. Data from the register deﬁned by the command byte will

then be sent by the PCA9555 (see Figure 12,Figure 13 and Figure 14). Data is clocked

into the register on the falling edge of the acknowledge clock pulse. After the ﬁrst byte is

read, additional bytes may be read but the data will now reﬂect the information in the other

Input Port 0. There is no limitation on the number of data bytes received in one read

transmission but the ﬁnal byte received, the bus master must not acknowledge the data.

Remark: Transfer can be stopped at any time by a STOP condition.

Fig 12. Read from register

START condition R/W

acknowledge

from slave

002aac222

acknowledge

from slave

SDA

A P

acknowledge

from master

DATA (first byte)

slave address

STOP

condition

(repeated)

START condition

(cont.)

(cont.) 1 0 0 A2 A1 A0 1 A0

R/W

acknowledge

from slave

slave address

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

no acknowledge

from master

COMMAND BYTE

1 0 0 A2 A1 A00 0

data from lower or

upper byte of register

LSBMSB

DATA (last byte)

data from upper or

lower byte of register

LSBMSB

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Product data sheet Rev. 08 — 22 October 2009 12 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It

is assumed that the command byte has previously been set to ‘00’ (read Input Port register).

Fig 13. Read Input port register, scenario 1

1 0 0 A2 A1 A0 1 AS0

START condition

R/W

acknowledge

from slave

002aac223

SCL

SDA A

read from port 0

987654321

I0.xslave address STOP condition

acknowledge

from master

I1.x

acknowledge

from master

I0.x

acknowledge

from master

I1.x

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

6543210765432107 65432107 65432107

INT

tv(INT_N) trst(INT_N)

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Product data sheet Rev. 08 — 22 October 2009 13 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It

is assumed that the command byte has previously been set to ‘00’ (read Input Port register).

Fig 14. Read Input port register, scenario 2

1 0 0 A2 A1 A0 1 AS0

START condition

R/W

acknowledge

from slave

002aac224

SCL

SDA A

read from port 0

987654321

I0.xslave address STOP condition

acknowledge

from master

I1.x

acknowledge

from master

I0.x

acknowledge

from master

I1.x

non acknowledge

from master

data into port 0

read from port 1

data into port 1

INT

tv(INT_N) trst(INT_N)

DATA 00 DATA 10 DATA 03 DATA 12

DATA 00 DATA 01

th(D)

DATA 02

tsu(D)

DATA 03

tsu(D)

DATA 10 DATA 11 DATA 12

Product data sheet Rev. 08 — 22 October 2009 14 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

6.5.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins changes state and

the pin is conﬁgured as an input. The interrupt is deactivated when the input returns to its

previous state or the Input Port register is read (see Figure 13). A pin conﬁgured as an

output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt

caused by Port 0 will not be cleared by a read of Port 1 or the other way around.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register.

7. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 15).

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 16).

Fig 15. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 16. Deﬁnition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 08 — 22 October 2009 15 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

7.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 17).

7.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 17. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 18. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 08 — 22 October 2009 16 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

8. Application design-in information

Device address conﬁgured as 0100 000xb for this example.

IO0_0, IO0_2, IO0_3 conﬁgured as outputs.

IO0_1, IO0_4, IO0_5 conﬁgured as inputs.

IO0_6, IO0_7, and IO1_0 to IO1_7 conﬁgured as inputs.

Fig 19. Typical application

PCA9555

IO0_0

IO0_1

SCL

SDA

VDD

(5 V)

MASTER

CONTROLLER

SCL

SDA

INT IO0_2

VDD

GND

INT

10 kΩSUB-SYSTEM 1

(e.g., temp sensor)

IO0_3

INT

SUB-SYSTEM 2

(e.g., counter)

RESET

controlled

switch

(e.g., CBT device)

VDD

ENABLE

SUB-SYSTEM 3

(e.g., alarm system)

ALARM

IO0_4

IO0_5

IO0_6

10 DIGIT

NUMERIC

KEYPAD

VSS

002aac704

10 kΩ10 kΩ2 kΩ

IO0_7

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

Product data sheet Rev. 08 — 22 October 2009 17 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

9. Limiting values

Table 13. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6.0 V

VI/O voltage on an input/output pin VSS −0.5 6 V

IOoutput current on an I/O pin - ±50 mA

IIinput current - ±20 mA

IDD supply current - 160 mA

ISS ground supply current - 200 mA

Ptot total power dissipation - 200 mW

Tstg storage temperature −65 +150 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 08 — 22 October 2009 18 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

10. Static characteristics

[1] VDD must be lowered to 0.2 V for at least 5 µs in order to reset part.

Table 14. Static characteristics

= 2.3 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.3 - 5.5 V

IDD supply current Operating mode; VDD = 5.5 V; no load;

fSCL = 100 kHz - 135 200 µA

Istb standby current Standby mode; VDD = 5.5 V; no load;

VI=V

SS; fSCL = 0 kHz; I/O = inputs - 1.1 1.5 mA

Standby mode; VDD = 5.5 V; no load;

VI=V

DD; fSCL = 0 kHz; I/O = inputs - 0.25 1 µA

VPOR power-on reset voltage[1] no load; VI=V

DD or VSS - 1.5 1.65 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

IOL LOW-level output current VOL = 0.4 V 3 - - mA

ILleakage current VI=V

DD =V

SS −1- +1µA

Ciinput capacitance VI=V

SS - 6 10 pF

I/Os

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

IOL LOW-level output current VDD = 2.3 V to 5.5 V; VOL = 0.5 V [2] 8 (8 to 20) - mA

VDD = 2.3 V to 5.5 V; VOL = 0.7 V [2] 10 (10 to 24) - mA

VOH HIGH-level output voltage IOH =−8 mA; VDD = 2.3 V [3] 1.8 - - V

IOH =−10 mA; VDD = 2.3 V [3] 1.7 - - V

IOH =−8 mA; VDD = 3.0 V [3] 2.6 - - V

IOH =−10 mA; VDD = 3.0 V [3] 2.5 - - V

IOH =−8 mA; VDD = 4.75 V [3] 4.1 - - V

IOH =−10 mA; VDD = 4.75 V [3] 4.0 - - V

ILIH HIGH-level input leakage

current VDD = 5.5 V; VI=V

DD -- 1µA

ILIL LOW-level input leakage

current VDD = 5.5 V; VI=V

SS -- −100 µA

Ciinput capacitance - 3.7 5 pF

Cooutput capacitance - 3.7 5 pF

Interrupt INT

IOL LOW-level output current VOL = 0.4 V 3 - - mA

Select inputs A0, A1, A2

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 5.5 V

ILI input leakage current −1- +1µA

Product data sheet Rev. 08 — 22 October 2009 19 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

[2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a

maximum current of 100 mA for a device total of 200 mA.

[3] The total current sourced by all I/Os must be limited to 160 mA.

(1) IOH =−8mA

(2) IOH =−10 mA (1) IOH =−8mA

(2) IOH =−10 mA

Fig 20. VOH maximum Fig 21. VOH minimum

VDD = 5.5 V; VI/O = 5.5 V; A2, A1, A0 set to logic 0.

(1) Tamb =−40 °C

(2) Tamb = +25 °C

(3) Tamb = +85 °C

Fig 22. IDD versus number of I/Os held LOW

2.0

5.0

4.0

3.0

6.0

VOH

(V)

VDD (V)

2.7 5.53.6

002aac706

(1)

(2)

2.5

3.5

4.5

VOH

(V)

1.5

VDD (V)

2.3 4.753.0

002aac707

(1)

(2)

1.2

0.8

0.4

1.6

IDD

(mA)

number of I/Os

002aac705

all 1s all 0sone 0 three 0s

(1)

(2)

(3)

Product data sheet Rev. 08 — 22 October 2009 20 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

11. Dynamic characteristics

[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3] Cb= total capacitance of one bus line in pF.

Table 15. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - µs

tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - µs

tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs

tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 µs

tHD;DAT data hold time 0 - 0 - ns

tVD;DAT data valid time [2] 300 - 50 - ns

tSU;DAT data set-up time 250 - 100 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - µs

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns

trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns

tSP pulse width of spikes that must be

suppressed by the input ﬁlter - 50 - 50 ns

Port timing

tv(Q) data output valid time - 200 - 200 ns

tsu(D) data input set-up time 150 - 150 - ns

th(D) data input hold time 1 - 1 - µs

Interrupt timing

tv(INT_N) valid time on pin INT - 4 - 4 µs

trst(INT_N) reset time on pin INT - 4 - 4 µs

Product data sheet Rev. 08 — 22 October 2009 21 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

12. Test information

Fig 23. Deﬁnition of timing on the I2C-bus

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

RL= load resistor.

CL = load capacitance includes jig and probe capacitance.

RT= termination resistance should be equal to the output impedance of Zoof the pulse generators.

Fig 24. Test circuitry for switching times

Fig 25. Load circuit

PULSE

GENERATOR

50 pF

500 Ω

002aab284

VDD

DUT

VDD

open

GND

50 pF

002aac226

500 Ω

from output under test 2VDD

open

GND

500 Ω

Product data sheet Rev. 08 — 22 October 2009 22 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

13. Package outline

Fig 26. Package outline SOT101-1 (DIP24)

UNIT A

max. 1 2 b1cD E e M

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT101-1 99-12-27

03-02-13

min. A

max. bw

1.7

1.3 0.53

0.38 0.32

0.23 32.0

31.4 14.1

13.7 3.9

3.4 0.252.54 15.24 15.80

15.24 17.15

15.90 2.25.1 0.51 4

0.066

0.051 0.021

0.015 0.013

0.009 1.26

1.24 0.56

0.54 0.15

0.13 0.010.1 0.6 0.62

0.60 0.68

0.63 0.0870.2 0.02 0.16

051G02 MO-015 SC-509-24

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

max.

(1)

(1)(1)

DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1

Product data sheet Rev. 08 — 22 October 2009 23 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 27. Package outline SOT137-1 (SO24)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 15.6

15.2 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT137-1

detail X

vMA

(A )

0.25

075E05 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.61

0.60 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

99-12-27

03-02-19

Product data sheet Rev. 08 — 22 October 2009 24 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 28. Package outline SOT340-1 (SSOP24)

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.38

0.25 0.20

0.09 8.4

8.0 5.4

5.2 0.65 1.25

7.9

7.6 0.9

0.7 0.8

0.4 8

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.03

0.63

SOT340-1 MO-150 99-12-27

03-02-19

detail X

vMA

(A )

112

24 13

0.25

pin 1 index

0 2.5 5 mm

scale

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

max.

Product data sheet Rev. 08 — 22 October 2009 25 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 29. Package outline SOT355-1 (TSSOP24)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 08 — 22 October 2009 26 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 30. Package outline SOT616-1 (HVQFN24)

0.51 0.2

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT616-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT616-1

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

712

24 19

01-08-08

02-10-22

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 08 — 22 October 2009 27 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

Fig 31. Package outline SOT994-1 (HWQFN24)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT994-1 - - -

MO-220

- - -

SOT994-1

07-02-07

07-03-03

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

UNIT A(1)

max

mm 0.8 0.05

0.00 0.30

0.18 4.1

3.9 2.25

1.95 4.1

3.9 2.25

1.95 2.5 2.5 0.1

DIMENSIONS (mm are the original dimensions)

HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.75 mm

0 2.5 5 mm

scale

b c

0.2

D(1) DhE(1) Ehe

0.5

e1e2L

0.5

0.3

v w

0.05

0.1

B A

terminal 1

index area E

detail X

A1c

1/2 e

AC B

∅ vMC∅ wM

terminal 1

index area

613

127

24 19

Product data sheet Rev. 08 — 22 October 2009 28 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

14. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in

JESD625-A

or equivalent standards.

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 08 — 22 October 2009 29 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

15.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 32) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 16 and 17

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 32.

Table 16. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 17. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 08 — 22 October 2009 30 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

16. Soldering of through-hole mount packages

16.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

16.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

16.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

MSL: Moisture Sensitivity Level

Fig 32. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 08 — 22 October 2009 31 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

16.4 Package related soldering information

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

17. Abbreviations

Table 18. Suitability of through-hole mount IC packages for dipping and wave soldering

Package Soldering method

Dipping Wave

CPGA, HCPGA - suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]

PMFP[2] - not suitable

Table 19. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

GPIO General Purpose Input/Output

I2C-bus Inter-Integrated Circuit bus

SMBus System Management Bus

I/O Input/Output

ACPI Advanced Conﬁguration and Power Interface

LED Light Emitting Diode

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

CDM Charged Device Model

PCB Printed-Circuit Board

FET Field-Effect Transistor

MSB Most Signiﬁcant Bit

LSB Least Signiﬁcant Bit

Product data sheet Rev. 08 — 22 October 2009 32 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

18. Revision history

Table 20. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9555_8 20091022 Product data sheet - PCA9555_7

Modiﬁcations: •Table 2 “Ordering options”, Topside mark for TSSOP24 package, PCA9555PW, is changed from

“PCA9555PW” to “PCA9555”

•Figure 13 “Read Input port register, scenario 1” modiﬁed

•Figure 14 “Read Input port register, scenario 2” modiﬁed

•Table 14 “Static characteristics”,Table note [1] modiﬁed (added phrase “for at least 5 µs”)

•updated soldering information

PCA9555_7 20070605 Product data sheet - PCA9555_6

PCA9555_6 20060825 Product data sheet - PCA9555_5

PCA9555_5

(9397 750 14125) 20040930 Product data sheet - PCA9555_4

PCA9555_4

(9397 750 13271) 20040727 Product data sheet - PCA9555_3

PCA9555_3

(9397 750 10164) 20020726 Product data 853-2252 28672 of

2002 July 26 PCA9555_2

PCA9555_2

(9397 750 09818) 20020513 Product data - PCA9555_1

PCA9555_1

(9397 750 08343) 20010507 Product data - -

Product data sheet Rev. 08 — 22 October 2009 33 of 34

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

19. Legal information

19.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

19.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA9555

16-bit I2C-bus and SMBus I/O port with interrupt

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 October 2009

Document identifier: PCA9555_8

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

21. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 6

6.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2.2 Registers 0 and 1: Input port registers . . . . . . . 7

6.2.3 Registers 2 and 3: Output port registers. . . . . . 7

6.2.4 Registers 4 and 5: Polarity Inversion registers . 7

6.2.5 Registers 6 and 7: Conﬁguration registers . . . . 8

6.3 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.4 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.5 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . . 9

6.5.1 Writing to the port registers . . . . . . . . . . . . . . . 9

6.5.2 Reading the port registers . . . . . . . . . . . . . . . 11

6.5.3 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Characteristics of the I2C-bus. . . . . . . . . . . . . 14

7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.1.1 START and STOP conditions . . . . . . . . . . . . . 14

7.2 System conﬁguration . . . . . . . . . . . . . . . . . . . 15

7.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15

8 Application design-in information . . . . . . . . . 16

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 18

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 20

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 21

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22

14 Handling information. . . . . . . . . . . . . . . . . . . . 28

15 Soldering of SMD packages . . . . . . . . . . . . . . 28

15.1 Introduction to soldering. . . . . . . . . . . . . . . . . 28

15.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 28

15.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 28

15.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 29

16 Soldering of through-hole mount packages . 30

16.1 Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

16.2 Soldering by dipping or by solder wave . . . . . 30

16.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 30

16.4 Package related soldering information . . . . . . 31

17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 31

18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32

19 Legal information . . . . . . . . . . . . . . . . . . . . . . 33

19.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 33

19.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33

20 Contact information . . . . . . . . . . . . . . . . . . . . 33

21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34