1. General description
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Output
and Polarity Inversion (active HIGH or active LOW operation) registers. The system
master can enable the I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding Input or Output
register. The polarity of the read register can be inverted with the Polarity Inversion
register. All registers can be read by the system master. Although pin-to-pin and I2C-bus
address compatible with the PCF8575, software changes are required due to the
enhancements, and are discussed in
Application Note AN469
.
The PCA9555 open-drain interrupt output is activated when any input state differs from its
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus. The fixed I2C-bus address of the PCA9555 is
the same as the PCA9554, allowing up to eight of these devices in any combination to
share the same I2C-bus/SMBus.
2. Features
nOperating power supply voltage range of 2.3 V to 5.5 V
n5 V tolerant I/Os
nPolarity Inversion register
nActive LOW interrupt output
nLow standby current
nNoise filter on SCL/SDA inputs
nNo glitch on power-up
nInternal power-on reset
n16 I/O pins which default to 16 inputs
n0 Hz to 400 kHz clock frequency
nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Rev. 08 — 22 October 2009 Product data sheet
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 2 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
nSix packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
PCA9555N DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
PCA9555D SO24 plastic small outline package; 24 leads;
body width 7.5 mm SOT137-1
PCA9555DB SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm SOT340-1
PCA9555PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
PCA9555BS HVQFN24 plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4 ×4×0.85 mm SOT616-1
PCA9555HF HWQFN24 plastic thermal enhanced very very thin quad flat
package; no leads; 24 terminals; body 4 ×4×0.75 mm SOT994-1
Table 2. Ordering options
Type number Topside mark Temperature range
PCA9555N PCA9555 40 °C to +85 °C
PCA9555D PCA9555D 40 °C to +85 °C
PCA9555DB PCA9555 40 °C to +85 °C
PCA9555PW PCA9555 40 °C to +85 °C
PCA9555BS 9555 40 °C to +85 °C
PCA9555HF P55H 40 °C to +85 °C
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 3 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
4. Block diagram
5. Pinning information
5.1 Pinning
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9555
PCA9555
POWER-ON
RESET
002aac702
I2C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
VDD
INPUT/
OUTPUT
PORTS
IO0_0
VSS
8-bit
write pulse
read pulse
IO0_2
IO0_1
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
INPUT/
OUTPUT
PORTS
IO1_0
8-bit
write pulse
read pulse
IO1_2
IO1_1
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
INT
A1
A0
A2
LP filter
VDD
Fig 2. Pin configuration for DIP24 Fig 3. Pin configuration for SO24
VDD
SDA
SCL
A0
IO1_7
IO1_6
IO1_5
IO1_4
IO1_3
IO1_2
IO1_1
IO1_0
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
VSS
PCA9555N
002aac697
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23 INT VDD
A1 SDA
A2 SCL
IO0_0 A0
IO0_1 IO1_7
IO0_2 IO1_6
IO0_3 IO1_5
IO0_4 IO1_4
IO0_5 IO1_3
IO0_6 IO1_2
IO0_7 IO1_1
VSS IO1_0
PCA9555D
002aac698
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 4 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Fig 4. Pin configuration for SSOP24 Fig 5. Pin configuration for TSSOP24
Fig 6. Pin configuration for HVQFN24 Fig 7. Pin configuration for HWQFN24
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
VSS
PCA9555DB
002aac699
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23 VDD
SDA
SCL
A0
IO1_7
IO1_6
IO1_5
IO1_4
IO1_3
IO1_2
IO1_1
IO1_0
VDD
SDA
SCL
A0
IO1_7
IO1_6
IO1_5
IO1_4
IO1_3
IO1_2
IO1_1
IO1_0
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
VSS
PCA9555PW
002aac700
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
002aac701
PCA9555BS
Transparent top view
IO1_3
IO0_4
IO0_5
IO1_4
IO0_3 IO1_5
IO0_2 IO1_6
IO0_1 IO1_7
IO0_0 A0
IO0_6
IO0_7
VSS
IO1_0
IO1_1
IO1_2
A2
A1
VDD
SDA
SCL
terminal 1
index area
613
514
4 15
3 16
2 17
118
7
8
9
10
11
12
24
23
22
21
20
19
INT
002aac881
Transparent top view
IO1_3
IO0_4
IO0_5
IO1_4
IO0_3 IO1_5
IO0_2 IO1_6
IO0_1 IO1_7
IO0_0 A0
IO0_6
IO0_7
VSS
IO1_0
IO1_1
IO1_2
A2
A1
INT
VDD
SDA
SCL
terminal 1
index area
613
514
4 15
3 16
2 17
118
7
8
9
10
11
12
24
23
22
21
20
19
PCA9555HF
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 5 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
5.2 Pin description
[1] HVQFN and HWQFN package die supply ground is connected to both the VSS pin and the exposed center
pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 3. Pin description
Symbol Pin Description
DIP24, SO24,
SSOP24, TSSOP24 HVQFN24,
HWQFN24
INT 1 22 interrupt output (open-drain)
A1 2 23 address input 1
A2 3 24 address input 2
IO0_0 4 1 port 0 input/output
IO0_1 5 2
IO0_2 6 3
IO0_3 7 4
IO0_4 8 5
IO0_5 9 6
IO0_6 10 7
IO0_7 11 8
VSS 12 9[1] supply ground
IO1_0 13 10 port 1 input/output
IO1_1 14 11
IO1_2 15 12
IO1_3 16 13
IO1_4 17 14
IO1_5 18 15
IO1_6 19 16
IO1_7 20 17
A0 21 18 address input 0
SCL 22 19 serial clock line
SDA 23 20 serial data line
VDD 24 21 supply voltage
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 6 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6. Functional description
Refer to Figure 1 “Block diagram of PCA9555”.
6.1 Device address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Fig 8. PCA9555 device address
R/W
002aac219
0 1 0 0 A2 A1 A0
programmable
slave address
fixed
Table 4. Command byte
Command Register
0 Input port 0
1 Input port 1
2 Output port 0
3 Output port 1
4 Polarity Inversion port 0
5 Polarity Inversion port 1
6 Configuration port 0
7 Configuration port 1
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 7 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.2.2 Registers 0 and 1: Input port registers
This register is an input-only port. It reflects the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
6.2.3 Registers 2 and 3: Output port registers
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined
as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
6.2.4 Registers 4 and 5: Polarity Inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Input port 0 Register
Bit 76543210
Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default XXXXXXXX
Table 6. Input port 1 register
Bit 76543210
Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default XXXXXXXX
Table 7. Output port 0 register
Bit 76543210
Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 11111111
Table 8. Output port 1 register
Bit 76543210
Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 11111111
Table 9. Polarity Inversion port 0 register
Bit 76543210
Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 00000000
Table 10. Polarity Inversion port 1 register
Bit 76543210
Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 00000000
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 8 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.2.5 Registers 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At
reset, the device's ports are inputs with a pull-up to VDD.
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset
condition until VDD has reached VPOR. At that point, the reset condition is released and the
PCA9555 registers and SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above VPOR. However, when it is required to reset the part by lowering the power
supply, it is necessary to lower it below 0.2 V.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up to VDD. The input voltage may be raised above
VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of
the Output Port register. Care should be exercised if an external voltage is applied to an
I/O configured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.
Table 11. Configuration port 0 register
Bit 76543210
Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 11111111
Table 12. Configuration port 1 register
Bit 76543210
Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 11111111
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 9 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address and setting the least
significant bit to a logic 0 (see Figure 8 “PCA9555 device address”). The command byte is
sent after the address and determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs.
The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration
Ports. After sending data to one register, the next data byte will be sent to the other
register in the pair (see Figure 10 and Figure 11). For example, if the first byte is sent to
Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, each 8-bit register may be updated independently of the other registers.
At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of I/Os
VDD
I/O pin
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity
inversion
register data
002aac703
FF
data from
shift register
FF
FF
FF
Q1
Q2
VSS
to INT
100 k
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 10 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Fig 10. Write to Output port registers
1 0 0 A2 A1 A0 0 AS0
START condition R/W acknowledge
from slave
002aac220
A
SCL
SDA A
write to port
data out
from port 0
P
tv(Q)
987654321
command byte data to port 0
DATA 0
slave address
00000100
STOP
condition
0.00.7
acknowledge
from slave acknowledge
from slave
data to port 1
DATA 1 1.01.7 A
data out
from port 1
tv(Q)
DATA VALID
Fig 11. Write to Configuration registers
1 0 0 A2 A1 A0 0 AS0
START condition R/W acknowledge
from slave
002aac221
A
SCL
SDA A P
987654321
command byte data to register
DATA 0
slave address
00001100
STOP
condition
LSBMSB
acknowledge
from slave acknowledge
from slave
data to register
DATA 1
LSBMSB
A
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 11 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must first send the PCA9555
address with the least significant bit set to a logic 0 (see Figure 8 “PCA9555 device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte will
then be sent by the PCA9555 (see Figure 12,Figure 13 and Figure 14). Data is clocked
into the register on the falling edge of the acknowledge clock pulse. After the first byte is
read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not acknowledge the data.
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 12. Read from register
AS
START condition R/W
acknowledge
from slave
002aac222
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.) 1 0 0 A2 A1 A0 1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1 0 0 A2 A1 A00 0
data from lower or
upper byte of register
LSBMSB
DATA (last byte)
data from upper or
lower byte of register
LSBMSB
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 12 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read Input Port register).
Fig 13. Read Input port register, scenario 1
1 0 0 A2 A1 A0 1 AS0
START condition
R/W
acknowledge
from slave
002aac223
A
SCL
SDA A
read from port 0
P
987654321
I0.xslave address STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
6543210765432107 65432107 65432107
INT
tv(INT_N) trst(INT_N)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 13 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read Input Port register).
Fig 14. Read Input port register, scenario 2
1 0 0 A2 A1 A0 1 AS0
START condition
R/W
acknowledge
from slave
002aac224
A
SCL
SDA A
read from port 0
P
987654321
I0.xslave address STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
tv(INT_N) trst(INT_N)
DATA 00 DATA 10 DATA 03 DATA 12
DATA 00 DATA 01
th(D)
th(D)
DATA 02
tsu(D)
DATA 03
tsu(D)
DATA 10 DATA 11 DATA 12
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 14 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read (see Figure 13). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16).
Fig 15. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 16. Definition of START and STOP conditions
mba608
SDA
SCL P
STOP condition
S
START condition
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 15 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 17. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 18. Acknowledgement on the I2C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 16 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
8. Application design-in information
Device address configured as 0100 000xb for this example.
IO0_0, IO0_2, IO0_3 configured as outputs.
IO0_1, IO0_4, IO0_5 configured as inputs.
IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.
Fig 19. Typical application
PCA9555
IO0_0
IO0_1
SCL
SDA
VDD
(5 V)
MASTER
CONTROLLER
SCL
SDA
INT IO0_2
VDD
A2
A1
A0
VDD
GND
INT
10 kSUB-SYSTEM 1
(e.g., temp sensor)
IO0_3
INT
SUB-SYSTEM 2
(e.g., counter)
RESET
controlled
switch
(e.g., CBT device)
VDD
A
B
ENABLE
SUB-SYSTEM 3
(e.g., alarm system)
ALARM
IO0_4
IO0_5
IO0_6
10 DIGIT
NUMERIC
KEYPAD
VSS
002aac704
10 k10 k2 k
IO0_7
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 17 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
9. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +6.0 V
VI/O voltage on an input/output pin VSS 0.5 6 V
IOoutput current on an I/O pin - ±50 mA
IIinput current - ±20 mA
IDD supply current - 160 mA
ISS ground supply current - 200 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature 65 +150 °C
Tamb ambient temperature operating 40 +85 °C
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 18 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
10. Static characteristics
[1] VDD must be lowered to 0.2 V for at least 5 µs in order to reset part.
Table 14. Static characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current Operating mode; VDD = 5.5 V; no load;
fSCL = 100 kHz - 135 200 µA
Istb standby current Standby mode; VDD = 5.5 V; no load;
VI=V
SS; fSCL = 0 kHz; I/O = inputs - 1.1 1.5 mA
Standby mode; VDD = 5.5 V; no load;
VI=V
DD; fSCL = 0 kHz; I/O = inputs - 0.25 1 µA
VPOR power-on reset voltage[1] no load; VI=V
DD or VSS - 1.5 1.65 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL = 0.4 V 3 - - mA
ILleakage current VI=V
DD =V
SS 1- +1µA
Ciinput capacitance VI=V
SS - 6 10 pF
I/Os
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VDD = 2.3 V to 5.5 V; VOL = 0.5 V [2] 8 (8 to 20) - mA
VDD = 2.3 V to 5.5 V; VOL = 0.7 V [2] 10 (10 to 24) - mA
VOH HIGH-level output voltage IOH =8 mA; VDD = 2.3 V [3] 1.8 - - V
IOH =10 mA; VDD = 2.3 V [3] 1.7 - - V
IOH =8 mA; VDD = 3.0 V [3] 2.6 - - V
IOH =10 mA; VDD = 3.0 V [3] 2.5 - - V
IOH =8 mA; VDD = 4.75 V [3] 4.1 - - V
IOH =10 mA; VDD = 4.75 V [3] 4.0 - - V
ILIH HIGH-level input leakage
current VDD = 5.5 V; VI=V
DD -- 1µA
ILIL LOW-level input leakage
current VDD = 5.5 V; VI=V
SS -- 100 µA
Ciinput capacitance - 3.7 5 pF
Cooutput capacitance - 3.7 5 pF
Interrupt INT
IOL LOW-level output current VOL = 0.4 V 3 - - mA
Select inputs A0, A1, A2
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
ILI input leakage current 1- +1µA
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 19 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
[2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a
maximum current of 100 mA for a device total of 200 mA.
[3] The total current sourced by all I/Os must be limited to 160 mA.
(1) IOH =8mA
(2) IOH =10 mA (1) IOH =8mA
(2) IOH =10 mA
Fig 20. VOH maximum Fig 21. VOH minimum
VDD = 5.5 V; VI/O = 5.5 V; A2, A1, A0 set to logic 0.
(1) Tamb =40 °C
(2) Tamb = +25 °C
(3) Tamb = +85 °C
Fig 22. IDD versus number of I/Os held LOW
2.0
5.0
4.0
3.0
6.0
VOH
(V)
VDD (V)
2.7 5.53.6
002aac706
(1)
(2)
2.5
3.5
4.5
VOH
(V)
1.5
VDD (V)
2.3 4.753.0
002aac707
(1)
(2)
0
1.2
0.8
0.4
1.6
IDD
(mA)
number of I/Os
002aac705
all 1s all 0sone 0 three 0s
(1)
(2)
(3)
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 20 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
11. Dynamic characteristics
[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] Cb= total capacitance of one bus line in pF.
Table 15. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode I2C-bus Unit
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition 4.7 - 1.3 - µs
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs
tSU;STA set-up time for a repeated START
condition 4.7 - 0.6 - µs
tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 µs
tHD;DAT data hold time 0 - 0 - ns
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - µs
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs
tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns
trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter - 50 - 50 ns
Port timing
tv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 150 - 150 - ns
th(D) data input hold time 1 - 1 - µs
Interrupt timing
tv(INT_N) valid time on pin INT - 4 - 4 µs
trst(INT_N) reset time on pin INT - 4 - 4 µs
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 21 of 34
NXP Semiconductors PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
12. Test information
Fig 23. Definition of timing on the I2C-bus
tSP
tBUF
tHD;STA PP S
tLOW
tr
tHD;DAT
tf
tHIGH tSU;DAT tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
002aaa986
RL= load resistor.
CL = load capacitance includes jig and probe capacitance.
RT= termination resistance should be equal to the output impedance of Zoof the pulse generators.
Fig 24. Test circuitry for switching times
Fig 25. Load circuit
PULSE
GENERATOR
VO
CL
50 pF
RL
500
002aab284
RT
VI
VDD
DUT
VDD
open
GND
CL
50 pF
002aac226
RL
500
from output under test 2VDD
open
GND
S1
RL
500