(M) MOTOROLA NMC 14585B 4-BIT MAGNITUDE COMPARATOR The MC14585B 4-Bit Magnitude Comparator ts constructed with complementary MOS (CMOS} enhancement mode devices, . The circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, AO, BO), three cascading inputs (A<B, A=B, and A>B), and three outputs (A<B, A=B, and A>B), This device compares two 4-bit words (A and B} and determines whether they are less than, equal to, or greater than by a high level on the app- ropriate output. For words greater than 4-bits, units can be cas- caded by connecting outputs (A>B), (A<B}, and (A= 8B) to the corresponding inputs of the next significant comparator. Inputs (A <B), (A=8), and (A>B) on the least significant (first) compa- and controls. Diode Protection on All Inputs Expandable : Applicable to Binary or 8421-BCD Code Supply Voltage Range = 3.0 Vdc to 18 Vdc Schottky TTL Load over the Rated Temperature Range e Can be Cascaded - See Fig. 3 rator are Connected to a low, a high, and a low, respectively. Applications include logic In CPU's, correction and/or detection of instrumentation conditions, comparator in testers, converters, Capable of Driving Two Low-power TTL Loads or One Low-power MAXIMUM RATINGS* (voltages Referenced to Vg) L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX soic ff CASE 751B ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD = =SOIC Ta + 55 to 125C for all packages. *Maximum Ratings are those values beyond which damage to the device may occur. tTemperature Derating: Plastic P and D/DW" Packages: 7.0 mW/C From 65C To 125C Ceramic L" Packages: 12 mWPC From 100C To 126C TRUTH TABLE : INPUTS COMPARING : CASCADING A3>B3 x x x A3=B3| A2>B2 x x A3=B3| A2=B2] A1>B1 x 1 A3 =B3 A2=B2|]A1=81 |] AO>BO A3=B3| A2=B2]A1=81] AO=B0 A3=B3 1 A2=B2]Ai=B1| AO=80 A3=B3{ A2=6821 Ai=B1] AO=B80 A3=83) A2=82]A1=B1] AO=BO0 A3=B3|] A2=B2] A1=B1 i AO<BO A3=83] A2=B2] A1<B1 x A3=B3| A2<B2 x * A3<B3 x x x * OUTPUTS A3, B3 | A2, B2] Al, B1| AO, 80 | A<B | A=B | A>B|A<B|A=8 [A>B| acglooce noo 1 i 1 eooo;= 4 eeocjsce- [Xxx -@==300 Kx Xx |n---:--00 0000 |x xxx @ OO x xk kK x [XK MM XK KX XX K x = DontCare | ! 6-507 Symbo! Parameter Value Unit Vpp |DC Supply Voltage -0,5 to + 18.0 Vv Vins Vout {input or Output Voltage (DC or Transient) -0.5 to Vpn +0.5 Vv tins lout [fneut or Output Current (OC or Transient), per Pin +10 mA Pp Power Dissipation, per Packaget 500 mw Tstg _|Storage Temperature - ~ 85 to +150 C TL Lead Temperature (8-Second Soldering) 260 C BLOCK DIAGRAM 40lA>B) 6 OSA=Bhin 6 Ot IASB), (A> Blout 100-j AO 110| BO 70- Al (A=B) out 9O0 81 20-4 A2 10| B2 (A<Bour 15 OJ Aa 140-j B83 P13 -o 3 -_O12 Voo 2 Pin 16 Vgs = Pin 8 MC14585B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vgg) Characteristi symbol | 22 = Sse are 125C Unit aracteristic mbo! y Vde Min Max Min Typ # Max Min Max Output Voltage "0" Level 5.0 _ 0.05 _ 0 0,05 _ 0.05 Vin = Vpp or 0 VoL 10 _ 0.05 _ 0 0.05 _ 0.05 | Vde 15 _ 0.05 _ 0 0.05 _ 0.05 1 Level 5.0 4.95 _ 4.95 5.0 _ 4.95 _ Vin = 0 or Vpp VOH 10 9.95 _ 9.95 10 9.95 = Vide i5 14.95 _ 14.95 15 _ 14.95 Input Voltage O" Level (Vo = 4.5 or 0.5 Vde} VIL 5.0 _ 1.5 _ 2.25 1.5 _ 1.5 Vde (Vo = 9.0 oF 1.0 Vde) ! 10 _ 3.0 - 4.50 30 | | 30 (Vo = 13.5 or 1.5 Vdc) 16 _ 4.0 - 6,75 4.0 - 4.0 1 Level (Vo = 0.5 or 4.5 Vdc) y 5.0 3.5 - 3.5 2.75 3.5 - Vde (VQ = 1.0 oF 9.0 Vac) lH to | 70 7.0 5.50 ~ | 70} (Vo = 1.5 oF 13.5 Vde} 15 11 - 14 8,25 1 Output Drive Current (VOH = 2.5 Vde) Source 5.0 ~3.0 _ -2.4 -4.2 - -1.7 _ (VOH = 4.6 Vdc) lon 50 | -o64/ -0.51 ] ~0.88 |-036) | mAdc (VOH = 9.5 Vde) 10 -1.6 ~13 | -2.25 _ ~09 | (VOH = 13.5 Vde) 15 -4.2 -3.4 ~8.8 -24 | (VOL = 0.4 Vde) Sink 5.0 0,64 _ 0.51 0.88 _ 0.36 _ (VOL = 0.5 Vdc) _ lot 10 16 1.3 2.25 | o9 | mAde (VOL = 1.5 Vde} 15 42 _ 3.4 8.8 2.4 _ Input Current _ lin 15 _ 0.4 _ +0.00001} +0.1 = 21.0 | pAde Input Capacitance Cin _ _ _- ~ 5.0 _ _ pF (Vin = 0) Quiescent Current lbp 5.0 ~_ 5.0 _ 0.005 5.0 - 150 | pAdc (Per Package) 10 _ 10 _ @.010 10 _ 300 _ ; 15 20 0.015 20 _ 600 Total Supply Current**t tr 5.0 IT = (0.6 nA/KHZ) f + IDp phAdc (Dynamic plus Quiescent, 10 IT = (1.2 wA/KHz) f + Ipp Per Package) 15 Ip = (1.8 pAKH2) f + Ippo (CL = 50 pF on all outputs, all buffers switching) #Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC's potential performance. PIN ASSIGNMENT _ The formulas given are for the typical characteristics only at 25C. - we tTo calculate total supply current at loads other than 50 pF: 1 ce Yoo 16 IT(CL) = I7(80 pF} + (CL ~ 50) Vik 20 a2 arf 15 where: I7 is in 4A (per package), C._in pF, V = (Vpp ~ Ygs) in volts, _ 3 4 ta Bloat as CF 14 fin kHz is input frequency, and k = 0.001, 4 CAs >a, (A>Biou, (5 13 Stace, (A<Blout 5 12 6 CHA eh, eo FS 11 7 Coat ao 5 16 84 vss si Fo9 6-508 MC14585B SWITCHING CHARACTERISTICS* (C= 50 pF, Ta = 25C) Characteristic = Symbol Vpp Min Typ # Max Unit Output Rise and Fall Time = : tTLH - ns tTLH tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 _ 100 200 tTLH. tTHL = (0.75 ns/pF) CL + 12.5 ns 10 _ 50 100 trip: tTHL = (0.55 ns/pF) CG, + 9.5 ns 16 - 40 80 Turn-On, Turn-Off Delay Time | tPLH, ns teLH, tPHL * (1.7 ns/pF) C, + 345 ns tPHL 5.0 - 430 860 tPLH, PHL = (0.66 ns/pF) C) + 147 ns 10 - 180 360 tPLH, tPHL & (0.5 ns/pF) C_ + 105 ns 15 _ 130 260 *The formulas given are for the typical characteristics onty at 26C, . . us #Data labelled Typ is not to be used for design purposes but is Intended as an indication of the IC's potential performance, FIGURE 1 - DYNAMIC POWER DISSIPATION SIGNAL WAVEFORMS FIGURE 2 DYNAMIC SIGNAL WAVEFORMS pe- 20 ns 20 ns Yoo ~VOH {A>Blout { \ Vor (A=Bl out / \ VoL Vou Vou (A<B)out VoL inputs {A >B) and (4=B)} high, and inputs 82, A2, B1, Al, BO, AO and (A< B) low tin respect to a system clack. 20 ns 20 ns v 90% 4 DD BO 50% 10% RB Vss - tPLH PHL v 30% N oH (A<Blout 50% | __F 10% VoL 'TLH +| TH. Inputs {A >8) and (A=B) high, and inputs B3, A3, B2, A2, B1, Al, AO, and {A< 8) low, be left open. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. How- ver, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high- impedance circuit. For proper operation, Vip, and Voyt should be constrained to the range Vgg < (Vin OF Vout) Vpp- Unused inputs must always be tied to an appropriate fogic voltage level (e.g., either Vgg or Vpp). Unused outputs must 6-509 MC14585B FIGURE 3 CASCADING COMPARATORS WORD . _ Los - B= B1t 810 BS BS B87 - BE BS B4 83 B2 B1 BO WoRD A= Alt A10 AS AB Al AG AS AA A3 A2 Al Ao | V<s Vpo ss 83 AS 82 A281 Al BO AO = Ga Output - an v A aos 6s Mc14585B << - 4 Vv A inputs 4 4 = , ; a MC14585B J - - MC145858 s @ = WORD B= B11, B10, =, BO. a & WORD A= A11, A10, --, AO, Outputs 15 LOGIC DIAGRAM Ag se B2 _ Al (A<Blour B1 Ao 80 (AcB) 6 (A=a)} (A=B)in our 4 (4> Aine Po > 8) out 6-510