REGULATING PULSE WIDTH MODULATOR
FEATURES
••
••
•8V to 35V operation
••
••
•5.1V reference trimmed to ±1%
••
••
•100Hz to 500KHz oscillator range
••
••
•Separate oscillator sync terminal
••
••
•Adjustable deadtime control
••
••
•Internal soft-start
••
••
•Input undervoltage lockout
••
••
•Latching P.W.M. to prevent multiple
pulses
••
••
•Dual source/sink output drivers
HIGH RELIABILITY FEATURES
- SG1525A, SG1527A
♦♦
♦♦
♦Available to MIL-STD-883B
♦♦
♦♦
♦MIL-M38510/12602BEA - JAN1525AJ
♦♦
♦♦
♦MIL-M38510/12604BEA - JAN1527AJ
♦♦
♦♦
♦Radiation data available
♦♦
♦♦
♦LMI level "S" processing available
DESCRIPTION
The SG1525A/1527A series of pulse width modulator integrated circuits are
designed to offer improved performance and lower external parts count when used
to implement all types of switching power supplies. The on-chip +5.1 volt reference
is trimmed to ±1% initial accuracy and the input common-mode range of the error
amplifier includes the reference voltage, eliminating external potentiometers and
divider resistors. A Sync input to the oscillator allows multiple units to be slaved
together, or a single unit to be synchronized to an external system clock. A single
resistor between the CT pin and the Discharge pin provides a wide range of deadtime
adjustment. These devices also feature built-in soft-start circuitry with only a timing
capacitor required externally. A Shutdown pin controls both the soft-start circuitry
and the output stages, providing instantaneous turn-off with soft-start recycle for
slow turn-on. These functions are also controlled by an undervoltage lockout which
keeps the outputs off and the soft-start capacitor discharged for input voltages less
than that required for normal operation. Another unique feature of these PWM
circuits is a latch following the comparator. Once a PWM pulse has been terminated
for any reason, the outputs will remain off for the duration of the period. The latch
is reset with each clock pulse. The output stages are totem-pole designs capable
of sourcing or sinking in excess of 200mA. The SG1525A output stage features
NOR logic, giving a LOW output for an OFF state. The SG1527A utilizes OR logic
which results in a HIGH output level when OFF.
BLOCK DIAGRAM
SG1525A/SG2525A/SG3525A
SG1527A/SG2527A/SG3527A
Rev 1.4a 3/19/2005 Microsemi Inc.
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
1(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
Rev 1.4a
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
2(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
Oscillator Charging Current ............................................
Operating Junction Temperature Range
Hermetic (J, L Packages) .....................................
Plastic (N, DW Packages ) .......................................
Storage Temperature Range ..........................
Lead Temperature (Soldering, 10 seconds) .................
Supply Voltage (+VIN) .......................................................
Collector Supply Voltage (VC) ...........................................
Logic Inputs .......................................................
Analog Inputs .......................................................
Output Current, Source or Sink ...................................
Reference Load Current ...............................................
40V
40V
-0.3V to 5.5V
-0.3V to VIN
500mA
50mA
5mA
150°C
150°C
-65°C to 150°C
300°C
ABSOLUTE MAXIMUM RATINGS (Note 1)
Note 1. Values beyond which damage may occur.
Input Voltage (+VIN) ................................................
Collector Voltage (VC) ..........................................
Sink/Source Load Current (steady state) .............
Sink/Source Load Current (peak) .........................
Reference Load Current ........................................
Oscillator Frequency Range .......................
Oscillator Timing Resistor (RT) ........................
8V to 35V
4.5V to 35V
0 to 100mA
0 to 400mA
0 to 20mA
100Hz to 350KHz
2KΩ to 150KΩ
Deadtime Resistor Range (RD) .............................
Maximum Shutdown Source Impedance .........................
Oscillator Timing Capacitor (CT) ...................
Operating Ambient Temperature Range
SG1525A/SG1527A ....................................
SG2525A/SG2527A ......................................
SG3525A/SG3527A .........................................
0Ω to 500Ω
5KΩ
0.001µF to 0.1µF
-55°C to 125°C
-25°C to 85°C
0°C to 70°C
Note 2: Range over which the device is functional.
RECOMMENDED OPERATING CONDITIONS (Note 2)
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1525A/SG1527A with -55 °C ≤ TA ≤ 125°C,
SG2525A/SG2527A with -25°C ≤ TA ≤ 85°C, SG3525A/SG3527A with 0°C ≤ TA ≤ 70°C, and +VIN = 20V. Low duty cycle pulse testing techniques are
used which maintains junction and case temperatures equal to the ambient temperature.)
5.05
5.00
Reference Section TJ = 25°C
VIN = 8V to 35V
IL = 0 to 20mA
Over Operating Temperature Range
Over Line, Load and Temperature
VREF = 0V, TJ = 25°C
10Hz ≤ f ≤ 10KHz, TJ = 25°C
TJ = 125°C
Output Voltage
Line Regulation
Load Regulation
Temperature Stability (Note 3)
Total Output Voltage Range (Note 3)
Short Circuit Current
Output Noise Voltage (Note 3)
Long Term Stability (Note 3)
Min. Typ. Max. Min. Typ. Max.
Note 3. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.
Note 4. FOSC = 40KHz (RT = 3.6KΩ, CT = 0.01µF, RD = 0Ω)
Note 5. Applies to SG1525A/2525A/3525A only, due to polarity of output pulses.
SG3525A
SG3527A
SG1525A/2525A
SG1527A/2527A UnitsTest ConditionsParameter
V
mV
mV
mV
V
mA
µVrms
mV/khr
5.20
30
50
50
5.25
100
200
50
5.10
10
20
20
80
40
20
5.00
4.95
5.15
30
50
50
5.20
100
200
50
5.10
10
20
20
80
40
20
THERMAL DATA
J Package:
Thermal Resistance-Junction to Case, θJC.................. 30°C/W
Thermal Resistance-Junction to Ambient, θJA .............. 80°C/W
DW Package:
Thermal Resistance-Junction to Case, θJC.................. 40°C/W
Thermal Resistance-Junction to Ambient, θJA ............. 95°C/W
L Package:
Thermal Resistance-Junction to Case, θJC.................. 35°C/W
Thermal Resistance-Junction to Ambient, θJA ........... 120°C/W
N Package:
Thermal Resistance-Junction to Case, θJC................... 40°C/W
Thermal Resistance-Junction to Ambient, θJA ............. 65°C/W
Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA).
Note B. The above numbers for θJC are maximums for the limiting
thermal resistance of the package in a standard mount-
ing configuration. The θJA numbers are meant to be
guidelines for the thermal performance of the device/pc-
board system. All of the above assume no ambient
airflow.
RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.)...... 260°C(+0, -5)
Rev 1.4a
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
3(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
18
17
6
Output Drivers Section (each transistor, VC = 20V)
ISOURCE = 20mA
ISOURCE = 100mA
ISINK = 20mA
ISINK = 100mA
VCOMP and VSS = High
VC = 35V
CL = 1nF, TJ = 25°C
CL = 1nF, TJ = 25°C
VSD = 3V, CS = 0, TJ = 25°C
Output High Level
Output Low Level
Undervoltage Lockout
Collector Leakage (Note 5)
Rise Time
Fall Time
Shutdown Delay (Note 3)
50
0.4
0.4
25
Soft-Start Section VSHUTDOWN = 0V
VSHUTDOWN = 2V
VSHUTDOWN = 2.5V
Soft Start Current
Soft Start Voltage
Shutdown Input Current
µA
V
mA
P.W.M. Comparator Section (Note 4)
VCOMP = 0.6V
VCOMP = 3.6V
Zero Duty Cycle
Maximum Duty Cycle
Minimum Duty Cycle
Maximum Duty Cycle
Input Threshold (Note 4)
Input Bias Current
%
%
V
V
µA
0.4
2.2
8
200
600
300
0.5
19
18
0.2
1.0
7
100
50
0.2
37.6
350
1.7
3.0
0.3
1.2
Oscillator Section (Note 4) TJ = 25°C
VIN = 8V to 35V
MIN ≤ TJ ≤ MAX
RT = 150KΩ, CT = 0.1µF
RT = 2KΩ, CT = 1nF
IRT = 2mA
TJ = 25°C
Sync Voltage = 3.5V
Initial Accuracy
Voltage Stability
Temperature Stability (Note 3)
Minimum Frequency (Note 3)
Maximum Frequency (Note 3)
Current Mirror
Clock Amplitude
Clock Width
Sync Threshold
Sync Input Current
Min. Typ. Max. Min. Typ. Max.
SG3525A
SG3527A
SG1525A/2525A
SG1527A/2527A UnitsTest ConditionsParameter
ELECTRICAL CHARACTERISTICS (continued)
KHz
%
%
Hz
KHz
mA
V
µs
V
mA
42.4
±2
±6
150
2.2
1.0
2.8
2.5
40
±1
±3
2.0
3.5
0.5
2.0
1.0
37.6
350
1.7
3.0
0.3
1.2
42.4
±1
±6
150
2.2
1.0
2.8
2.5
40
±0.3
±3
2.0
3.5
0.5
2.0
1.0
Error Amplifier Section (VCM = 5.1V)
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
Gain-Bandwidth Product (Note 3)
Output Low Level
Output High Level
Common Mode Rejection
Supply Voltage Rejection
RL ≥10MΩ, TJ = 25°C
AV = 0dB, TJ = 25°C
VCM = 1.5V to 5.2V
VIN = 8V to 35V
60
1
3.8
60
50
0.5
1
75
2
0.2
5.6
75
60
5
10
1
0.5
60
1
3.8
60
50
2
1
75
2
0.2
5.6
75
60
10
10
1
0.5
mV
µA
µA
dB
MHz
V
V
dB
dB
45
0.6
0
3.6
2.0
49
0.9
3.3
.05
45
0.6
0
3.6
2.0
49
0.9
3.3
.05
80
0.6
1.0
25 50
0.4
0.4
80
0.6
1.0
19
18
0.2
1.0
7
100
50
0.2
18
17
6
0.4
2.2
8
200
600
300
0.5
V
V
V
V
V
µA
ns
ns
µs
Total Standby Current
Standby Current VIN = 35V mA20142014
Rev 1.4a
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
4(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
FIGURE 1 - OSCILLATOR SCHEMATIC
ERROR AMPLIFIER SECTION
FIGURE 3 - OSCILLATOR DISCHARGE TIME VS. RD AND CT
FIGURE 2 - OSCILLATOR CHARGE TIME VS. RT AND CT
FIGURE 5 - ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
FIGURE 4 - ERROR AMPLIFIER
OSCILLATOR SECTION
Rev 1.4a
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
5(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
FIGURE 7 - OUTPUT SATURATION CHARACTERISTICSFIGURE 6 -OUTPUT CIRCUIT (½ Circuit Shown)
APPLICATION INFORMATION
Low power transformers can be driven directly by the SG1525A.
Automatic reset occurs during deadtime, when both ends of the
primary winding are switched to ground.
The low source impedance of the output drivers provides rapid
charging of power FET input capacitance while minimizing exter-
nal components.
For single-ended supplies, the driver outputs are grounded. The
VC terminal is switched to ground by the totem-pole source
transistors on alternate oscillator cycles.
In conventional push-pull bipolar designs, forward base drive is
controlled by R1 - R3 . Rapid turn-off times for the power devices
are achieved with speed-up capacitors C1 and C2 .
OUTPUT SECTION
Rev 1.4a
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
6(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
APPLICATION INFORMATION (continued)
SHUTDOWN OPTIONS
1. Use an external transistor or open-collector comparator to pull
down on the Comp terminal. This will set the PWM latch turning
off both outputs. If the shutdown signal is momentary, pulse-
by-pulse protection can be accomplished as the PWM latch will
be reset with each clock pulse.
2. The same results can be accomplished by pulling down on the
Soft-Start terminal with the difference that on this pin, shutdown
will not affect the amplifier compensation network but must
discharge any Soft-Start capacitor.
3. Apply a positive-going signal to the Shutdown terminal. This
will provide most rapid shutdown of the outputs but will not
immediately set the PWM latch if there is a Soft-Start capacitor.
This capacitor will discharge but with a current of approxi-
mately twice the charging current.
4. The shutdown terminal can be used to set the PWM latch on
a pulse-by-pulse basis if there is no external capacitance on
Soft-Start terminal. Slow turn-on may still be accomplished by
applying an external capacitor, blocking diode, and charging
resistor to the comp terminal. (See SG1524 Application Note).
SG1525A/1527A LAB TEST FIXTURE
Rev 1.4a
Copyright 1996 11861 Western Avenue ∞ ∞
∞ ∞
∞ Garden Grove, CA 92841
7(714) 898-8121 ∞∞
∞∞
∞ FAX: (714) 893-2570
Note 1. Contact factory for JAN and DESC product availablity.
2. All packages are viewed from the top.
CONNECTION DIAGRAMS & ORDERING INFORMATION (See Notes Below)
16-PIN CERAMIC DIP
J - PACKAGE
Ambient
Temperature Range
SG1525AJ/883B -55°C to 125°C
JAN1525AJ -55°C to 125°C
SG1525AJ/DESC -55°C to 125°C
SG1525AJ -55°C to 125°C
SG2525AJ -25°C to 85°C
SG3525AJ 0°C to 70°C
SG1527AJ/883B -55°C to 125°C
JAN1527AJ -55°C to 125°C
SG1527AJ/DESC -55°C to 125°C
SG1527AJ -55°C to 125°C
SG2527AJ -25°C to 85°C
SG3527AJ 0°C to 70°C
Part No.Package Connection Diagram
VREF
+VIN
OUTPUT B
VC
GROUND
OUTPUT A
SHUTDOWN
COMPENSATIONSOFT-START
N.I. INPUT
INV. INPUT
RT
2
3
4
5
6
7
8
1
15
16
14
13
10
9
12
11
CT
DISCHARGE
SYNC
OSC. OUTPUT
SG2525AN -25°C to 85°C
SG3525AN 0°C to 70°C
SG2527AN -25°C to 85°C
SG3527AN 0°C to 70°C
16-PIN PLASTIC DIP
N - PACKAGE
2
3
4
5
6
7
8
VREF
+VIN
SHUTDOWN
COMPENSATION
N.I. INPUT
INV. INPUT
RT
15
16
14
13
10
9
12
11
1
SOFT-START
OUTPUT B
VC
GROUND
OUTPUT A
CT
DISCHARGE
SYNC
OSC. OUTPUT
20-PIN CERAMIC
LEADLESS CHIP CARRIER
L- PACKAGE 4
5
6
7
8
321
9 11121310
14
15
16
17
18
20 19 11. N.C.
12. COMP.
13. SHUTDOWN
14. OUTPUT A
15. GROUND
16. N.C.
17. VC
18. OUTPUT B
19. +VIN
20. VREF
1. N.C.
2. INV. INPUT
3. N.I. INPUT
4. SYNC
5. OSC. OUTPUT
6. N.C.
7. CT
8. RT
9. DISCHARGE
10. SOFT-START
SG1525AL/883B -55°C to 125°C
SG1525AL -55°C to 125°C
SG1527AL/883B -55°C to 125°C
SG1527AL -55°C to 125°C
16-PIN WIDE BODY
PLASTIC S.O.I.C.
DW - PACKAGE
SG2525ADW -25°C to 85°C
SG3525ADW 0°C to 70°C
SG2527ADW -25°C to 85°C
SG3527ADW 0°C to 70°C
N Package: RoHS Compliant / Pb-free Transition DC: 0503
N Package: RoHS / Pb-free 100% Matte Tin Lead Finish
DW Package: RoHS Compliant / Pb-free Transition DC: 0516
DW Package: RoHS / Pb-free 100% Matte Tin Lead Finish
