(S) MOTOROLA MC14516B BINARY UP/DOWN COUNTER The MC14516B synchronous up/down binary counter is constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. . . -. 7 This counter can be preset by applying the desired value, in binary, to the Preset inputs (PO, P1, P2, P3) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a fow (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input. Cascading can be accomplished by connecting the Carry Out to the Carry Inof the next stage while clocking each counter in parallel. The outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the reset (R) pin. . This CMOS counter finds primary use in up/down and difference counting. Other applications include: (1) Frequency synthesizer appli- cations where low power dissipation and/or high noise immunity is de- sited, (2) Analog-to-digital and digital-to-analog conversions, L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX 6 solic CASE 751B and (3) Magnitude and sign generation. ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD = SOIC Ta = -55 to 125C for all packages. Diode Protection on Ail Inputs Supply Voltage Range = 3.0 Vde to 18 Vdc Internally Synchronous for High Speed @ Logic Edge-Clocked Design - Count Occurs on Positive Going Edge of Clock @ Single Pin Reset Asynchronous Preset Enable Operation @ Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to Vgg) Symbol Parameter Value Unit Vop Oc Supply Voltage 0.5 to + 18.0 Vv Vin: Vout | input or Output Voltage (DC or Transient) ~0.5 to Vop +0.5 v line faye | input or Output Current (DC or Transient), per Pin #10 mA Pp Power Dissipation, per Packaget 500 mw Tstg Storage Temperature -65 to +150 C TL Lead Temperature (8-Second Scldering) 260 c Maximum Ratings are those values beyond which damage to the device may occur. tTemperature Derating: Plastic "P and D/DW" Packages: ~ 7.0 mW/C From 65C To 125C Ceramic L Packages: ~ 12 mWPC From 100C Te 125C TRUTH TABLE BLOCK DIAGRAM 1O- PE Q0-o 6 5 o4 Carry In. 8 o+ Resat Qi-o it 40 O} Up/Down 15 Om4 Clock Q2r-0 14 4 o~-1 Po 1204 P1 aQ3-0 2 130-] P2 30-1P3 Catt} ig Vpp = Pin 16 Vsgs = Ping Preset Carry tn Up/Down Enable Reset Clock Action 1 x Qo oO x No Count This device contains protection circuitry to 0 1 oO 9 Y_ Count Up guard against damage due to high static 0 0 0 0 _7 | Count Down voltages or electric fields. However, precau- tions must be taken to avoid applications of x x 1 0 x Praset any voltage higher than maximum rated voltages to this high-impedance circuit. For x x x 1 x Reset Proper operation, Vin and Voyt should be X = Don't Care constrained to the range Vss = (Vin or Note: When counting up, the Carry Out signal is normally high and is low only when QO through Q3 are high and Carry In is low. When counting down, Garry Out is low only when QO through O3 and Carry In are low. Vout) = Vpop- Unused inputs must always be tled to an ap- propriate logic voltage level (e.g., either Vss or Vpp). Unused outputs must be teft open. 6-280MC714516B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vgs)_ - oe Vpp 55C 25C 125C . Characteristic Symbo! | vdco 7 = = - Unit Min Max Min Typ # Max Min Max Output Voltage 0 Level 5.0 -] 0.05 - 0 0.05 _ 0.05 Vin = Vop oro VoL 10 - | 0.05 0 0.05 | - | 0.05 | Vde 16 =! 0,05 _ 0 0.05 -_ 0,05 1 Level 5.0 4.95 _ 4.95 5.0 _ 4.95 _- Vin = Oor Vpp VOH 10 | 9.95 9.95 10 --| 995 | - | Vde 15 14.95 _ 14.95 15 -=| 14.95 _ Input Voltage oO Level (Vo = 4.5 or 0.5 Vde) VIL 5.0 _ 1.5 _ 2.25 15 _ 15 Vide (VQ = 9.0 or 1.0 Vde) 10 _ 3.0 _ 4.56 3.0 _ 3.0 (Vo = 13.5 or 1.5 Vdc) 15 _- 4.0 _ 6.75 4.0 _ 4.0 1 Level (Vo = 0.5 or 4.5 Vde) Vv 5.0 3.5 _ 3.5 2.75 3.6 _ Vde (VQ = 1.0 or 9,0 Vdc) - IH 0 | 7o ] 7.0 5.50 -| 7o | (Vo = 15 or 13.5 Vdc) 15 a oF 8.25 _ 1 Output Drive Current {(VOH = 2.5 Vdc) Source 5.0 -~3.0 _ -2.4 ~4.2 _ -17 _ (YOK = 4.6 Vdc) low 5.0 | -064| | -0.51 | -0.86 | -036] | mAde (VOH = 9.5 Vde) 10 -1.6 _ ~41.3 - 2.25 - -0.9 _ (VoH = 13.5 Vdc) 16 | -42 | -3.4 ~8.8 - -24, (VoL = 0.4 Vde) Sink 5.0 0.64 _ 0.51 0,88 _ 0.36 - (VoL = 0.5'Vde) lot 10 1.6. _ 13 2.25 _ 0.9 | mAdc (VOL _= 1.5 Vde) a 16 42 _ 3.4 8.8 |] 24 - Input Current . lin 15 _ 20.1 -4|+#0,00001; 40.1 - +1.0 | wAdc Input Capacitance - Cin _ _ _ _-- 5.0 7.5 _ _ pF (Vin = 9) Quiescent Current lop 5.0 _ 5.0 - =| 0,005 5,0 _- 150 | wAde (Per Package) 10 10 _- 0.010 10 _ 300 15 20 _ 0.015 20 - 600 Total Supply Current**t Ir 5.0 Iz = (0.58 pAVKHz) f + IDpD BAdc (Dynamic plus Quiescent, 10 ir = (1.20 pAVkKH2) f + Ipp Per Package) 15 = (1.70 pAVKHz) f + Ipp (CL = 50 pF on all outputs, all buffers switching) #Data labelied Typ is nat to be used for design purposes but is intended as an indication of the IC's potential performance. PIN ASSIGNMENT The formulas given are for the typical characteristics only at 25C. . al 1 coyere Vopr 16 {To calculate total supply current at loads other than 50 pF: - I7(CL) = 17050 pF Cc 50) Vfk 203 ce hy f ter pak nog ey Vss) in vol 3 PS al where: {7 is in #A (per package), CL in p' DD Vgss) in volts, f in kHz is input frequency, and k = 0.001 _ 4 = PO Pee 13 6 Carry in Pi 12 6 a0 acs 7 CoGarry Out V/O 3 10 8 vss RC 49 6-281SWITCHING CHARACTERISTICS* (c,_=50 pF, Ta = 25C) MC14516B Ali Types Characteristic Symbol Vpp Min Typ # Max Unit Output Rise and Fall Time tTLH ns tro: trHi.= (1-5 ns/pF) C_ +25 ns tTHL 5.0 100 200 | TLH> tTHL = (0.75 ns/pF) C+ 12,5 ns 10 _- 50 100 tTLH: tTHL = (0.55 ns/pF) C_ + 9.5 ns 15 _ 40 80 Propagation Delay Time 'pLH, ns Clock to Q PHL tpey: tPHL = (1.7 ns/pF) Cy + 230 ns 5.0 _ 315 630 tpeH tPHL = (0.66 ns/pF) Cr + 97 ns 10 _ 130 260 tpLH tPHL = (0.5 ns/pF) CL + 75 ns 15 _ 100 200 Clock to Carry Out Oo teLH, ns tPLH: tPHL = (1.7 ns/pF) CL + 230 ns tPHL 5.0 ~ 315 30 tPLH: (PHL = (0.66 ns/pF} C_ + 97 ns 10 ~ 130 250 tpLH: tpHL = (0.5 ns/pF) Cy + 75 ns 15 _ 100 200 Carry In to Carry Out : 'PLH, ns tpLH tPHL = (1.7 ns/pF} CL + 230 ns tPpHL 5.0 - 180 360 tPLH> tpHL = (0.66 ns/pF) C, + 97 ns 10 _ 80 160 tPLH) tPHL = (0.5 ns/pF) CL + 75 ns 15 = 60 120 Preset or Reset to Q teLH, ns tPLH: tPHL = (1.7 ns/pF) Cy + 230 ns tout 5.0 - 315 630 tPLH: tPHL = (0.66 8/pF) Cy + 97 ns 10 - 130 360 tPLH (PHL = (0.8 ns/pF) CL + 75 ns 15 - 100 200 Preset or Reset to Carry Out tpLH, ns tpLHy (PHL = (1.7 ns/pF) Cy + 465 ns tPHL 5.0 - 550 1100 tpLH tPHL = (0.66 ns/pF) CL + 192 ns 10 _ 225 450 tPpLH. tpHL = (0.5 ns/pF) C, + 125 ns 18 _ 150 300 Reset Pulse Width tw 5.0 380 190 _- ns 10 200 100 _ 15 160 80 _ Ciock Pulse Width - _ tWH 5.0 350 200 _ ns 10 170 100 _ 15 140 75 _ Clock Pulse Frequency fol 5.0 _ 3.0 1.5 MHz 10 =- 6.0 3.0 15 _ 8.0 4.0. Preset or Reset Removal Time tram 5.0 650 325 _ ns The Preset or Reset signal must be low prior to a 10 230 115 positive-going transition of the clock. 15 180 90 _ Clock Rise and Fall Time ~ - tTLH: 5.0 _ --- 15 aS 'THL 10 _ - 5 16 _ _- 4 Setup Time tep 5.0 260 130 - ns Carry In to Clock 10 120 60 _ 15 100 50 _ Hold Time ~ th 8.0 0 ~ 60 _ as Clock to Carry In 10 20 -20 _ 15 20 0 _ Setup Time tsu 5.0 500 250 ns Up/Dewn to Clock 10 200 100 _ 1& 150 75 _ Hold Time th 5.0 -70 - 160 ns Clock to Up/Down 10 -10 -60 _ 15 0 ~40 Setup Time tsu 5.0 ~40 - 120 _ RS Pn to PE 10 =30 -760 _ 15 = 25 -50 _ Hold Time . - th 5.0 480 249 - ns PE to Pn 10 420 210 _ 15 420 210 _ Preset Enable Pulse Width tw 5.0 200 100 _ ns 10 100 50 _ 15 80 40 _ The formulas given are for the typical charactaristics only at 25C. #Data labelled "Typ" is not to be used for design Purposes but is intended as an indication of the IC's potential performance, 6-282MC14516B FIGURE 1 POWER DISSIPATION TEST CIRCUIT AND WAVEFORM Up/Down Clock ag Pulse {Generator IY Preset Enable 1 Clock 15 Sarry Gut 7 o- Carryin & Up/Down 10 TOGGLE FLIP-FLOP Farailelin o ope? G- eCc oT at CL re 20 ns Yoo Clock 10% Ves Variable Width LOGIC DIAGRAM PO Qo P41 at P2 Q2 PS a3 4 6 12 41 13 14 3 2 FLIP-FLOP FUNCTIONAL TRUTH TABLE _ PRESET ENABLE CLOCK T One oe 1 x x Parailel in 0 a 0 Qn 0 a 1 a, - 0 _ x Qn X = Don't Care 6-283MC14516B FIGURE 2 SWITCHING TIME WAVEFORMS tram a th _ toy _ Carry En or Vop Up/Down NO vss Clock 50% i \ f \ DD 7 = i" Vss IF w(t) ===== Voo Preset Enable Vss | Carry Gut only Qg or Carry Out 4 tTLH ! 90% You + 10% 9, Reset 50% 30% 10% tTHL 'PLH trem --| Yop 4 Voi L ) FP IPHL . ~ PL PIN DESCRIPTIONS INPUTS PO, Pt, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) Data on these inputs is loaded into the counter when PE is taken high. . Carry In, (Pin 5) This active-low input is used when cascading stages. Carry In is usually connected to Carry Out of the previous stage. While high, Clock is inhibited. Clock, (Pin 15) Binary data is incremented or decremented, depending on the direction of count, on the positive transition of this input. OUTPUTS Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) Binary data is present on these outputs with QO corre- sponding to the least significant bit, arr ut, (Pin 7) Used when cascading stages, Carry Sit is usually connected to Carry In of the next stage. This synchronous output is active low and may also be used to indicate termina! count. CONTROLS PE, Preset Enable, (Pin 1) Asynchronously loads data on the Preset Inputs. This pin is active high and in- hibits the clock when high. R, Reset, (Pin 9) Asynchronously resets the Q out- puts to a low state. This pin is active high and inhibits the clock when high. Up/Down, (Pin 10) Controls the direction of count, high for up count, low for down count. SUPPLY PINS Vss, Negative Supply Voltage, (Pin 8) This pin - Is usually connected to ground. Vpp, Positive Supply Voltage, (Pin 16) This pin is connected to a positive supply voltage ranging from 3.0 valts to 18.0 volts. ; 6-284MC14516B FIGURE 3 PRESETTABLE CASCADED 8-BIT UP/DOWN COUNTER ao ai a2 a3 a4 Qs ae ar Preset Enable O= Count Qo ai Q2 a3 | Qo Qi Q2 a3 Pe PE 1 = Preset a ___ , LS Cour Cin Sour Terminal Count = Clock LSD. . _} etock M.S.D. ndicator = MC14516B MC14516B eve u/B u/o O~ Down 4R R PO Pq P2 P3 PO Pt P2 P3 PO POA I PO Pq | P2 P3! , P4 ' PS P6 p7E, I*Vop I*Vbp Thumbwheel Switches (open for 0") Resistors = 10 k22 Clock (= _ VE Rest | . Open = Count Note: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant Digit (M.S.D.) is disabled while Cinq is high. When the count of the L.S.D. reaches 0 (count down mode} or reaches 15 {count up mode), Gout goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count. (See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated. 6-285MC14516B TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8-BIT UP/DOWN COUNTER 1asoy eo | | tose it ' : | a)qguy jesald | | | | | | | ll. { | | | | | | ; | | | | | i | | | Sd | | EL | wh | Sb] OF | 2b] ot] Gt] et] 2b | ob] Sed ont ep | | | | wesey (as) NO Aueg b G Ssi rS2|esz] ose qunog oD Lo Zz o rd se) 95 0 (asw) ING Aneg Gd i @d d rd Se 9d d ad (asw) uj Aueg uaodsdn 49019 6-286MC14516B FIGURE 4 PROGRAMMABLE CASCADED FREQUENCY DIVIDER fout Buffer cy, : : a Cout Clock M.S.0. MC14516B6 Clack Ls Dp. MC14516B P1 P2 Pt P2 *Vop Thumbwhee! Switches {Open for ''0"'} *Vpoo Clock {fj_) _Sre *Voo Open = Count Resistors = 10 22 fin = out Note: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example, the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs PO to P7. For this divide operation, both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided. 6-287(S) MOTOROLA MC14517B @ Fully Static Operation e e Clock Input DUAL 64-BIT STATIC SHIFT REGISTER The MC14577B6 dual 64-bit static shift register consists of two identical, independent, 64-bit registers, Each register has separate clock and write enabie inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, regardless of the state of the write enable input. An output is disabled {open circuited) when the write enable input is high. During this time, data appearing at the data input as well as the 16-bit, 32-bit, and 48-bit taps may be entered into the device by application of a clock pulse. This feature permits the register to be loaded with 64 bits in 16 clock periods, and also permits bus logic to be used. This device is useful in time delay circuits, temporary memory storage circuits, and other serial shift register applications, Diode Protection on Ali Inputs Output Transitions Occur on the Rising Edge of the Clock Pulse | Exceedingly Siow Input Transition Rates May Be Applied to the 3-State Output at 64th-Bit Allows Use in Bus Logic Applications @ Shift Registers of any Length may be Fully Loaded with 16 L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXxXBDW SOIC Clock Pulses TA = ~58 to 125C for all packages. Supply Voltage Range = 3.0 Vdc to 18 Vide . Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range . PIN ASSIGNMENT MAXIMUM RATINGS (Voltages reterenced to Vgs) Na Symbol , y Parameter Value Unit i tate, Vpp ta 16 Vop {DC Supply Voltage -0.5 to + 18.0 Vv 2 4 04s, O16, 3 16 Vins Vout | Input or Output Voltage (DC or Transient) 70.5 to Vop +0.5 v 3 4 Wea, o48,-214 line lout [input or Output Current (DC or Transient), per Pin #10 mA 475, WE, F213 Pp _{Power Dissipation, per Package+ 500 mw 5 Casa, CgFa t2 Tstg [Storage Temperature ~ 65 to +150 C & Co as2, O64, 411 7 7g Jo TL Lead Temperature (8-Second Soldering) 260 *c 8 Pa O32 9 Vv. Do Maximum Ratings are those values beyond which damage to the device may occur, Ss 8 fTemperature Derating: Plastic P and D/DW" Packages: - 7.0 mW/C From 65C To 125C Ceramic L. Packages: - 12 mWPC From 100C To 125C WAITE CLOCK |JENABLE DATA 16-BIT TAP 32-BiT TAP 48-BiT TAP 64-BIT TAP x Content of 16-Bit | Content of 32-Bit | Content of 48-Bit Content of 64-Bit Cispiayed Displayed Displayed Dispisyed 1 x High Impedance High Impedance High !mpedance High Impedance Content of 16-Bit | Content of 32-Bit | Content of 48-Bit | Content of 64-Bit FUNCTIONAL ' o x Displayed Disptaved Displayed Displayed TRUTH TABLE 1 1 x High Impedance High Impedance High impedance High Impedance Sr 0 Data antered| Content of 16-Bit | Content of 32-Bit Content of 48-Bit | Content of 64-Bit into 1st Bit Displayed Displayed Displayed Displayed Date entered Data at tap Data at tap Data at tap S 1 into 1st Bit |entared into 17-Bit| entered into 33-Bit] entered into 49-Bit| High Impedance A x Content of 16-Bit | Content of 32-Git| Content of 48-Bit Content of 64-Bit Displayed Cisptayed Displayed Olep layed ~L 1 x High impedance High Impedance High Impedance High Impedance X = Don't Care 6-288MC14517B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vg) Characteristi symbol | YOD = 85C | zc vee Unit aracteristic mbol ee " Vde |~in | Max | Min | Typ | Max | Min | Max Output Voltage 0 Level 5.0 _ 0.05 _ 0 0.05 _ 0.05 Vin = Vpp or 0 VOL 10 0,05 - 0 005 | 0.05 | Vdc 15 _ 0.05 _>: 0 0.05 _ 0.05. 1 Level 5.0 4.95 _ 4.95 5.0 _: 4.95 _ Vin = Cor Vop Vou |. 10 | 9.95 _ 9.95 10 _ 995 | | Vde 15 14.95 _ 14.95 15 _ 14.95 _ Input Voltage O" Level (Vo = 4.5 or 0,5 Vde) VIL 5.0 _ 1.5 _ 2.25 1.5 _ 1.5 Vde (VQ = 9.0 or 1.0 Vdc) 10 _ 3.0 .- 4,50 3.0 _ 3.0 (Vo = 13.5 or 15 Vde) 15 4.0 _ 6.75 4.0 _ 4.0 "1" Level (Vo = 0.5 or 4.5 Vdc) a ; VK 5.0 3.5 _ 3.5 2.75 _- 3.5 _ Vde (VQ = 1.0 or 9.0 Vde} 10 7.0 _ 7.0 5.50 _ 7.0 (Vo = 1.5 or 13.5 Vdc) 15 11 - "1 8.25 _ 11 _ Gutput Drive Current (VOH = 2.5 Vde) Source 5.0 -3.0 _ -2.4 -4.2 _ -1.7 _ (VOH = 4.6 Vdc) low 5.0 | -0.64, | -0.51] -0.88 |-o36] | made (VOH = 9.5 Vde) 10 | -16] -1.3 ) -2.25 |} -o9; (VoH = 13.5 Vde) 15 | -42 | . | -34 ~8.8 _ -24, (VoL = 0.4 Vde) Sink 5.0 0.64 0.51 0.88 0.36 (VOL = 0.5 Vdc) loL 10 1.6 _ 1.3 2.25 - _ 0.9 - mAdc (VoL = 1.5 Vde) 15 4.2 3.4 88 2.4 _ Input Current lin 15 _ +01 _ +0,00001| +0.1 _ 1.0 | Ade Input Capacitance Cin _ _ _ _ 5.0 7.5 _ _ pF (Win = 9) Quiescent Current lbp 5.0 _ 5.0 - 0.005 5.0 _- 150 | wAdc (Per Package) 10 _ 10 _ 0.010 10 _ 300 . 15 _ 20 -} 0,015 20 _ 600 / Total Supply Current"*t ly 5.0 iu = (4.2 pA/KHz) f + Ipp pAde (Dynamic plus Quiescent, 10 = (8.8 pA/KHz)f + IDD Per Package) 15 = (13.7 wA/KHz) f + IDD (CL = 50 pF on all outputs, all buffers switching) Three-State Leakage Current Ith is | | +01 | |<o.00001] 0.1 | | =3.0 | wAde #Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC's potential performance. _ _. **The formulas given are for the typical characteristics only at 25C. To calculate tota) supply current at loads other than 50 pF: t7(50 pF) + (CL 50) Vik (CL) = This device contains protection circuitry to where: IT is in wA (per package), Cy in pF Vv = (VpD - vss) i in volts, f in kHz is input frequency, and k = 0. 004 6-289 guard against damage due to high static voltages or electric tields. However, precau- tions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Voy should be constrained to the range Vgs = (Vin or Vout) = Vpp- Unused inputs must always be tied to an ap- propriate logic voltage level (e.g., either Vgg or Vpp). Unused outputs must be left open.MC14517B SWITCHING CHARACTERISTICS* (CL ~ 50 pF, Ta = 25C) Characteristic , Symbo! Vop Min Typ # Max Unit ; - Output Rise and Fall Time - tTLH THLE ns tTLH. tTHL = (1.5 ns/pF) CL + 25 ns 5.0 . 100 200 tTLH. THL = (0.75 nsipF) Cr + 12.5 ns 10 _- 50 100 TLH: tTHE = (0.55 ns/pF) CL + 9.5 ns 15 - 40 80 Propagation Delay Time 'PLH. (PHL ns tPLH: PHL = (1.7 ns/pF) CL + 390 ns 5.0 > 475 770 tPLH. tPHL = (0.66 ns/pF} CL + 177 ns 10 _ 210 300 tPLH. (PHL = (0.5 ns/pF) CL + 115 ns 15 _- 140 215 _ Clock Pulse Width - tWH 5.0 330 170 ns 10 125 75 _ 15 100 0 _ Clock Pulse Frequency tet 5.0 __ 3.0 15 MHz 10 - 67 40 15 8.3 53 _ Clock Pulse Rise and Fali Time tfLH {THLE 5.0 _ 10 *See Note 15 Data to Clock Setup Time : tsu 5.0 6 ~40 _ ns 10 10 -15 - ; oo 15 15 0 _ __ Data to Clock Hold Time th 5.0 150 75 _ ns 10 75 25 -- oa: 15 35 10 - Write Enable to Clock Setup Time {su 5.0 400 170 _ ns : 10 200 65 _ 15 140 50 - = i Write Enable to Clock Release Time. ~ trel 5.0 380 160 _- ns 10 180 55 _ 15 100 40 _-- * The formutas given are for the iypical characteristics only at 25C. - a = # Data labelled Typ is not to be_used for design Purposes but is intended as an indication of the IC's potential performance, * When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall time of the data outputs, driving data inputs, plus the Propagation delay of the output driving stage. 5 FIGURE 1 POWER DISSIPATION TEST CIRCUIT AND WAVEFORM e Yoo CL | 2 ilk REPETITIVE WAVEFORM DO op Q16 032 Q48 ase : Vop co OIC o -O] WE WOE ) << & 8 0 th o fc (f = 1/2 to) ~ ro AY cdededed : 50 pF AN (0) t t t t . 6-290FIGURE 2 TYPICAL OUTPUT SOURCE CURRENT CHARACTERISTICS TEST CIRCUIT Vout = VOH Vpp = Yes Voo Ves Qi6 Q32 048 G64 Q16 Q32 048 064 eoO-1D D OC c WE -O-j WE 4 4 o 9 9 e-oD o LOC . c -o we ou WE Q16 032 048 064 Q16 Q32 Q48 a64 6 External OO b Power i dVss Suppiy Vss MC14517B FIGURE 3 TYPICAL OUTPUT SINK CURRENT CHARACTERISTICS TEST CIRCUIT (Output being tested should be in the high-togic state). Vout = You Oo mm i ee C External Power Supply FIGURE 4 AC TEST WAVEFORMS {Output being tested should be in the low logic state). my TWH twe Pe V oo Pin No's 1 2 16 7 18 19 90% 33 on 10% Vv Clock 4 (12) ----- 5 aore ss Trel OO v - Write 3413) DD tan tho & Vss teul = e- teud -we 20 n6 . Yoo Data In ? (9) \ 7 \ ata ln tht, 50% Vss Poo ; teu bw bh *su0 Vop Yop 16-bit output 1(18) thoes , = 17-bit input tht] . Vss eo Th be 20ns HL *THL teu be tu Yop teLH So Vou Voo --- 32-bit output 6 (10) th tho 50% \ 33-bit input 1 10% { te aa 20ns tp oan Trane Vss teu aaa P= Teud Vpp HL =| _ tH voy - 4 Von 48-bit output 2 (14) tho y 49 bit input VoL Vss 20 ns _ wih tTHL -_ ee eee _ -- Voo 64 bit output 5(J 1) v eee vss betT LH | tro EXPANDED BLOCK DIAGRAMI{1/2 OF DEVICE SHOWN) clock oo ---4% . = + ~-- --- Datao|>o Dp afro oft4o atettin oattyp ote oat tim ~~ atetin ~s at +o 4c 1 c 2 Cc 16 c Ww Cc 32 c 33 Cc 48 IC 49 Cc 64a 3-State WE 3Stete WE 3-State 7 WE 3-State Write _-- ! [ - [ [ it [ Enable . " T oe T sae 7a Write Enable = 0, 16-bit output 32-bit output 48-bit output 64-bit output Write Enable = 1, 17-bit input 33-bit input 6-291 49-dit input High Impedance(A) MOTOROLA MC14518B MC14520B DUAL UP COUNTERS The MC14518B dual BCD counter and the MC14520B dual bi- nary counter are constructed with MOS P-channel and N-channel! enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4- stage counters, The counter stages are type D flip-flops, with inter. changeable Clock and Enable lines for incrementing on either the positive-going or negative-going transition as required when cascad- ing multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the MC 145 18B will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multi-stage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. Diode Protection on All Inputs Supply Voltage Range = 3.6 Vdc to 18 Vde Internally Synchronous for High Internal and External Speeds Logic Edge-Clocked Design Incremented on Positive Transition of Clock or Negative Transition on Enable Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to Vgs) L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX 16 ee Soic CASE 751G 1 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC Ta = ~55 to 125C for all packages. Symbol Parameter Value Unit Yop DC Supply Voltage -0.5 to + 18.0 v Vin Vout | 'nput or Output Voltage (DC or Transient) 9.5 106 Vpp +0.5 Vv lin lout [Input or Output Current (DC or Transient), per Pin +10 mA Pp Power Dissipation, per Packaget 500 mw Tstg |Storage Temperature - 65 to +150 C Th Lead Temperature (8-Second Soldering) 260 C "Maximum Ratings are those values beyond which damage to the device may occur, {Temperature Derating: Plastic "P and D/DW" Packages; - 7.0 mW*C From 65C To 125C Ceramic "L" Packages: 12 mW/C From 100C To 125C TRUTH TABLE CLOCK | ENABLE | RESET ACTION _/ 1 0 Incremant Counter Increment Counter _~.. x No Change x _/_ 0 No Change _/ oa 9 No Change 1 _~. a No Change x x 1 Q0 thru Q3 =O X = Gon't Care BLOCK DIAGRAM Ctock aoto 3 c Q1iro 4 2 Q2----O 5 Enable a3 6 R 7 o_________]} a Clock ao o11 9 aip-o 12 10 a2;o 13 Enable as}o 14 BR 15 . Vop ~ Pin 16 Vsggt Pin & This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precau- tlons must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For Proper operation, Vin and Voyt should be constrained to the range Vss = (Vin or Vout) Vpp- Unused inputs must always be tied to an ap- propriate logic voltage level (e.g., either Vss or Vpp). Unused outputs must be left open. 6-292MC14518BeMC14520B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vgs) 25C . Vpp 55C 125C Characteristic Symbol | yde 7 Unit Min Max Min Typ # Max Min Max Output Voltage ~ 0 Level 5.0 -| 0,05 _ 0 0.05 _ 0.05. Vin = Vpp or 0 VOL 10 -| 0.05 _- 0 0.05 | | 0.05 | Vde 15 = 0.05 _ 0 0.05 _ 0.05 1 Level 5.0 4.95 _ 4.95 5.0 _ 4.95 _ Vin = 0 or Vpp VOH 10 9.95 - 9.95 . 10 _ 9.95 Vde 15 14.95 _ 44.95 15 _ 14,95 Input Voltage oO Level (VQ = 4.5 or 0.5 Vdc) Vv 5.0 -| 15 - 2.25 15 _ 15 | Vado (Vo = 3.0 or 1.0 Vde) IL 10 3.0 4.50 30 | 3.0 (Vo = 13.5 or 1.5 Vde) 15 _ 4.0 - 6.75 4.0 - 4.0 "1" Level (Vo = 0.5 or 4.5 Vdc) - Vv 5.0 3.5 _ 35 2.75 _ 3.5 _ Vde (Vg = 1.0 or 9.0 Vd) IH 10 | 7.0 7.0 5,50 | 70] (Vo = 1.5 or 13.5 Vdc) 15 11 _ 1 8.25 _ 11 _ Output Drive Current (VOH = 2.5 Vde) Source 5,0 -3.0 _ 2.4 ~4.2 _ -1.7 _ (VOH = 4.6 Vdc) lou 5.0 - 0.64 _ -0.51 | ~0.88 _ -0.36/ mAdc (VoH = 9.5 Vde) 10 ~ 1.6 - -13 - 2.25 _ -09 _ (VOH = 13.5 Vde) 15 ~4.2 = -3.4 ~8.8 _ -24} (VoL = 0.4 Vde) Sink 5.0 | 0.64 _ 0.51 0.88 | o36} (VOL = 0.5 Vdc) - lot 10 1.6 _ 1.3 2.25 - 0.9 | made (VOL = 1.5 Vde) 15 42 3.4 8.8 _ 24 Input Current _ lin 15 _ +01 _ 0.00001) +0.1 _ +1.0 | Ade Input Capacitance : Cin _ _ _ _ 5.0 7.5 - - pF (Vin = 9) Quiescent Current IDD 5.0 _ 5.0 -- =] 0,005 5.0 - 150 | pAdc (Per Package) 10 _ 10 _ 0.010 10 _ 300 15 _ 20 _ 0.015 20 - 600 Total Supply Current**t . IT 5.0 tt = (0.6 hAkHz) f + Ipp- pAdc (Dynamic plus Quiescent, 10 ly = (1.2 wAKHz) f + Ipp Per Package) 15 lt = (1.7 pA-kH2) f + IDD (CL = 50 pF on all outputs, all buffers switching) #Data labelled Typ is not to be used for design purposes butis . intended as an indication of the ICs potential performance. > **The formulas given are for the typical characteristics only at 25C. PIN ASSIGNMENT Cam tTo calculate total supply current at loads other than 50 pF: 1 Ca Voo Ep 16 Hr(CL) = I1(60 pF) + (CL 50) Vik 2H Ea Rak 15 where: IT is in 2A (per package), C_ in pF, V = (Vpp Vgs) in volts, 35 3 14 f in kHz is input frequency, and k = 0.002. . Q04: 03g 4c Ol, Q2,F3 13 5 Co 2, Qig-5 12 6 Hj 3, Q0_f 11 77 Ra Eg E22 10 8 CS Vss Ca 9 6-293MC14518BeMC14520B SWITCHING CHARACTERISTICS* (c, = 50 pF, Ta = 28C} All Types Characteristic Symbol Vop Min Typ # Max Unie Output Rise and Fall Time {TLH: ne 'TLH: trHL = (1.5 na/pF) CL + 25 ns tTHL 5.0 - 100 200 ttLH> tTHL = (0.75 ns/pF} CL + 12.5 a8 10 - 50 100 'TLH: trHL = (0.55 ns/pF}) CL + 9.5 ns 15 -_ 40 80 Propagation Delay Time tPLH. ns Clock to G/Enable to O tpHL tPLH. tPHEL = (1.7 ns/pF) C_ + 215 ns 5.0 - 280 560 tPLH. tPHL = (0.66 ns/pF) Cy +97 ns 10 ~ 115 230 tPLH- tpHy, @ (0.5 ns/pF) Cy + 75 ns 15 - 80 160 Reset to 0 teHL ms PHL = (1.7 ns/pF) CL + 265 ns 5.0 - x0 650 tPHL = (0,66 ns/pF} Cy + 117 ns 10 - 130 230 tpHe = (0.66 ns/pF) C, +95 ns 16 - so 170 Clock Pulse Width tw(H) 5.0 200 100 - ne tw(L) 10 100 50 - 15 70 36 = Clock Pulse Frequency fel 5.0 - 2.5 1.5 MHz 10 - 6.0 3.0 15 = 8.0 40 Clock or Enable Rise and Fall Time TTHL, TTLH 5.0 - - 15 us 10 ~ - 5 15 - ~ 4 Enable Pulse Width twHie} 5.0 440 220 - ns 10 200 100 - 15 140 70 = Reset Pulse Width tWHIR) .0 280 125 - ns 10 120 85 15 90 40 - Reset Removal Time trem 5.0 75 ~ 45 _ ns 10 15 -15 - 15 20 ~ - The formulas given are for the typical characteristics only at 25C. #Data labelled "Typ" is not to be used for design purposes but ts intended as an indication of the ICs potential performance. FIGURE 1 POWER DISSIPATION TEST CIRCUIT AND WAVEFORM 500 pF Pulse Generator RC. Variadie Width 6-294MC14518BeMC14520B FIGURE 2 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS Voo Pulse . Cl) Generator c 1b __ EEE L_o E 2 L aR oe R o3-O7 AKCL ARoL c L_gvss_ To + - FIGURE 3 TIMING DIAGRAM 1) 2)3) 4/5] 6) 7) 8) 9 [10/11 13/14/18) 16/17 Clock Enable Tizisia is je |/7js/ejOrr/2;3/4 18 1/6)7 js [9 oO mc14518B8 az a3 t/2,3)4;)8 | 8)7] 8 | 9)10/11)12}13)14/18) oO | 1 ao at MC145208 Q2 6-295MC14518BeMC14520B FIGURE 4 DECADE COUNTER (MC14518B) LOGIC DIAGRAM (1/2 OF DEVICE SHOWN) ao ai a2 a3 rjip af ro af m2 gf bD af ac = c & rac &- rac at no a rol R R Reset >o-of> 4 ; 4 1 J a Enable + 4 Clock FIGURE & - BINARY COUNTER (MC145208) LOGIC DIAGRAM (1/2 OF DEVICE SHOWN) rr a r-sb apd -1D ar 4D a| sD a ac G-. 4c Ge ac 7 qc ] ce Dep LS Ensble Clock : 6-296