S-8243A/B Series
www.sii-ic.com
BATTERY PROTECTION IC
FOR 3-SERIAL OR 4-SERIAL CELL PACK
© Seiko Instruments Inc., 2002-2010 Rev.3.0_00
Seiko Instruments Inc. 1
The S-8243A/B Series is a protection IC for lithium-ion rechargeable battery. The S-8243A Series protects 3-series, the S-8243B
Series protects 4-series cell pack from the overcharge, overdischarge, overcurrent voltages. This IC has a high-accuracy battery
protection circuit and a battery monitor amplifier, and also a voltage regulator w hich operates the microcomputer or gas gauge IC.
Combining this IC and a microcomputer or a gas gauge IC allow s to display the amount of charge remained in a battery .
Features
(1) High-accuracy voltage detection for each cell
Overcharge detection voltage n (n = 1 to 4)
3.9 V to 4.4 V (50 mV step) Accuracy ±25 mV
Hysteresis voltage n (n = 1 to 4) of overcharge detection
0.10 V to 0.40 V (50 mV step) or 0 V Accuracy ±50 mV
(Overcharge release voltage n (= Overcharge detection voltage n + Hysteresis voltage n) can be selected within
the range 3.8 V to 4.4 V.)
Overdischarge detection voltage n (n = 1 to 4)
2.0 V to 3.0 V (100 mV step) Accuracy ±80 mV
Hysteresis voltage n (n = 1 to 4) of overdischarge detection
0.15 V to 0.70 V or 0 V (50 mV step) Accuracy ±100 mV
(Overdischarge release voltage n (
=
Overdischarge detection voltage n + Hysteresis voltage n) can be selected
within the range 2.0 V to 3.4 V.)
(2) Three-level overcurrent protection including protection for short-circuiting
Overcurrent detection voltage 1 0.05 V to 0.3 V (50 mV step) Accuracy ±25 mV
Overcurrent detection voltage 2 0.5 V Accuracy ±100 mV
Overcurrent detection voltage 3 VDD / 2 Accuracy ±15 %
(3) Delay times for overcharge detection, overdischarge detection and overcurrent detection 1 can be set by external
capacitors. (Delay times for overcurrent detection 2 and 3 are fixed internally.)
(4) Charge/discharge operation can be controlled through the control pins.
(5) High-accuracy battery monitor amp GAMP = VBATTERY × 0.2 ±1.0%
(6) Voltage regulator VOUT = 3.3 V ±2.4 % (3 mA max.)
(7) High input-voltage device Absolute maximum rating: 26 V
(8) Wide operating voltage range 6 V to 18 V
(9) Wide operating temperature range: 40°C to +85°C
(10) Low current consumption
Operation mode 120 μA max.
Power down mode 0.1 μA max.
(11) Lead-free, Sn 100%, halogen-free*1
*1. Refer to “ Product Name Structure” for details.
Applications
Lithium-ion rechargeable battery packs
Lithium polymer rechargeable battery packs
Package
16-Pin TSSOP
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
2
Block Diagrams
1. S-8243A Series
Battery protection
VC3
VC2
VC1
VDD
DOP
COP
VMP
VREG
VBATOUT
200 nA
CTL1
CTL2
CTL3
1.4 MΩ
1.4 MΩ
1 MΩ
1 MΩ
5 MΩ
5 MΩ
CTL4
VREG
VREG
VREG
Delay
control
RVCM,RVSM
DOP,COP,
Delay
Delay
Delay
Batter y mo nitor amp
Voltage
regulator
1.4 MΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
660 kΩ
660 kΩ
440 kΩ
CCT
VSS
CDT
Battery
selection
Remark1. Diodes in the figure are parasitic diodes.
2. Numerical values are typical values.
Figure 1
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 3
2. S-8243B Series
Battery protection
VC3
VC2
VC1
VDD
DOP
COP
VMP
VREG
VBATOUT
200 nA
CTL1
CTL2
CTL3
1.4 MΩ
1.4 MΩ
1 MΩ
1 MΩ
5 MΩ
5 MΩ
CTL4
VREG
VREG
VREG
Delay
control
RVCM, RVSM
DOP, COP,
Delay
Delay
Delay
Battery monitor amp
Voltage
regulator
1.4 MΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
660 kΩ
660 kΩ
440 kΩ
CCT
VSS
CDT
Battery
selection
Remark1. Diodes in the figure are parasitic diodes.
2. Numerical values are typical values.
Figure 2
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
4
Product Name Structure
1. Product Name
S-8243 x xx FT - TB x
Environmental code
U : Lead-f ree (Sn 100% ), halogen-free
G : Lead-free (for details, please contact our sales office)
IC direction in tape specifications*1
Package name (abbreviation)
FT: 16-Pin TSSOP
Serial code*2
Sequentially set from AA to ZZ
Product series name
A : 3-cell
B : 4-cell
*1. Refer to the tape specif ications at the end of this book.
*2. Refer to the “3. Product Name List”.
2. Package
Drawing Code
Package Name Package Tape Reel
Environmental code = G FT016-A-P-SD FT016-A-C-SD FT016-A-R-SD
16-Pin TSSOP Environmental code = U FT016-A-P-SD FT016-A-C-SD FT016-A-R-S1
3. Product Name List
Table 1 S-8243A Series (For 3-Serial Cell)
Product name / Item Overcharge
detection voltage
[V
CU
]
Hysteresis voltage for
overcharge detection
[V
HC
]
Overdischarge
detection voltage
[V
DL
]
Hysteresis voltage for
overdischarge detection
[V
HD
]
Overcurrent
detection voltage1
[V
IOV1
]
0 V battery
charging
function
S-8243AACFT-TB-x 4.350
±
0.025 V
0.15
±
0.05 V 2.40
±
0.08 V 0.20
±
0.10 V 0.20
±
0.025 V Available
S-8243AADFT-TB-x 4.350
±
0.025 V
0.35
±
0.05 V 2.40
±
0.08 V 0 V 0.20
±
0.025 V Available
Table 2 S-8243B Series (For 4-Serial Cell)
Product name / Item Overcharge
detection voltage
[V
CU
]
Hysteresis voltage for
overcharge detection
[V
HC
]
Overdischarge
detection voltage
[V
DL
]
Hysteresis voltage for
overdischarge detection
[V
HD
]
Overcurrent
detection voltage1
[V
IOV1
]
0 V battery
charging
function
S-8243BADFT-TB-x 4.350
±
0.025 V
0.25
±
0.05 V 2.40
±
0.08 V 0 V 0.25
±
0.025 V Available
S-8243BAEFT-TB-x 4.350
±
0.025 V
0.15
±
0.05 V 2.40
±
0.08 V 0.20
±
0.10 V 0.20
±
0.025 V Available
S-8243BAFFT-TB-x 4.250
±
0.025 V
0.25
±
0.05 V 2.40
±
0.08 V 0 V 0.20
±
0.025 V Available
S-8243BAHFT-TB-x 4.315
±
0.025 V
0.20
±
0.05 V 2.00
±
0.08 V 0.15
±
0.10 V 0.20
±
0.025 V Available
Remark 1. Change in the detection voltage is available in products other than listed above. Cont act our sales office.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 5
Pin Configuration
16-Pin TSSOP
Top view
VDD
DOP
COP
VMP
VC1
VC2
VC3
VSS
VREG
CTL1
CTL2
CTL3
CTL4
VBATOUT
CCT
CDT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 3
Table 3 Pin description (S-8243A Series)
Pin No. Symbol Description
1 VDD
Input pin for positive power supply, Connection pin for battery 1’s positive voltage
2 DOP Connection pin for discharge control FET gate (CMOS output)
3 COP Connection pin for charge control FET gate (Nch open drain output)
4 VMP Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)
5 VC1 No connection
6 VC2
Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage
7 VC3
Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage
8 VSS
Input pin for negative power supply, Connection pin for battery 3’s negative voltage
9 CDT
Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1
10 CCT Connection pin to capacitor for overcharge detection delay
11 VBATOUT Output pin for battery voltage and offset voltage
12 CTL4 Pin for selecting output from VBATOUT pin
13 CTL3 Pin for selecting output from VBATOUT pin
14 CTL2 Control pin for charge / discharge FET
15 CTL1 Control pin for charge / discharge FET
16 VREG Output pin for voltage regulator (3.3 V)
Table 4 Pin description (S-8243B Series)
Pin No. Symbol Description
1 VDD Input pin for positive power supply, Connection pin for battery 1’s positive voltage
2 DOP
Connection pin for discharge control FET gate (CMOS output)
3 COP
Connection pin for charge control FET gate (Nch open drain output)
4 VMP
Pin for voltage detection between VDD-VMP pin (Pin for overcurrent detection)
5 VC1
Connection pin for battery 1’s negative voltage, for battery 2’s positive voltage
6 VC2 Connection pin for battery 2’s negative voltage, for battery 3’s positive voltage
7 VC3 Connection pin for battery 3’s negative voltage, for battery 4’s positive voltage
8 VSS Input pin for negative power supply, Connection pin for battery 4’s negative voltage
9 CDT Connection pin to capacitor for overdischarge detection delay, for overcurrent detection delay 1
10 CCT
Connection pin to capacitor for overcharge detection delay
11 VBATOUT
Output pin for battery voltage and offset voltage
12 CTL4
Pin for selecting output from VBATOUT pin
13 CTL3
Pin for selecting output from VBATOUT pin
14 CTL2
Control pin for charge / discharge FET
15 CTL1
Control pin for charge / discharge FET
16 VREG
Output pin for voltage regulator (3.3 V)
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
6
Absolute Maximum Ratings
Table 5 (Ta = 25°C unless otherwise specified)
Item Symbol Applied Pins Absolute Maximum Ratings Unit
Input voltage VDD VDS V
SS0.3 to VSS+26 V
Input voltage VIN VC1, VC2, VC3, CCT,
CDT VSS0.3 to VDD+0.3 V
VMP pin Input voltage VMP VMP VSS0.3 to VSS+26 V
DOP pin output voltage VDOP DOP VSS0.3 to VDD+0.3 V
COP pin output voltage VCOP COP VSS0.3 to VSS+26 V
VREG pin output voltage VOUT VREG VSS0.3 to VDD+0.3 V
CTL1 pin input voltage VCTL1 CTL1 VSS0.3 to VDD+0.3 V
CTL2 to CTL4 pin input voltage VCTLn CTL2, CTL3, CTL4 VSS0.3 to VOUT+0.3 V
Cell voltage output voltage VBATOUT VBATOUT VSS0.3 to VOUT+0.3 V
300 (When not mounted on board) mW
Power dissipation PD 1100*1 mW
Operation ambient temperature Topr 40 to +85 °C
Storage temperature Tstg 40 to +125 °C
*1. When mounted on board
[Mounted board]
(1) Board size : 114.3 mm × 76.2 mm × t1.6 mm
(2) Board name : JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
0 50 100
150
800
400
0
Power Dissipation (P
D
) [mW]
Ambient Temperature (Ta) [°C]
1000
600
200
1200
Figure 4 Pow er Dissipation of Package (When Mounted on Board)
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 7
Electrical Characteristics
1. S-8243A Series
Table 6 (1 / 2) (Ta
=
25°C unless otherwise specified)
Item Symbol Conditions Min. Typ. Max. Unit Test circuit
BATTERY PROTECTION
Overcharge detection voltage n
n=1, 2, 3 V
CUn
3.9 V to 4.4 V, 50 mV Step V
CUn
0.025 V
CUn
V
CUn
+
0.025 V 4
Hysteresis voltage n of overcharge
detection
n
= 1, 2, 3 V
HCn
0.10 V to
0.40 V, and 0 V V
HCn
0.05 V
HCn
V
HCn
+
0.05 V 4
Overdischarge detection voltage
n
= 1, 2, 3 V
DLn
2.0 V to 3.0 V, 100 mV Step V
DLn
0.08 V
DLn
V
DLn
+
0.08 V 4
Hysteresis voltage n of
Overdischarge detection
n
= 1, 2, 3 V
HDn
0.15 V to 0.70 V, and 0 V V
HDn
0.10 V
HDn
V
HDn
+
0.10 V 4
Overcurrent detection voltage 1 V
IOV1
0.05 V to 0.3 V, 50 mV Step
VM voltage based on V
DD
V
IOV1
0.025 V
IOV1
V
IOV1
+
0.025 V 4
Overcurrent detection voltage 2 V
IOV2
VM voltage based on V
DD
0.40 0.50 0.60 V 4
Overcurrent detection voltage 3 V
IOV3
V
DD
×
0.425 V
DD
×
0.5 V
DD
×
0.575 V 4
Temperature coefficient for
detection and release voltage
*1
T
COE1
Ta =
5
°
C to
+
55
°
C
*3
1.0 0 1.0 mV/
°
C 4
Temperature coefficient for
overcurrent detection voltage
*2
T
COE2
Ta =
5
°
C to
+
55
°
C
*3
0.5 0 0.5 mV/
°
C 4
0 V BATTERY CHARGING FUNCTION
(The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited."
depending upon the product type.)
0 V battery charge starting charger
voltage V
0CHA
0 V battery charging available
0.8 1.5 V 7
0 V battery charge inhibition battery
voltage V
0INH
0 V battery charging unavailable 0.4 0.7 1.1 V 7
INTERNAL RESISTANCE
Internal resistance between
VMP and VDD R
VDM
V1 = V2 = V3 = 3.5 V 500 1100 2400 k
Ω
8
Internal resistance between
VMP and VSS R
VSM
V1 = V2 = V3 = 1.8 V 300 700 1500 k
Ω
8
VOLTAGE REGULATOR
Output voltage V
OUT
V
DD
= 14 V, I
OUT
= 3 mA 3.221 3.300 3.379 V 2
Line regulation
Δ
V
OUT1
V
DD
= 6 V
18 V, I
OUT
= 3 mA
5 15 mV 2
Load regulation
Δ
V
OUT2
V
DD
= 14 V, I
OUT
= 5
μ
A
3 mA
15 30 mV 2
BATTERY MONITOR AMP
Input offset voltage n
n
= 1, 2, 3 V
OFFn
V1 = V2 = V3 = 3.5 V 60 165 270 mV 3
Voltage gain n
n
= 1, 2, 3 GAMPn V1 = V2 = V3 = 3.5 V 0.2
×
0.99 0.2 0.2
×
1.01
3
INPUT VOLTAGE, OPERATING VOLTAGE
Operating voltage between
V
DD
and V
SS
V
DSOP
6
18 V 4
CTL1 input voltage for High V
CTL1H
V
DD
×
0.8
V 6
CTL1 input voltage for Low V
CTL1L
V
DD
×
0.2 V 6
CTLn input voltage for High
n = 2, 3, 4 V
CTLnH
V
OUT
×
0.9
V
OUT
V 3, 6
CTLn input voltage for Low
n = 2, 3, 4 V
CTLnL
V
OUT
×
0.1 V 3, 6
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
8
Table 6 (2 / 2)
Item Symbol Remarks Min. Typ. Max. Unit Test circuit
INPUT CURRENT
Current consumption at not
monitoring V
BATOUT
I
OPE
V1 = V2 = V3 = 3.5 V, V
MP
= V
DD
65 120
μ
A 1
Current consumption at power down I
PDN
V1 = V2 = V3 = 1.5 V, V
MP
= V
SS
0.1
μ
A 1
Current for VCn at not monitoring
V
BATOUT
(n = 2, 3) I
VCnN
V1 = V2 = V3 = 3.5 V
0.3 0 0.3
μ
A 3
Current for VC2 at monitoring of
V
BATOUT
I
VC2
V1 = V2 = V3 = 3.5 V
2.0 7.2
μ
A 3
Current for VC3 at monitoring of
V
BATOUT
I
VC3
V1 = V2 = V3 = 3.5 V
1.0 4.0
μ
A 3
Current for CTL1 at Low I
CTL1L
V1 = V2 = V3 = 3.5 V, V
CTL1
= 0 V
0.4
0.2
μ
A 5
Current for CTLn at High
n = 2,3,4 I
CTLnH
V
CTLn
= V
OUT
2.5 5
μ
A 9
Current for CTLn at Low
n = 2,3,4 I
CTLnL
V
CTLn
= 0 V
5
2.5
μ
A 9
OUTPUT CURRENT
Leak current COP I
COH
V
COP
= 24 V
0.1
μ
A 9
Sink current COP I
COL
V
COP
= V
SS
+
0.5 V 10
μ
A 9
Source current DOP I
DOH
V
DOP
= V
DD
0.5 V 10
μ
A 9
Sink current DOP I
DOL
V
DOP
= V
SS
+
0.5 V 10
μ
A 9
Source current V
BATOUT
I
VBATH
V
BATOUT
= V
DD
0.5 V 100
μ
A 9
Sink current V
BATOUT
I
VBATL
V
BATOUT
= V
SS
+
0.5 V 100
μ
A 9
Applied to S-8243AACFT and S-8243AADFT
Item Symbol Conditions Min. Typ. Max. Unit Test circuit
DELAY TIME
Overcharge detection delay time t
CU
C
CT
= 0.1
μ
F 0.5 1.0 1.5 s 5
Overdischarge detection delay time t
DL
C
DT
= 0.1
μ
F 50 100 150 ms 5
Overcurrent detection delay time 1 t
lOV1
C
DT
= 0.1
μ
F 5 10 15 ms 5
Overcurrent detection delay time 2 t
lOV2
1.5 2.5 4.0 ms 4
Overcurrent detection delay time 3 t
lOV3
100 300 600
μ
s 4
*1.
Temperature coefficient for detection and release voltage is applied to overcharge detection voltage n, overcharge release voltage n, overdischarge
detection voltage n, and overdischarge release voltage n.
*2.
Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2.
*3.
Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in
production.
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 9
2. S-8243B Series
Table 7 (1 / 2) (Ta
=
25°C unless otherwise specified)
Item Symbol Conditions Min. Typ. Max. Unit Test circuit
DETECTION VOLTAGE
Overcharge detection voltage n
n = 1, 2, 3, 4 V
CUn
3.9 V to 4.4 V, 50 mV Step V
CUn
0.025 V
Cun
V
CUn
+
0.025 V 4
Hysteresis voltage n of overcharge
detection
n = 1, 2, 3, 4 V
HCn
0.10 V to
0.40 V, and 0 V V
HCn
0.05 V
HCn
V
HCn
+
0.05 V 4
Overdischarge detection voltage
n = 1, 2, 3, 4 V
DLn
2.0 V to 3.0 V, 100 mV Step V
DLn
0.08 V
DLn
V
DLn
+
0.08 V 4
Hysteresis voltage n of
overdischarge detection
n = 1, 2, 3, 4 V
HDn
0.15 V to 0.70 V, and 0 V V
HDn
0.10 V
HDn
V
HDn
+
0.10 V 4
Overcurrent detection voltage 1 V
IOV1
0.05 V to 0.3 V, 50 mV Step
VM voltage based on V
DD
V
IOV1
0.025 V
IOV1
V
IOV1
+
0.025 V 4
Overcurrent detection voltage 2 V
IOV2
VM voltage based on V
DD
0.40 0.50 0.60 V 4
Overcurrent detection voltage 3 V
IOV3
V
DD
×
0.425 V
DD
×
0.5 V
DD
×
0.575 V 4
Temperature coefficient for
detection and release voltage
*1
T
COE1
Ta =
5
°
C to
+
55
°
C
*3
1.0 0 1.0 mV/
°
C 4
Temperature coefficient for
overcurrent detection voltage
*2
T
COE2
Ta =
5
°
C to
+
55
°
C
*3
0.5 0 0.5 mV/
°
C 4
0 V BATTERY CHARGING FUNCTION
(The 0 V battery function is either "0 V battery charging is allowed." or "0 V battery charging is inhibited.
"
depending upon the product type.)
0 V battery charge starting charger
voltage V
0CHA
0 V battery charging allowed
0.8 1.5 V 7
0 V battery charge inhibition battery
voltage V
0INH
0 V battery charging inhibited 0.4 0.7 1.1 V 7
INTERNAL RESISTANCE
Internal resistance between
VMP and VDD R
VDM
V1 = V2 = V3 = V4 = 3.5 V 500 1100 2400 k
Ω
8
Internal resistance between
VMP and VSS R
VSM
V1 = V2 = V3 = V4 = 1.8 V 300 700 1500 k
Ω
8
VOLTAGE REGULATOR
Output voltage V
OUT
V
DD
= 14V, I
OUT
= 3 mA 3.221 3.300 3.379 V 2
Line regulation
Δ
V
OUT1
V
DD
= 6 V
18 V, I
OUT
= 3 mA
5 15 mV 2
Load regulation
Δ
V
OUT2
V
DD
= 14 V, I
OUT
= 5
μ
A
3 mA
15 30 mV 2
BATTERY MONITOR AMP
Input offset voltage n
n = 1, 2, 3, 4 V
OFFn
V1 = V2 = V3 = V4 = 3.5 V 60 165 270 mV 3
Voltage gain n
n = 1, 2, 3, 4 GAMPn V1 = V2 = V3 = V4 = 3.5 V 0.2
×
0.99 0.2 0.2
×
1.01
3
INPUT VOLTAGE, OPERATING VOLTAGE
Operating voltage between
V
DD
and V
SS
V
DSOP
6
18 V 4
CTL1 input voltage for High V
CTL1H
V
DD
×
0.8
V 6
CTL1 input voltage for Low V
CTL1L
V
DD
×
0.2 V 6
CTLn input voltage for High
n = 2, 3, 4 V
CTLnH
V
OUT
×
0.9
V
OUT
V 3, 6
CTLn input voltage for Low
n = 2, 3, 4 V
CTLnL
V
OUT
×
0.1 V 3, 6
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
10
Table 7 (2 / 2)
Item Symbol Remarks Min. Typ. Max. Unit Test circuit
INPUT CURRENT
Current consumption at not
monitoring V
BATOUT
I
OPE
V1 = V2 = V3 = V4 = 3.5 V, V
MP
= V
DD
65 120
μ
A 1
Current consumption at power down I
PDN
V1 = V2 = V3 = V4 = 1.5 V, V
MP
= V
SS
0.1
μ
A 1
Current for VCn at not monitoring
V
BATOUT
(n = 2, 3) I
VCnN
V1 = V2 = V3 = V4 = 3.5 V
0.3 0 0.3
μ
A 3
Current for VC1 at monitoring of
V
BATOUT
I
VC1
V1 = V2 = V3 = V4 = 3.5 V
3.2 10.4
μ
A 3
Current for VC2 at monitoring of
V
BATOUT
I
VC2
V1 = V2 = V3 = V4 = 3.5 V
2.0 7.2
μ
A 3
Current for VC3 at monitoring of
V
BATOUT
I
VC3
V1 = V2 = V3 = V4 = 3.5 V, V
CTL1
= 0 V
1.0 4.0
μ
A 3
Current for CTL1 at Low I
CTL1L
V1 = V2 = V3 = V4 = 3.5 V, V
CTL1
= 0 V
0.4
0.2
μ
A 5
Current for CTLn at High
n = 2, 3, 4 I
CTLnH
V
CTLn
= V
OUT
2.5 5
μ
A 9
Current for CTLn at Low
n = 2, 3, 4 I
CTLnL
V
CTLn
= 0 V
5
2.5
μ
A 9
OUTPUT CURRENT
Leak current COP I
COH
V
COP
= 24 V
0.1
μ
A 9
Sink current COP I
COL
V
COP
= V
SS
+
0.5 V 10
μ
A 9
Source current DOP I
DOH
V
DOP
= V
DD
0.5 V 10
μ
A 9
Sink current DOP I
DOL
V
DOP
= V
SS
+
0.5 V 10
μ
A 9
Source current V
BATOUT
I
VBATH
V
BATOUT
= V
DD
0.5 V 100
μ
A 9
Sink current V
BATOUT
I
VBATL
V
BATOUT
= V
SS
+
0.5 V 100
μ
A 9
Applied to S-8243BAEFT, S-8243BAFFT, S-8243BAHFT
Item Symbol Conditions Min. Typ. Max. Unit Test circuit
DELAY TIME
Overcharge detection delay time t
CU
C
CT
= 0.1
μ
F 0.5 1.0 1.5 s 5
Overdischarge detection delay time t
DL
C
DT
= 0.1
μ
F 50 100 150 ms 5
Overcurrent detection delay time 1 t
lOV1
C
DT
= 0.1
μ
F 5 10 15 ms 5
Overcurrent detection delay time 2 t
lOV2
1.5 2.5 4.0 ms 4
Overcurrent detection delay time 3 t
lOV3
100 300 600
μ
s 4
Applied to S-8243BADFT
Item Symbol Conditions Min. Typ. Max. Unit Test circuit
DELAY TIME
Overcharge detection delay time t
CU
C
CT
= 0.1
μ
F 0.5 1.0 1.5 s 5
Overdischarge detection delay time t
DL
C
DT
= 0.1
μ
F 55.5 111 222 ms 5
Overcurrent detection delay time 1 t
lOV1
C
DT
= 0.1
μ
F 3.31 6.62 13.2 ms 5
Overcurrent detection delay time 2 t
lOV2
1.5 2.5 4.0 ms 4
Overcurrent detection delay time 3 t
lOV3
100 300 600
μ
s 4
*1.
Temperature coeffi cient for detection and release voltage is applied to overcharge detection vol tage n, overcharge release vol tage n, overdischarge
detection voltage n, and overdischarge release voltage n.
*2.
Temperature coefficient for overcurrent detection voltage is applied to over current detection voltage 1 and 2.
*3.
Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in
production.
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 11
Test Circuits
In this chapter test methods are explained for the case of S-8243B series, which is designed for 4-serial cell pack. For the
case of S-8243A series, which is designed for 3-serial cell, voltage source V2 should be shorted, V3 should be read as V2,
and V4 as V3.
1. Current consumption (Test circuit 1)
Current consumption at not monitoring VBATOUT, IOPE, is a current measured at the VSS pin when V1 = V2 = V3 = V4 =
3.5 V and VMP = VDD. Current consumption at power down, IPDN, is a current measured at the VSS pin when V1 = V2 =
V3 = V4 = 1.5 V and VMP = VSS.
2. Voltage regulator (Test circuit 2)
Output voltage of the regulator VOUT is a voltage measured at the VREG pin when VDD = VMP = 14 V and IOUT = 3 mA.
Line regulation of the voltage regulator ΔVOUT1 is defined by the equation ΔVOUT1 = VOUT2VOUT1 where VOUT1 is the
output voltage when VDD = VMP = 6 V and IOUT = 3 mA, and VOUT2 is the output voltage when VDD = VMP = 18 V and IOUT
= 3 mA.
Load regulation of the regulator is defined by the equation ΔVOUT2 = VOUT3VOUT where VOUT3 is the output voltage when
VDD = VMP = 14 V and IOUT = 5 μA.
3. Battery monitor amp and pin current for VC1 to VC3 (Test circuit 3)
Voltage gain of the battery monitor amp for each cell is defined by the input offset voltage and the measurement result
provided from the VBATOUT pin for the combination of the CTL3 pin and CTL4 pin expressed by the following table at
the condition where V1 = V2 = V3 = V4 = 3.5 V. Pin current for VC1 to VC3, IVCn and IVCnN are at the same time
measured.
Table 8
CTL3 pin status CTL4 pin status VBATOUT pin output VCn (n = 1, 2, 3) pin current
VCTL3H min. VCTL4H min. VOFF1 I
VC1 at VC1 pin
VCTL3H min. Open VBAT1
VCTL3H min. VCTL4L max. VOFF2 I
VC2 at VC2 pin
Open VCTL4H min. VBAT2
Open Open VOFF3 I
VC3 at VC3 pin
Open VCTL4L max. VBAT3
VCTL3L max. VCTL4H min. VOFF4 I
VCnN at VCn pin (n = 1, 2, 3)
VCTL3L max. Open VBAT4
Voltage gain of the battery monitor amp for each cell is calculated by the equation
GAMPn = (VBATnVOFFn) / Vn (n = 1 to 4)
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
12
4. Overcharge detection voltages, overcharge detection hysteresis, overdischarge detection
voltages, overdischarge detection hysteresis, and overcurrent detection voltages (Test circuit 4)
4. 1 Overcharge detection vo ltag es, hysteresis voltages, and overdischarge detection voltages
In the following VMP = VDD and the CDT pin is open.
The COP pin and the DOP pin should provide “Low”, w hich is a voltage equal to VDD × 0.1 V or lower, in the condition
that V1 = V2 = V3 = V4 = 3.5 V.
The overcharge detection voltage VCU1 is defined by the voltage at which COP pin voltage becomes “High”, which is
a voltage equal to VDD × 0.9 V or higher, when the voltage V1 is gradually increased from the starting condition V1
= 3.5 V. The overcharge release voltage VCL1 is defined by the voltage at wh ich COP pin voltage becomes “Low”
when the voltage V1 is gradually decreased. The hysteresis voltage of the overcharge detection VHC1 is then defined
by the difference between the overcharge detection voltage V CU1 and the overcharge release voltage VCL1.
The overdischarge detection voltage VDL1 is defined by the voltage at which DOP pin voltage becomes “High” when
the voltage V1 is gradually decreased from the starting condition V1 = 3.5 V. The overdischarge release voltage
VDU1 is defined by the voltage at wh ich DOP pin voltage becomes “Low” w hen the voltage V1 is gradually increased.
The hysteresis of the overdischarge detection voltage VHD1 is then defined by the difference between the
overdischarge release voltage VDU1 and the overdischarge detection voltage VDL1.
Other overcharge detection voltage VCUn, hysteresis voltage of overcharge detection VHCn, overdischarge detection
voltage VDLn, and hysteresis of the overdischarge detection voltage VHDn ( for n = 2 to 4) are defined in the same
manner as in the case for n = 1.
4. 2 Overcurrent detection voltages
Starting condition is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and the CDT pin is open. T he DOP pin voltage thus
provides “Low”
The overcurrent detection voltage 1, VIOV1 is defined by the voltage difference VDD VMP at which the DOP pin
voltage becomes “High” when the voltage of VMP pin is decreased.
Starting condition for measuring the overcurrent detection voltage 2 and 3 is V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD
and the CDT pin voltage VCDT = VSS . The DOP pin voltage thus provides “Low”.
The overcurrent detection voltage 2, VIOV2 is defined by the voltage difference VDDVMP at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased.
The overcurrent detection delay time 2, tIOV2 is a time needed for the DOP pin to become “High” from “Low” w hen the
VM pin voltage is changed quickly to VIOV2 min.0.2 V from the starting condition VMP = VDD.
The overcurrent detection voltage 3, VIOV3 is defined by the voltage of the VM pin at which the DOP pin voltage
becomes “High” when the voltage of VMP pin is decreased at the speed 10 V / ms.
The overcurrent detection delay time 3, tIOV3 is a time needed for the DOP pin to become “High” from “Low” w hen the
VM pin voltage is changed quickly to VIOV3 min.0.2 V from the starting condition VMP = VDD.
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 13
5. CTL1 pin current, overcharge detection delay, overdischarge detection delay, and overcurrent
detection delay 1 (Test circuit 5)
Starting condition is V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD.
Current that flows between the CT L1 pin and VSS is the CTL1 pin current ICTL1L.
The overcharge detection delay time tCU is a time needed for the COP pin voltage to change from “Low” to “High” just
after the V1 voltage is rapidly increased from 3.5 V to 4.5 V.
The overdischarge detection delay time tDL is a time needed for the DOP pin voltage to change from “Low” to “High” just
after the V1 voltage is rapidly decreased from 3.5 V to 1.5 V.
The overcurrent detection delay time 1 is a time needed for the DOP pin voltage to change from “Low” to “High” just after
the VMP pin voltage is decreased from VDD to VDD0.35 V when V1 = 3.5 V.
6. Input voltages for CTL1 and CTL2 (Test circuit 6)
Starting condition is V1 = V2 = V3 = V4 = 3.5 V.
Pin voltages of the COP and the DOP should be “High” when VCTL1 = VCTL1H min. and CTL2 is OPEN.
Pin voltages of the COP and the DOP should be “Low” when VCTL1 = VCTL1L max. and CTL2 is OPEN.
Pin voltage of the COP is “High” and the pin voltage of the DOP is “Low” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2H
min.
Pin voltage of the COP is “Low” and the pin voltage of the DOP is “High” when VCTL1 = VCTL1L max. and VCTL2 = VCTL2L
max.
7. 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage (Test
circuit 7)
One of the 0 V battery charge starting charger voltage and 0 V battery charge inhibition battery voltage is
applied to each product according to the 0V battery charging function.
Starting condition is V1 = V2 = V3 = V4 = 0 V for a product in which 0 V battery charging is available.
The COP pin voltage should be lower than V0CHA max.1 V when the VMP pin voltage VMP = V0CHA max.
Starting condition is V1 = V2 = V3 = V4 = V0INH for a product in which 0 V battery charging is inhibited.
The COP pin voltage should be higher than VMP1 V when the VMP pin voltage VMP = 24 V.
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
14
8. Internal resistance (Test circuit 8)
The resistance between VDD and VMP is RVDM and is calculated by the equation RVDM = VDD / IVDM w here IVDM is a VMP
pin current after VMP is changed to VSS from the starting condition V1 = V2 = V3 = V4 = 3.5 V and VMP = VDD.
The resistance between VSS and VMP is RVSM and is calculated by the equation RVSM = VDD / IVSM w here IVSM is a VMP
pin current at the condition V1 = V2 = V3 = V4 = 1.8 V and VMP = VDD.
9. Pin current for CTL2 to CTL4, COP, DOP, VBATOUT (Test circuit 9)
Starting condition is V1 = V2 = V3 = V4 = 3.5 V.
Pin current for CTL2 at “High” is ICTL2H and is obtained by setting VCTL2 = VOUT.
Pin current for CTL2 at “Low” is ICTL2L and is obtained by setting VCTL2 = VSS.
Pin current for CTL3 and CTL4 can be obtained in the same manner as in the CTL2.
Pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 = V4 = 6 V, VMP = VDD, and VCOP = VDD. And
pin current for COP at “Low” is ICOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VCOP = 0.5 V.
Pin current for DOP at “Low” is IDOL and is obtained by setting V1 = V2 = V3 = V4 = 3.5 V, VMP = VDD, and VDOP = 0.5 V.
And pin current for COP at “High” is ICOH and is obtained by setting V1 = V2 = V3 =V4 = 3.5 V, VMP = VDD1 V, and VDOP
= VDD0.5 V.
Pin current for VBATOUT at “High” is IVBATH and is obtained by setting CTL3 and CTL4 are open and VBATOUT =
VOFF30.5 V. And pin current for VBATOUT at “Low” is IVBATL and is obtained by setting VBATOUT = VOFF3+0.5 V.
C1=1 μF
V4
V3
V2
V1
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
A
C1=1 μF IOUT
V
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
Test circuit 1 Test circuit 2
C1=1 μF
V4
V3
V2
V1
V
A
A
A
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
R1=1 MΩ
V4
V3
V2
V1
V
V
C1=1 μF
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
Test circuit 3 Test circuit 4
Figure 5 (1 / 2)
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 15
C2=0.1 μF
V4
V3
V2
V1
A
C1=1 μF C3=0.1 μF
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
C1=1 μF
V4
V3
V2
V1
R1=1 MΩ
V
V8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
Test circuit 5 Test circuit 6
V4
V3
V2
V1
R1=1 MΩ
V
C1=1 μF
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
V4
V3
V2
V1
A
C1=1 μF
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
Test circuit 7 Test circuit 8
V4
V3
V2
V1
A
A
A
A
A
A
C1=1 μF
8 VSS
7 VC3
6 VC2
5 VC1
3 COP
2 DOP
4 VMP
1 VDD
VBATOUT 11
VREG 16
CDT 9
CCT 10
CTL4 12
CTL2 14
CTL1 15
CTL3 13
Test circuit 9
Figure 5 (2 / 2)
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
S-8243A/B Series Rev.3.0_00
Seiko Instruments Inc.
16
Operation
1. Battery protection circuit
Remark Refer to “ Battery Protection IC Connection Example”.
Battery protection protects batteries from overcharge and overdischarge, and also protects external FETs from
overcurrent.
1. 1 Normal status
When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than a specified
value (the VMP pin voltage is lower than VIOV1), the charging and discharging FETs are turned on.
1. 2 Overcharge status
When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP
pin becomes high impedance and is pulled up to EB+ pin voltage by an external resistor, and the charging FET is
turned off to stop charging. The overcharge status is released when one of the following two conditions holds.
(a) All battery voltages become lower than VCUn + VHCn.
(b) VDDVMP>VIOV1 (A load is connected, and discharging starts.)
1. 3 Overdischarge status
When any one of the battery voltages becomes low er than VDLn and the state continues for tDL or longer, the DOP pin
voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is the overdischarge
status.
1. 4 Power down status
After stopping discharging due to overdischarge status, the S-8243 enters power dow n status. In this status, almost
all circuits of the S-8243 are stopped to save current consumption. The current consumption becomes lower than
IPDN. In the power dow n status, the VMP pin is pulled dow n to VSS level by the internal RVSM resistor. In pow er dow n
status, output pin voltages are fixed at the following levels.
(a) COP High-Z (Charging FET is turned off)
(b) DOP VDD (Discharging FET is turned off)
(c) VREG VSS (Voltage regulator circuit is off)
(d) VBATOUT VSS (Battery voltage monitor amp circuit is off)
The power down status is released when the following condition holds.
(a) VMP>VIOV3 (A charger is connected, and charging starts.)
The overdischarging status is released when the following condition holds.
(a) All of the battery voltages are VDLn or higher, and the VMP pin voltage is VDD / 2 or higher. (A charger is
connected.)
1. 5 Overcurrent status
The S-8243 has three overcurrent detection levels (VIOV1, VIOV2 and VIOV3) and three overcurrent detection delay
times (tIOV1, tIOV2 and tIOV3) corresponding to each overcurrent detection levels. When the discharging current
becomes higher than a specified value (the voltage between VDD and VMP is greater than VIOV1) and the state
continues for tIOV1 or longer, the S-8243 enters the overcurrent status in which the DOP pin voltage becomes VDD
level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to
EB+ pin voltage by an external resistor to turn off the charging FET to stop charging, and the VMP pin is pulled up to
VDD voltage by the internal resistor RVDM. Operation of two other overcurrent detection levels (VIOV2 and V IOV3) and
overcurrent detection delay times (tIOV2 and tIOV3) is the same as that for VIOV1 and tIOV1.
The overcurrent status is released when the following condition holds.
(a) VMP> {VIOV3 / (1VIOV3) × 3 / 52 / 5} × RVDM (A load is released, and the impedance between the EB and
EB+ pin becomes higher. )
BATTERY PROTECTION IC FOR 3-SERIAL OR 4-SERIAL CELL PACK
Rev.3.0_00 S-8243A/B Series
Seiko Instruments Inc. 17
1. 6 0 V battery charging function
Regarding the charging of a self-discharged battery (0 V battery) the S-8243 has two functions from which one
should be selected.
(a) 0 V battery charging is allowed (0 V battery charging is available)
When a charger voltage is higher than V0CHA, 0 V battery can be charged.
(b) 0 V battery charging is forbidden (0 V battery charging is impossible)
When one of the battery voltages is lower than V0INH, 0 V battery can not be charged.
Caution When the VDD pin voltage is lower than minimum of VDSOP, the operation of S-8243 series is not
guaranteed.
1. 7 Delay time setting
Overcharge detection delay times (tCU1 to tCU4) are determined by the external capacitor at the CCT pin.
Overdischarge detection delay times (tDL1 to tDL4) and overcurrent detection delay time 1 (tIOV1) are determined by the
external capacitor at CDT pin. Overcurrent detection delay time 2,3 (tIOV2, tIOV3) are fixed internally.
S-8243AAC, S-8243AAD, S-8243BAE, S-8243BAF, S-8243BAH
min. typ. max.
tCU [s] = Delay factor ( 5 10 15 ) × CCT [μF]
tDL [ms] = Delay factor ( 500 1000 1500 ) × CDT [μF]
tIOV1 [ms] = Delay factor ( 50 100 150 ) × CDT [μF]
S-8243BAD min. typ. max.
tCU [s] = Delay factor ( 5 10 15 ) × CCT [μF]
tDL [ms] = Delay factor ( 555 1110 2220 ) × CDT [μF]
tIOV1 [ms] = Delay factor ( 33.1 66.2 132 ) × CDT [μF]
2. Voltage regulator circui t
Built-in voltage regulator can be used to drive a micro computer, etc. The voltage regulator supplies voltage of 3.3 V (3
mA maximum) and an external capacitor is needed.
Caution In the pow er down status the voltage regulator output is pulled dow n to the VSS level by an internal
resistor.
3. Battery monitor amp circuit
Battery monitor amp sends information of the batteries to a microcomputer. The battery monitor amp output is
controlled and selected by CTL3 and CTL4 pins to give the following two voltages.
(a) VBATn = GAMPn × VBATTERYn + VOFFn where GAMPn is the n-th voltage gain of the amp, VBATTERYn is the n-th
battery voltage, and VOFFn is the n-th offset voltage of the amp.
(b) N-th offset voltage VOFFn
Each battery voltage VBATTERYn (n = 1 to 4) is thus calculated by following equation.
VBATTERYn = (VBATn VOFFn) / GAMPn (n = 1, 2, 3, 4)
After the state of CTL3 and CTL4 are changed, a time between 25 μs and 250 μs is needed for the battery monitor
amp to become stable.
Caution In the power down status the battery monitor amp output is the VSS level.