ADP7183ACPZN1.0-R7 - ANALOG DEVICES

−300 mA, Ultralow Noise, High PSRR,

Low Dropout Linear Regulator

Data Sheet ADP7183

Rev. B Document Feedback

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FEATURES

Input voltage range: −2.0 V to −5.5 V

Maximum output current: −300 mA

Fixed output voltage options: −0.5 V to −4.5 V

Adjustable output from −0.5 V to −VIN + 0.5 V

Low output noise: 4 μV rms from 100 Hz to 100 kHz

Noise spectral density: 20 nV/√Hz, 10 kHz to 1 MHz

Power supply rejection ratio (PSRR) at −300 mA load

75 dB typical at 10 kHz

62 dB typical at 100 kHz

40 dB typical at 1 MHz

Low dropout voltage: −130 mV typical at IOUT = −300 mA

Initial output voltage accuracy (VOUT): ±0.5% at IOUT = −10 mA

Output voltage accuracy over line, load, and temperature: ±2.6%

Operating supply current (IGND): −0.6 mA typical at no load

Low shutdown current: −2 μA typical at VIN = −5.5 V

Stable with small 4.7 μF ceramic input and output capacitor

Positive or negative enable logic

Current-limit and thermal overload protection

8-lead, 2 mm × 2 mm LFCSP package

Supported by ADIsimPOWER voltage regulator design tool

APPLICATIONS

Regulation to noise sensitive applications: analog-to-digital

converters (ADCs), digital-to-analog converters (DACs),

precision amplifiers

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation

TYPICAL APPLICATION CIRCUITS

OUT

= –3.3

OUT

4.7µF

1µF

AFB

10nF

+1.25V

–1.3V

OFF

VIN

VREG GND

VOUT

SENSE

VAFB

4.7µF

= –3.8V

REG

1µF

ADP7183

12897-001

Figure 1. ADP7183 with Fixed Output Voltage, VOUT = −3.3 V

OUT

= –2.5

OUT

4.7µF

+1.25V

–1.3V

OFF

VIN

VREG GND

VOUT

SENSE

VAFB

4.7µF

= –3V

REG

1µF

ADP7183

1µF

AFB

10nF

24.9kΩ

100kΩ

12897-002

Figure 2. ADP7183 with Adjustable Output Voltage, VOUT = −2.5 V

GENERAL DESCRIPTION

The ADP7183 is a complementary metal oxide semiconductor

(CMOS), low dropout (LDO) linear regulator that operates

from −2.0 V to −5.5 V and provides up to −300 mA of output

current. This LDO regulator is ideal for regulation of high

performance analog and mixed-signal circuits operating

from −0.5 V down to −4.5 V. Using an advanced proprietary

architecture, the ADP7183 provides high PSRR and low noise,

and it achieves excellent line and load transient response with a

small 4.7 μF ceramic output capacitor.

The ADP7183 is available in 15 fixed output voltage options.

The following voltages are available from stock: −0.5 V, −1.0 V,

−1.2 V, −1.5 V, −1.8 V, −2.0 V, −2.5 V, −3.0 V, and −3.3 V.

Additional voltages available by special order are −0.8 V, −0.9 V,

−1.3 V, −2.8 V, −4.2 V, and −4.5 V. An adjustable version is also

available that allows output voltages that range from −0.5 V to

−VIN + 0.5 V with an external feedback divider.

The enable logic feature is capable of interfacing with positive

or negative logic levels for maximum flexibility.

The ADP7183 regulator output noise is 4 μV rms independent

of the output voltage. The ADP7183 is available in an 8-lead,

2 mm × 2 mm LFCSP, making it not only a very compact

solution but also providing excellent thermal performance for

applications requiring up to −300 mA of output current in a

small, low profile footprint.

ADP7183* PRODUCT PAGE QUICK LINKS

Last Content Update: 10/03/2017

COMPARABLE PARTS

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EVALUATION KITS

•ADP7183/ADP7185 Evaluation Board

DOCUMENTATION

Data Sheet

• ADP7183: −300 mA, Ultralow Noise, High PSRR, Low

Dropout Linear Regulator Data Sheet

User Guides

•UG-795: Evaluating the ADP7183 and ADP7185 Ultralow

Noise, High PSRR, Low Dropout Linear Regulators

TOOLS AND SIMULATIONS

•ADI Linear Regulator Design Tool and Parametric Search

• ADIsimPower™ Voltage Regulator Design Tool

DESIGN RESOURCES

•ADP7183 Material Declaration

•PCN-PDN Information

•Quality And Reliability

•Symbols and Footprints

DISCUSSIONS

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ADP7183 Data Sheet

Rev. B | Page 2 of 19

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuits ............................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Input and Output Capacitor Recommended Specifications ... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Data ................................................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 13

Adjustable Mode Operation ..................................................... 13

Enable Pin Operation ................................................................ 13

Start-Up Time ............................................................................. 14

Applications Information .............................................................. 15

ADIsimPower Design Tool ....................................................... 15

Capacitor Selection .................................................................... 15

Undervoltage Lockout (UVLO) ............................................... 16

Current-Limit and Thermal Overload Protection ................. 16

Thermal Considerations ............................................................ 17

PCB Layout Considerations ...................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

5/2017—Rev. A to Rev. B

Change to Low Noise Reference Voltage Parameter, Table 1 ...... 3

Changes to Figure 31 to Figure 33 ................................................ 11

Changes to Input and Output Capacitor Properties Section and

Figure 49 .......................................................................................... 16

2/2017—Rev. 0 to Rev. A

Changes to Specifications Section .................................................. 3

Change to Output Accuracy Voltage Parameter, Table 1 ............ 3

Changes to Ordering Guide .......................................................... 19

10/2016—Revision 0: Initial Version

Data Sheet ADP7183

Rev. B | Page 3 of 19

SPECIFICATIONS

VIN = (VOUT − 0.5 V) or −2 V (whichever is more negative), EN = VIN, IOUT = −10 mA, CIN = COUT = 4.7 µF, CAFB = 10 n F, C A = CREG = 1 µF, TA =

25°C for typical specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT VOLTAGE RANGE

−2.0

−5.5

OPERATING SUPPLY CURRENT IGND IOUT = 0 µA −0.6 −0.90 mA

IOUT = −300 mA −4.0 −7.0 mA

SHUTDOWN CURRENT IGND-SD EN = GND, VIN = −5.5 V −2 −7 µA

OUTPUT NOISE1 OUTNOISE 10 Hz to 100 kHz, CAFB = 1 nF 7 µV rms

10 Hz to 100 kHz, CAFB = 10 nF 5 µV rms

100 Hz to 100 kHz, CAFB = 1 nF 6 µV rms

100 Hz to 100 kHz, CAFB = 10 nF 4 µV rms

NOISE SPECTRAL DENSITY1 OUTNSD 100 Hz, CAFB = 1 nF 300 nV/√Hz

100 Hz, CAFB = 10 nF 100 nV/√Hz

10 kHz to 1 MHz, C

AFB

= 1 nF to 1 µF

nV/√Hz

POWER SUPPLY REJECTION RATIO1 PSRR IOUT = −300 mA, VOUT = −3.3 V, VIN = −3.8 V

At 1 kHz 85 dB

At 10 kHz 75 dB

At 100 kHz 62 dB

At 1 MHz 40 dB

OUTPUT VOLTAGE VOUT −0.5 −4.5 V

Output Voltage Accuracy IOUT = −10 mA, TA = 25°C −0.5 +0.5 %

−1 mA < IOUT < −300 mA,

VIN = (VOUT − 0.5 V) to −5.5 V

−2.6 +2.6 %

OUTPUT VOLTAGE REFERENCE FEEDBACK VAFB Adjustable model voltage reference −0.487 −0.5 −0.513 V

VAFB Accuracy Adjustable model, VIN = −2 V, IOUT = −10 mA −2.6 +2.6 %

REGULATION

Line ΔVOUT/∆VIN VIN = (VOUT − 0.5 V) to −5.5 V −0.1 +0.3 %/V

Load2 ∆VOUT/∆IOUT IOUT = −1 mA to −300 mA 0.8 2.6 %/A

INPUT BIAS CURRENT

SENSE SENSEI-BIAS −1 mA < IOUT < −300 mA,

VIN = (VOUT − 0.5 V) to −5.5 V

−10 nA

VAFB VAFB-BIAS −1 mA < IOUT < −300 mA,

VIN = (VOUT − 0.5 V) to −5.5 V

−10 nA

DROPOUT VOLTAGE3 VDROPOUT IOUT = −100 mA −40 −65 mV

IOUT = −300 mA −130 −220 mV

PULL-DOWN RESISTANCE VEN = 0 V

Output Voltage VOUT-PULL VOUT = −1 V 280 Ω

Regulated Input Supply Voltage VREG-PULL VREG = −1 V 1.3 kΩ

Low Noise Reference Voltage VA-PULL VA = −1 V 61 Ω

START-UP TIME4 tSTART-UP VOUT = −4.5 V, CAFB = 1 nF, CA = 1 µF 15 ms

VOUT = −4.5 V, CAFB = 10 nF, CA = 1 µF 55 ms

VOUT = −1.2 V, CAFB = 1 nF, CA = 1 µF 4 ms

OUT

= −1.2 V, C

AFB

= 10 nF, C

= 1 µF

VOUT = −0.5 V, no CAFB, CA = 1 µF 1.5 ms

CURRENT-LIMIT THRESHOLD5 ILIMIT −400 −600 −800 mA

THERMAL SHUTDOWN

Threshold TSSD TJ rising 150 °C

Hysteresis TSSD-HYS 15 °C

ADP7183 Data Sheet

Rev. B | Page 4 of 19

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

UNDERVOLTAGE LOCKOUT THRESHOLDS

Input Voltage

Rising UVLORISE −1.77 V

Falling UVLOFALL −1.58 V

Hysteresis

UVLO

HYS

EN INPUT (NEGATIVE) −2 V ≤ VIN ≤ −5.5 V

Logic High VEN-NEG-HIGH VOUT = off to on −1.3 −1.16 V

Logic Low VEN-NEG_LOW VOUT = on to off −0.96 −0.88 V

Hysteresis ENHYS-NEG 191 mV

Leakage Current IEN-LKG EN = VIN or GND −0.25 µA

EN INPUT (POSITIVE)

−2 V ≤ V

≤ −5.5 V

Logic High VEN-POS-HIGH VOUT = off to on 0.96 1.25 V

Logic Low VEN-POS-LOW VOUT = on to off 0.5 0.89 V

Leakage Current IEN-LKG VEN = 5 V, VIN = −5.5 V 4.0 6.0 µA

1 Guaranteed by characterization but not production tested.

2 Based on an endpoint calculation using −1 mA and −300 mA loads.

3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output

voltages below −2 V.

4 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.

5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current-limit threshold for a

−3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of −3.0 V, or −2.7 V.

INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

CAPACITANCE TA = −40°C to +125°C

Minimum C

and C

OUT

Capacitance

, C

OUT

3.3

4.7

µF

Minimum CA and CREG Capacitance2 CA, CREG 0.7 1 µF

Minimum CAFB Capacitance3 CAFB 0.7 10 nF

Capacitor Equivalent Series Resistance (ESR) RESR 0.1 Ω

1 The minimum input and output capacitance must be greater than 3.3 µF over the full range of operating conditions. X7R and X5R type capacitors are recommended;

Y5V and Z5U capacitors are not recommended for use with any LDO.

2 The minimum CA and CREG capacitance must be greater than 0.7 µF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V

and Z5U capacitors are not recommended for use with any LDO.

3 The minimum CAFB capacitance must be greater than 0.7 nF over the full range of operating conditions. X7R and X5R type capacitors are recommended; Y5V and Z5U

capacitors are not recommended for use with any LDO.

Data Sheet ADP7183

Rev. B | Page 5 of 19

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND +0.3 V to −6 V

VOUT to GND +0.3 V to −VIN

EN to GND +5.0 V to −6 V

VA to GND +0.3 V to −6 V

VAFB to GND +0.3 V to −6 V

VREG to GND +0.3 V to −2.16 V

SENSE to GND +0.3 V to −6 V

Storage Temperature Range

−65°C to +150°C

Operating Junction Temperature Range −40°C to +125°C

Soldering Conditions JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in

combination. The ADP7183 can be damaged when the junction

temperature limits are exceeded. Monitoring ambient temperature

does not guarantee that TJ is within the specified temperature

limits. In applications with high power dissipation and poor

thermal resistance, the maximum ambient temperature may

have to be derated.

In applications with moderate power dissipation and low printed

circuit board (PCB) thermal resistance, the maximum ambient

temperature can exceed the maximum limit as long as the

junction temperature is within specification limits. The junction

temperature (TJ) of the device is dependent on the ambient

temperature (TA), the power dissipation of the device (PD), and

the junction to ambient thermal resistance of the package (θJA).

Use the following equation to calculate the junction temperature

(TJ) from the ambient temperature (TA) and power dissipation (PD):

TJ = TA + (PD × θJA)

The junction to ambient thermal resistance (θJA) of the package

is based on modeling and calculation using a 4-layer board. The

junction to ambient thermal resistance is highly dependent on

the application and board layout. In applications where high

maximum power dissipation exists, close attention to thermal

board design is required. The θJA value may vary, depending on

the PCB material, layout, and environmental conditions. The

specified θJA values are based on a 4-layer, 4 in. × 3 in. circuit board.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 4. Thermal Resistance

Package Type θJA θJC Unit

CP-8-271 68.8 10.0 °C/W

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with four thermal vias. See JEDEC JESD51.

ESD CAUTION

ADP7183 Data Sheet

Rev. B | Page 6 of 19

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

3VA

4VAFB

1VOUT

2SENSE

6GND

5 EN

8 VIN

7 VREG

ADP7183

TOP VI EW

(No t t o Scal e)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD ENHANCES THE

THE RM AL PERFO RM ANCE AND IS ELECTRI CALLY

CONNE CTED T O VIN INS IDE THE PACKAGE. I T IS

RECO M M E NDE D THAT THE E X P OSED P AD CONNECT

TO THE INPUT VOLTAGE PLANE ON THE BOARD.

12897-003

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VOUT Regulated Output Voltage. Bypass the VOUT pin to the GND pin with a 4.7 µF or greater capacitor.

2 SENSE Sense Input. Connect this pin to the VOUT pin.

3 VA Low Noise Reference Voltage. Connect a 1 µF capacitor to GND to reduce noise. Do not connect a load to ground.

4 VAFB Output Voltage Reference Feedback (Adjust Mode). Connect a 1 nF to 1 µF capacitor between the VAFB pin and

the VA pin to reduce noise. Start-up time is increased as a function of the capacitance. Connect an external resistor

divider between the VA pin and the VAFB pin to set the output voltage in adjust mode.

5 EN Enable. Drive EN at least +1.25 V above or −1.3 V below ground to enable the regulator or drive EN to ground to

turn the regulator off. For automatic startup, connect EN to VIN.

6 GND Ground.

7 VREG Regulated Input Supply to the LDO Amplifier. Bypass VREG to GND with a 1 µF or greater capacitor. Do not

connect a load to ground.

8 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor.

EP Exposed Pad. The exposed pad enhances the thermal performance and is electrically connected to VIN inside the

package. It is recommended that the exposed pad connect to the input voltage plane on the board.

Data Sheet ADP7183

Rev. B | Page 7 of 19

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = −3.8 V, VOUT = −3.3 V, IOUT = −10 mA, CIN = COUT = 4.7 μF, CAFB = 10 nF, CA = CREG = 1 μF, TA = 25°C, unless otherwise noted.

OUT

(V)

JUNCTION TEMPERATURE (°C)

–60 –40 –20 0 20 40 60 80 100 120 140

NO LOAD

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –300mA

12897-204

–1.216

–1.211

–1.206

–1.201

–1.196

–1.191

–1.186

Figure 4. Output Voltage (VOUT) vs. Junction Temperature, VOUT = −1.2 V

OUT

(V)

LOAD

(mA)

–1000 –100 –10

12897-205

–1.216

–1.211

–1.206

–1.201

–1.196

–1.191

–1.186

Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.2 V

OUT

(V)

–5.5 –5.0 –4.5 –4.0 –3.5 –3.0 –2.5 –2.0

NO LOAD

LOAD

=–10mA

LOAD

= –100mA

LOAD

= –300mA

12897-206

–1.246

–1.236

–1.226

–1.216

–1.206

–1.196

–1.186

Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.2 V

GROUND CURRENT (mA)

JUNCTION TEMPERATURE (°C)

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–15–40 10 35 60 85 110 135

NO LOAD

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –300mA

12897-017

Figure 7. Ground Current vs. Junction Temperature (TJ), VOUT = −1.2 V

ILOAD (mA)

–300 –200 –100 0

GROUND CURRENT (mA)

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

12897-018

Figure 8. Ground Current vs. Load Current (ILOAD), VOUT = −1.2 V

GROUND CURRENT (mA)

(V)

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–5.5 –5.0 –4.5 –4.0 –3.5 –3.0 –2.5 –2.0

NO LOAD

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –300mA

12897-019

Figure 9. Ground Current vs. Input Voltage (VIN), VOUT = −1.2 V

ADP7183 Data Sheet

Rev. B | Page 8 of 19

SHUTDOWN CURRENT (µA)

JUNCTION TEMPERATURE (°C)

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–40 –15 10 35 60 85 110 135

= –2.0V

= –2.5V

= –3.0V

= –3.5V

= –4.0V

= –4.5V

= –5.0V

= –5.5V

12897-020

Figure 10. Shutdown Current vs. Junction Temperature at Various Input Voltages,

VOUT = −1.2 V

–2.555

–2.535

–2.515

–2.495

–2.475

–2.455

–2.435

VOUT (V)

JUNCTION TEMPERATURE (°C)

–60 –40 –20 0 20 40 60 80 100 120 140

NO LOAD

ILOAD =–10mA

ILOAD = –100mA

ILOAD = –300mA

12897-211

Figure 11. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −2.5 V

VOUT (V)

ILOAD (mA)

–1000 –100 –10

12897-212

–2.555

–2.535

–2.515

–2.495

–2.475

–2.455

Figure 12. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −2.5 V

OUT

(V)

–5.5 –5.0 –4.5 –4.0 –3.5 –3.0

NO LOAD

LOAD

=–10mA

LOAD

= –100mA

LOAD

= –300mA

12897-213

–2.575

–2.555

–2.535

–2.515

–2.495

–2.475

–2.455

–2.435

Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −2.5 V

ILOAD (mA)

–3.5

–4.0

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–300 –200 –100–250 –150 –50 0

GROUND CURRENT (mA)

12897-124

Figure 14. Ground Current vs. Load Current (ILOAD), VOUT = −2.5 V

VIN (V)

–3.5

–4.0

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–5.5 –4.5 –3.5–5.0 –4.0 –3.0

GROUND CURRENT (mA)

12897-125

ILOAD = –10mA

ILOAD = –100mA

ILOAD = –200mA

ILOAD = –300mA

Figure 15. Ground Current vs. Input Voltage (VIN), VOUT = −2.5 V

Data Sheet ADP7183

Rev. B | Page 9 of 19

DROPOUT VOLTAGE (mV)

LOAD

(mA)

–1000 –100 –10

–140

–120

–100

–80

–60

–40

–20

12897-029

Figure 16. Dropout Voltage vs. Load Current (ILOAD), VOUT = −2.5 V

OUT

(V)

–2.52

–2.50

–2.48

–2.46

–2.44

–2.42

–

2.36

–2.38

–2.40

–3.1 –3.0 –2.9 –2.8 –2.7 –2.6 –2.5 –2.4

NO LOAD

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –300mA

12897-030

Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout at

Various Loads, VOUT = −2.5 V

OUT

(V)

JUNCTION TEMPERATURE (°C)

–60 –40 –20 0 20 40 60 80 100 120 140

NO LOAD

LOAD

=–10mA

LOAD

= –100mA

LOAD

= –300mA

12897-218

–3.359

–3.339

–3.319

–3.299

–3.279

–3.259

–3.239

Figure 18. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −3.3 V

OUT

(V)

LOAD

(mA)

–1000 –100 –10

12897-219

–3.369

–3.349

–3.329

–3.309

–3.289

–3.269

–3.249

Figure 19. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −3.3 V

VOUT (V)

VIN (V)

NO LOAD

ILOAD =–10mA

ILOAD = –100mA

ILOAD = –300mA

12897-220

–3.38

–3.36

–3.34

–3.32

–3.30

–3.28

–3.26

–5.5 –5.3 –5.1 –4.9 –4.7 –4.5 –4.3 –4.1 –3.9

Figure 20. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −3.3 V

GROUND CURRENT (mA)

JUNCTION TEMPERATURE (°C)

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–15–40 10 35 60 85 110 135

NO LOAD

LOAD

=–10mA

LOAD

= –100mA

LOAD

= –300mA

12897-007

Figure 21. Ground Current vs. Junction Temperature (TJ), VOUT = −3.3 V

ADP7183 Data Sheet

Rev. B | Page 10 of 19

LOAD

(mA)

–3.5

–4.0

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–300 –200 –100 0

GROUND CURRENT ( mA)

12897-008

Figure 22. Ground Current vs. Load Current (ILOAD), VOUT = −3.3 V

GRO UND CURRE NT (mA)

(V)

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

–5.5 –5.3 –5.1 –4.9 –4.7 –4.5 –4.3 –4.1 –3.9

LOAD

= NO LOAD

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –300mA

12897-009

Figure 23. Ground Current vs. Input Voltage (VIN), VOUT = −3.3 V

SHUTDOW N CURRE NT (µ A)

JUNCTI ON T E M P E RATURE (°C)

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

= –3.8V

= –4.0V

= –4.5V

= –5.0V

= –5.5V

–40 –20 020 40 60 80 100 120 140

12897-010

Figure 24. Shutdown Current vs. Junction Temperature (TJ) at

Various Input Voltages, VOUT = −3.3 V

12897-011

DROPOUT VOLTAGE (mV)

LOAD

(mA)

–1000 –100 –10

–140

–120

–100

–80

–60

–40

–20

Figure 25. Dropout Voltage vs. Load Current (ILOAD), VOUT = −3.3 V

VOUT (V)

VIN (V)

–3.31

–3.21

–3.22

–3.23

–3.24

–3.25

–3.26

–3.27

–3.28

–3.29

–3.30

–3.9 –3.8 –3.7 –3.6 –3.5 –3.4 –3.3 –3.2

NO LOAD

ILOAD = –10mA

ILOAD = –100mA

ILOAD = –300mA

12897-012

Figure 26. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout at

Various Loads, VOUT = −3.3 V

GRO UND CURRE NT (mA)

VIN (V)

–25

–20

–15

–10

–5

–3.9 –2.7

–2.8–2.9–3.0–3.1–3.2

–3.3–3.4–3.5–3.6–3.7–3.8

ILOAD = –10mA

ILOAD = –100mA

ILOAD = –300mA

12897-013

Figure 27. Ground Current vs. Input Voltage (VIN) in Dropout at

Various Loads, VOUT = −3.3 V

Data Sheet ADP7183

Rev. B | Page 11 of 19

PSRR (dB)

FREQUENCY ( Hz )

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

110 100 1k 10k 100k 1M 10M

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –200mA

LOAD

= –300mA

12897-032

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Loads, VOUT = −1.2 V, VIN = −2 V

PSRR (dB)

FREQUENCY ( Hz )

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

110 100 1k 10k 100k 1M 10M

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –200mA

LOAD

= –300mA

12897-033

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Loads, VOUT = −2.5 V, VIN = −3 V

PSRR (dB)

FREQUENCY ( Hz )

110 100 1k 10k 100k 1M 10M

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

LOAD

= –10mA

LOAD

= –100mA

LOAD

= –200mA

LOAD

= –300mA

12897-034

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Loads, VOUT = −3.3 V, VIN = −3.8 V

–90

–80

–70

–60

–50

–40

–30

–20

–10

110 100 1k 10k 100k 1M 10M

PSRR ( dB)

FRE Q UE NCY ( Hz )

VIN = –2.0V

VIN = –2.1V

VIN = –2.2V

VIN = –2.3V

VIN = –2.4V

VIN = –2.5V

12897-331

Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Input Voltages, VOUT = −1.2 V, ILOAD = −300 mA

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

110 100 1k 10k 100k 1M 10M

PSRR ( dB)

FREQUENCY ( Hz )

= –3.0V

= –3.1V

= –3.2V

= –3.3V

= –3.4V

= –3.5V

12897-332

Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Input Voltages, VOUT = −2.5 V, ILOAD = −300 mA

–100

–110

–120

–90

–80

–70

–60

–50

–40

–30

–20

–10

110 100 1k 10k 100k 1M 10M

PSRR (dB)

FREQUENCY (Hz)

= –3.8V

= –3.9V

= –4.0V

= –4.1V

= –4.2V

= –4.3V

12897-333

Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency at

Various Input Voltages, VOUT = −3.3 V, ILOAD = −300 mA

ADP7183 Data Sheet

Rev. B | Page 12 of 19

RMS NOISE (µV rms)

LOAD CURRENT (mA)

–1000 –100 –10

3.80

3.85

3.90

3.95

4.00

4.05

4.10

4.15

4.20

4.25

4.30

4.35

4.40

10Hz TO 100kHz

100Hz TO 100kHz

12897-038

Figure 34. RMS Noise vs. Load Current (ILOAD) at Various Frequencies

NSD (nV/

√

Hz)

0.1

100

10k

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M

–1.2V

–2.5V

–3.3V

–4.5V

–4.5V ADJ

12897-235

Figure 35. Noise Spectral Density (NSD) vs. Frequency at Various Output Voltages

12897-139

CH1 500mV CH2 2.0mV 5.0µs/DIV

1MS 20GSPS

A CH2 40mV

VIN

VOUT

Figure 36. Line Transient Response, 500 mV Step, VOUT = −1.2 V, ILOAD = −300 mA

12897-140

CH1 500mV CH2 2.0mV 5.0µs/DIV

1MS 20GSPS

A CH2 40mV

OUT

Figure 37. Line Transient Response, 500 mV Step, VOUT = −3.3 V, ILOAD = −300 mA

12897-141

CH1 200mA CH2 2.00mV M10.00µs A CH1 –222mA

T 21.4µs

LOAD

OUT

Figure 38. Load Transient Response, VOUT = −1.2 V, ILOAD = −10 mA to −300 mA

12897-142

CH1 200mA CH2 2.00mV M10.00µs A CH1 –200mA

T 21.2µs

LOAD

OUT

Figure 39. Load Transient Response, VOUT = −2.5 V, ILOAD = −10 mA to −300 mA

Data Sheet ADP7183

Rev. B | Page 13 of 19

THEORY OF OPERATION

The ADP7183 is a low quiescent current, LDO linear regulator

that operates from −2.0 V to −5.5 V and can provide up to

−300 mA of output current. Total integrated output noise is

4 μV rms independent of the output voltage, making it ideal for

high performance and noise sensitive applications. Shutdown

current consumption is −7 μA (maximum).

The ADP7183 is optimized for use with a 4.7 μF ceramic capacitor

for excellent transient performance. Using advanced proprietary

architecture, the ADP7183 provides ultralow noise and high power

supply rejection up to high frequencies of operation. Figure 40

shows the fixed output voltage internal block diagram of the

ADP7183, and Figure 41 show the adjustable output voltage

internal block diagram of the ADP7183.

VAFB

OVERCURRENT

THERMAL

PROTECTION

REFERENCE

–0.5V

REG

GND

VREG

VIN

SENSE

VOUT

12897-046

Figure 40. Fixed Output Voltage Internal Block Diagram

OVERCURRENT

THERMAL

PROTECTION

REFERENCE

–0.5V

REG

GND

VREG

VIN

VAFB

SENSE

VOUT

12897-047

Figure 41. Adjustable Output Voltage Internal Block Diagram

Internally, the ADP7183 consists of a regulator block, reference

block, GM amplifier, feedback voltage divider, LDO regulator and a N

channel MOSFET pass transistor. The regulator block produces an

internal voltage rail (VREG) of −1.8 V to serve as the supply

voltage for the succeeding internal blocks. The GM amplifier

produces a reference voltage (VA) used as a reference to the

LDO regulator.

For fixed option models, the VA voltage is generated through the

resistor divider ratio depending on the VOUT option. For adjustable

models, the VA voltage generates externally through the R1 and

R2 resistors that are connected across the VA and VAFB pins.

Because the reference voltage to the LDO regulator already

adjusts according to the desired VOUT, the LDO regulator now

connects in a buffer configuration for improved noise performance.

If the load draws higher current, the LDO regulator pulls the gate

of the NMOS device higher towards GND to allow more current

to pass. If the load draws less current, the LDO regulator pulls

the gate of the NMOS device lower toward −VIN to restrict the

amount of current passing through the device.

ADJUSTABLE MODE OPERATION

The adjustable mode version of the ADP7183 has an output that

can be set to from −0.5 V to −4.5 V by an external voltage divider.

To calculate the output voltage, use the following equation:

VOUT = −0.5 V(1 + R1/R2) (1)

Figure 42 shows an example of an adjustable setting where R1 =

280 kΩ and R2 = 49.9 kΩ, setting the output voltage to −3.3 V.

R2 must be at least 10 kΩ to maximize PSRR performance.

4.7µF

= –3.8V

+1.25V

–1.3V

OFF

OUT

= –3.3V

REG

1µF

VIN

VREG

GND

VOUT

SENSE

VAFB

ADP7183

OUT

4.7µF

1µF

280kΩ

49.9kΩ

AFB

10nF

12897-048

Figure 42. Setting the Adjustable Output Voltage

ENABLE PIN OPERATION

The ADP7183 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is +1.25 V above

or −1.3 V below with respect to GND, VOUT turns on and when

EN is at 0 V, VOUT turns off, as shown in Figure 43. For

automatic startup, connect EN to VIN.

12897-149

CH2 1.0V

–15mV

CH3 1.0V

0mV

200ms/DIV

2MS 1MSPS

A CH2 40mV

OUT

Figure 43. Typical EN Pin Operation

ADP7183 Data Sheet

Rev. B | Page 14 of 19

START-UP TIME

When the output is enabled, the ADP7183 uses an internal soft

start to limit the inrush current. The start-up time for a −1.2 V

output is approximately 12 ms from the time the EN active

threshold is crossed to the time when the output reaches 90%

of its final value (see Figure 44). As shown in Figure 44 and

Figure 45, the start-up time is dependent upon the output

voltage option and the value of the CAFB capacitor.

VOUT, EN (V)

TIME (ms)

VOUT = –4. 5V

VOUT = –3. 3V

VOUT = –2. 5V

VOUT = –1. 2V

–6

–5

–4

–3

–2

–1

12897-244

0510 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Figure 44. Start-Up Time at Various Output Voltages, CAFB = 10 nF, CA = 1 µF

The total start-up time depends mostly on the CA and CAFB

values expressed by the τ1 and τ2 equations (see Equation 1 and

Equation 2). During startup, an internal circuit, GM_START, turns

on and helps charge CA up to 90% of the final value. Estimate the

first time constant, τ1, due to CA by

τ1 ≈ CA × ((R1 + R2) // ZOUT) (2)

During this time, keep ZOUT low to approximately 1 kΩ to allow

quick start-up times, keeping τ1 in the order of 1 ms.

VOUT (V)

TIME (ms)

12897-245

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0.5

10 30 50 70 90 110 130 150 170 190 210 230

CAFB = 1n F

CAFB = 10n F

CAFB = 100n F

CAFB = 1µF

Figure 45. Start-Up Time at Various CAFB Capacitor Values, CA = 1 µF

A second time constant, τ2, is dependent mainly on CAFB. Figure 45

shows how the CAFB value affects the start-up time. Estimate τ2 by

τ2 ≈ CAFB × R1 (3)

The R1 value scales vs. the VOUT option. Table 6 shows the R1

value depending on the fixed output voltage option, whereas R2

is constant at 500 kΩ. For example, at a fixed VOUT = −3.3 V, R1

is equal to 2.8 MΩ. To keep τ2 at a minimum, it is recommended

that CAFB be in the approximately nanofarad range. A typical setup

for the ADP7183 is CAFB = 10 nF; therefore, τ2 = 28 ms. The total

time constant, τTOTAL, is the sum of τ1 and τ2. At 2.2 × τTOTAL, VA is

equal to ~90% of the final value. Therefore, for a fixed VOUT =

−3.3 V, the output voltage is ~90% of the final value after 63.8 ms.

Table 6. R1 and R2 Values for the Fixed Output Options

Output Voltage (V) R1 (Ω) R2 (kΩ)

−1.2 700 k 500

−2.5 2 M 500

−3.3

2.8 M

500

−4.5 4 M 500

Note that τ1 and τ2 are estimates only and do not take into account

that GM and ZOUT dynamically change. It is an accurate estimate

of ~90% of the start-up time for the CAFB < 10 nF recommended

setup, where ~100% of the settling time can easily be achieved.

Note that for setups with CAFB >> 10 nF, the equation may not

hold true anymore. However, it is still a convenient estimate on

the amount of time needed to achieve ~100% of the settling time.

Data Sheet ADP7183

Rev. B | Page 15 of 19

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADIsimPower™ design tool set supports the ADP7183.

ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and parts count,

taking into consideration the operating conditions and

limitations of the IC and all external components. For more

information about, and to obtain ADIsimPower design tools,

visit www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Output Capacitor

The ADP7183 operates with small, space-saving ceramic

capacitors; however, it functions with general-purpose

capacitors as long as care is taken with regard to the ESR value.

The ESR of the output capacitor affects the stability of the LDO

regulator control loop. A minimum of 4.7 μF capacitance with

an ESR of 0.05 Ω or less is recommended to ensure the stability of

the ADP7183. Output capacitance affects the transient response

to changes in load currents. Using a larger value for the output

capacitance improves the transient response of the ADP7183 to

large changes in load current. Figure 46 shows the transient

response for an output capacitance value of 4.7 μF.

12897-300

CH1 200mA CH2 2.00mV M10.00µs A CH1 –222mA

T 21.4µs

LOAD

OUT

Figure 46. Output Transient Response, COUT = 4.7 μF, VOUT = −1.2 V

Input Bypass Capacitor

Connecting a 4.7 μF or greater capacitor from VIN to GND

reduces the circuit sensitivity to the PCB layout, especially when

long input traces or high source impedance are encountered.

When more than 4.7 μF of output capacitance is required,

increase the input capacitance to match it.

CA and CAFB Capacitors

The ultralow output noise of the ADP7183 is achieved by

keeping the LDO error amplifier in unity gain and setting the

reference voltage equal to the output voltage. In this architecture,

the resistor driven by the GM amplifier adjusts the reference

voltage to the selected output voltage. To ensure the GM amplifier

stability, the CA capacitor is needed to generate the dominant

pole and to keep the GM amplifier stable across all conditions.

CA also serves as a dampening capacitor to the inputs of the

LDO error amplifier for improved PSRR. However, the LDO

output noise scales by the GM amplifier amount of gain as a

function of the output voltage. To minimize the output voltage

noise contributed by the GM amplifier, the CAFB capacitor must

be connected between the VA and VAFB pins to keep the ac

gain of the GM amplifier in unity.

REFERENCE G

VAFB

GND

AFB

12897-100

Figure 47. CA and CAFB Connection to GM Amplifier

Input and Output Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADP7183 if they meet the minimum capacitance and maximum

ESR requirements. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R and X7R dielectrics with a

voltage rating from 6.3 V to 10 V are recommended. Due to their

poor temperature and dc bias characteristics, Y5V and Z5U

dielectrics are not recommended.

ADP7183 Data Sheet

Rev. B | Page 16 of 19

Figure 48 shows the capacitance change vs. the bias voltage

characteristics of a 0805 case, 4.7 µF, 1 0 V, X5R capacitor. The

capacitor size and voltage rating strongly influences the voltage

stability of a capacitor. In general, a capacitor in a larger package

or with a higher voltage rating exhibits improved stability. The

temperature variation of the X5R dielectric is about ±15% over

the −55°C to +85°C temperature range and is not a function of

package size or voltage rating.

00246810 12

CHANGE IN CAPACIT ANCE ( µ F)

DC BIAS V OL TAGE ( V dc)

5.64

4.70

1.88

2.82

3.76

0.94

12897-053

Figure 48. Change in Capacitance vs. DC Bias Voltage

Use Equation 4 to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

CEFF = COUT × (1 − Tempco) × (1 − TOL) (4)

where:

CEFF is the effective capacitance at the operating voltage.

COUT is the output capacitor.

Tempco is the worst case capacitor temperature coefficient.

TOL is the worst case component tolerance.

In this example, the worst-case temperature coefficient (Tempco)

over −55°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

COUT = 4.7 µF at 1.0 V.

Substituting these values in Equation 4 yields

CEFF = 4.7 µF × (1 − 0.15) × (1 − 0.1) = 3.6 µF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO regulator over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7183, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO circuitry protects the system from power supply

brownouts. If the input voltage on VIN is more positive than

the minimum −1.58 V UVLO falling threshold, the LDO output

shuts down. The LDO enables again when the voltage to VIN is

more negative than the maximum −1.77 V UVLO rising threshold.

A typical hysteresis of 90 mV within the UVLO circuitry prevents

the device from oscillating due to the noise from VIN.

–0.55

–0.50

–0.45

–0.40

–0.35

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

0.05

–1.75 –1.73 –1.71 –1.69 –1.67 –1.65 –1.63 –1.61

OUT

(V)

12897-349

Figure 49. Typical UVLO Behavior, VOUT = −0.5 V

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7183 is protected against damage due to excessive

power dissipation by current-limit and thermal overload

protection circuits. The ADP7183 is designed to reach the

current limit when the output load reaches −600 mA (typical).

When the output load exceeds −600 mA, the output voltage

reduces to maintain a constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a threshold of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and

power dissipation) when the junction temperature begins to

rise above 150°C, the output turns off, reducing the output

current to zero. When the junction temperature drops below

135°C (typical), the output turns on again, and the output

current is restored to its nominal value.

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADP7183 reaches the current limit so that only

−600 mA is conducted into the short. If self heating of the junction

becomes great enough to cause its temperature to rise above 150°C,

thermal shutdown activates, turning off the output and reducing

the output current to 0 mA. As the junction temperature cools

and drops below 135°C, the output turns on and conducts

−600 mA into the short circuit, again causing the junction

temperature to rise above 150°C. This thermal oscillation between

135°C and 150°C causes a current oscillation between −600 mA

and 0 mA that continues as long as the short remains at the output.

Current-limit and thermal overload protections protect the device

against accidental overload conditions. For reliable operation,

device power dissipation must be externally limited so that

junction temperatures do not exceed 125°C.

Data Sheet ADP7183

Rev. B | Page 17 of 19

THERMAL CONSIDERATIONS

In applications with a low input-to-output voltage differential,

the ADP7183 does not dissipate much heat. However, in

applications with high ambient temperature and/or high input

voltage, the heat dissipated in the package may become large

enough to cause the junction temperature of the die to exceed

the maximum junction temperature of 125°C.

When the junction temperature exceeds 150°C, the converter

enters thermal shutdown. The converter recovers only after the

junction temperature decreases below 135°C to prevent any

permanent damage. Therefore, thermal analysis for the chosen

application is important to guarantee reliable performance over

all conditions. The junction temperature of the die is the sum of

the ambient temperature of the environment and the temperature

rise of the package due to the power dissipation, as shown in

Equation 5.

To guarantee reliable operation, the junction temperature of the

ADP7183 must not exceed 125°C. To ensure that the junction

temperature stays below this maximum value, the user must be

aware of the parameters that contribute to junction temperature

changes. These parameters include ambient temperature, power

dissipation in the power device, and thermal resistances between

the junction and ambient air (θJA). The θJA number is dependent

on the package assembly compounds that are used, and the amount

of copper used to solder the package VIN pins to the PCB.

Table 7 shows the typical θJA values for the 8-lead LFCSP

package for various PCB copper sizes.

Table 7. Typical θJA Values for the 8-Lead LFCSP

Copper Size (mm2) θJA (°C/W)

25 146.6

100 105.4

500 75.38

1000 65.16

6400 53.5

Calculate the junction temperatures of the ADP7183 by

TJ = TA + (PD × θJA) (5)

where:

TA is the ambient temperature.

PD is the power dissipation in the die, given by

PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND) (6)

where:

VIN and VOUT are the input and output voltages, respectively.

ILOAD is the load current.

IGND is the ground current.

Power dissipation due to ground current is quite small and can

be ignored. Therefore, the junction temperature equation

simplifies to

TJ = TA + (((VIN − VOUT) × ILOAD) × θJA) (7)

As shown in Equation 7, for a given ambient temperature,

input-to-output voltage differential, and continuous load current,

a minimum copper size requirement exists for the PCB to ensure

that the junction temperature does not rise above 125°C.

Figure 50 to Figure 52 show the junction temperature calculations

for the different ambient temperatures, power dissipation, and

areas of the PCB copper.

140

100

120

01.6

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

0.2 0.4 0.6 0.8 1.0 1.2 1.4

TJ MAX

6400mm2

1000mm2

500mm2

100mm2

25mm2

12897-055

Figure 50. Junction Temperature vs. Total Power Dissipation, TA = 25°C

140

100

120

01.6

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

0.2 0.4 0.6 0.8 1.0 1.2 1.4

TJ MAX

6400mm2

1000mm2

500mm2

100mm2

25mm2

12897-056

Figure 51. Junction Temperature vs. Total Power Dissipation, TA = 50°C

140

100

120

1.6

JUNCTION TEM P E RATURE (°C)

TOTAL POWER DISSIPATION (W)

TJ MAX

6400mm2

1000mm2

500mm2

100mm2

25mm2

0.200.4 0.6 0.8 1.0 1.2 1.4

12897-057

Figure 52. Junction Temperature vs. Total Power Dissipation, TA = 85°C

ADP7183 Data Sheet

Rev. B | Page 18 of 19

PCB LAYOUT CONSIDERATIONS

Place the input capacitor (CIN) as close as possible to the VIN

and GND pins. Place the output capacitor (COUT) as close as

possible to the VOUT and GND pins. Place bypass capacitors

(CA and CREG) close to the respective pins (VA and VREG) and

GND. Use of 0805 or 0603 size capacitors and resistors achieves

the smallest possible footprint solution on boards where area is

limited. Connect the exposed pad to VIN.

12897-059

Figure 53. Evaluation Board

12897-060

Figure 54. Typical Board Layout, Top Side

12897-061

Figure 55. Typical Board Layout, Bottom Side

Data Sheet ADP7183

Rev. B | Page 19 of 19

OUTLINE DIMENSIONS

1.60

1.50

1.40

0.30

0.25

0.20

TOP VIEW

SIDE VIEW

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

0.60

0.55

0.50

1.10

1.00

0.90

0.152 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

08-24-2016-A

PKG-004752

2.10

2.00 SQ

1.90

SEATING

PLANE

PIN 1

INDICATOR AREA OPTIONS

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP]

2 mm × 2 mm Body and 0.55 mm Package Height

(CP-8-27)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Output Voltage (V)2 Package Description Package Option Branding

ADP7183ACPZN0.5-R7 −40°C to +125°C −0.5 8-Lead LFCSP CP-8-27 LS9

ADP7183ACPZN1.0-R7 −40°C to +125°C −1.0 8-Lead LFCSP CP-8-27 LSA

ADP7183ACPZN1.2-R7 −40°C to +125°C −1.2 8-Lead LFCSP CP-8-27 LSB

ADP7183ACPZN1.5-R7 −40°C to +125°C −1.5 8-Lead LFCSP CP-8-27 LSC

ADP7183ACPZN1.8-R7 −40°C to +125°C −1.8 8-Lead LFCSP CP-8-27 LSD

ADP7183ACPZN2.0-R7 −40°C to +125°C −2.0 8-Lead LFCSP CP-8-27 LSS

ADP7183ACPZN2.5-R7 −40°C to +125°C −2.5 8-Lead LFCSP CP-8-27 LSE

ADP7183ACPZN3.0-R7 −40°C to +125°C −3.0 8-Lead LFCSP CP-8-27 LSF

ADP7183ACPZN3.3-R7 −40°C to +125°C −3.3 8-Lead LFCSP CP-8-27 LTM

ADP7183ACPZN-R7 −40°C to +125°C Adjustable 8-Lead LFCSP CP-8-27 LS8

ADP7183-3.3-EVALZ −3.3 Evaluation Board for the

Fixed Voltage Option

ADP7183-ADJ-EVALZ −2.5 Evaluation Board for the

Adjustable Voltage Option

1 Z = RoHS Compliant Part.

2 For additional voltage options, contact a local Analog Devices Inc., sales or distribution representative.

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D12897-0-5/17(B)