MT5C2568 32K x 8 SRAM SRAM 32K x 8 SRAM FEATURES High speed: 10, 12, 15, 20 and 25 High-performance, low-power, CMOS double-metal process Single +5V +10% power supply Easy memory expansion with CE and OE options All inputs and outputs are TTL-compatible OPTIONS MARKING * Timing 10ns access -10 12ns access -12 15ns access -15 20ns access -20 25ns access -25 Packages Plastic DIP (300 mil) None Plastic SOJ (300 mil) DJ 2V data retention (optional) L Low power (optional) P Temperature Commercial (0C to +70C) None Industrial (-40C to +85C) IT Automotive (-40C to +125C) AT Extended (-55C to +125C) XT Part Number Example: MT5C2568DJ-20 L NOTE: Not all combinations of operating temperature, speed, data retention and low power are necessarily available. Please contact the factory for availabil- ity of specific part number combinations GENERAL DESCRIPTION The MT5C2568 is organized as a 32,768 x 8 SRAM using a four-transistor memory cell witha high-speed, low-power CMOS process. Micron SRAMsare fabricated using double- layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Micron offers chip enable (CE) and output enable (OE) with this organization. These enhancements can place the out- puts in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode PIN ASSIGNMENT (Top View) 28-Pin DIP 28-Pin SOJ (SA-4) (SD-2) Alta [] 1 28 [] Veco At2 [}2 27 [] WE a7 (| 3 26 |] Ala As [| 4 25 {] ag Ad (5 24 {] AS aa (6 23] Ait A3 [|7 22 [] OE A2 [| 8 2t [] Alo At {]9 20 [] CE Ao (] 10 19 [] Das pat fj 11 18 {] 0a7 ae [] 12 17 {] Dae bas [13 16 (] Das vss [| 14 15] 004 when disabled. This allows system designers to meet low standby power requirements. The P version provides a reduction in both operating current (Icc) and TTL standby current (Is1). The latter is achieved through the use of gated inputs on the WE, OE and address lines, which also facilitates the design of battery backed systems. That is, the gated inputs simplify the design effort and circuitry required to protect against inad- vertent battery current drain during power-down, when inputs may be at undefined levels. All devices operate froma single +5V power supply and all inputs and outputs are fully TTL-compatible. MT5C2568 Rev 11/04 MH 6111549 0010285 175 Micron Semiconductor, Inc , reserves the right to change products or specrficabons without notce 1994, Micron Sermconductor Inc INVUS SNONOYHONASV ASWVuS SNONOYHONASY AS MICRON anole prarateti 32K x 8 SRAM FUNCTIONAL BLOCK DIAGRAM Vec GND A > A > DasB A 5 5 A O o o 262,144-BIT 5 ra) MEMORY ARRAY Oo 1 A = oO DQ1 3 Q A Cry * A oS LSB __ CH oO WE COLUMN DECODER (LSB) POWER ror tot tf to f GEM A A A A A A A TRUTH TABLE MODE OE CE | WE ba POWER STANDBY Xx H Xx HIGH-Z | STANDBY READ L L H Q ACTIVE NOT SELECTED] H L H HIGH-Z ACTIVE WRITE Xx L L D ACTIVE MTS5C2568 Rev 11/94 MB 6111549 0010286 0Ol 1 62 Micron Semiconductor, Inc , raserves the nght to change products or specificatons without notice 1984, Micron Semiconductor, Inc.MICRON MT5C2568 32K x 8 SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vs5 0.0.0.0... -1V to +7V Stresses greater than those listed under Absolute Maxi- Storage Temperature (plastic) .............+ mum Ratings may cause permanent damage to the device. o Short Circuit Output Current -.0...0.. ee eeeeenees This is a stress rating only and functional operation of the Voltage on Any Pin Relative to VSS... device at these or any other conditions above those indi- < Junction Temperature ........csceseccssseecssssssessessssveees cated in the operational sections of this specification is not > implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. w Maximum junction temperature depends upon package =< type, cycle time, loading, ambient temperature and airflow. =< See technical note TN-05-14 for more information. O ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS Oo (OC < T, < 70C; Veco = SV 10%) =< DESCRIPTION CONDITIONS SYMBOL | MIN MAX UNITS | NOTES O Input High (Logic 1) Voltage Vin 22 Vec+1 Vv 1 Cc Input Low (Logic 0) Voltage ViL -0.5 0.8 Vv 12 1Q) Input Leakage Current OV < Vin < Vcc Iki 5 5 pA ~ Output Leakage Current Output(s) disabled ILo 5 5 pA UU OV < VouT < Vcc > Output High Voltage lon = -4.0mMA Vou 2.4 Vv 1 Output Low Voltage lo. = 8.0MA Vou 0.4 Vv 1 = Supply Voltage Vcc 4.5 5.5 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL | TYP -10t | -12t | -15t | -20 | -25 |UNITS|NOTES Power Supply CE < Vii; Voc = MAX Current: Operating f = MAX = 1/'RC loc 130 200 | 180 | 165 | 150 | 140] mA | 3, 13 outputs open | _P version lec 100 - | - | 140] 125 | 120] ma [3, 13 Power Supply CE > Vin; Vcc = MAX Current: Standby f = MAX = 1/'RC IsBt 24 55 | 50 | 45 ; 40 | 35 | mA] 13 outputs open | P version isB1 1.4 : - | 4 | 4 | 4 | mal 13 CE 2 Vcc -0.2V; Voc = MAX Vin < Vss +0.2V or Isp2 0.6 5 5 5 5 5 mA |} 13 VIN 2 Vcc -0.2V; f=0 | P version IsB2 0.4 - | - | 3] 3 | 3 | mal 43 +P version not available with this speed. MTSC2566 1 63 Micron Semiconductor, Inc , reserves the right lo change products or specifications without notica Rev. 11/94 1964, Micron Semiconductor inc MH 6111549 00102867 TuaINVES SNONOYHONASV AS MICRON MT5C2568 32K x 8 SRAM CAPACITANCE DESCRIPTION CONDITIONS SYMBOL | MAX UNITS NOTES Input Capacitance Ta = 25C; f= 1 MHz Cc 6 pF 4 Output Capacitance Vcc = 5V Co 6 pF 4 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (0C < T, < 70C; Voc = 5V +10%) -10 -12 -15 -20 -25 DESCRIPTION SYM | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX [UNITS|NOTES READ Cycle READ cycle time 'RC 10 12 15 20 25 ns Address access time AA 10 12 15 20 25 ns Chip Enable access time tACE 10 12 15 20 25 ns Output hold from address change OH 3 3 3 3 3 ns Chip Enable to output in Low-Z LZCE | 3 3 3 3 3 ns | 7 Chip disable to output in High-Z tHZCE 5 6 8 9 9 ns | 6,7 Chip Enable to power-up time 'PU 0 0 0 0 0 ns | 4 Chip disable to power-down time 'PD 10 12 15 20 25 | ns 4 Output Enable access time 'AOE 5 6 8 8 8 ns Output Enable to output in Low-Z2 'LZOE 0 0 0 0 0 ns Output disable to out put in High-Z 'HZOE 5 6 6 7 7 | ns} 6 WRITE Cycle WRITE cycle time WC 10 12 15 20 25 ns Chip Enable to end of write cw 7 8 10 12 15 ns Chip Enable to end of write (P and LP version) cw - : 12 12 15 ns Address valid to end of write tAW 7 8 10 12 15 ns Address valid to end of write (P and LP version) TAW : : 12 12 16 ns Address setup time tAS 0 0 0 0 0 ns Address hold from end of write AH 1 1 1 1 1 ns WRITE pulse width wP1 | 7 8 10 12 15 ns WRITE pulse width twP2 10 12 12 15 15 ns Data setup time DS 6 7 7 10 10 ns Data hold time 'DH 0 0 0 0 0 ns Write disable to output in Low-Z LZ2WE | 2 2 2 2 2 ns 7 Write Enable to output in High-Z 'HZWE 5 6 7 8 10 | ns | 6,7 fev 1184 1-64 eee ee a re rage Mason Somkoreaador, ne MM 6412545 0010268 164MT5C2568 32K x 8 SRAM INDUSTRIAL TEMPERATURE SPECIFICATIONS (IT) The following specifications are to be used for Industrial Temperature (IT) MT5C2568 SRAMs. (-40C < T, < 85C) MAX DESCRIPTION CONDITIONS SYMBOL -10 12 -15 -20 -25 | UNITS | NOTES Power Supply CE < Vit; Vcc = MAX Current: Operating f = MAX = 1/'RC Icc 210 | 190 | 170 | 160 | 150 mA 3 outputs open Power Supply CE = Vin; Voc = MAX Current: Standby f = MAX = 1/'RC ise1 65 60 50 45 40 mA outputs open CE 2 Voc -0.2V; Voc = MAX Vin < Vss +0.2V or IsB2 6 6 6 6 6 mA Vin > Voc -0.2V; f= 0 DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only) DESCRIPTION CONDITIONS SYMBOL MAX UNITS NOTES Data Retention Current | CE > (Vcc -0.2V) Vcc = 2V Iccor 400 yA Vin 2 (Vcc -0.2V) or <0.2V Voc = 3V IccpR 600 pA ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Refer to commercial temperature timing parameters for specifications not listed here. (Notes 5, 13) (-40C < T, < 85C) 12 15 -20 25 DESCRIPTION sym | MIN | MAX] MIN | MAX | MIN ] max | MIN | Max | UNITS | NOTES READ Cycle Output hold from address change OH 2 2 2 2 ns Chip Enable to output in Low-Z 1LZCE}] 2 2 2 2 ns 7 WRITE Cycle Address hold from end of write TtaH | 2 | | 2 | | 2 | | 2 | [ns | ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-40C < T, < 85C) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage Vin 2.3 Vec +1 Vv 1 Mrscasss 1 6 5 Micron Semiconductor, Inc , reserves the nght to change products ah specications io notice Mi 61115459 0010269 610 WVYS SNONOYHONASV ASa _ a MT5C2568 MICRON 32K x 8 SRAM AUTOMOTIVE AND EXTENDED TEMPERATURE SPECIFICATIONS (AT AND XT) The following specifications are to be used for Automotive Temperature (AT) and Extended Temperature (XT) MT5C2568 Ol SRAMs. (-40C <T, $ 125C - AT) (55C <T, Ss 125C - XT) < MAX > DESCRIPTION CONDITIONS SYMBOL; -12 15 -20 25 UNITS | NOTES Power Supply CE < Vit; Voc = MAX =< | Current: Operating f= MAX = 1/'RC icc | 195 | 175 | 165 | 155 | mA | 3 za outputs open ) | Power Supply CE = Vin; Voc = MAX = Current: Standby f= MAX = 1/'RC IsB1 60 50 45 40 mA outputs open BS CE 2 Vec -0.2V; Veco = MAX O Vin < Vss +0.2V or Ise2 7 7 7 7 mA z Vin 2 Voc -0.2V; f= 0 n DATA RETENTION ELECTRICAL CHARACTERISTICS (L version only) % DESCRIPTION CONDITIONS _| SYMBOL MAX UNITS NOTES Data Retention Current CE > (Vee -0.2V) Veco = 2V Icepr 00 pA > Vin 2 (Vcc -0.2V) = or <0.2V Vcc = 38V lccor 800 BA ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Refer to commercia! temperature timing parameters for specifications not listed here. (Notes 5, 13) (-40C < T, < 125C - AT; -55C < T, < 125C - XT; Voc = 5V 410%) 12 15 -20 -25 DESCRIPTION sym | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | UNITS | NOTES READ Cycle Qutput hold from address change OH 2 2 2 2 ns Chip Enable to output in Low-Z ZCE| 2 2 2 2 ns 7 WRITE Cycle Address hold from end of write [ AH | 2 | [ 2] | 2 | | 2 | { ns | ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-40C < T, < 125C - AT) (-55C < Ty < 125C - XT) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage Vin 2.3 Vec +1 Vv 1 MTscesee 1-66 - Micron Samiconductor, Inc, reserves the nght to change products or specications without notice M@@ 6111549 0010290 532 mmMICRON MT5C2568 ara 32K x 8 SRAM AC TEST CONDITIONS +8V +8 Input pulse levels... cc eetseeteeeeseeees Vss to 3.0V a 480 a 480 Input rise and fall times ..........sccssceccceecssecsesseeeaees 3ns 255 a7 90 pF 255 5 pF Input timing reference levels ........... cee 1.5V Vv Output reference levels uo... eens 1.5V . ; ; Fig. 1 OUTPUT LOAD Fig. 2 OUTPUT LOAD Output load oo... eee eeeees See Figures 1 and 2 EQUIVALENT EQUIVALENT NOTES 1. All voltages referenced to Vss (GND). 8. WEis HIGH for READ cycle. 2. -3V for pulse width < *RC/2. 9. Device is continuously selected. All chip enables are 3. Icc is dependent on output loading and cycle rates. held in their active state. 4. This parameter is sampled. 10. Address valid prior to, or coincident with, latest 5. Test conditions as specified with the output loading occurring chip enable. as shown in Fig. 1 unless otherwise noted. 11. RC = Read Cycle Time. 6. 'HZCE, 'HZOE and 'HZWE are specified with C, = 12. Chip enable and write enable can initiate and 5pF as in Fig. 2. Transition is measured +500mV from terminate a WRITE cycle. steady state voltage. 13. Typical values are measured at 5V, 25C and 15ns 7. Atany given temperature and voltage condition, cycle time. tHZCE is less than *LZCE, and HZWE is less than 14. Typical currents are measured at 25C. 'LZWE. DATA RETENTION ELECTRICAL CHARACTERISTICS (L and LP versions only) DESCRIPTION CONDITIONS SYMBOL | MIN TYP MAX UNITS | NOTES Vcc for Retention Data Vor 2 Vv Data Retention Current CE 2 (Vee -0.2V) | Vec = 2V]_Iccoar 125 300 pA 14 L version Vin > (Vec -0.2V) or<0.2V Vec = 3V Iccor 175 500 pA 14 Data Retention Current CE 2 (Vec -0.2V) | Voc = 2V}__Iccor 100 300 pA 14 LP version Vcc = 3V kccpR 150 500 pA 14 Chip Deselect to Data CDR 0 ns 4 Retention Time Operation Recovery Time 'R RC ns 4,11 MTS5C2568 Micron Semiconductor, Inc , reserves the right to change products or specifications without notice Rav 41/94 1 -67 1994 Micron Semiconductor Inc MH 6131549 0010291 479 WVYS SNONOYHONASV ASINVYS SNONOYHONASV AS KY 4 MT5C2568 x 8 SRAM Vec LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE NY 4.5 4sv~ K Vor A tcDR ty e/a * ~L. ADDR DQ READ CYCLE NO. 12 tac | VALID y taa |__| tou PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 278.10 tac | /_- N } Xe) LZ0E tHZ0E | tace "2cCE HIGH-Z DATA VALID tpu _A_$<$_$____| | tpp DON'T CARE RY UNDEFINED MTSC2568 Rev 11/94 MB 61121549 001029e 305 | 6 8 Micron Semiconductor inc , reserves the nght to change products or specifications without notice 7 @ 1984, Micron Semiconductor, ncMT5C2568 32K x 8 SRAM WRITE CYCLE NO. 1 72 (Chip Enable Controlled) we ADDR tAW tas \ tow AH YO aT FT twe1 MU, WLLL tos tbH do 4 DATA VALID ya Q HIGH-Z WRITE CYCLE NO. 272 (Write Enable Controlled) two ADDR Y taw | tow tan = TMD: YLILLLILLLL | tas \ twe4 7 _ WE J} tps 'bH $i | bd (4 DATA VALID by Vi Vi Yi Q HIGH-Z DONT CARE RRQ] UNDEFINED NOTE: Output enable (OE) is inactive (HIGH). MT5C2568 1-69 Micron Semiconductor, Inc., reserves the nght to changa products or specifications without notice Rev 11/04 - @1994 Micron Semiconductor, Inc. MB 6113549 0010293 241 WVYS SNONOYHONASV ASWVdS SNONOYHONASV AS MICRON MT5C2568 32K x 8 SRAM WRITE CYCLE NO. 37: 12.16 (Write Enable Controlled) two ADDR CE WE tps Db DATA VALID Q DON'T CARE BX) UNDEFINED NOTE: Output enable (OE) is active (LOW). MTBC255S 1 -70 Micron Semiconductor Inc , reserves the nght to change. Product oa spearicatons thou eons MH 6111549 0010294 188